pkg/ifuzz: update to latest intelxed

Update all-enc-instructions.txt to b7231de4c808db821d64f4018d15412640c34113 and regenerate instruction info.
author: Dmitry Vyukov <dvyukov@google.com> 2019-06-23 14:58:12 +0200
committer: Dmitry Vyukov <dvyukov@google.com> 2019-06-23 15:10:27 +0200
commit: 472f0082fd8a2f82b85ab0682086e10b71529a51 (patch)
tree: 0b74081142e7464da99263f6e1d0076a0e965a29 /pkg
parent: da9246f6d754caed30a65276b41e32a05f0c8fa2 (diff)
3 files changed, 9331 insertions, 3937 deletions
diff --git a/pkg/ifuzz/gen/all-enc-instructions.txt b/pkg/ifuzz/gen/all-enc-instructions.txt
index 9afe5353b..717ac8ec2 100644
--- a/pkg/ifuzz/gen/all-enc-instructions.txt
+++ b/pkg/ifuzz/gen/all-enc-instructions.txt
@@ -4,7 +4,7 @@
 
 #BEGIN_LEGAL
 #
-#Copyright (c) 2016 Intel Corporation
+#Copyright (c) 2018 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -730,7 +730,7 @@ ATTRIBUTES: NOTSX
 CPL       : 3
 CATEGORY  : FCMOV
 EXTENSION : X87
-ISA_SET   : PPRO
+ISA_SET   : FCMOV
 FLAGS     : MUST [ cf-tst fc0-u fc1-mod fc2-u fc3-u  ]
 PATTERN   : 0xDA MOD[0b11] MOD=3 REG[0b000] RM[nnn]
 OPERANDS  : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP
@@ -741,7 +741,7 @@ ATTRIBUTES: NOTSX
 CPL       : 3
 CATEGORY  : FCMOV
 EXTENSION : X87
-ISA_SET   : PPRO
+ISA_SET   : FCMOV
 FLAGS     : MUST [ zf-tst fc0-u   fc1-mod fc2-u   fc3-u   ]
 PATTERN   : 0xDA MOD[0b11] MOD=3 REG[0b001] RM[nnn]
 OPERANDS  : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP
@@ -752,7 +752,7 @@ ATTRIBUTES: NOTSX
 CPL       : 3
 CATEGORY  : FCMOV
 EXTENSION : X87
-ISA_SET   : PPRO
+ISA_SET   : FCMOV
 FLAGS     : MUST [ cf-tst zf-tst  fc0-u   fc1-mod fc2-u   fc3-u   ]
 PATTERN   : 0xDA MOD[0b11] MOD=3 REG[0b010] RM[nnn]
 OPERANDS  : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP
@@ -763,7 +763,7 @@ ATTRIBUTES: NOTSX
 CPL       : 3
 CATEGORY  : FCMOV
 EXTENSION : X87
-ISA_SET   : PPRO
+ISA_SET   : FCMOV
 FLAGS     : MUST [ pf-tst fc0-u   fc1-mod fc2-u   fc3-u   ]
 PATTERN   : 0xDA MOD[0b11] MOD=3 REG[0b011] RM[nnn]
 OPERANDS  : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP
@@ -834,7 +834,7 @@ ATTRIBUTES: NOTSX
 CPL       : 3
 CATEGORY  : FCMOV
 EXTENSION : X87
-ISA_SET   : PPRO
+ISA_SET   : FCMOV
 FLAGS     : MUST [  cf-tst fc0-u   fc1-mod fc2-u   fc3-u   ]
 PATTERN   : 0xDB MOD[0b11] MOD=3 REG[0b000] RM[nnn]
 OPERANDS  : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP
@@ -845,7 +845,7 @@ ATTRIBUTES: NOTSX
 CPL       : 3
 CATEGORY  : FCMOV
 EXTENSION : X87
-ISA_SET   : PPRO
+ISA_SET   : FCMOV
 FLAGS     : MUST [  zf-tst fc0-u   fc1-mod fc2-u   fc3-u   ]
 PATTERN   : 0xDB MOD[0b11] MOD=3 REG[0b001] RM[nnn]
 OPERANDS  : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP
@@ -856,7 +856,7 @@ ATTRIBUTES: NOTSX
 CPL       : 3
 CATEGORY  : FCMOV
 EXTENSION : X87
-ISA_SET   : PPRO
+ISA_SET   : FCMOV
 FLAGS     : MUST [  cf-tst zf-tst fc0-u   fc1-mod fc2-u   fc3-u   ]
 PATTERN   : 0xDB MOD[0b11] MOD=3 REG[0b010] RM[nnn]
 OPERANDS  : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP
@@ -867,7 +867,7 @@ ATTRIBUTES: NOTSX
 CPL       : 3
 CATEGORY  : FCMOV
 EXTENSION : X87
-ISA_SET   : PPRO
+ISA_SET   : FCMOV
 FLAGS     : MUST [  pf-tst fc0-u   fc1-mod fc2-u   fc3-u   ]
 PATTERN   : 0xDB MOD[0b11] MOD=3 REG[0b011] RM[nnn]
 OPERANDS  : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP
@@ -1091,6 +1091,7 @@ ICLASS    : FISTTP
 CPL       : 3
 CATEGORY  : X87_ALU
 EXTENSION : SSE3
+ISA_SET   : SSE3X87
 ATTRIBUTES :  NOTSX
 FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
 PATTERN   : 0xDD MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()
@@ -1361,6 +1362,7 @@ ATTRIBUTES: NOTSX
 CPL       : 3
 CATEGORY  : X87_ALU
 EXTENSION : SSE3
+ISA_SET   : SSE3X87
 FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
 PATTERN   : 0xDF MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()
 OPERANDS  : MEM0:w:mem16int REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP
@@ -3795,6 +3797,7 @@ PATTERN   : 0xFF MOD[0b11] MOD=3 REG[0b001] RM[nnn]
 OPERANDS  : REG0=GPRv_B():rw
 IFORM     : DEC_GPRv_FFr1
 }
+
 {
 ICLASS    : CALL_NEAR
 DISASM_INTEL: call
@@ -3803,12 +3806,7 @@ CPL       : 3
 CATEGORY  : CALL
 EXTENSION : BASE
 ISA_SET   : I86
-ATTRIBUTES: MPX_PREFIX_ABLE
-
-PATTERN   : 0xE8 not64 BRDISPz()
-OPERANDS  : RELBR:r:z REG0=XED_REG_STACKPUSH:w:spw:SUPP REG1=rIP():rw:SUPP
-PATTERN   : 0xE8 mode64  BRDISP32() DF64() FORCE64()
-OPERANDS  : RELBR:r:d REG0=XED_REG_STACKPUSH:w:spw:SUPP REG1=rIP():rw:SUPP
+ATTRIBUTES: MPX_PREFIX_ABLE INDIRECT_BRANCH
 
 PATTERN   : 0xFF MOD[mm] MOD!=3 REG[0b010] RM[nnn]  DF64() IMMUNE66_LOOP64() MODRM()
 OPERANDS  : MEM0:r:v REG0=XED_REG_STACKPUSH:w:spw:SUPP REG1=rIP():rw:SUPP
@@ -3816,12 +3814,30 @@ PATTERN   : 0xFF MOD[0b11] MOD=3 REG[0b010] RM[nnn]  DF64() IMMUNE66_LOOP64()
 OPERANDS  : REG0=GPRv_B():r REG1=XED_REG_STACKPUSH:w:spw:SUPP REG2=rIP():rw:SUPP
 }
 {
+ICLASS    : CALL_NEAR
+DISASM_INTEL: call
+DISASM_ATTSV: call
+CPL       : 3
+CATEGORY  : CALL
+EXTENSION : BASE
+ISA_SET   : I86
+ATTRIBUTES: MPX_PREFIX_ABLE
+
+PATTERN   : 0xE8 not64 BRDISPz()
+OPERANDS  : RELBR:r:z REG0=XED_REG_STACKPUSH:w:spw:SUPP REG1=XED_REG_EIP:rw:SUPP
+PATTERN   : 0xE8 mode64  BRDISP32() DF64() FORCE64()
+OPERANDS  : RELBR:r:d REG0=XED_REG_STACKPUSH:w:spw:SUPP REG1=XED_REG_RIP:rw:SUPP
+}
+
+
+
+{
 ICLASS    : JMP
 CPL       : 3
 CATEGORY  : UNCOND_BR
 EXTENSION : BASE
 ISA_SET   : I86
-ATTRIBUTES: MPX_PREFIX_ABLE
+ATTRIBUTES: MPX_PREFIX_ABLE INDIRECT_BRANCH
 PATTERN   : 0xFF MOD[mm] MOD!=3 REG[0b100] RM[nnn] DF64() IMMUNE66_LOOP64() MODRM()
 OPERANDS  : MEM0:r:v REG0=rIP():w:SUPP
 PATTERN   : 0xFF MOD[0b11] MOD=3 REG[0b100] RM[nnn] DF64() IMMUNE66_LOOP64()
@@ -3832,7 +3848,7 @@ ICLASS    : JMP_FAR
 DISASM_INTEL: jmp far
 DISASM_ATTSV: ljmp
 CPL       : 3
-ATTRIBUTES : FAR_XFER NOTSX
+ATTRIBUTES : FAR_XFER NOTSX  INDIRECT_BRANCH
 CATEGORY  : UNCOND_BR
 EXTENSION : BASE
 ISA_SET   : I86
@@ -3959,6 +3975,8 @@ CATEGORY  : SYSTEM
 EXTENSION : BASE
 ISA_SET   : I286REAL
 ATTRIBUTES: NOTSX
+COMMENT   : 66 is OSZ; F2/F3 ignored
+
 PATTERN   : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010]  RM[nnn] mode64 FORCE64() MODRM()
 OPERANDS  : MEM0:r:s64 REG0=XED_REG_GDTR:w:SUPP
 PATTERN   : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010]  RM[nnn] not64 MODRM()
@@ -3970,6 +3988,8 @@ CPL       : 3
 CATEGORY  : SYSTEM
 EXTENSION : BASE
 ISA_SET   : I286REAL
+COMMENT   : 66 is OSZ; F2/F3 ignored
+
 PATTERN   : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()
 OPERANDS  : MEM0:w:w REG0=XED_REG_CR0:r:SUPP
 }
@@ -3979,6 +3999,8 @@ CPL       : 3
 CATEGORY  : SYSTEM
 EXTENSION : BASE
 ISA_SET   : I286REAL
+COMMENT   : 66 is OSZ; F2/F3 ignored
+
 PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]
 OPERANDS  : REG0=GPRv_B():w REG1=XED_REG_CR0:r:SUPP
 }
@@ -4120,28 +4142,33 @@ OPERANDS  : REG0=GPRv_B():rw IMM0:r:b
 
 {
 ICLASS    : VMCLEAR
-CPL       : 3
+CPL       : 0
 CATEGORY  : VTX
 EXTENSION : VTX
 ATTRIBUTES: NOTSX
+FLAGS     : MUST [ cf-mod zf-mod sf-0 of-0 af-0 pf-0 ]
 PATTERN   : 0x0F 0xC7  MOD[mm] MOD!=3 REG[0b110] RM[nnn] osz_refining_prefix REFINING66() MODRM()
 OPERANDS  : MEM0:r:q
 }
 {
 ICLASS    : VMPTRLD
-CPL       : 3
+CPL       : 0
 CATEGORY  : VTX
 EXTENSION : VTX
 ATTRIBUTES: NOTSX
+FLAGS     : MUST [ cf-mod zf-mod sf-0 of-0 af-0 pf-0 ]
+
 PATTERN   : 0x0F 0xC7  MOD[mm] MOD!=3 REG[0b110] RM[nnn] no_refining_prefix  MODRM()
 OPERANDS  : MEM0:r:q
 }
 {
 ICLASS    : VMPTRST
-CPL       : 3
+CPL       : 0
 CATEGORY  : VTX
 EXTENSION : VTX
 ATTRIBUTES: NOTSX
+FLAGS     : MUST [ cf-mod zf-mod sf-0 of-0 af-0 pf-0 ]
+
 PATTERN   : 0x0F 0xC7  MOD[mm] MOD!=3 REG[0b111] RM[nnn] no_refining_prefix MODRM()
 OPERANDS  : MEM0:w:q
 }
@@ -4149,10 +4176,12 @@ OPERANDS  : MEM0:w:q
 
 {
 ICLASS    : VMXON
-CPL       : 3
+CPL       : 0
 CATEGORY  : VTX
 EXTENSION : VTX
 ATTRIBUTES: PROTECTED_MODE NOTSX
+FLAGS     : MUST [ cf-mod zf-mod sf-0 of-0 af-0 pf-0 ]
+
 PATTERN   : 0x0F 0xC7  MOD[mm] MOD!=3 REG[0b110] RM[nnn] f3_refining_prefix IGNORE66() MODRM()
 OPERANDS  : MEM0:r:q
 }
@@ -4496,7 +4525,7 @@ OPERANDS  : MEM0:w:d REG0=XED_REG_MXCSR:r:SUPP
 ICLASS    : PREFETCHNTA
 CPL       : 3
 CATEGORY  : PREFETCH
-ATTRIBUTES: PREFETCH
+ATTRIBUTES: PREFETCH NONTEMPORAL
 EXTENSION : SSE
 ISA_SET   : SSE_PREFETCH
 PATTERN   : 0x0F 0x18 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()
@@ -4711,34 +4740,42 @@ CPL       : 3
 CATEGORY  : VTX
 EXTENSION : VTX
 ATTRIBUTES: NOTSX
-PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b001]
+COMMENT   : on some execution paths loads all flags from VMCS. Always writes CF/PF/AF/ZF/SF/OF.
+FLAGS     : MAY [ id-mod vip-mod vif-mod ac-mod vm-tst rf-mod nt-mod iopl-tst iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
+PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b001] no_refining_prefix
 OPERANDS  :
 }
 {
 ICLASS    : VMLAUNCH
-CPL       : 3
+CPL       : 0
 CATEGORY  : VTX
 EXTENSION : VTX
 ATTRIBUTES: NOTSX
-PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b010]
+COMMENT   : on some execution paths loads all flags from VMCS. Always writes CF/PF/AF/ZF/SF/OF.
+FLAGS     : MAY [ id-mod vip-mod vif-mod ac-mod vm-tst rf-mod nt-mod iopl-tst iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
+PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b010] no_refining_prefix
 OPERANDS  :
 }
 {
 ICLASS    : VMRESUME
-CPL       : 3
+CPL       : 0
 CATEGORY  : VTX
 EXTENSION : VTX
 ATTRIBUTES: NOTSX
-PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b011]
+COMMENT   : on some execution paths loads all flags from VMCS. Always writes CF/PF/AF/ZF/SF/OF.
+FLAGS     : MAY [ id-mod vip-mod vif-mod ac-mod vm-tst rf-mod nt-mod iopl-tst iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
+PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b011] no_refining_prefix
 OPERANDS  :
 }
 {
 ICLASS    : VMXOFF
-CPL       : 3
+CPL       : 0
 CATEGORY  : VTX
 EXTENSION : VTX
 ATTRIBUTES: NOTSX
-PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b100]
+FLAGS     : MUST [ cf-mod zf-mod sf-mod of-mod af-mod pf-mod ]
+
+PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b100] no_refining_prefix
 OPERANDS  :
 }
 {
@@ -4760,6 +4797,7 @@ CATEGORY  : SYSTEM
 EXTENSION : BASE
 ISA_SET   : I286REAL
 ATTRIBUTES: RING0 NOTSX
+COMMENT   : 66 is OSZ; F2/F3 ignored
 PATTERN   : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()
 OPERANDS  : MEM0:r:s64 REG0=XED_REG_IDTR:w:SUPP
 PATTERN   : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()
@@ -4769,19 +4807,31 @@ OPERANDS  : MEM0:r:s REG0=XED_REG_IDTR:w:SUPP
 ICLASS    : MONITOR
 CPL       : 0
 CATEGORY  : MISC
-EXTENSION : SSE3
+EXTENSION : MONITOR
+ISA_SET   : MONITOR
 ATTRIBUTES: RING0 NOTSX
-PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b000]
+
+PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b000] no_refining_prefix not64 eamode32
 OPERANDS  : REG0=XED_REG_EAX:r:SUPP REG1=XED_REG_ECX:r:SUPP REG2=XED_REG_EDX:r:SUPP
+
+PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b000] no_refining_prefix not64 eamode16
+OPERANDS  : REG0=XED_REG_AX:r:SUPP REG1=XED_REG_ECX:r:SUPP REG2=XED_REG_EDX:r:SUPP
+
+PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b000] no_refining_prefix mode64 eamode64
+OPERANDS  : REG0=XED_REG_RAX:r:SUPP REG1=XED_REG_ECX:r:SUPP REG2=XED_REG_EDX:r:SUPP
+
+PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b000] no_refining_prefix mode64 eamode32
+OPERANDS  : REG0=XED_REG_RAX:r:SUPP REG1=XED_REG_ECX:r:SUPP REG2=XED_REG_EDX:r:SUPP
 }
 {
 ICLASS    : MWAIT
 CPL       : 0
 CATEGORY  : MISC
-EXTENSION : SSE3
+EXTENSION : MONITOR
+ISA_SET   : MONITOR
 ATTRIBUTES: RING0 NOTSX
-PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b001]
-OPERANDS  : REG0=XED_REG_EAX:rw:SUPP REG1=XED_REG_ECX:r:SUPP
+PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b001] no_refining_prefix
+OPERANDS  : REG0=XED_REG_EAX:r:SUPP REG1=XED_REG_ECX:r:SUPP
 }
 {
 ICLASS    : SIDT
@@ -4790,6 +4840,7 @@ CATEGORY  : SYSTEM
 EXTENSION : BASE
 ISA_SET   : I286REAL
 ATTRIBUTES: NOTSX
+COMMENT   : 66 is OSZ; F2/F3 ignored
 PATTERN   : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()
 OPERANDS  : MEM0:w:s REG0=XED_REG_IDTR:r:SUPP
 }
@@ -4799,6 +4850,7 @@ CPL       : 3
 CATEGORY  : SYSTEM
 EXTENSION : BASE
 ISA_SET   : I286REAL
+COMMENT   : 66 is OSZ; F2/F3 ignored
 PATTERN   : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()
 OPERANDS  : MEM0:w:s64 REG0=XED_REG_IDTR:r:SUPP
 }
@@ -6125,7 +6177,7 @@ EXTENSION : BASE
 ISA_SET   : I86
 PATTERN   : 0b0101_1 SRM[rrr] DF64()
 OPERANDS  : REG0=GPRv_SB():w REG1=XED_REG_STACKPOP:r:spw:SUPP
-IFORM     : POP_GPRv_51
+IFORM     : POP_GPRv_58
 }
 {
 ICLASS    : PUSHA
@@ -6172,9 +6224,9 @@ CATEGORY  : INTERRUPT
 EXTENSION : BASE
 ATTRIBUTES: EXCEPTION_BR
 ISA_SET   : I186
-PATTERN   : 0x62 mode16 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+PATTERN   : 0x62 not64 eosz16 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS  : REG0=GPRv_R():r MEM0:r:a16
-PATTERN   : 0x62 mode32 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+PATTERN   : 0x62 not64 eosz32 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS  : REG0=GPRv_R():r MEM0:r:a32
 }
 {
@@ -6460,9 +6512,9 @@ ISA_SET   : I86
 FLAGS     : READONLY [ of-tst ]
 ATTRIBUTES: MPX_PREFIX_ABLE
 PATTERN   : 0x70 mode64 FORCE64() BRANCH_HINT() BRDISP8()
-OPERANDS  : RELBR:r:b:i8 REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
 PATTERN   : 0x70 not64 BRANCH_HINT() BRDISP8()
-OPERANDS  : RELBR:r:b:i8 REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
 }
 {
 ICLASS    : JNO
@@ -6473,9 +6525,9 @@ ISA_SET   : I86
 FLAGS     : READONLY [ of-tst ]
 ATTRIBUTES: MPX_PREFIX_ABLE
 PATTERN   : 0x71 mode64 FORCE64() BRANCH_HINT() BRDISP8()
-OPERANDS  : RELBR:r:b:i8 REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
 PATTERN   : 0x71 not64 BRANCH_HINT() BRDISP8()
-OPERANDS  : RELBR:r:b:i8 REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
 }
 {
 ICLASS    : JB
@@ -6486,9 +6538,9 @@ ISA_SET   : I86
 FLAGS     : READONLY [ cf-tst ]
 ATTRIBUTES: MPX_PREFIX_ABLE
 PATTERN   : 0x72 mode64 FORCE64() BRANCH_HINT() BRDISP8()
-OPERANDS  : RELBR:r:b:i8 REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
 PATTERN   : 0x72 not64 BRANCH_HINT() BRDISP8()
-OPERANDS  : RELBR:r:b:i8 REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
 }
 {
 ICLASS    : JNB
@@ -6499,9 +6551,9 @@ ISA_SET   : I86
 FLAGS     : READONLY [ cf-tst ]
 ATTRIBUTES: MPX_PREFIX_ABLE
 PATTERN   : 0x73 mode64 FORCE64() BRANCH_HINT() BRDISP8()
-OPERANDS  : RELBR:r:b:i8 REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
 PATTERN   : 0x73 not64 BRANCH_HINT() BRDISP8()
-OPERANDS  : RELBR:r:b:i8 REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
 }
 {
 ICLASS    : JZ
@@ -6512,9 +6564,9 @@ ISA_SET   : I86
 FLAGS     : READONLY [ zf-tst ]
 ATTRIBUTES: MPX_PREFIX_ABLE
 PATTERN   : 0x74 mode64 FORCE64() BRANCH_HINT() BRDISP8()
-OPERANDS  : RELBR:r:b:i8 REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
 PATTERN   : 0x74 not64 BRANCH_HINT() BRDISP8()
-OPERANDS  : RELBR:r:b:i8 REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
 }
 {
 ICLASS    : JNZ
@@ -6525,9 +6577,9 @@ ISA_SET   : I86
 FLAGS     : READONLY [ zf-tst ]
 ATTRIBUTES: MPX_PREFIX_ABLE
 PATTERN   : 0x75 mode64 FORCE64() BRANCH_HINT() BRDISP8()
-OPERANDS  : RELBR:r:b:i8 REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
 PATTERN   : 0x75 not64  BRANCH_HINT() BRDISP8()
-OPERANDS  : RELBR:r:b:i8 REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
 }
 {
 ICLASS    : JBE
@@ -6538,9 +6590,9 @@ ISA_SET   : I86
 FLAGS     : READONLY [ cf-tst zf-tst ]
 ATTRIBUTES: MPX_PREFIX_ABLE
 PATTERN   : 0x76 mode64 FORCE64() BRANCH_HINT() BRDISP8()
-OPERANDS  : RELBR:r:b:i8  REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:b:i8  REG0=XED_REG_RIP:rw:SUPP
 PATTERN   : 0x76 not64  BRANCH_HINT() BRDISP8()
-OPERANDS  : RELBR:r:b:i8 REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
 }
 {
 ICLASS    : JNBE
@@ -6551,9 +6603,9 @@ ISA_SET   : I86
 FLAGS     : READONLY [ cf-tst zf-tst ]
 ATTRIBUTES: MPX_PREFIX_ABLE
 PATTERN   : 0x77 mode64 FORCE64() BRANCH_HINT() BRDISP8()
-OPERANDS  : RELBR:r:b:i8 REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
 PATTERN   : 0x77 not64  BRANCH_HINT() BRDISP8()
-OPERANDS  : RELBR:r:b:i8 REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
 }
 {
 ICLASS    : JS
@@ -6564,9 +6616,9 @@ ISA_SET   : I86
 FLAGS     : READONLY [ sf-tst ]
 ATTRIBUTES: MPX_PREFIX_ABLE
 PATTERN   : 0x78 mode64 FORCE64() BRANCH_HINT() BRDISP8()
-OPERANDS  : RELBR:r:b:i8 REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
 PATTERN   : 0x78 not64  BRANCH_HINT() BRDISP8()
-OPERANDS  : RELBR:r:b:i8 REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
 }
 {
 ICLASS    : JNS
@@ -6577,9 +6629,9 @@ ISA_SET   : I86
 FLAGS     : READONLY [ sf-tst ]
 ATTRIBUTES: MPX_PREFIX_ABLE
 PATTERN   : 0x79 mode64 FORCE64() BRANCH_HINT() BRDISP8()
-OPERANDS  : RELBR:r:b:i8 REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
 PATTERN   : 0x79 not64  BRANCH_HINT() BRDISP8()
-OPERANDS  : RELBR:r:b:i8 REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
 }
 {
 ICLASS    : JP
@@ -6590,9 +6642,9 @@ ISA_SET   : I86
 FLAGS     : READONLY [ pf-tst ]
 ATTRIBUTES: MPX_PREFIX_ABLE
 PATTERN   : 0x7A mode64 FORCE64() BRANCH_HINT() BRDISP8()
-OPERANDS  : RELBR:r:b:i8 REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
 PATTERN   : 0x7A not64  BRANCH_HINT() BRDISP8()
-OPERANDS  : RELBR:r:b:i8 REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
 }
 {
 ICLASS    : JNP
@@ -6603,9 +6655,9 @@ ISA_SET   : I86
 FLAGS     : READONLY [ pf-tst ]
 ATTRIBUTES: MPX_PREFIX_ABLE
 PATTERN   : 0x7B mode64 FORCE64() BRANCH_HINT() BRDISP8()
-OPERANDS  : RELBR:r:b:i8 REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
 PATTERN   : 0x7B not64  BRANCH_HINT() BRDISP8()
-OPERANDS  : RELBR:r:b:i8 REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
 }
 {
 ICLASS    : JL
@@ -6616,9 +6668,9 @@ ISA_SET   : I86
 FLAGS     : READONLY [ sf-tst of-tst ]
 ATTRIBUTES: MPX_PREFIX_ABLE
 PATTERN   : 0x7C mode64 FORCE64() BRANCH_HINT() BRDISP8()
-OPERANDS  : RELBR:r:b:i8 REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
 PATTERN   : 0x7C not64 BRANCH_HINT() BRDISP8()
-OPERANDS  : RELBR:r:b:i8 REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
 }
 {
 ICLASS    : JNL
@@ -6629,9 +6681,9 @@ ISA_SET   : I86
 FLAGS     : READONLY [ sf-tst of-tst ]
 ATTRIBUTES: MPX_PREFIX_ABLE
 PATTERN   : 0x7D mode64 FORCE64() BRANCH_HINT() BRDISP8()
-OPERANDS  : RELBR:r:b:i8 REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
 PATTERN   : 0x7D not64 BRANCH_HINT() BRDISP8()
-OPERANDS  : RELBR:r:b:i8 REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
 }
 {
 ICLASS    : JLE
@@ -6642,9 +6694,9 @@ ISA_SET   : I86
 FLAGS     : READONLY [ sf-tst of-tst zf-tst ]
 ATTRIBUTES: MPX_PREFIX_ABLE
 PATTERN   : 0x7E mode64 FORCE64() BRANCH_HINT() BRDISP8()
-OPERANDS  : RELBR:r:b:i8 REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
 PATTERN   : 0x7E not64 BRANCH_HINT() BRDISP8()
-OPERANDS  : RELBR:r:b:i8 REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
 }
 {
 ICLASS    : JNLE
@@ -6655,9 +6707,9 @@ ISA_SET   : I86
 FLAGS     : READONLY [ sf-tst of-tst zf-tst ]
 ATTRIBUTES: MPX_PREFIX_ABLE
 PATTERN   : 0x7F mode64 FORCE64() BRANCH_HINT() BRDISP8()
-OPERANDS  : RELBR:r:b:i8 REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
 PATTERN   : 0x7F not64 BRANCH_HINT() BRDISP8()
-OPERANDS  : RELBR:r:b:i8 REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
 }
 {
 ICLASS    : TEST
@@ -6857,9 +6909,10 @@ CATEGORY  : DATAXFER
 EXTENSION : BASE
 ISA_SET   : I86
 ATTRIBUTES: NOTSX
-COMMENT   : MOV to SS Inhibits all interrupts until after next instr
+COMMENT   : MOV to SS Inhibits all interrupts until after next instr. Cannot write to CS
 PATTERN   : 0x8E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=SEG():w MEM0:r:w
+OPERANDS  : REG0=SEG_MOV():w MEM0:r:w
+IFORM     : MOV_SEG_MEMw
 }
 {
 ICLASS    : MOV
@@ -6868,8 +6921,10 @@ CATEGORY  : DATAXFER
 EXTENSION : BASE
 ISA_SET   : I86
 ATTRIBUTES: NOTSX
+COMMENT   : MOV to SS Inhibits all interrupts until after next instr. Cannot write to CS
 PATTERN   : 0x8E MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=SEG():w REG1=GPR16_B():r
+OPERANDS  : REG0=SEG_MOV():w REG1=GPR16_B():r
+IFORM     : MOV_SEG_GPR16
 }
 
 
@@ -6982,15 +7037,34 @@ DISASM_INTEL    : call far
 DISASM_ATTSV    : lcall
 CPL       : 3
 CATEGORY  : CALL
-ATTRIBUTES : FAR_XFER NOTSX
+ATTRIBUTES : FAR_XFER NOTSX INDIRECT_BRANCH
 EXTENSION : BASE
 ISA_SET   : I86
+
 COMMENT   : same privilege level does 2 pushes (spw2). inter-privilege level does 4 (not represented)
+
 PATTERN   : 0xFF MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()
 OPERANDS  : MEM0:r:p2 REG0=XED_REG_STACKPUSH:w:spw2:SUPP REG1=rIP():w:SUPP
+}
+
+
+{
+ICLASS    : CALL_FAR
+DISASM_INTEL    : call far
+DISASM_ATTSV    : lcall
+CPL       : 3
+CATEGORY  : CALL
+ATTRIBUTES : FAR_XFER NOTSX
+EXTENSION : BASE
+ISA_SET   : I86
+
+COMMENT   : same privilege level does 2 pushes (spw2). inter-privilege level does 4 (not represented)
+
 PATTERN   : 0x9A not64 BRDISPz() UIMM16()
-OPERANDS  : PTR:r:p IMM0:r:w REG0=XED_REG_STACKPUSH:w:spw2:SUPP REG1=rIP():w:SUPP
+OPERANDS  : PTR:r:p IMM0:r:w REG0=XED_REG_STACKPUSH:w:spw2:SUPP REG1=XED_REG_EIP:w:SUPP
 }
+
+
 {
 ICLASS    : FWAIT
 CPL       : 3
@@ -7816,7 +7890,7 @@ ISA_SET   : I86
 PATTERN   : 0b1011_0 SRM[rrr] UIMM8()
 OPERANDS  : REG0=GPR8_SB():w IMM0:r:b
 # i had to come up with a partial nibble name
-IFORM     : MOV_GPR8_IMMb_D0
+IFORM     : MOV_GPR8_IMMb_B0
 }
 {
 ICLASS    : MOV
@@ -7947,7 +8021,7 @@ EXTENSION : BASE
 ISA_SET   : I86
 FLAGS     : MUST [ ac-mod vm-tst vm-mod rf-0 nt-mod iopl-tst of-tst if-mod tf-mod ]
 PATTERN   : 0xCE not64
-OPERANDS  : REG0=rIP():w:SUPP
+OPERANDS  : REG0=XED_REG_EIP:w:SUPP
 }
 {
 ICLASS    : IRET
@@ -7958,7 +8032,7 @@ EXTENSION : BASE
 ISA_SET   : I86
 FLAGS     : MUST [ id-pop vip-pop vif-pop ac-pop vm-tst vm-pop rf-pop nt-tst nt-pop iopl-tst iopl-pop of-pop df-pop if-pop tf-pop sf-pop zf-pop af-pop pf-pop cf-pop ]
 PATTERN   : 0xCF EOSZ=1
-OPERANDS  : REG0=XED_REG_STACKPOP:r:spw3:SUPP REG1=rIP():w:SUPP
+OPERANDS  : REG0=XED_REG_STACKPOP:r:spw5:SUPP REG1=rIP():w:SUPP
 }
 {
 ICLASS    : IRETD
@@ -7969,7 +8043,7 @@ EXTENSION : BASE
 ISA_SET   : I386
 FLAGS     : MUST [ id-pop vip-pop vif-pop ac-pop vm-tst vm-pop rf-pop nt-tst nt-pop iopl-tst iopl-pop of-pop df-pop if-pop tf-pop sf-pop zf-pop af-pop pf-pop cf-pop ]
 PATTERN   : 0xCF EOSZ=2
-OPERANDS  : REG0=XED_REG_STACKPOP:r:spw3:SUPP REG1=rIP():w:SUPP
+OPERANDS  : REG0=XED_REG_STACKPOP:r:spw5:SUPP REG1=rIP():w:SUPP
 }
 {
 ICLASS    : IRETQ
@@ -7980,7 +8054,7 @@ EXTENSION : LONGMODE
 FLAGS     : MUST [ id-pop vip-pop vif-pop ac-pop vm-tst vm-pop rf-pop nt-tst nt-pop iopl-tst iopl-pop of-pop df-pop if-pop tf-pop sf-pop zf-pop af-pop pf-pop cf-pop ]
 PATTERN   : 0xCF EOSZ=3 mode64
 # FIXME: This is only an approximate width for the stack pops
-OPERANDS  : REG0=XED_REG_STACKPOP:r:spw3:SUPP REG1=rIP():w:SUPP
+OPERANDS  : REG0=XED_REG_STACKPOP:r:spw5:SUPP REG1=XED_REG_RIP:w:SUPP
 }
 {
 ICLASS    : AAM
@@ -7989,7 +8063,7 @@ CATEGORY  : DECIMAL
 EXTENSION : BASE
 ISA_SET   : I86
 FLAGS     : MUST [ of-u sf-mod zf-mod af-u pf-mod cf-u ]
-PATTERN   : 0xD4 not64 SIMM8()
+PATTERN   : 0xD4 not64 UIMM8()
 OPERANDS  : IMM0:r:b:i8 REG0=XED_REG_AL:rw:SUPP REG1=XED_REG_AH:w:SUPP
 }
 {
@@ -7999,7 +8073,7 @@ CATEGORY  : DECIMAL
 EXTENSION : BASE
 ISA_SET   : I86
 FLAGS     : MUST [ of-u sf-mod zf-mod af-u pf-mod cf-u ]
-PATTERN   : 0xD5 not64 SIMM8()
+PATTERN   : 0xD5 not64 UIMM8()
 OPERANDS  : IMM0:r:b:i8 REG0=XED_REG_AL:rw:SUPP REG1=XED_REG_AH:rw:SUPP
 }
 {
@@ -8039,7 +8113,7 @@ OPERANDS  : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP
 PATTERN   : 0xE0 MODEP5=0         DF64() BRDISP8() IMMUNE66_LOOP64()
 OPERANDS  : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP
 
-# REPNE WITH A E1 (LOOPE) makes a LOOPNE on P5-class machines UNDOC
+COMMENT   : REPNE WITH A E1 (LOOPE) makes a LOOPNE on P5-class machines UNDOC
 PATTERN   : 0xE1 MODEP5=1 REP=2  DF64() BRDISP8() IMMUNE66_LOOP64()
 OPERANDS  : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP
 }
@@ -8057,7 +8131,7 @@ OPERANDS  : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP
 PATTERN   : 0xE1 MODEP5=0       DF64() BRDISP8() IMMUNE66_LOOP64()
 OPERANDS  : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP
 
-# REPE WITH A E0 (LOOPNE) makes a LOOPE on P5-class machines UNDOC
+COMMENT   : REPE WITH A E0 (LOOPNE) makes a LOOPE on P5-class machines UNDOC
 PATTERN   : 0xE0 MODEP5=1 REP=3  DF64() BRDISP8() IMMUNE66_LOOP64()
 OPERANDS  : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP
 }
@@ -8082,7 +8156,7 @@ CATEGORY  : COND_BR
 EXTENSION : BASE
 ISA_SET   : I386
 PATTERN   : 0xE3 eamode16 BRDISP8()
-OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_CX:r:SUPP REG1=rIP():rw:SUPP
+OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_CX:r:SUPP REG1=XED_REG_IP:rw:SUPP
 }
 {
 ICLASS    : JECXZ
@@ -8091,8 +8165,10 @@ CPL       : 3
 CATEGORY  : COND_BR
 EXTENSION : BASE
 ISA_SET   : I386
-PATTERN   : 0xE3 eamode32 BRDISP8()
-OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_ECX:r:SUPP REG1=rIP():rw:SUPP
+PATTERN   : 0xE3 eamode32 not64 BRDISP8()
+OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_ECX:r:SUPP REG1=XED_REG_EIP:rw:SUPP
+PATTERN   : 0xE3 eamode32 mode64 BRDISP8() FORCE64()
+OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_ECX:r:SUPP REG1=XED_REG_RIP:rw:SUPP
 }
 {
 ICLASS    : JRCXZ
@@ -8102,7 +8178,7 @@ CATEGORY  : COND_BR
 EXTENSION : BASE
 ISA_SET   : LONGMODE
 PATTERN   : 0xE3 eamode64 BRDISP8() FORCE64()
-OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_RCX:r:SUPP REG1=rIP():rw:SUPP
+OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_RCX:r:SUPP REG1=XED_REG_RIP:rw:SUPP
 }
 
 {
@@ -8113,7 +8189,7 @@ EXTENSION : BASE
 ISA_SET   : I86
 ATTRIBUTES : BYTEOP NOTSX
 FLAGS     : READONLY [ iopl-tst ]
-PATTERN   : 0xE4 UIMM8() IMMUNE_REXW()
+PATTERN   : 0xE4 UIMM8()
 OPERANDS  : REG0=XED_REG_AL:w:IMPL IMM0:r:b
 }
 {
@@ -8136,7 +8212,7 @@ EXTENSION : BASE
 ISA_SET   : I86
 ATTRIBUTES: NOTSX BYTEOP
 FLAGS     : READONLY [ iopl-tst ]
-PATTERN   : 0xE6 UIMM8() IMMUNE_REXW()
+PATTERN   : 0xE6 UIMM8()
 OPERANDS  : IMM0:r:b REG0=XED_REG_AL:r:IMPL
 }
 
@@ -8160,9 +8236,9 @@ EXTENSION : BASE
 ISA_SET   : I86
 ATTRIBUTES: MPX_PREFIX_ABLE
 PATTERN   : 0xE9 not64 BRDISPz()
-OPERANDS  : RELBR:r:z REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
 PATTERN   : 0xE9 mode64 FORCE64() BRDISP32()
-OPERANDS  : RELBR:r:d REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
 }
 {
 ICLASS    : JMP_FAR
@@ -8174,7 +8250,7 @@ ATTRIBUTES : FAR_XFER NOTSX
 EXTENSION : BASE
 ISA_SET   : I86
 PATTERN   : 0xEA not64 BRDISPz() UIMM16()
-OPERANDS  : PTR:r:p IMM0:r:w REG0=rIP():w:SUPP
+OPERANDS  : PTR:r:p IMM0:r:w REG0=XED_REG_EIP:w:SUPP
 }
 {
 ICLASS    : JMP
@@ -8182,8 +8258,10 @@ CPL       : 3
 CATEGORY  : UNCOND_BR
 EXTENSION : BASE
 ISA_SET   : I86
-PATTERN   : 0xEB DF64() BRDISP8()
-OPERANDS  : RELBR:r:b:i8 REG0=rIP():rw:SUPP
+PATTERN   : 0xEB not64 BRDISP8()
+OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
+PATTERN   : 0xEB mode64 FORCE64() BRDISP8()
+OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
 }
 {
 ICLASS    : IN
@@ -8193,7 +8271,7 @@ EXTENSION : BASE
 ISA_SET   : I86
 ATTRIBUTES : BYTEOP
 FLAGS     : READONLY [ iopl-tst ]
-PATTERN   : 0xEC IMMUNE_REXW()
+PATTERN   : 0xEC
 OPERANDS  : REG0=XED_REG_AL:w:IMPL REG1=XED_REG_DX:r:IMPL
 }
 {
@@ -8214,7 +8292,7 @@ EXTENSION : BASE
 ISA_SET   : I86
 ATTRIBUTES : BYTEOP
 FLAGS     : READONLY [ iopl-tst ]
-PATTERN   : 0xEE IMMUNE_REXW()
+PATTERN   : 0xEE
 OPERANDS  : REG0=XED_REG_DX:r:IMPL REG1=XED_REG_AL:r:IMPL
 }
 {
@@ -8234,7 +8312,7 @@ CATEGORY  : INTERRUPT
 EXTENSION : BASE
 ISA_SET   : I86
 PATTERN   : 0xF1
-OPERANDS  :
+OPERANDS  : REG0=rIP():w:SUPP
 COMMENT   : UNDOC by Intel, but in AMD's opcode map
 }
 {
@@ -8359,7 +8437,7 @@ EXTENSION : LONGMODE
 ISA_SET   : LONGMODE
 FLAGS     : MUST [ id-mod vip-mod vif-mod ac-mod vm-0 rf-0 nt-mod iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
 PATTERN   : 0x0F 0x05 mode64 FORCE64()
-OPERANDS  : REG0=rIP():w:SUPP
+OPERANDS  : REG0=XED_REG_RIP:w:SUPP REG1=XED_REG_RCX:w:SUPP REG2=XED_REG_R11:w:SUPP
 COMMENT   : 32B VERSION IS ONLY SUPPORTED ON AMD
 }
 {
@@ -8381,9 +8459,9 @@ EXTENSION : LONGMODE
 ISA_SET   : LONGMODE
 FLAGS     : MUST [ id-mod vip-mod vif-mod ac-mod rf-0 nt-mod iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
 PATTERN   : 0x0F 0x07 mode64 eosz64
-OPERANDS  : REG0=XED_REG_RIP:w:SUPP
-PATTERN   : 0x0F 0x07 mode64 eosz32
-OPERANDS  : REG0=XED_REG_EIP:w:SUPP
+OPERANDS  : REG0=XED_REG_RIP:w:SUPP  REG1=XED_REG_RCX:r:SUPP  REG2=XED_REG_R11:r:SUPP
+PATTERN   : 0x0F 0x07 mode64 eosznot64
+OPERANDS  : REG0=XED_REG_EIP:w:SUPP  REG1=XED_REG_ECX:r:SUPP
 COMMENT   : 32B VERSION IS ONLY SUPPORTED ON AMD
 }
 {
@@ -8414,7 +8492,7 @@ CATEGORY  : DATAXFER
 EXTENSION : SSE
 EXCEPTIONS: SSE_TYPE_5
 ATTRIBUTES :
-PATTERN   : 0x0F 0x13 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  no_refining_prefix MODRM()
+PATTERN   : 0x0F 0x13 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS  : MEM0:w:q:f32 REG0=XMM_R():r:ps:f32
 }
 {
@@ -8449,7 +8527,7 @@ CATEGORY  : DATAXFER
 EXTENSION : SSE
 EXCEPTIONS: SSE_TYPE_5
 ATTRIBUTES :
-PATTERN   : 0x0F 0x17 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  no_refining_prefix MODRM()
+PATTERN   : 0x0F 0x17 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS  : MEM0:w:q:f32 REG0=XMM_R():r:ps:f32
 }
 {
@@ -8643,10 +8721,10 @@ EXTENSION : BASE
 ISA_SET   : I86
 ATTRIBUTES : RING0 NOTSX
 COMMENT   :  MODRM.MOD=00/01/10 aliased to MODRM.MOD=11
-PATTERN   : 0x0F 0x23 MOD[mm] REG[rrr] RM[nnn] DF64() not64
+PATTERN   : 0x0F 0x23 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() not64
 OPERANDS  : REG0=DR_R():w REG1=GPR32_B():r
 
-PATTERN   : 0x0F 0x23 MOD[mm] REG[rrr] RM[nnn] DF64() mode64
+PATTERN   : 0x0F 0x23 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() mode64
 OPERANDS  : REG0=DR_R():w REG1=GPR64_B():r
 }
 
@@ -8659,10 +8737,10 @@ EXTENSION : BASE
 ISA_SET   : I86
 ATTRIBUTES : RING0
 COMMENT   :  MODRM.MOD=00/01/10 aliased to MODRM.MOD=11
-PATTERN   : 0x0F 0x21 MOD[mm] REG[rrr] RM[nnn] DF64() not64
+PATTERN   : 0x0F 0x21 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() not64
 OPERANDS  : REG0=GPR32_B():w REG1=DR_R():r
 
-PATTERN   : 0x0F 0x21 MOD[mm] REG[rrr] RM[nnn] DF64() mode64
+PATTERN   : 0x0F 0x21 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() mode64
 OPERANDS  : REG0=GPR64_B():w REG1=DR_R():r
 }
 
@@ -8713,8 +8791,10 @@ EXTENSION : BASE
 ISA_SET   : PPRO
 ATTRIBUTES: PROTECTED_MODE NOTSX
 FLAGS     : MUST [ vm-0 rf-0 if-0 ]
-PATTERN   : 0x0F 0x34
-OPERANDS  : REG0=rIP():w:SUPP
+PATTERN   : 0x0F 0x34 not64
+OPERANDS  : REG0=XED_REG_EIP:w:SUPP REG1=XED_REG_ESP:w:SUPP
+PATTERN   : 0x0F 0x34 mode64
+OPERANDS  : REG0=XED_REG_RIP:w:SUPP REG1=XED_REG_RSP:w:SUPP
 COMMENT   : AMD does not document support for this in 64b mode
 }
 {
@@ -8724,8 +8804,10 @@ CATEGORY  : SYSRET
 EXTENSION : BASE
 ISA_SET   : PPRO
 ATTRIBUTES: PROTECTED_MODE RING0 NOTSX
-PATTERN   : 0x0F 0x35
-OPERANDS  : REG0=rIP():w:SUPP
+PATTERN   : 0x0F 0x35 not64
+OPERANDS  : REG0=XED_REG_EIP:w:SUPP  REG1=XED_REG_ESP:w:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_EDX:r:SUPP
+PATTERN   : 0x0F 0x35 mode64
+OPERANDS  : REG0=XED_REG_RIP:w:SUPP  REG1=XED_REG_RSP:w:SUPP REG2=XED_REG_RCX:r:SUPP REG3=XED_REG_RDX:r:SUPP
 COMMENT   : AMD does not document support for this in 64b mode
 }
 {
@@ -8733,7 +8815,7 @@ ICLASS    : CMOVO
 CPL       : 3
 CATEGORY  : CMOV
 EXTENSION : BASE
-ISA_SET   : PPRO
+ISA_SET   : CMOV
 FLAGS     : READONLY [ of-tst ]
 PATTERN   : 0x0F 0x40 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS  : REG0=GPRv_R():cw MEM0:r:v
@@ -8745,7 +8827,7 @@ ICLASS    : CMOVNO
 CPL       : 3
 CATEGORY  : CMOV
 EXTENSION : BASE
-ISA_SET   : PPRO
+ISA_SET   : CMOV
 FLAGS     : READONLY [ of-tst ]
 PATTERN   : 0x0F 0x41 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS  : REG0=GPRv_R():cw MEM0:r:v
@@ -8757,7 +8839,7 @@ ICLASS    : CMOVB
 CPL       : 3
 CATEGORY  : CMOV
 EXTENSION : BASE
-ISA_SET   : PPRO
+ISA_SET   : CMOV
 FLAGS     : READONLY [ cf-tst ]
 PATTERN   : 0x0F 0x42 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS  : REG0=GPRv_R():cw MEM0:r:v
@@ -8769,7 +8851,7 @@ ICLASS    : CMOVNB
 CPL       : 3
 CATEGORY  : CMOV
 EXTENSION : BASE
-ISA_SET   : PPRO
+ISA_SET   : CMOV
 FLAGS     : READONLY [ cf-tst ]
 PATTERN   : 0x0F 0x43 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS  : REG0=GPRv_R():cw MEM0:r:v
@@ -8781,7 +8863,7 @@ ICLASS    : CMOVZ
 CPL       : 3
 CATEGORY  : CMOV
 EXTENSION : BASE
-ISA_SET   : PPRO
+ISA_SET   : CMOV
 FLAGS     : READONLY [ zf-tst ]
 PATTERN   : 0x0F 0x44 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS  : REG0=GPRv_R():cw MEM0:r:v
@@ -8793,7 +8875,7 @@ ICLASS    : CMOVNZ
 CPL       : 3
 CATEGORY  : CMOV
 EXTENSION : BASE
-ISA_SET   : PPRO
+ISA_SET   : CMOV
 FLAGS     : READONLY [ zf-tst ]
 PATTERN   : 0x0F 0x45 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS  : REG0=GPRv_R():cw MEM0:r:v
@@ -8805,7 +8887,7 @@ ICLASS    : CMOVBE
 CPL       : 3
 CATEGORY  : CMOV
 EXTENSION : BASE
-ISA_SET   : PPRO
+ISA_SET   : CMOV
 FLAGS     : READONLY [ cf-tst zf-tst ]
 PATTERN   : 0x0F 0x46 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS  : REG0=GPRv_R():cw MEM0:r:v
@@ -8817,7 +8899,7 @@ ICLASS    : CMOVNBE
 CPL       : 3
 CATEGORY  : CMOV
 EXTENSION : BASE
-ISA_SET   : PPRO
+ISA_SET   : CMOV
 FLAGS     : READONLY [ cf-tst zf-tst ]
 PATTERN   : 0x0F 0x47 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS  : REG0=GPRv_R():cw MEM0:r:v
@@ -8877,9 +8959,9 @@ EXTENSION : SSE
 EXCEPTIONS: SSE_TYPE_4
 ATTRIBUTES :  REQUIRES_ALIGNMENT
 PATTERN   : 0x0F 0x54 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
-OPERANDS  : REG0=XMM_R():rw:ps MEM0:r:ps
+OPERANDS  : REG0=XMM_R():rw:xud MEM0:r:xud
 PATTERN   : 0x0F 0x54 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps
+OPERANDS  : REG0=XMM_R():rw:xud REG1=XMM_B():r:xud
 }
 {
 ICLASS    : ANDNPS
@@ -8889,9 +8971,9 @@ EXTENSION : SSE
 EXCEPTIONS: SSE_TYPE_4
 ATTRIBUTES :  REQUIRES_ALIGNMENT
 PATTERN   : 0x0F 0x55 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
-OPERANDS  : REG0=XMM_R():rw:ps MEM0:r:ps
+OPERANDS  : REG0=XMM_R():rw:xud MEM0:r:xud
 PATTERN   : 0x0F 0x55 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps
+OPERANDS  : REG0=XMM_R():rw:xud REG1=XMM_B():r:xud
 }
 {
 ICLASS    : ORPS
@@ -8901,9 +8983,9 @@ EXTENSION : SSE
 EXCEPTIONS: SSE_TYPE_4
 ATTRIBUTES :  REQUIRES_ALIGNMENT
 PATTERN   : 0x0F 0x56 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
-OPERANDS  : REG0=XMM_R():rw:ps MEM0:r:ps
+OPERANDS  : REG0=XMM_R():rw:xud MEM0:r:xud
 PATTERN   : 0x0F 0x56 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps
+OPERANDS  : REG0=XMM_R():rw:xud REG1=XMM_B():r:xud
 }
 {
 ICLASS    : XORPS
@@ -8913,9 +8995,9 @@ EXTENSION : SSE
 EXCEPTIONS: SSE_TYPE_4
 ATTRIBUTES :  REQUIRES_ALIGNMENT
 PATTERN   : 0x0F 0x57 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
-OPERANDS  : REG0=XMM_R():rw:ps MEM0:r:ps
+OPERANDS  : REG0=XMM_R():rw:xud MEM0:r:xud
 PATTERN   : 0x0F 0x57 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps
+OPERANDS  : REG0=XMM_R():rw:xud REG1=XMM_B():r:xud
 }
 {
 ICLASS    : SQRTSS
@@ -8982,9 +9064,9 @@ EXTENSION : SSE2
 EXCEPTIONS: SSE_TYPE_4
 ATTRIBUTES :  REQUIRES_ALIGNMENT
 PATTERN   : 0x0F 0x54 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
-OPERANDS  : REG0=XMM_R():rw:pd MEM0:r:pd
+OPERANDS  : REG0=XMM_R():rw:xuq MEM0:r:xuq
 PATTERN   : 0x0F 0x54 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
-OPERANDS  : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd
+OPERANDS  : REG0=XMM_R():rw:xuq REG1=XMM_B():r:xuq
 }
 {
 ICLASS    : ANDNPD
@@ -8994,9 +9076,9 @@ EXTENSION : SSE2
 EXCEPTIONS: SSE_TYPE_4
 ATTRIBUTES :  REQUIRES_ALIGNMENT
 PATTERN   : 0x0F 0x55 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
-OPERANDS  : REG0=XMM_R():rw:pd MEM0:r:pd
+OPERANDS  : REG0=XMM_R():rw:xuq MEM0:r:xuq
 PATTERN   : 0x0F 0x55 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
-OPERANDS  : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd
+OPERANDS  : REG0=XMM_R():rw:xuq REG1=XMM_B():r:xuq
 }
 {
 ICLASS    : ORPD
@@ -9006,9 +9088,9 @@ EXTENSION : SSE2
 EXCEPTIONS: SSE_TYPE_4
 ATTRIBUTES :  REQUIRES_ALIGNMENT
 PATTERN   : 0x0F 0x56 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
-OPERANDS  : REG0=XMM_R():rw:pd MEM0:r:pd
+OPERANDS  : REG0=XMM_R():rw:xuq MEM0:r:xuq
 PATTERN   : 0x0F 0x56 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
-OPERANDS  : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd
+OPERANDS  : REG0=XMM_R():rw:xuq REG1=XMM_B():r:xuq
 }
 {
 ICLASS    : XORPD
@@ -9018,9 +9100,9 @@ EXTENSION : SSE2
 EXCEPTIONS: SSE_TYPE_4
 ATTRIBUTES :  REQUIRES_ALIGNMENT
 PATTERN   : 0x0F 0x57 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
-OPERANDS  : REG0=XMM_R():rw:pd MEM0:r:pd
+OPERANDS  : REG0=XMM_R():rw:xuq MEM0:r:xuq
 PATTERN   : 0x0F 0x57 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
-OPERANDS  : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd
+OPERANDS  : REG0=XMM_R():rw:xuq REG1=XMM_B():r:xuq
 }
 {
 ICLASS    : SQRTSD
@@ -9421,7 +9503,7 @@ FLAGS     : READONLY [ of-tst ]
 ATTRIBUTES: MPX_PREFIX_ABLE
 
 PATTERN   : 0x0F 0x80 mode64 FORCE64() BRANCH_HINT() BRDISP32()
-OPERANDS  : RELBR:r:d REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
 }
 {
 ICLASS    : JO
@@ -9432,7 +9514,7 @@ ISA_SET   : I86
 FLAGS     : READONLY [ of-tst ]
 ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
 PATTERN   : 0x0F 0x80 not64 BRANCH_HINT() BRDISPz()
-OPERANDS  : RELBR:r:z REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
 }
 
 
@@ -9445,7 +9527,7 @@ ISA_SET   : I86
 FLAGS     : READONLY [ of-tst ]
 ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
 PATTERN   : 0x0F 0x81 not64 BRANCH_HINT() BRDISPz()
-OPERANDS  : RELBR:r:z REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
 }
 {
 ICLASS    : JNO
@@ -9457,7 +9539,7 @@ FLAGS     : READONLY [ of-tst ]
 ATTRIBUTES: MPX_PREFIX_ABLE
 
 PATTERN   : 0x0F 0x81 mode64 FORCE64() BRANCH_HINT() BRDISP32()
-OPERANDS  : RELBR:r:d REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
 }
 
 
@@ -9470,7 +9552,7 @@ ISA_SET   : I86
 FLAGS     : READONLY [ cf-tst ]
 ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
 PATTERN   : 0x0F 0x82 not64 BRANCH_HINT() BRDISPz()
-OPERANDS  : RELBR:r:z REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
 }
 {
 ICLASS    : JB
@@ -9482,7 +9564,7 @@ FLAGS     : READONLY [ cf-tst ]
 ATTRIBUTES: MPX_PREFIX_ABLE
 
 PATTERN   : 0x0F 0x82 mode64 FORCE64() BRANCH_HINT() BRDISP32()
-OPERANDS  : RELBR:r:d REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
 }
 
 
@@ -9496,7 +9578,7 @@ ISA_SET   : I86
 FLAGS     : READONLY [ cf-tst ]
 ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
 PATTERN   : 0x0F 0x83 not64 BRANCH_HINT() BRDISPz()
-OPERANDS  : RELBR:r:z REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
 
 }
 {
@@ -9509,7 +9591,7 @@ FLAGS     : READONLY [ cf-tst ]
 ATTRIBUTES: MPX_PREFIX_ABLE
 
 PATTERN   : 0x0F 0x83 mode64 FORCE64() BRANCH_HINT() BRDISP32()
-OPERANDS  : RELBR:r:d REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
 }
 
 
@@ -9522,7 +9604,7 @@ ISA_SET   : I86
 FLAGS     : READONLY [ zf-tst ]
 ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
 PATTERN   : 0x0F 0x84 not64 BRANCH_HINT() BRDISPz()
-OPERANDS  : RELBR:r:z REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
 }
 {
 ICLASS    : JZ
@@ -9534,7 +9616,7 @@ FLAGS     : READONLY [ zf-tst ]
 ATTRIBUTES: MPX_PREFIX_ABLE
 
 PATTERN   : 0x0F 0x84 mode64 FORCE64() BRANCH_HINT() BRDISP32()
-OPERANDS  : RELBR:r:d REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
 }
 
 
@@ -9547,7 +9629,7 @@ ISA_SET   : I86
 FLAGS     : READONLY [ zf-tst ]
 ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
 PATTERN   : 0x0F 0x85 not64 BRANCH_HINT() BRDISPz()
-OPERANDS  : RELBR:r:z REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
 
 }
 {
@@ -9560,7 +9642,7 @@ FLAGS     : READONLY [ zf-tst ]
 ATTRIBUTES: MPX_PREFIX_ABLE
 
 PATTERN   : 0x0F 0x85 mode64 FORCE64() BRANCH_HINT() BRDISP32()
-OPERANDS  : RELBR:r:d REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
 }
 
 
@@ -9574,7 +9656,7 @@ ISA_SET   : I86
 FLAGS     : READONLY [ cf-tst zf-tst ]
 ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
 PATTERN   : 0x0F 0x86 not64 BRANCH_HINT() BRDISPz()
-OPERANDS  : RELBR:r:z REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
 }
 {
 ICLASS    : JBE
@@ -9586,7 +9668,7 @@ FLAGS     : READONLY [ cf-tst zf-tst ]
 ATTRIBUTES: MPX_PREFIX_ABLE
 
 PATTERN   : 0x0F 0x86 mode64 FORCE64() BRANCH_HINT() BRDISP32()
-OPERANDS  : RELBR:r:d REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
 }
 
 
@@ -9600,7 +9682,7 @@ ISA_SET   : I86
 FLAGS     : READONLY [ cf-tst zf-tst ]
 ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
 PATTERN   : 0x0F 0x87 not64 BRANCH_HINT() BRDISPz()
-OPERANDS  : RELBR:r:z REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
 }
 {
 ICLASS    : JNBE
@@ -9612,7 +9694,7 @@ FLAGS     : READONLY [ cf-tst zf-tst ]
 ATTRIBUTES: MPX_PREFIX_ABLE
 
 PATTERN   : 0x0F 0x87 mode64 FORCE64() BRANCH_HINT() BRDISP32()
-OPERANDS  : RELBR:r:d REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
 }
 
 
@@ -10008,7 +10090,7 @@ ICLASS    : MOVNTI
 CPL       : 3
 CATEGORY  : DATAXFER
 EXTENSION : SSE2
-ATTRIBUTES : IGNORES_OSFXSR NOTSX
+ATTRIBUTES : IGNORES_OSFXSR NOTSX NONTEMPORAL
 PATTERN   : 0x0F 0xC3 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  EOSZ!=3 MODRM()
 OPERANDS  : MEM0:w:d REG0=GPR32_R():r
 PATTERN   : 0x0F 0xC3 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  EOSZ=3 MODRM()
@@ -10193,6 +10275,7 @@ ATTRIBUTES: NOTSX
 CPL       : 3
 CATEGORY  : MMX
 EXTENSION : SSE2
+ISA_SET   : SSE2MMX
 PATTERN   : 0x0F 0xD4 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
 OPERANDS  : REG0=MMX_R():rw:q:u64 MEM0:r:q:u64
 PATTERN   : 0x0F 0xD4 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
@@ -10500,7 +10583,7 @@ OPERANDS  : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q:i16
 {
 ICLASS    : MOVNTQ
 EXCEPTIONS: mmx-nofp2
-ATTRIBUTES: NOTSX
+ATTRIBUTES: NOTSX NONTEMPORAL
 CPL       : 3
 CATEGORY  : DATAXFER
 EXTENSION : MMX
@@ -10620,7 +10703,7 @@ OPERANDS  : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:pd:f64
 }
 {
 ICLASS    : MOVNTDQ
-ATTRIBUTES: REQUIRES_ALIGNMENT NOTSX
+ATTRIBUTES: REQUIRES_ALIGNMENT NOTSX NONTEMPORAL
 CPL       : 3
 CATEGORY  : DATAXFER
 EXTENSION : SSE2
@@ -10698,6 +10781,7 @@ ATTRIBUTES: NOTSX
 CPL       : 3
 CATEGORY  : MMX
 EXTENSION : SSE2
+ISA_SET   : SSE2MMX
 PATTERN   : 0x0F 0xF4 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
 OPERANDS  : REG0=MMX_R():rw:q:u32 MEM0:r:q:u32
 PATTERN   : 0x0F 0xF4 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
@@ -10736,7 +10820,7 @@ CPL       : 3
 CATEGORY  : DATAXFER
 EXTENSION : MMX
 ISA_SET   : PENTIUMMMX
-ATTRIBUTES : fixed_base0 maskop NOTSX
+ATTRIBUTES : fixed_base0 maskop NOTSX NONTEMPORAL
 PATTERN   : 0x0F 0xF7 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  OVERRIDE_SEG0()
 OPERANDS  : REG0=MMX_R():r:q:u8 REG1=MMX_B():r:q:i8 MEM0:w:q:SUPP BASE0=ArDI():r:SUPP SEG0=FINAL_DSEG():r:SUPP
 }
@@ -10855,7 +10939,7 @@ CPL       : 3
 CATEGORY  : DATAXFER
 EXTENSION : SSE2
 EXCEPTIONS: SSE_TYPE_4
-ATTRIBUTES : fixed_base0 maskop NOTSX
+ATTRIBUTES : fixed_base0 maskop NOTSX NONTEMPORAL
 PATTERN   : 0x0F 0xF7 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66() OVERRIDE_SEG0()
 OPERANDS  : REG0=XMM_R():r:dq REG1=XMM_B():r:dq MEM0:w:dq:SUPP BASE0=ArDI():r:SUPP SEG0=FINAL_DSEG():r:SUPP
 }
@@ -10890,6 +10974,31 @@ PATTERN   : 0x0F 0x09
 OPERANDS  :
 }
 {
+ICLASS    : UD0
+CPL       : 3
+CATEGORY  : MISC
+EXTENSION : BASE
+ISA_SET   : PPRO
+ATTRIBUTES: NOTSX
+COMMENT   : Older processors (before NHM) did not take a MODRM byte sequence.
+PATTERN   : 0x0F 0xFF MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
+OPERANDS  : REG0=GPR32_R():r MEM0:r:d
+PATTERN   : 0x0F 0xFF MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=GPR32_R():r REG1=GPR32_B():r
+}
+{
+ICLASS    : UD1
+CPL       : 3
+CATEGORY  : MISC
+EXTENSION : BASE
+ISA_SET   : PPRO
+ATTRIBUTES: NOTSX
+PATTERN   : 0x0F 0xB9 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
+OPERANDS  : REG0=GPR32_R():r MEM0:r:d
+PATTERN   : 0x0F 0xB9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=GPR32_R():r REG1=GPR32_B():r
+}
+{
 ICLASS    : UD2
 CPL       : 3
 CATEGORY  : MISC
@@ -10935,7 +11044,7 @@ OPERANDS  : REG0=XMM_R():w:q:f32 REG1=MMX_B():r:q:i32
 }
 {
 ICLASS    : MOVNTPS
-ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT
+ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT NONTEMPORAL
 CPL       : 3
 CATEGORY  : DATAXFER
 EXTENSION : SSE
@@ -10963,9 +11072,9 @@ CATEGORY  : CONVERT
 EXTENSION : SSE
 ATTRIBUTES : MXCSR MMX_EXCEPT NOTSX
 PATTERN   : 0x0F 0x2D no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
-OPERANDS  : REG0=MMX_R():w:q:f32 MEM0:r:q:i32
+OPERANDS  : REG0=MMX_R():w:q:i32 MEM0:r:q:f32
 PATTERN   : 0x0F 0x2D no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=MMX_R():w:q:f32 REG1=XMM_B():r:q:i32
+OPERANDS  : REG0=MMX_R():w:q:i32 REG1=XMM_B():r:q:f32
 }
 {
 ICLASS    : UCOMISS
@@ -11076,7 +11185,7 @@ OPERANDS  : REG0=XMM_R():w:pd:f64 REG1=MMX_B():r:q:i32
 }
 {
 ICLASS    : MOVNTPD
-ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT
+ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT NONTEMPORAL
 CPL       : 3
 CATEGORY  : DATAXFER
 EXTENSION : SSE2
@@ -11187,7 +11296,7 @@ ICLASS    : CMOVS
 CPL       : 3
 CATEGORY  : CMOV
 EXTENSION : BASE
-ISA_SET   : PPRO
+ISA_SET   : CMOV
 FLAGS     : READONLY [ sf-tst ]
 PATTERN   : 0x0F 0x48 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS  : REG0=GPRv_R():cw MEM0:r:v
@@ -11197,7 +11306,7 @@ ICLASS    : CMOVS
 CPL       : 3
 CATEGORY  : CMOV
 EXTENSION : BASE
-ISA_SET   : PPRO
+ISA_SET   : CMOV
 FLAGS     : READONLY [ sf-tst ]
 PATTERN   : 0x0F 0x48 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
 OPERANDS  : REG0=GPRv_R():cw REG1=GPRv_B():r
@@ -11207,7 +11316,7 @@ ICLASS    : CMOVNS
 CPL       : 3
 CATEGORY  : CMOV
 EXTENSION : BASE
-ISA_SET   : PPRO
+ISA_SET   : CMOV
 FLAGS     : READONLY [ sf-tst ]
 PATTERN   : 0x0F 0x49 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS  : REG0=GPRv_R():cw MEM0:r:v
@@ -11217,7 +11326,7 @@ ICLASS    : CMOVNS
 CPL       : 3
 CATEGORY  : CMOV
 EXTENSION : BASE
-ISA_SET   : PPRO
+ISA_SET   : CMOV
 FLAGS     : READONLY [ sf-tst ]
 PATTERN   : 0x0F 0x49 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
 OPERANDS  : REG0=GPRv_R():cw REG1=GPRv_B():r
@@ -11227,7 +11336,7 @@ ICLASS    : CMOVP
 CPL       : 3
 CATEGORY  : CMOV
 EXTENSION : BASE
-ISA_SET   : PPRO
+ISA_SET   : CMOV
 FLAGS     : READONLY [ pf-tst ]
 PATTERN   : 0x0F 0x4A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS  : REG0=GPRv_R():cw MEM0:r:v
@@ -11237,7 +11346,7 @@ ICLASS    : CMOVP
 CPL       : 3
 CATEGORY  : CMOV
 EXTENSION : BASE
-ISA_SET   : PPRO
+ISA_SET   : CMOV
 FLAGS     : READONLY [ pf-tst ]
 PATTERN   : 0x0F 0x4A MOD[0b11] MOD=3 REG[rrr] RM[nnn]
 OPERANDS  : REG0=GPRv_R():cw REG1=GPRv_B():r
@@ -11247,7 +11356,7 @@ ICLASS    : CMOVNP
 CPL       : 3
 CATEGORY  : CMOV
 EXTENSION : BASE
-ISA_SET   : PPRO
+ISA_SET   : CMOV
 FLAGS     : READONLY [ pf-tst ]
 PATTERN   : 0x0F 0x4B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS  : REG0=GPRv_R():cw MEM0:r:v
@@ -11257,7 +11366,7 @@ ICLASS    : CMOVNP
 CPL       : 3
 CATEGORY  : CMOV
 EXTENSION : BASE
-ISA_SET   : PPRO
+ISA_SET   : CMOV
 FLAGS     : READONLY [ pf-tst ]
 PATTERN   : 0x0F 0x4B MOD[0b11] MOD=3 REG[rrr] RM[nnn]
 OPERANDS  : REG0=GPRv_R():cw REG1=GPRv_B():r
@@ -11267,7 +11376,7 @@ ICLASS    : CMOVL
 CPL       : 3
 CATEGORY  : CMOV
 EXTENSION : BASE
-ISA_SET   : PPRO
+ISA_SET   : CMOV
 FLAGS     : READONLY [ sf-tst of-tst ]
 PATTERN   : 0x0F 0x4C MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS  : REG0=GPRv_R():cw MEM0:r:v
@@ -11277,7 +11386,7 @@ ICLASS    : CMOVL
 CPL       : 3
 CATEGORY  : CMOV
 EXTENSION : BASE
-ISA_SET   : PPRO
+ISA_SET   : CMOV
 FLAGS     : READONLY [ sf-tst of-tst ]
 PATTERN   : 0x0F 0x4C MOD[0b11] MOD=3 REG[rrr] RM[nnn]
 OPERANDS  : REG0=GPRv_R():cw REG1=GPRv_B():r
@@ -11287,7 +11396,7 @@ ICLASS    : CMOVNL
 CPL       : 3
 CATEGORY  : CMOV
 EXTENSION : BASE
-ISA_SET   : PPRO
+ISA_SET   : CMOV
 FLAGS     : READONLY [ sf-tst of-tst ]
 PATTERN   : 0x0F 0x4D MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS  : REG0=GPRv_R():cw MEM0:r:v
@@ -11297,7 +11406,7 @@ ICLASS    : CMOVNL
 CPL       : 3
 CATEGORY  : CMOV
 EXTENSION : BASE
-ISA_SET   : PPRO
+ISA_SET   : CMOV
 FLAGS     : READONLY [ sf-tst of-tst ]
 PATTERN   : 0x0F 0x4D MOD[0b11] MOD=3 REG[rrr] RM[nnn]
 OPERANDS  : REG0=GPRv_R():cw REG1=GPRv_B():r
@@ -11307,7 +11416,7 @@ ICLASS    : CMOVLE
 CPL       : 3
 CATEGORY  : CMOV
 EXTENSION : BASE
-ISA_SET   : PPRO
+ISA_SET   : CMOV
 FLAGS     : READONLY [ sf-tst of-tst zf-tst ]
 PATTERN   : 0x0F 0x4E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS  : REG0=GPRv_R():cw MEM0:r:v
@@ -11317,7 +11426,7 @@ ICLASS    : CMOVLE
 CPL       : 3
 CATEGORY  : CMOV
 EXTENSION : BASE
-ISA_SET   : PPRO
+ISA_SET   : CMOV
 FLAGS     : READONLY [ sf-tst of-tst zf-tst ]
 PATTERN   : 0x0F 0x4E MOD[0b11] MOD=3 REG[rrr] RM[nnn]
 OPERANDS  : REG0=GPRv_R():cw REG1=GPRv_B():r
@@ -11327,7 +11436,7 @@ ICLASS    : CMOVNLE
 CPL       : 3
 CATEGORY  : CMOV
 EXTENSION : BASE
-ISA_SET   : PPRO
+ISA_SET   : CMOV
 FLAGS     : READONLY [ sf-tst of-tst zf-tst ]
 PATTERN   : 0x0F 0x4F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS  : REG0=GPRv_R():cw MEM0:r:v
@@ -11337,7 +11446,7 @@ ICLASS    : CMOVNLE
 CPL       : 3
 CATEGORY  : CMOV
 EXTENSION : BASE
-ISA_SET   : PPRO
+ISA_SET   : CMOV
 FLAGS     : READONLY [ sf-tst of-tst zf-tst ]
 PATTERN   : 0x0F 0x4F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
 OPERANDS  : REG0=GPRv_R():cw REG1=GPRv_B():r
@@ -12009,26 +12118,30 @@ IFORM     : MOVDQU_XMMdq_XMMdq_0F7F
 }
 {
 ICLASS    : VMREAD
-CPL       : 3
+CPL       : 0
 CATEGORY  : VTX
 EXTENSION : VTX
+FLAGS     : MUST [ cf-mod zf-mod sf-0 of-0 af-0 pf-0 ]
+
 PATTERN   : 0x0F 0x78 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64   MODRM() CR_WIDTH()
-OPERANDS  : MEM0:rw:q REG0=GPR64_R():r
+OPERANDS  : MEM0:w:q REG0=GPR64_R():r
 
 PATTERN   : 0x0F 0x78 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 CR_WIDTH()
-OPERANDS  : REG0=GPR64_B():rw REG1=GPR64_R():r
+OPERANDS  : REG0=GPR64_B():w REG1=GPR64_R():r
 
 PATTERN   : 0x0F 0x78 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64  MODRM() CR_WIDTH()
-OPERANDS  : MEM0:rw:d REG0=GPR32_R():r
+OPERANDS  : MEM0:w:d REG0=GPR32_R():r
 
 PATTERN   : 0x0F 0x78 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 CR_WIDTH()
-OPERANDS  : REG0=GPR32_B():rw REG1=GPR32_R():r
+OPERANDS  : REG0=GPR32_B():w REG1=GPR32_R():r
 }
 {
 ICLASS    : VMWRITE
-CPL       : 3
+CPL       : 0
 CATEGORY  : VTX
 EXTENSION : VTX
+FLAGS     : MUST [ cf-mod zf-mod sf-0 of-0 af-0 pf-0 ]
+
 PATTERN   : 0x0F 0x79 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64  MODRM() CR_WIDTH()
 OPERANDS  : REG0=GPR64_R():r MEM0:r:q
 
@@ -12119,7 +12232,7 @@ ISA_SET   : I86
 FLAGS     : READONLY [ sf-tst ]
 ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
 PATTERN   : 0x0F 0x88 not64 BRANCH_HINT() BRDISPz()
-OPERANDS  : RELBR:r:z REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
 }
 {
 ICLASS    : JS
@@ -12131,7 +12244,7 @@ FLAGS     : READONLY [ sf-tst ]
 ATTRIBUTES: MPX_PREFIX_ABLE
 
 PATTERN   : 0x0F 0x88 mode64 FORCE64() BRANCH_HINT() BRDISP32()
-OPERANDS  : RELBR:r:d REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
 }
 
 
@@ -12144,7 +12257,7 @@ ISA_SET   : I86
 FLAGS     : READONLY [ sf-tst ]
 ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
 PATTERN   : 0x0F 0x89 not64 BRANCH_HINT() BRDISPz()
-OPERANDS  : RELBR:r:z REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
 }
 {
 ICLASS    : JNS
@@ -12156,7 +12269,7 @@ FLAGS     : READONLY [ sf-tst ]
 ATTRIBUTES: MPX_PREFIX_ABLE
 
 PATTERN   : 0x0F 0x89 mode64 FORCE64() BRANCH_HINT() BRDISP32()
-OPERANDS  : RELBR:r:d REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
 }
 
 
@@ -12170,7 +12283,7 @@ ISA_SET   : I86
 FLAGS     : READONLY [ pf-tst ]
 ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
 PATTERN   : 0x0F 0x8A not64 BRANCH_HINT() BRDISPz()
-OPERANDS  : RELBR:r:z REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
 }
 {
 ICLASS    : JP
@@ -12182,7 +12295,7 @@ FLAGS     : READONLY [ pf-tst ]
 ATTRIBUTES: MPX_PREFIX_ABLE
 
 PATTERN   : 0x0F 0x8A mode64 FORCE64() BRANCH_HINT() BRDISP32()
-OPERANDS  : RELBR:r:d REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
 }
 
 
@@ -12195,7 +12308,7 @@ ISA_SET   : I86
 FLAGS     : READONLY [ pf-tst ]
 ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
 PATTERN   : 0x0F 0x8B not64 BRANCH_HINT() BRDISPz()
-OPERANDS  : RELBR:r:z REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
 }
 {
 ICLASS    : JNP
@@ -12207,7 +12320,7 @@ FLAGS     : READONLY [ pf-tst ]
 ATTRIBUTES: MPX_PREFIX_ABLE
 
 PATTERN   : 0x0F 0x8B mode64 FORCE64() BRANCH_HINT() BRDISP32()
-OPERANDS  : RELBR:r:d REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
 }
 
 
@@ -12220,7 +12333,7 @@ ISA_SET   : I86
 FLAGS     : READONLY [ sf-tst of-tst ]
 ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
 PATTERN   : 0x0F 0x8C not64 BRANCH_HINT() BRDISPz()
-OPERANDS  : RELBR:r:z REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
 }
 {
 ICLASS    : JL
@@ -12232,7 +12345,7 @@ FLAGS     : READONLY [ sf-tst of-tst ]
 ATTRIBUTES: MPX_PREFIX_ABLE
 
 PATTERN   : 0x0F 0x8C mode64 FORCE64() BRANCH_HINT() BRDISP32()
-OPERANDS  : RELBR:r:d REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
 }
 
 
@@ -12246,7 +12359,7 @@ ISA_SET   : I86
 FLAGS     : READONLY [ sf-tst of-tst ]
 ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
 PATTERN   : 0x0F 0x8D not64 BRANCH_HINT() BRDISPz()
-OPERANDS  : RELBR:r:z REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
 }
 {
 ICLASS    : JNL
@@ -12258,7 +12371,7 @@ FLAGS     : READONLY [ sf-tst of-tst ]
 ATTRIBUTES: MPX_PREFIX_ABLE
 
 PATTERN   : 0x0F 0x8D mode64 FORCE64() BRANCH_HINT() BRDISP32()
-OPERANDS  : RELBR:r:d REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
 }
 
 
@@ -12272,7 +12385,7 @@ ISA_SET   : I86
 FLAGS     : READONLY [ sf-tst of-tst zf-tst ]
 ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
 PATTERN   : 0x0F 0x8E not64 BRANCH_HINT() BRDISPz()
-OPERANDS  : RELBR:r:z REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
 }
 {
 ICLASS    : JLE
@@ -12284,7 +12397,7 @@ FLAGS     : READONLY [ sf-tst of-tst zf-tst ]
 ATTRIBUTES: MPX_PREFIX_ABLE
 
 PATTERN   : 0x0F 0x8E mode64 FORCE64() BRANCH_HINT() BRDISP32()
-OPERANDS  : RELBR:r:d REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
 }
 
 
@@ -12298,7 +12411,7 @@ ISA_SET   : I86
 FLAGS     : READONLY [ sf-tst of-tst zf-tst ]
 ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
 PATTERN   : 0x0F 0x8F not64 BRANCH_HINT() BRDISPz()
-OPERANDS  : RELBR:r:z REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
 }
 {
 ICLASS    : JNLE
@@ -12310,7 +12423,7 @@ FLAGS     : READONLY [ sf-tst of-tst zf-tst ]
 ATTRIBUTES: MPX_PREFIX_ABLE
 
 PATTERN   : 0x0F 0x8F mode64 FORCE64() BRANCH_HINT() BRDISP32()
-OPERANDS  : RELBR:r:d REG0=rIP():rw:SUPP
+OPERANDS  : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
 }
 
 
@@ -13176,6 +13289,7 @@ ATTRIBUTES: NOTSX
 CPL       : 3
 CATEGORY  : MMX
 EXTENSION : SSE2
+ISA_SET   : SSE2MMX
 PATTERN   : 0x0F 0xFB no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
 OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
 PATTERN   : 0x0F 0xFB no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
@@ -13311,6 +13425,7 @@ ATTRIBUTES: NOTSX
 CPL       : 3
 CATEGORY  : MMX
 EXTENSION : SSSE3
+ISA_SET   : SSSE3MMX
 PATTERN   : 0x0F 0x38 0x01 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
 OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
 PATTERN   : 0x0F 0x38 0x01 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
@@ -13335,6 +13450,7 @@ ATTRIBUTES: NOTSX
 CPL       : 3
 CATEGORY  : MMX
 EXTENSION : SSSE3
+ISA_SET   : SSSE3MMX
 PATTERN   : 0x0F 0x38 0x02 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
 OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
 PATTERN   : 0x0F 0x38 0x02 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
@@ -13359,6 +13475,7 @@ ATTRIBUTES: NOTSX
 CPL       : 3
 CATEGORY  : MMX
 EXTENSION : SSSE3
+ISA_SET   : SSSE3MMX
 PATTERN   : 0x0F 0x38 0x03 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
 OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
 PATTERN   : 0x0F 0x38 0x03 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
@@ -13383,6 +13500,7 @@ ATTRIBUTES: NOTSX
 CPL       : 3
 CATEGORY  : MMX
 EXTENSION : SSSE3
+ISA_SET   : SSSE3MMX
 PATTERN   : 0x0F 0x38 0x05 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
 OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
 PATTERN   : 0x0F 0x38 0x05 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
@@ -13407,6 +13525,7 @@ ATTRIBUTES: NOTSX
 CPL       : 3
 CATEGORY  : MMX
 EXTENSION : SSSE3
+ISA_SET   : SSSE3MMX
 PATTERN   : 0x0F 0x38 0x06 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
 OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
 PATTERN   : 0x0F 0x38 0x06 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
@@ -13431,6 +13550,7 @@ ATTRIBUTES: NOTSX
 CPL       : 3
 CATEGORY  : MMX
 EXTENSION : SSSE3
+ISA_SET   : SSSE3MMX
 PATTERN   : 0x0F 0x38 0x07 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
 OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
 PATTERN   : 0x0F 0x38 0x07 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
@@ -13454,6 +13574,7 @@ EXCEPTIONS: mmx-mem
 CPL       : 3
 CATEGORY  : MMX
 EXTENSION : SSSE3
+ISA_SET   : SSSE3MMX
 ATTRIBUTES : DOUBLE_WIDE_OUTPUT NOTSX
 PATTERN   : 0x0F 0x38 0x04 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
 OPERANDS  : REG0=MMX_R():rw:q:i8 MEM0:r:q:i8
@@ -13479,6 +13600,7 @@ ATTRIBUTES: NOTSX
 CPL       : 3
 CATEGORY  : MMX
 EXTENSION : SSSE3
+ISA_SET   : SSSE3MMX
 PATTERN   : 0x0F 0x38 0x0B no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
 OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
 PATTERN   : 0x0F 0x38 0x0B no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
@@ -13503,6 +13625,7 @@ ATTRIBUTES: NOTSX
 CPL       : 3
 CATEGORY  : MMX
 EXTENSION : SSSE3
+ISA_SET   : SSSE3MMX
 PATTERN   : 0x0F 0x38 0x00 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
 OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
 PATTERN   : 0x0F 0x38 0x00 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
@@ -13527,6 +13650,7 @@ ATTRIBUTES: NOTSX
 CPL       : 3
 CATEGORY  : MMX
 EXTENSION : SSSE3
+ISA_SET   : SSSE3MMX
 PATTERN   : 0x0F 0x38 0x08 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
 OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
 PATTERN   : 0x0F 0x38 0x08 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
@@ -13551,6 +13675,7 @@ ATTRIBUTES: NOTSX
 CPL       : 3
 CATEGORY  : MMX
 EXTENSION : SSSE3
+ISA_SET   : SSSE3MMX
 PATTERN   : 0x0F 0x38 0x09 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
 OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
 PATTERN   : 0x0F 0x38 0x09 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
@@ -13574,6 +13699,7 @@ ATTRIBUTES: NOTSX
 CPL       : 3
 CATEGORY  : MMX
 EXTENSION : SSSE3
+ISA_SET   : SSSE3MMX
 EXCEPTIONS: mmx-mem
 PATTERN   : 0x0F 0x38 0x0A no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
 OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
@@ -13599,6 +13725,7 @@ ATTRIBUTES: NOTSX
 CPL       : 3
 CATEGORY  : MMX
 EXTENSION : SSSE3
+ISA_SET   : SSSE3MMX
 PATTERN   : 0x0F 0x3A 0x0F no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM() UIMM8()
 OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q IMM0:r:b
 PATTERN   : 0x0F 0x3A 0x0F no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  UIMM8()
@@ -13623,6 +13750,7 @@ ATTRIBUTES: NOTSX
 CPL       : 3
 CATEGORY  : MMX
 EXTENSION : SSSE3
+ISA_SET   : SSSE3MMX
 PATTERN   : 0x0F 0x38 0x1C no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
 OPERANDS  : REG0=MMX_R():w:q MEM0:r:q
 PATTERN   : 0x0F 0x38 0x1C no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
@@ -13647,6 +13775,7 @@ ATTRIBUTES: NOTSX
 CPL       : 3
 CATEGORY  : MMX
 EXTENSION : SSSE3
+ISA_SET   : SSSE3MMX
 PATTERN   : 0x0F 0x38 0x1D no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
 OPERANDS  : REG0=MMX_R():w:q MEM0:r:q
 PATTERN   : 0x0F 0x38 0x1D no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
@@ -13671,6 +13800,7 @@ CPL       : 3
 ATTRIBUTES : simd_scalar NOTSX
 CATEGORY  : MMX
 EXTENSION : SSSE3
+ISA_SET   : SSSE3MMX
 PATTERN   : 0x0F 0x38 0x1E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
 OPERANDS  : REG0=MMX_R():w:q MEM0:r:q
 }
@@ -13680,6 +13810,7 @@ CPL       : 3
 ATTRIBUTES : simd_scalar NOTSX
 CATEGORY  : MMX
 EXTENSION : SSSE3
+ISA_SET   : SSSE3MMX
 PATTERN   : 0x0F 0x38 0x1E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
 OPERANDS  : REG0=MMX_R():w:q REG1=MMX_B():r:q
 }
@@ -13868,7 +13999,7 @@ CPL       : 3
 CATEGORY  : SSE
 EXTENSION : SSE4
 EXCEPTIONS: SSE_TYPE_1
-ATTRIBUTES :  REQUIRES_ALIGNMENT NOTSX
+ATTRIBUTES :  REQUIRES_ALIGNMENT NOTSX NONTEMPORAL
 PATTERN   : 0x0F 0x38 0x2A osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS  : REG0=XMM_R():w:dq MEM0:r:dq
 }
@@ -14433,16 +14564,26 @@ EXCEPTIONS: SSE_TYPE_4
 ATTRIBUTES:
 FLAGS     : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ]
 
-PATTERN   : 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
+PATTERN   : 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() EOSZ=2 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
 OPERANDS  : REG0=XMM_R():r:dq     MEM0:r:dq         IMM0:r:b REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_EDX:r:SUPP REG3=XED_REG_ECX:w:SUPP
 
-PATTERN   : 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
+PATTERN   : 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() EOSZ=2  MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
 OPERANDS  : REG0=XMM_R():r:dq     REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_ECX:w:SUPP
+}
+{
+ICLASS    : PCMPESTRI
+CPL       : 3
+CATEGORY  : SSE
+EXTENSION : SSE4
+ISA_SET   : SSE42
+EXCEPTIONS: SSE_TYPE_4
+ATTRIBUTES:
+FLAGS     : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ]
 
-PATTERN   : 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
+PATTERN   : 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() EOSZ=3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
 OPERANDS  : REG0=XMM_R():r:dq     MEM0:r:dq         IMM0:r:b REG1=XED_REG_RAX:r:SUPP REG2=XED_REG_RDX:r:SUPP REG3=XED_REG_RCX:w:SUPP
 
-PATTERN   : 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
+PATTERN   : 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() EOSZ=3 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
 OPERANDS  : REG0=XMM_R():r:dq     REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_RAX:r:SUPP REG3=XED_REG_RDX:r:SUPP REG4=XED_REG_RCX:w:SUPP
 }
 {
@@ -14455,16 +14596,26 @@ EXCEPTIONS: SSE_TYPE_4
 ATTRIBUTES:
 FLAGS     : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ]
 
-PATTERN   : 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
+PATTERN   : 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() EOSZ=2 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
 OPERANDS  : REG0=XMM_R():r:dq     MEM0:r:dq         IMM0:r:b REG1=XED_REG_ECX:w:SUPP
 
-PATTERN   : 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
+PATTERN   : 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() EOSZ=2 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
 OPERANDS  : REG0=XMM_R():r:dq     REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_ECX:w:SUPP
+}
+{
+ICLASS    : PCMPISTRI
+CPL       : 3
+CATEGORY  : SSE
+EXTENSION : SSE4
+ISA_SET   : SSE42
+EXCEPTIONS: SSE_TYPE_4
+ATTRIBUTES:
+FLAGS     : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ]
 
-PATTERN   : 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
+PATTERN   : 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() EOSZ=3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
 OPERANDS  : REG0=XMM_R():r:dq     MEM0:r:dq         IMM0:r:b REG1=XED_REG_RCX:w:SUPP
 
-PATTERN   : 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
+PATTERN   : 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() EOSZ=3 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
 OPERANDS  : REG0=XMM_R():r:dq     REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_RCX:w:SUPP
 }
 
@@ -14478,16 +14629,26 @@ EXCEPTIONS: SSE_TYPE_4
 ATTRIBUTES:
 FLAGS     : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ]
 
-PATTERN   : 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
+PATTERN   : 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() EOSZ=2 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
 OPERANDS  : REG0=XMM_R():r:dq     MEM0:r:dq         IMM0:r:b REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_EDX:r:SUPP REG3=XED_REG_XMM0:w:dq:SUPP
 
-PATTERN   : 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
+PATTERN   : 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() EOSZ=2 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
 OPERANDS  : REG0=XMM_R():r:dq     REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_XMM0:w:dq:SUPP
+}
+{
+ICLASS    : PCMPESTRM
+CPL       : 3
+CATEGORY  : SSE
+EXTENSION : SSE4
+ISA_SET   : SSE42
+EXCEPTIONS: SSE_TYPE_4
+ATTRIBUTES:
+FLAGS     : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ]
 
-PATTERN   : 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
+PATTERN   : 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() EOSZ=3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
 OPERANDS  : REG0=XMM_R():r:dq     MEM0:r:dq         IMM0:r:b REG1=XED_REG_RAX:r:SUPP REG2=XED_REG_RDX:r:SUPP REG3=XED_REG_XMM0:w:dq:SUPP
 
-PATTERN   : 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
+PATTERN   : 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() EOSZ=3 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
 OPERANDS  : REG0=XMM_R():r:dq     REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_RAX:r:SUPP REG3=XED_REG_RDX:r:SUPP REG4=XED_REG_XMM0:w:dq:SUPP
 
 }
@@ -14532,18 +14693,18 @@ ICLASS    : XSAVE
 CPL       : 3
 CATEGORY  : XSAVE
 EXTENSION : XSAVE
-COMMENT   : variable length store
+COMMENT   : Variable length store and conditional reg read. Reads/writes XSTATE_BV from header.
 ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED
 PATTERN   : 0x0F 0xAE MOD[mm]  MOD!=3 REG[0b100] RM[nnn] no_refining_prefix norexw_prefix MODRM()
 #FIXME 2007-06-25 need a meaningful width code for XSAVE/XRSTOR
-OPERANDS  : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP
+OPERANDS  : MEM0:rw:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP
 }
 {
 ICLASS    : XRSTOR
 CPL       : 3
 CATEGORY  : XSAVE
 EXTENSION : XSAVE
-COMMENT   : variable length load and conditianal reg write
+COMMENT   : variable length load and conditional reg write
 ATTRIBUTES : xmm_state_cw REQUIRES_ALIGNMENT x87_mmx_state_cw NOTSX SPECIAL_AGEN_REQUIRED
 PATTERN   : 0x0F 0xAE MOD[mm]  MOD!=3 REG[0b101] RM[nnn] no_refining_prefix norexw_prefix MODRM()
 #FIXME 2007-06-25 need a meaningful width code for XSAVE/XRSTOR
@@ -14556,11 +14717,11 @@ ICLASS    : XSAVE64
 CPL       : 3
 CATEGORY  : XSAVE
 EXTENSION : XSAVE
-COMMENT   : variable length store
+COMMENT   : Variable length store and conditional reg read. Reads/writes XSTATE_BV from header.
 ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED
 PATTERN   : 0x0F 0xAE MOD[mm]  MOD!=3 REG[0b100] RM[nnn] no_refining_prefix rexw_prefix MODRM()
 #FIXME 2007-06-25 need a meaningful width code for XSAVE/XRSTOR
-OPERANDS  : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP
+OPERANDS  : MEM0:rw:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP
 }
 
 {
@@ -14568,7 +14729,7 @@ ICLASS    : XRSTOR64
 CPL       : 3
 CATEGORY  : XSAVE
 EXTENSION : XSAVE
-COMMENT   : variable length load and conditianal reg write
+COMMENT   : variable length load and conditional reg write
 ATTRIBUTES : xmm_state_cw REQUIRES_ALIGNMENT x87_mmx_state_cw NOTSX SPECIAL_AGEN_REQUIRED
 PATTERN   : 0x0F 0xAE MOD[mm]  MOD!=3 REG[0b101] RM[nnn] no_refining_prefix rexw_prefix MODRM()
 #FIXME 2007-06-25 need a meaningful width code for XSAVE/XRSTOR
@@ -14603,7 +14764,7 @@ CPL       : 3
 CATEGORY  : SYSTEM
 ATTRIBUTES: PROTECTED_MODE NOTSX
 EXTENSION : SMX
-PATTERN   : 0x0F 0x37
+PATTERN   : 0x0F 0x37 no_refining_prefix
 OPERANDS  : REG0=XED_REG_EAX:rcw:SUPP  REG1=XED_REG_EBX:r:SUPP
 }
 
@@ -14703,9 +14864,10 @@ CPL       : 0
 CATEGORY  : VTX
 EXTENSION : VTX
 ATTRIBUTES : RING0 NOTSX
+FLAGS     : MUST [ cf-mod zf-mod sf-0 of-0 af-0 pf-0 ]
 PATTERN   : 0x0F 0x38 0x80 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() mode64 MODRM() CR_WIDTH()
 OPERANDS  : REG0=GPR64_R():r MEM0:r:dq
-PATTERN   : 0x0F 0x38 0x80 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() mode32 MODRM() CR_WIDTH()
+PATTERN   : 0x0F 0x38 0x80 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() not64  MODRM() CR_WIDTH()
 OPERANDS  : REG0=GPR32_R():r MEM0:r:dq
 COMMENT   : SDM rev 27
 }
@@ -14715,9 +14877,10 @@ CPL       : 0
 CATEGORY  : VTX
 EXTENSION : VTX
 ATTRIBUTES : RING0 NOTSX
+FLAGS     : MUST [ cf-mod zf-mod sf-0 of-0 af-0 pf-0 ]
 PATTERN   : 0x0F 0x38 0x81 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() mode64 MODRM() CR_WIDTH()
 OPERANDS  : REG0=GPR64_R():r MEM0:r:dq
-PATTERN   : 0x0F 0x38 0x81 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() mode32 MODRM() CR_WIDTH()
+PATTERN   : 0x0F 0x38 0x81 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() not64  MODRM() CR_WIDTH()
 OPERANDS  : REG0=GPR32_R():r MEM0:r:dq
 COMMENT   : SDM rev 27
 }
@@ -14731,7 +14894,7 @@ COMMENT   : SDM rev 27
 
 #BEGIN_LEGAL
 #
-#Copyright (c) 2016 Intel Corporation
+#Copyright (c) 2018 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -14840,7 +15003,7 @@ IFORM     : PREFETCH_RESERVED_0F0Dr7
 
 #BEGIN_LEGAL
 #
-#Copyright (c) 2016 Intel Corporation
+#Copyright (c) 2018 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -14932,11 +15095,179 @@ OPERANDS  :
 }
 
 
+###FILE: ../xed/datafiles/via-padlock-isa.xed.txt
+
+#BEGIN_LEGAL
+#
+#Copyright (c) 2018 Intel Corporation
+#
+#  Licensed under the Apache License, Version 2.0 (the "License");
+#  you may not use this file except in compliance with the License.
+#  You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+#  Unless required by applicable law or agreed to in writing, software
+#  distributed under the License is distributed on an "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#  See the License for the specific language governing permissions and
+#  limitations under the License.
+#
+#END_LEGAL
+
+{
+ICLASS    : XSTORE
+CPL       : 3
+CATEGORY  : VIA_PADLOCK
+EXTENSION : VIA_PADLOCK_RNG
+ISA_SET   : VIA_PADLOCK_RNG
+PATTERN   : 0x0F 0xA7 MOD[0b11] REG[0b000] RM[0b000]  not_refining
+OPERANDS  : MEM0:w:SUPP:b REG0=OrCX():r:SUPP REG1=OrDX():rw:SUPP REG2=OrAX():w:SUPP BASE0=ArDI():rw:SUPP  SEG0=FINAL_ESEG():r:SUPP
+}
+
+
+{
+ICLASS    : REP_XSTORE
+DISASM    : xstore
+CPL       : 3
+CATEGORY  : VIA_PADLOCK
+EXTENSION : VIA_PADLOCK_RNG
+ISA_SET   : VIA_PADLOCK_RNG
+ATTRIBUTES : REP  FIXED_BASE0 BYTEOP
+PATTERN   : 0x0F 0xA7 MOD[0b11] REG[0b000] RM[0b000] f3_refining_prefix
+OPERANDS  : MEM0:w:SUPP:b REG0=OrCX():rw:SUPP REG1=OrDX():rw:SUPP REG2=OrAX():w:SUPP BASE0=ArDI():rw:SUPP  SEG0=FINAL_ESEG():r:SUPP
+}
+
+
+{
+ICLASS    : REP_XCRYPTECB
+DISASM    : xcryptecb
+CPL       : 3
+CATEGORY  : VIA_PADLOCK
+EXTENSION : VIA_PADLOCK_AES
+ISA_SET   : VIA_PADLOCK_AES
+ATTRIBUTES : REP  FIXED_BASE0 BYTEOP
+PATTERN   : 0x0F 0xA7 MOD[0b11] REG[0b001] RM[0b000] f3_refining_prefix
+OPERANDS  : MEM0:w:SUPP:b REG0=OrCX():rw:SUPP REG1=OrDX():r:SUPP REG2=OrBX():r:SUPP  BASE0=ArDI():rw:SUPP  SEG0=FINAL_ESEG():r:SUPP  MEM1:cr:SUPP:b BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP
+}
+
+{
+ICLASS    : REP_XCRYPTCBC
+DISASM    : xcryptcbc
+CPL       : 3
+CATEGORY  : VIA_PADLOCK
+EXTENSION : VIA_PADLOCK_AES
+ISA_SET   : VIA_PADLOCK_AES
+ATTRIBUTES : REP  FIXED_BASE0 BYTEOP
+PATTERN   : 0x0F 0xA7 MOD[0b11] REG[0b010] RM[0b000] f3_refining_prefix
+COMMENT   : rAX contains a pointer to memory using ES segment.
+OPERANDS  : MEM0:w:SUPP:b REG0=OrCX():rw:SUPP REG1=OrDX():r:SUPP REG2=OrBX():r:SUPP REG3=ArAX():r:SUPP  BASE0=ArDI():rw:SUPP  SEG0=FINAL_ESEG():r:SUPP  MEM1:cr:SUPP:b BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP
+}
+
+
+{
+ICLASS    : REP_XCRYPTCTR
+DISASM    : xcryptctr
+CPL       : 3
+CATEGORY  : VIA_PADLOCK
+EXTENSION : VIA_PADLOCK_AES
+ISA_SET   : VIA_PADLOCK_AES
+ATTRIBUTES : REP  FIXED_BASE0 BYTEOP
+PATTERN   : 0x0F 0xA7 MOD[0b11] REG[0b011] RM[0b000] f3_refining_prefix
+COMMENT   : rAX contains a pointer to memory using ES segment.
+OPERANDS  : MEM0:w:SUPP:b REG0=OrCX():rw:SUPP REG1=OrDX():r:SUPP REG2=OrBX():r:SUPP REG3=ArAX():r:SUPP  BASE0=ArDI():rw:SUPP  SEG0=FINAL_ESEG():r:SUPP  MEM1:cr:SUPP:b BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP
+}
+{
+ICLASS    : REP_XCRYPTCFB
+DISASM    : xcryptcfb
+CPL       : 3
+CATEGORY  : VIA_PADLOCK
+EXTENSION : VIA_PADLOCK_AES
+ISA_SET   : VIA_PADLOCK_AES
+ATTRIBUTES : REP  FIXED_BASE0 BYTEOP
+PATTERN   : 0x0F 0xA7 MOD[0b11] REG[0b100] RM[0b000] f3_refining_prefix
+COMMENT   : rAX contains a pointer to memory using ES segment.
+OPERANDS  : MEM0:w:SUPP:b REG0=OrCX():rw:SUPP REG1=OrDX():r:SUPP REG2=OrBX():r:SUPP REG3=ArAX():r:SUPP  BASE0=ArDI():rw:SUPP  SEG0=FINAL_ESEG():r:SUPP  MEM1:cr:SUPP:b BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP
+}
+{
+ICLASS    : REP_XCRYPTOFB
+DISASM    : xcryptofb
+CPL       : 3
+CATEGORY  : VIA_PADLOCK
+EXTENSION : VIA_PADLOCK_AES
+ISA_SET   : VIA_PADLOCK_AES
+ATTRIBUTES : REP  FIXED_BASE0 BYTEOP
+PATTERN   : 0x0F 0xA7 MOD[0b11] REG[0b101] RM[0b000]  f3_refining_prefix
+COMMENT   : rAX contains a pointer to memory using ES segment.
+OPERANDS  : MEM0:w:SUPP:b REG0=OrCX():rw:SUPP REG1=OrDX():r:SUPP REG2=OrBX():r:SUPP REG3=ArAX():r:SUPP  BASE0=ArDI():rw:SUPP  SEG0=FINAL_ESEG():r:SUPP  MEM1:cr:SUPP:b BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP
+}
+
+
+
+{
+ICLASS    : REP_XSHA1
+DISASM    : xsha1
+CPL       : 3
+CATEGORY  : VIA_PADLOCK
+EXTENSION : VIA_PADLOCK_SHA
+ISA_SET   : VIA_PADLOCK_SHA
+ATTRIBUTES : REP FIXED_BASE0 BYTEOP
+PATTERN   : 0x0F 0xA6 MOD[0b11] REG[0b001] RM[0b000] f3_refining_prefix
+OPERANDS  : REG0=ArAX():rcw:SUPP REG1=OrCX():rcw:SUPP MEM0:w:SUPP:b  BASE0=ArSI():rw:SUPP  SEG0=FINAL_ESEG():r:SUPP MEM1:r:SUPP:b  BASE1=ArDI():r:SUPP   SEG1=FINAL_ESEG1():r:SUPP
+}
+
+
+
+{
+ICLASS    : REP_XSHA256
+DISASM    : xsha256
+CPL       : 3
+CATEGORY  : VIA_PADLOCK
+EXTENSION : VIA_PADLOCK_SHA
+ISA_SET   : VIA_PADLOCK_SHA
+ATTRIBUTES : REP FIXED_BASE0 BYTEOP
+PATTERN   : 0x0F 0xA6 MOD[0b11] REG[0b010] RM[0b000] f3_refining_prefix
+OPERANDS  : REG0=ArAX():rcw:SUPP REG1=OrCX():rcw:SUPP MEM0:w:SUPP:b  BASE0=ArSI():rw:SUPP  SEG0=FINAL_ESEG():r:SUPP MEM1:r:SUPP:b  BASE1=ArDI():r:SUPP   SEG1=FINAL_ESEG1():r:SUPP
+}
+
+
+
+{
+ICLASS    : REP_MONTMUL
+DISASM    : montmul
+CPL       : 3
+CATEGORY  : VIA_PADLOCK
+EXTENSION : VIA_PADLOCK_MONTMUL
+ISA_SET   : VIA_PADLOCK_MONTMUL
+ATTRIBUTES : REP FIXED_BASE0
+COMMENT   : EAX output value undefined, so list as write.
+
+PATTERN   : 0x0F 0xA6 MOD[0b11] REG[0b000] RM[0b000] f3_refining_prefix eamode16
+OPERANDS  : REG0=XED_REG_EAX:rw:SUPP \
+            REG1=XED_REG_ECX:rw:SUPP \
+            REG2=XED_REG_EDX:w:SUPP \
+            MEM0:rw:SUPP:pmmsz16 \
+            BASE0=ArSI():r:SUPP \
+            SEG0=FINAL_ESEG():r:SUPP
+
+PATTERN   : 0x0F 0xA6 MOD[0b11] REG[0b000] RM[0b000] f3_refining_prefix eamode32
+OPERANDS  : REG0=XED_REG_EAX:rw:SUPP \
+            REG1=XED_REG_ECX:rw:SUPP \
+            REG2=XED_REG_EDX:w:SUPP \
+            MEM0:rw:SUPP:pmmsz32 \
+            BASE0=ArSI():r:SUPP \
+            SEG0=FINAL_ESEG():r:SUPP
+}
+
+
+
+
+
 ###FILE: ../xed/datafiles/xed-amd-3dnow.txt
 
 #BEGIN_LEGAL
 #
-#Copyright (c) 2016 Intel Corporation
+#Copyright (c) 2018 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -14958,7 +15289,7 @@ ICLASS    : FEMMS
 CPL       : 3
 CATEGORY  : MMX
 EXTENSION : 3DNOW
-ATTRIBUTES : x87_mmx_state_w
+ATTRIBUTES : x87_mmx_state_w AMDONLY
 PATTERN   : 0x0F 0x0E
 OPERANDS  :
 }
@@ -14967,6 +15298,7 @@ ICLASS    : PI2FW
 CPL       : 3
 CATEGORY  : 3DNOW
 EXTENSION : 3DNOW
+ATTRIBUTES : AMDONLY
 PATTERN   : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x0C
 OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
 }
@@ -14975,6 +15307,7 @@ ICLASS    : PI2FW
 CPL       : 3
 CATEGORY  : 3DNOW
 EXTENSION : 3DNOW
+ATTRIBUTES : AMDONLY
 PATTERN   : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x0C
 OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
 }
@@ -14983,6 +15316,7 @@ ICLASS    : PI2FD
 CPL       : 3
 CATEGORY  : 3DNOW
 EXTENSION : 3DNOW
+ATTRIBUTES : AMDONLY
 PATTERN   : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x0D
 OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
 }
@@ -14991,6 +15325,7 @@ ICLASS    : PI2FD
 CPL       : 3
 CATEGORY  : 3DNOW
 EXTENSION : 3DNOW
+ATTRIBUTES : AMDONLY
 PATTERN   : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x0D
 OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
 }
@@ -14999,6 +15334,7 @@ ICLASS    : PF2IW
 CPL       : 3
 CATEGORY  : 3DNOW
 EXTENSION : 3DNOW
+ATTRIBUTES : AMDONLY
 PATTERN   : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x1C
 OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
 }
@@ -15007,6 +15343,7 @@ ICLASS    : PF2IW
 CPL       : 3
 CATEGORY  : 3DNOW
 EXTENSION : 3DNOW
+ATTRIBUTES : AMDONLY
 PATTERN   : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x1C
 OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
 }
@@ -15015,6 +15352,7 @@ ICLASS    : PF2ID
 CPL       : 3
 CATEGORY  : 3DNOW
 EXTENSION : 3DNOW
+ATTRIBUTES : AMDONLY
 PATTERN   : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x1D
 OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
 }
@@ -15023,6 +15361,7 @@ ICLASS    : PF2ID
 CPL       : 3
 CATEGORY  : 3DNOW
 EXTENSION : 3DNOW
+ATTRIBUTES : AMDONLY
 PATTERN   : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x1D
 OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
 }
@@ -15031,6 +15370,7 @@ ICLASS    : PFNACC
 CPL       : 3
 CATEGORY  : 3DNOW
 EXTENSION : 3DNOW
+ATTRIBUTES : AMDONLY
 PATTERN   : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x8A
 OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
 }
@@ -15039,6 +15379,7 @@ ICLASS    : PFNACC
 CPL       : 3
 CATEGORY  : 3DNOW
 EXTENSION : 3DNOW
+ATTRIBUTES : AMDONLY
 PATTERN   : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x8A
 OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
 }
@@ -15047,6 +15388,7 @@ ICLASS    : PFPNACC
 CPL       : 3
 CATEGORY  : 3DNOW
 EXTENSION : 3DNOW
+ATTRIBUTES : AMDONLY
 PATTERN   : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x8E
 OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
 }
@@ -15055,6 +15397,7 @@ ICLASS    : PFPNACC
 CPL       : 3
 CATEGORY  : 3DNOW
 EXTENSION : 3DNOW
+ATTRIBUTES : AMDONLY
 PATTERN   : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x8E
 OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
 }
@@ -15063,6 +15406,7 @@ ICLASS    : PFCMPGE
 CPL       : 3
 CATEGORY  : 3DNOW
 EXTENSION : 3DNOW
+ATTRIBUTES : AMDONLY
 PATTERN   : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x90
 OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
 }
@@ -15071,6 +15415,7 @@ ICLASS    : PFCMPGE
 CPL       : 3
 CATEGORY  : 3DNOW
 EXTENSION : 3DNOW
+ATTRIBUTES : AMDONLY
 PATTERN   : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x90
 OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
 }
@@ -15079,6 +15424,7 @@ ICLASS    : PFMIN
 CPL       : 3
 CATEGORY  : 3DNOW
 EXTENSION : 3DNOW
+ATTRIBUTES : AMDONLY
 PATTERN   : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x94
 OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
 }
@@ -15087,6 +15433,7 @@ ICLASS    : PFMIN
 CPL       : 3
 CATEGORY  : 3DNOW
 EXTENSION : 3DNOW
+ATTRIBUTES : AMDONLY
 PATTERN   : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x94
 OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
 }
@@ -15095,6 +15442,7 @@ ICLASS    : PFRCP
 CPL       : 3
 CATEGORY  : 3DNOW
 EXTENSION : 3DNOW
+ATTRIBUTES : AMDONLY
 PATTERN   : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x96
 OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
 }
@@ -15103,22 +15451,25 @@ ICLASS    : PFRCP
 CPL       : 3
 CATEGORY  : 3DNOW
 EXTENSION : 3DNOW
+ATTRIBUTES : AMDONLY
 PATTERN   : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x96
 OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
 }
 {
-ICLASS    : PFSQRT
+ICLASS    : PFRSQRT
 CPL       : 3
 CATEGORY  : 3DNOW
 EXTENSION : 3DNOW
+ATTRIBUTES : AMDONLY
 PATTERN   : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x97
 OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
 }
 {
-ICLASS    : PFSQRT
+ICLASS    : PFRSQRT
 CPL       : 3
 CATEGORY  : 3DNOW
 EXTENSION : 3DNOW
+ATTRIBUTES : AMDONLY
 PATTERN   : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x97
 OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
 }
@@ -15127,6 +15478,7 @@ ICLASS    : PFSUB
 CPL       : 3
 CATEGORY  : 3DNOW
 EXTENSION : 3DNOW
+ATTRIBUTES : AMDONLY
 PATTERN   : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x9A
 OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
 }
@@ -15135,6 +15487,7 @@ ICLASS    : PFSUB
 CPL       : 3
 CATEGORY  : 3DNOW
 EXTENSION : 3DNOW
+ATTRIBUTES : AMDONLY
 PATTERN   : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x9A
 OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
 }
@@ -15143,6 +15496,7 @@ ICLASS    : PFADD
 CPL       : 3
 CATEGORY  : 3DNOW
 EXTENSION : 3DNOW
+ATTRIBUTES : AMDONLY
 PATTERN   : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x9E
 OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
 }
@@ -15151,6 +15505,7 @@ ICLASS    : PFADD
 CPL       : 3
 CATEGORY  : 3DNOW
 EXTENSION : 3DNOW
+ATTRIBUTES : AMDONLY
 PATTERN   : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x9E
 OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
 }
@@ -15159,6 +15514,7 @@ ICLASS    : PFCMPGT
 CPL       : 3
 CATEGORY  : 3DNOW
 EXTENSION : 3DNOW
+ATTRIBUTES : AMDONLY
 PATTERN   : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xA0
 OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
 }
@@ -15167,6 +15523,7 @@ ICLASS    : PFCMPGT
 CPL       : 3
 CATEGORY  : 3DNOW
 EXTENSION : 3DNOW
+ATTRIBUTES : AMDONLY
 PATTERN   : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xA0
 OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
 }
@@ -15175,6 +15532,7 @@ ICLASS    : PFMAX
 CPL       : 3
 CATEGORY  : 3DNOW
 EXTENSION : 3DNOW
+ATTRIBUTES : AMDONLY
 PATTERN   : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xA4
 OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
 }
@@ -15183,22 +15541,25 @@ ICLASS    : PFMAX
 CPL       : 3
 CATEGORY  : 3DNOW
 EXTENSION : 3DNOW
+ATTRIBUTES : AMDONLY
 PATTERN   : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xA4
 OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
 }
 {
-ICLASS    : PFCPIT1
+ICLASS    : PFRCPIT1
 CPL       : 3
 CATEGORY  : 3DNOW
 EXTENSION : 3DNOW
+ATTRIBUTES : AMDONLY
 PATTERN   : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xA6
 OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
 }
 {
-ICLASS    : PFCPIT1
+ICLASS    : PFRCPIT1
 CPL       : 3
 CATEGORY  : 3DNOW
 EXTENSION : 3DNOW
+ATTRIBUTES : AMDONLY
 PATTERN   : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xA6
 OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
 }
@@ -15207,6 +15568,7 @@ ICLASS    : PFRSQIT1
 CPL       : 3
 CATEGORY  : 3DNOW
 EXTENSION : 3DNOW
+ATTRIBUTES : AMDONLY
 PATTERN   : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xA7
 OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
 }
@@ -15215,6 +15577,7 @@ ICLASS    : PFRSQIT1
 CPL       : 3
 CATEGORY  : 3DNOW
 EXTENSION : 3DNOW
+ATTRIBUTES : AMDONLY
 PATTERN   : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xA7
 OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
 }
@@ -15223,6 +15586,7 @@ ICLASS    : PFSUBR
 CPL       : 3
 CATEGORY  : 3DNOW
 EXTENSION : 3DNOW
+ATTRIBUTES : AMDONLY
 PATTERN   : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xAA
 OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
 }
@@ -15231,6 +15595,7 @@ ICLASS    : PFSUBR
 CPL       : 3
 CATEGORY  : 3DNOW
 EXTENSION : 3DNOW
+ATTRIBUTES : AMDONLY
 PATTERN   : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xAA
 OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
 }
@@ -15239,6 +15604,7 @@ ICLASS    : PFACC
 CPL       : 3
 CATEGORY  : 3DNOW
 EXTENSION : 3DNOW
+ATTRIBUTES : AMDONLY
 PATTERN   : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xAE
 OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
 }
@@ -15247,6 +15613,7 @@ ICLASS    : PFACC
 CPL       : 3
 CATEGORY  : 3DNOW
 EXTENSION : 3DNOW
+ATTRIBUTES : AMDONLY
 PATTERN   : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xAE
 OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
 }
@@ -15255,6 +15622,7 @@ ICLASS    : PFCMPEQ
 CPL       : 3
 CATEGORY  : 3DNOW
 EXTENSION : 3DNOW
+ATTRIBUTES : AMDONLY
 PATTERN   : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xB0
 OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
 }
@@ -15263,6 +15631,7 @@ ICLASS    : PFCMPEQ
 CPL       : 3
 CATEGORY  : 3DNOW
 EXTENSION : 3DNOW
+ATTRIBUTES : AMDONLY
 PATTERN   : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xB0
 OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
 }
@@ -15271,6 +15640,7 @@ ICLASS    : PFMUL
 CPL       : 3
 CATEGORY  : 3DNOW
 EXTENSION : 3DNOW
+ATTRIBUTES : AMDONLY
 PATTERN   : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xB4
 OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
 }
@@ -15279,6 +15649,7 @@ ICLASS    : PFMUL
 CPL       : 3
 CATEGORY  : 3DNOW
 EXTENSION : 3DNOW
+ATTRIBUTES : AMDONLY
 PATTERN   : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xB4
 OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
 }
@@ -15287,6 +15658,7 @@ ICLASS    : PFRCPIT2
 CPL       : 3
 CATEGORY  : 3DNOW
 EXTENSION : 3DNOW
+ATTRIBUTES : AMDONLY
 PATTERN   : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xB6
 OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
 }
@@ -15295,6 +15667,7 @@ ICLASS    : PFRCPIT2
 CPL       : 3
 CATEGORY  : 3DNOW
 EXTENSION : 3DNOW
+ATTRIBUTES : AMDONLY
 PATTERN   : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xB6
 OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
 }
@@ -15303,6 +15676,7 @@ ICLASS    : PMULHRW
 CPL       : 3
 CATEGORY  : 3DNOW
 EXTENSION : 3DNOW
+ATTRIBUTES : AMDONLY
 PATTERN   : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xB7
 OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
 }
@@ -15311,6 +15685,7 @@ ICLASS    : PMULHRW
 CPL       : 3
 CATEGORY  : 3DNOW
 EXTENSION : 3DNOW
+ATTRIBUTES : AMDONLY
 PATTERN   : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xB7
 OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
 }
@@ -15319,6 +15694,7 @@ ICLASS    : PSWAPD
 CPL       : 3
 CATEGORY  : 3DNOW
 EXTENSION : 3DNOW
+ATTRIBUTES : AMDONLY
 PATTERN   : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xBB
 OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
 }
@@ -15327,6 +15703,7 @@ ICLASS    : PSWAPD
 CPL       : 3
 CATEGORY  : 3DNOW
 EXTENSION : 3DNOW
+ATTRIBUTES : AMDONLY
 PATTERN   : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xBB
 OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
 }
@@ -15335,6 +15712,7 @@ ICLASS    : PAVGUSB
 CPL       : 3
 CATEGORY  : 3DNOW
 EXTENSION : 3DNOW
+ATTRIBUTES : AMDONLY
 PATTERN   : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xBF
 OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
 }
@@ -15343,6 +15721,7 @@ ICLASS    : PAVGUSB
 CPL       : 3
 CATEGORY  : 3DNOW
 EXTENSION : 3DNOW
+ATTRIBUTES : AMDONLY
 PATTERN   : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xBF
 OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
 }
@@ -15352,7 +15731,7 @@ OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
 
 #BEGIN_LEGAL
 #
-#Copyright (c) 2016 Intel Corporation
+#Copyright (c) 2018 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -15379,6 +15758,7 @@ CPL       : 3
 CATEGORY  : SYSCALL
 EXTENSION : BASE
 ISA_SET   : AMD
+ATTRIBUTES : AMDONLY
 FLAGS     : MUST [ id-mod vip-mod vif-mod ac-mod vm-0 rf-0 nt-mod iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
 PATTERN   : 0x0F 0x05 not64 IGNORE66()
 OPERANDS  : REG0=rIP():w:SUPP
@@ -15390,9 +15770,10 @@ ICLASS    : SYSRET_AMD
 DISASM    : sysret
 CPL       : 0
 CATEGORY  : SYSRET
-ATTRIBUTES: PROTECTED_MODE RING0
+ATTRIBUTES: PROTECTED_MODE RING0 AMDONLY
 EXTENSION : BASE
 ISA_SET   : AMD
+
 FLAGS     : MUST [ id-mod vip-mod vif-mod ac-mod rf-0 nt-mod iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
 PATTERN   : 0x0F 0x07 not64
 OPERANDS  : REG0=XED_REG_EIP:w:SUPP
@@ -15403,7 +15784,7 @@ OPERANDS  : REG0=XED_REG_EIP:w:SUPP
 
 #BEGIN_LEGAL
 #
-#Copyright (c) 2016 Intel Corporation
+#Copyright (c) 2018 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -15424,15 +15805,16 @@ ICLASS    : VMRUN
 CPL       : 3
 CATEGORY  : SYSTEM
 EXTENSION : SVM
-ATTRIBUTES: PROTECTED_MODE
+ATTRIBUTES: PROTECTED_MODE AMDONLY
 PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]
-OPERANDS  : REG0=OrAX():r:IMPL
+OPERANDS  : REG0=ArAX():r:IMPL
 }
 {
 ICLASS    : VMMCALL
 CPL       : 3
 CATEGORY  : SYSTEM
 EXTENSION : SVM
+ATTRIBUTES : AMDONLY
 PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]
 OPERANDS  :
 }
@@ -15441,16 +15823,16 @@ ICLASS    : VMLOAD
 CPL       : 3
 CATEGORY  : SYSTEM
 EXTENSION : SVM
-ATTRIBUTES: PROTECTED_MODE
+ATTRIBUTES: PROTECTED_MODE AMDONLY
 PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]
-OPERANDS  : REG0=OrAX():r:IMPL
+OPERANDS  : REG0=ArAX():r:IMPL
 }
 {
 ICLASS    : VMSAVE
 CPL       : 3
 CATEGORY  : SYSTEM
 EXTENSION : SVM
-ATTRIBUTES: PROTECTED_MODE
+ATTRIBUTES: PROTECTED_MODE AMDONLY
 PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]
 OPERANDS  :
 }
@@ -15459,7 +15841,7 @@ ICLASS    : STGI
 CPL       : 3
 CATEGORY  : SYSTEM
 EXTENSION : SVM
-ATTRIBUTES: PROTECTED_MODE
+ATTRIBUTES: PROTECTED_MODE AMDONLY
 PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]
 OPERANDS  :
 }
@@ -15468,7 +15850,7 @@ ICLASS    : CLGI
 CPL       : 3
 CATEGORY  : SYSTEM
 EXTENSION : SVM
-ATTRIBUTES: PROTECTED_MODE
+ATTRIBUTES: PROTECTED_MODE AMDONLY
 PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]
 OPERANDS  :
 }
@@ -15477,7 +15859,7 @@ ICLASS    : SKINIT
 CPL       : 3
 CATEGORY  : SYSTEM
 EXTENSION : SVM
-ATTRIBUTES: PROTECTED_MODE
+ATTRIBUTES: PROTECTED_MODE AMDONLY
 PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]
 OPERANDS  : REG0=XED_REG_EAX:r:IMPL
 }
@@ -15486,9 +15868,9 @@ ICLASS    : INVLPGA
 CPL       : 0
 CATEGORY  : SYSTEM
 EXTENSION : SVM
-ATTRIBUTES: PROTECTED_MODE
+ATTRIBUTES: PROTECTED_MODE AMDONLY
 PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]
-OPERANDS  : REG0=OrAX():r:IMPL REG1=XED_REG_ECX:r:IMPL
+OPERANDS  : REG0=ArAX():r:IMPL REG1=XED_REG_ECX:r:IMPL
 }
 
 
@@ -15496,7 +15878,7 @@ OPERANDS  : REG0=OrAX():r:IMPL REG1=XED_REG_ECX:r:IMPL
 
 #BEGIN_LEGAL
 #
-#Copyright (c) 2016 Intel Corporation
+#Copyright (c) 2018 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -15519,9 +15901,9 @@ ICLASS    : EXTRQ
 CPL       : 3
 CATEGORY  : BITBYTE
 EXTENSION : SSE4a
-ATTRIBUTES : ATT_OPERAND_ORDER_EXCEPTION
+ATTRIBUTES : ATT_OPERAND_ORDER_EXCEPTION AMDONLY
 PATTERN   : 0x0F 0x78 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM8() UIMM8_1()
-OPERANDS  : REG0=XMM_R():w:q      IMM0:r:b IMM1:r:b
+OPERANDS  : REG0=XMM_B():w:q      IMM0:r:b IMM1:r:b
 PATTERN   : 0x0F 0x79 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
 OPERANDS  : REG0=XMM_R():w:q      REG1=XMM_B():r:dq
 }
@@ -15534,7 +15916,7 @@ ICLASS    : INSERTQ
 CPL       : 3
 CATEGORY  : BITBYTE
 EXTENSION : SSE4a
-ATTRIBUTES : ATT_OPERAND_ORDER_EXCEPTION
+ATTRIBUTES : ATT_OPERAND_ORDER_EXCEPTION AMDONLY
 PATTERN   : 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1()
 OPERANDS  : REG0=XMM_R():w:q      REG1=XMM_B():r:q    IMM0:r:b IMM1:r:b
 PATTERN   : 0x0F 0x79 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
@@ -15550,6 +15932,7 @@ ICLASS    : MOVNTSD
 CPL       : 3
 CATEGORY  : DATAXFER
 EXTENSION : SSE4a
+ATTRIBUTES: NONTEMPORAL AMDONLY
 PATTERN   : 0x0F 0x2B f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS  : MEM0:w:q      REG0=XMM_R():r:q
 }
@@ -15558,6 +15941,7 @@ ICLASS    : MOVNTSS
 CPL       : 3
 CATEGORY  : DATAXFER
 EXTENSION : SSE4a
+ATTRIBUTES: NONTEMPORAL AMDONLY
 PATTERN   : 0x0F 0x2B f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS  : MEM0:w:d      REG0=XMM_R():r:d
 }
@@ -15603,7 +15987,7 @@ OPERANDS  : REG0=GPRv_R():cw REG1=GPRv_B():r
 
 #BEGIN_LEGAL
 #
-#Copyright (c) 2016 Intel Corporation
+#Copyright (c) 2018 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -15624,17 +16008,71 @@ ICLASS    : CLZERO
 CPL       : 3
 CATEGORY  : CLZERO
 EXTENSION : CLZERO
+ATTRIBUTES : AMDONLY
+
 PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]
-OPERANDS  : REG0=OrAX():r:IMPL
+OPERANDS  : REG0=ArAX():r:SUPP
 COMMENT   : AMD "Zen" ~2016 (expected) CPU
 }
 
 
+###FILE: ../xed/datafiles/xed-amd-monitorx.txt
+
+#BEGIN_LEGAL
+#
+#Copyright (c) 2018 Intel Corporation
+#
+#  Licensed under the Apache License, Version 2.0 (the "License");
+#  you may not use this file except in compliance with the License.
+#  You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+#  Unless required by applicable law or agreed to in writing, software
+#  distributed under the License is distributed on an "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#  See the License for the specific language governing permissions and
+#  limitations under the License.
+#
+#END_LEGAL
+
+{
+ICLASS    : MONITORX
+CPL       : 3
+CATEGORY  : MISC
+EXTENSION : MONITORX
+ISA_SET   : MONITORX
+ATTRIBUTES: AMDONLY
+
+PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b010] no_refining_prefix not64 eamode32
+OPERANDS  : REG0=XED_REG_EAX:r:SUPP REG1=XED_REG_ECX:r:SUPP REG2=XED_REG_EDX:r:SUPP
+
+PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b010] no_refining_prefix not64 eamode16
+OPERANDS  : REG0=XED_REG_AX:r:SUPP REG1=XED_REG_ECX:r:SUPP REG2=XED_REG_EDX:r:SUPP
+
+PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b010] no_refining_prefix mode64 eamode64
+OPERANDS  : REG0=XED_REG_RAX:r:SUPP REG1=XED_REG_ECX:r:SUPP REG2=XED_REG_EDX:r:SUPP
+
+PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b010] no_refining_prefix mode64 eamode32
+OPERANDS  : REG0=XED_REG_EAX:r:SUPP REG1=XED_REG_ECX:r:SUPP REG2=XED_REG_EDX:r:SUPP
+}
+{
+ICLASS    : MWAITX
+CPL       : 3
+CATEGORY  : MISC
+EXTENSION : MONITORX
+ISA_SET   : MONITORX
+ATTRIBUTES: AMDONLY
+PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b011] no_refining_prefix
+OPERANDS  : REG0=XED_REG_EAX:rw:SUPP REG1=XED_REG_ECX:r:SUPP
+}
+
+
 ###FILE: ../xed/datafiles/amdxop/amd-xop-isa.txt
 
 #BEGIN_LEGAL
 #
-#Copyright (c) 2016 Intel Corporation
+#Copyright (c) 2018 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -15657,6 +16095,7 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
 PATTERN: XOPV 0x85 VNP W0 VL128  XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
 OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i16
@@ -15671,6 +16110,7 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
 PATTERN: XOPV 0x86 VNP W0 VL128  XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
 OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i32
@@ -15685,6 +16125,7 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
 PATTERN: XOPV 0x87 VNP W0 VL128  XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
 OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 REG2=XMM_SE():r:dq:i64
@@ -15699,6 +16140,7 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
 PATTERN: XOPV 0x95 VNP W0 VL128  XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
 OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i16
@@ -15713,6 +16155,7 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
 PATTERN: XOPV 0x96 VNP W0 VL128  XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
 OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i32
@@ -15727,6 +16170,7 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
 PATTERN: XOPV 0x97 VNP W0 VL128  XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
 OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 REG2=XMM_SE():r:dq:i64
@@ -15741,6 +16185,7 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
 PATTERN: XOPV 0xA2 VNP W0 VL128  XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
 OPERANDS: REG0=XMM_R():w:dq:i1 REG1=XMM_N():r:dq:i1 MEM0:r:dq:i1 REG2=XMM_SE():r:dq:i1
@@ -15773,6 +16218,7 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
 PATTERN: XOPV 0xA3 VNP W0 VL128  XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
 OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i16
@@ -15793,6 +16239,7 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
 PATTERN: XOPV 0xA6 VNP W0 VL128  XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
 OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i32
@@ -15807,6 +16254,7 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
 PATTERN: XOPV 0xB6 VNP W0 VL128  XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
 OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i32
@@ -15821,6 +16269,7 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
 PATTERN: XOPV 0xC0 VNP W0 VL128 NOVSR XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
 OPERANDS: REG0=XMM_R():w:dq:u8 MEM0:r:dq:u8 IMM0:r:b:u8
@@ -15835,12 +16284,13 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
 PATTERN: XOPV 0xC1 VNP W0 VL128 NOVSR XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
-OPERANDS: REG0=XMM_R():w:dq:u16 MEM0:r:dq:u16 IMM0:r:b:u16
+OPERANDS: REG0=XMM_R():w:dq:u16 MEM0:r:dq:u16 IMM0:r:b:u8
 
 PATTERN: XOPV 0xC1 VNP W0 VL128 NOVSR XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
-OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:dq:u16 IMM0:r:b:u16
+OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:dq:u16 IMM0:r:b:u8
 }
 
 {
@@ -15849,12 +16299,13 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
 PATTERN: XOPV 0xC2 VNP W0 VL128 NOVSR XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
-OPERANDS: REG0=XMM_R():w:dq:u32 MEM0:r:dq:u32 IMM0:r:b:u32
+OPERANDS: REG0=XMM_R():w:dq:u32 MEM0:r:dq:u32 IMM0:r:b:u8
 
 PATTERN: XOPV 0xC2 VNP W0 VL128 NOVSR XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
-OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:dq:u32 IMM0:r:b:u32
+OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:dq:u32 IMM0:r:b:u8
 }
 
 {
@@ -15863,12 +16314,13 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
 PATTERN: XOPV 0xC3 VNP W0 VL128 NOVSR XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
-OPERANDS: REG0=XMM_R():w:dq:u64 MEM0:r:dq:u64 IMM0:r:b:u64
+OPERANDS: REG0=XMM_R():w:dq:u64 MEM0:r:dq:u64 IMM0:r:b:u8
 
 PATTERN: XOPV 0xC3 VNP W0 VL128 NOVSR XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
-OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:dq:u64 IMM0:r:b:u64
+OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:dq:u64 IMM0:r:b:u8
 }
 
 {
@@ -15877,6 +16329,7 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
 PATTERN: XOPV 0x8E VNP W0 VL128  XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
 OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 REG2=XMM_SE():r:dq:i32
@@ -15891,6 +16344,7 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
 PATTERN: XOPV 0x8F VNP W0 VL128  XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
 OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 REG2=XMM_SE():r:dq:i64
@@ -15905,6 +16359,7 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
 PATTERN: XOPV 0x9E VNP W0 VL128  XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
 OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 REG2=XMM_SE():r:dq:i32
@@ -15919,6 +16374,7 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
 PATTERN: XOPV 0x9F VNP W0 VL128  XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
 OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 REG2=XMM_SE():r:dq:i64
@@ -15933,12 +16389,13 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
 PATTERN: XOPV 0xCC VNP W0 VL128  XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
-OPERANDS: REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 IMM0:r:b:i8
+OPERANDS: REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 IMM0:r:b:u8
 
 PATTERN: XOPV 0xCC VNP W0 VL128  XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
-OPERANDS: REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 IMM0:r:b:i8
+OPERANDS: REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 IMM0:r:b:u8
 }
 
 {
@@ -15947,12 +16404,13 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
 PATTERN: XOPV 0xCD VNP W0 VL128  XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
-OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 IMM0:r:b:i16
+OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 IMM0:r:b:u8
 
 PATTERN: XOPV 0xCD VNP W0 VL128  XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
-OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 IMM0:r:b:i16
+OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 IMM0:r:b:u8
 }
 
 {
@@ -15961,12 +16419,13 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
 PATTERN: XOPV 0xCE VNP W0 VL128  XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
-OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 IMM0:r:b:i32
+OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 IMM0:r:b:u8
 
 PATTERN: XOPV 0xCE VNP W0 VL128  XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
-OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 IMM0:r:b:i32
+OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 IMM0:r:b:u8
 }
 
 {
@@ -15975,12 +16434,13 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
 PATTERN: XOPV 0xCF VNP W0 VL128  XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
-OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 MEM0:r:dq:i64 IMM0:r:b:i64
+OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 MEM0:r:dq:i64 IMM0:r:b:u8
 
 PATTERN: XOPV 0xCF VNP W0 VL128  XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
-OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 REG2=XMM_B():r:dq:i64 IMM0:r:b:i64
+OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 REG2=XMM_B():r:dq:i64 IMM0:r:b:u8
 }
 
 {
@@ -15989,6 +16449,7 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
 PATTERN: XOPV 0xEC VNP W0 VL128  XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
 OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 IMM0:r:b:u8
@@ -16003,12 +16464,13 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
 PATTERN: XOPV 0xED VNP W0 VL128  XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
-OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 IMM0:r:b:u16
+OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 IMM0:r:b:u8
 
 PATTERN: XOPV 0xED VNP W0 VL128  XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
-OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 IMM0:r:b:u16
+OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 IMM0:r:b:u8
 }
 
 {
@@ -16017,12 +16479,13 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
 PATTERN: XOPV 0xEE VNP W0 VL128  XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
-OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 IMM0:r:b:u32
+OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 IMM0:r:b:u8
 
 PATTERN: XOPV 0xEE VNP W0 VL128  XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
-OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 IMM0:r:b:u32
+OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 IMM0:r:b:u8
 }
 
 {
@@ -16031,12 +16494,13 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
 PATTERN: XOPV 0xEF VNP W0 VL128  XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
-OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 IMM0:r:b:u64
+OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 IMM0:r:b:u8
 
 PATTERN: XOPV 0xEF VNP W0 VL128  XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
-OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 IMM0:r:b:u64
+OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 IMM0:r:b:u8
 }
 
 {
@@ -16045,7 +16509,7 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
-ATTRIBUTES:  MXCSR
+ATTRIBUTES:  MXCSR AMDONLY
 
 PATTERN: XOPV 0x80 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS: REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32
@@ -16066,7 +16530,7 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
-ATTRIBUTES:  MXCSR
+ATTRIBUTES:  MXCSR AMDONLY
 
 PATTERN: XOPV 0x81 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS: REG0=XMM_R():w:dq:f64 MEM0:r:dq:f64
@@ -16087,7 +16551,7 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
-ATTRIBUTES: SIMD_SCALAR  MXCSR
+ATTRIBUTES: SIMD_SCALAR  MXCSR AMDONLY
 
 PATTERN: XOPV 0x82 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS: REG0=XMM_R():w:dq:f32 MEM0:r:d:f32
@@ -16102,7 +16566,7 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
-ATTRIBUTES: SIMD_SCALAR  MXCSR
+ATTRIBUTES: SIMD_SCALAR  MXCSR AMDONLY
 
 PATTERN: XOPV 0x83 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS: REG0=XMM_R():w:dq:f64 MEM0:r:q:f64
@@ -16117,6 +16581,7 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
 PATTERN: XOPV 0x90 VNP W0 VL128  XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS: REG0=XMM_R():w:dq:u8 MEM0:r:dq:u8 REG1=XMM_N():r:dq:u8
@@ -16137,6 +16602,7 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
 PATTERN: XOPV 0x91 VNP W0 VL128  XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS: REG0=XMM_R():w:dq:u16 MEM0:r:dq:u16 REG1=XMM_N():r:dq:u16
@@ -16157,6 +16623,7 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
 PATTERN: XOPV 0x92 VNP W0 VL128  XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS: REG0=XMM_R():w:dq:u32 MEM0:r:dq:u32 REG1=XMM_N():r:dq:u32
@@ -16177,6 +16644,7 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
 PATTERN: XOPV 0x93 VNP W0 VL128  XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS: REG0=XMM_R():w:dq:u64 MEM0:r:dq:u64 REG1=XMM_N():r:dq:u64
@@ -16197,6 +16665,7 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
 PATTERN: XOPV 0x94 VNP W0 VL128  XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS: REG0=XMM_R():w:dq:u8 MEM0:r:dq:u8 REG1=XMM_N():r:dq:u8
@@ -16217,6 +16686,7 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
 PATTERN: XOPV 0x95 VNP W0 VL128  XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS: REG0=XMM_R():w:dq:u16 MEM0:r:dq:u16 REG1=XMM_N():r:dq:u16
@@ -16237,6 +16707,7 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
 PATTERN: XOPV 0x96 VNP W0 VL128  XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS: REG0=XMM_R():w:dq:u32 MEM0:r:dq:u32 REG1=XMM_N():r:dq:u32
@@ -16257,6 +16728,7 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
 PATTERN: XOPV 0x97 VNP W0 VL128  XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS: REG0=XMM_R():w:dq:u64 MEM0:r:dq:u64 REG1=XMM_N():r:dq:u64
@@ -16277,6 +16749,7 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
 PATTERN: XOPV 0xC1 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS: REG0=XMM_R():w:dq:i8 MEM0:r:dq:i8
@@ -16291,6 +16764,7 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
 PATTERN: XOPV 0xC2 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS: REG0=XMM_R():w:dq:i32 MEM0:r:dq:i8
@@ -16305,6 +16779,7 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
 PATTERN: XOPV 0xC3 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS: REG0=XMM_R():w:dq:i64 MEM0:r:dq:i8
@@ -16319,6 +16794,7 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
 PATTERN: XOPV 0xC6 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS: REG0=XMM_R():w:dq:i32 MEM0:r:dq:i16
@@ -16333,6 +16809,7 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
 PATTERN: XOPV 0xC7 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS: REG0=XMM_R():w:dq:i64 MEM0:r:dq:i16
@@ -16347,6 +16824,7 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
 PATTERN: XOPV 0xD1 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS: REG0=XMM_R():w:dq:u16 MEM0:r:dq:u8
@@ -16361,6 +16839,7 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
 PATTERN: XOPV 0xD2 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS: REG0=XMM_R():w:dq:u32 MEM0:r:dq:u8
@@ -16375,6 +16854,7 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
 PATTERN: XOPV 0xD3 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS: REG0=XMM_R():w:dq:u64 MEM0:r:dq:u8
@@ -16389,6 +16869,7 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
 PATTERN: XOPV 0xD6 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS: REG0=XMM_R():w:dq:u32 MEM0:r:dq:u16
@@ -16403,6 +16884,7 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
 PATTERN: XOPV 0xD7 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS: REG0=XMM_R():w:dq:u64 MEM0:r:dq:u16
@@ -16417,6 +16899,7 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
 PATTERN: XOPV 0xE1 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS: REG0=XMM_R():w:dq:i16 MEM0:r:dq:i8
@@ -16431,6 +16914,7 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
 PATTERN: XOPV 0xE2 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS: REG0=XMM_R():w:dq:i32 MEM0:r:dq:i16
@@ -16445,6 +16929,7 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
 PATTERN: XOPV 0xE3 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS: REG0=XMM_R():w:dq:i64 MEM0:r:dq:i32
@@ -16459,6 +16944,7 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
 PATTERN: XOPV 0x98 VNP W0 VL128  XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS: REG0=XMM_R():w:dq:i8 MEM0:r:dq:i8 REG1=XMM_N():r:dq:i8
@@ -16479,6 +16965,7 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
 PATTERN: XOPV 0x99 VNP W0 VL128  XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS: REG0=XMM_R():w:dq:i16 MEM0:r:dq:i16 REG1=XMM_N():r:dq:i16
@@ -16499,6 +16986,7 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
 PATTERN: XOPV 0x9A VNP W0 VL128  XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS: REG0=XMM_R():w:dq:i32 MEM0:r:dq:i32 REG1=XMM_N():r:dq:i32
@@ -16519,6 +17007,7 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
 PATTERN: XOPV 0x9B VNP W0 VL128  XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS: REG0=XMM_R():w:dq:i64 MEM0:r:dq:i64 REG1=XMM_N():r:dq:i64
@@ -16539,6 +17028,7 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
 PATTERN: XOPV 0xCB VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS: REG0=XMM_R():w:dq:i64 MEM0:r:dq:i32
@@ -16553,6 +17043,7 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
 PATTERN: XOPV 0xDB VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS: REG0=XMM_R():w:dq:u64 MEM0:r:dq:u32
@@ -16563,16 +17054,23 @@ OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:dq:u32
 
 {
 ICLASS: BEXTR_XOP
+DISASM: bextr
 CPL: 3
 CATEGORY: TBM
 ISA_SET: TBM
 EXTENSION: TBM
+ATTRIBUTES: AMDONLY
+
 FLAGS: MUST [ cf-0 pf-u af-u zf-mod sf-u of-0 ]
 
-PATTERN: XOPV 0x10 VNP W0 VL128 NOVSR XMAPA MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM32()
+PATTERN: XOPV 0x10 VNP not64 VL128 NOVSR XMAPA MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM32()
+OPERANDS: REG0=GPR32_R():w:d MEM0:r:d IMM0:r:d
+PATTERN: XOPV 0x10 VNP mode64  VL128 NOVSR XMAPA MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM32()
 OPERANDS: REG0=GPRy_R():w:y MEM0:r:y IMM0:r:d
 
-PATTERN: XOPV 0x10 VNP W0 VL128 NOVSR XMAPA MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM32()
+PATTERN: XOPV 0x10 VNP not64 VL128 NOVSR XMAPA MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM32()
+OPERANDS: REG0=GPR32_R():w:d REG1=GPR32_B():r:d IMM0:r:d
+PATTERN: XOPV 0x10 VNP mode64 VL128 NOVSR XMAPA MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM32()
 OPERANDS: REG0=GPRy_R():w:y REG1=GPRy_B():r:y IMM0:r:d
 }
 
@@ -16582,13 +17080,19 @@ CPL: 3
 CATEGORY: TBM
 ISA_SET: TBM
 EXTENSION: TBM
+ATTRIBUTES: AMDONLY
+
 FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ]
 
-PATTERN: XOPV 0x01 VNP W0 VL128  XMAP9 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()
-OPERANDS: REG0=GPRy_N():w:y MEM0:r:y
+PATTERN: XOPV 0x01 VNP not64 VL128  XMAP9 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()
+OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d
+PATTERN: XOPV 0x01 VNP mode64 VL128  XMAP9 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()
+OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y
 
-PATTERN: XOPV 0x01 VNP W0 VL128  XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]
-OPERANDS: REG0=GPRy_N():w:y REG1=GPRv_B():r:y
+PATTERN: XOPV 0x01 VNP not64 VL128  XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]
+OPERANDS: REG0=VGPR32_N():w:d REG1=GPR32_B():r:d
+PATTERN: XOPV 0x01 VNP mode64 VL128  XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]
+OPERANDS: REG0=VGPRy_N():w:y REG1=GPRy_B():r:y
 }
 
 {
@@ -16597,13 +17101,19 @@ CPL: 3
 CATEGORY: TBM
 ISA_SET: TBM
 EXTENSION: TBM
+ATTRIBUTES: AMDONLY
+
 FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ]
 
-PATTERN: XOPV 0x01 VNP W0 VL128  XMAP9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()
-OPERANDS: REG0=GPRy_N():w:y MEM0:r:y
+PATTERN: XOPV 0x01 VNP not64 VL128  XMAP9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()
+OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d
+PATTERN: XOPV 0x01 VNP mode64 VL128  XMAP9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()
+OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y
 
-PATTERN: XOPV 0x01 VNP W0 VL128  XMAP9 MOD[0b11] MOD=3 REG[0b010] RM[nnn]
-OPERANDS: REG0=GPRy_N():w:y REG1=GPRv_B():r:y
+PATTERN: XOPV 0x01 VNP not64 VL128  XMAP9 MOD[0b11] MOD=3 REG[0b010] RM[nnn]
+OPERANDS: REG0=VGPR32_N():w:d REG1=GPR32_B():r:d
+PATTERN: XOPV 0x01 VNP mode64 VL128  XMAP9 MOD[0b11] MOD=3 REG[0b010] RM[nnn]
+OPERANDS: REG0=VGPRy_N():w:y REG1=GPRy_B():r:y
 }
 
 {
@@ -16612,13 +17122,19 @@ CPL: 3
 CATEGORY: TBM
 ISA_SET: TBM
 EXTENSION: TBM
+ATTRIBUTES: AMDONLY
+
 FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ]
 
-PATTERN: XOPV 0x01 VNP W0 VL128  XMAP9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()
-OPERANDS: REG0=GPRy_N():w:y MEM0:r:y
+PATTERN: XOPV 0x01 VNP not64 VL128  XMAP9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()
+OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d
+PATTERN: XOPV 0x01 VNP mode64 VL128  XMAP9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()
+OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y
 
-PATTERN: XOPV 0x01 VNP W0 VL128  XMAP9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]
-OPERANDS: REG0=GPRy_N():w:y REG1=GPRv_B():r:y
+PATTERN: XOPV 0x01 VNP not64 VL128  XMAP9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]
+OPERANDS: REG0=VGPR32_N():w:d REG1=GPR32_B():r:d
+PATTERN: XOPV 0x01 VNP mode64 VL128  XMAP9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]
+OPERANDS: REG0=VGPRy_N():w:y REG1=GPRy_B():r:y
 }
 
 {
@@ -16627,13 +17143,19 @@ CPL: 3
 CATEGORY: TBM
 ISA_SET: TBM
 EXTENSION: TBM
+ATTRIBUTES: AMDONLY
+
 FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ]
 
-PATTERN: XOPV 0x01 VNP W0 VL128  XMAP9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()
-OPERANDS: REG0=GPRy_N():w:y MEM0:r:y
+PATTERN: XOPV 0x01 VNP not64 VL128  XMAP9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()
+OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d
+PATTERN: XOPV 0x01 VNP mode64 VL128  XMAP9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()
+OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y
 
-PATTERN: XOPV 0x01 VNP W0 VL128  XMAP9 MOD[0b11] MOD=3 REG[0b100] RM[nnn]
-OPERANDS: REG0=GPRy_N():w:y REG1=GPRv_B():r:y
+PATTERN: XOPV 0x01 VNP not64 VL128  XMAP9 MOD[0b11] MOD=3 REG[0b100] RM[nnn]
+OPERANDS: REG0=VGPR32_N():w:d REG1=GPR32_B():r:d
+PATTERN: XOPV 0x01 VNP mode64 VL128  XMAP9 MOD[0b11] MOD=3 REG[0b100] RM[nnn]
+OPERANDS: REG0=VGPRy_N():w:y REG1=GPRy_B():r:y
 }
 
 {
@@ -16642,13 +17164,19 @@ CPL: 3
 CATEGORY: TBM
 ISA_SET: TBM
 EXTENSION: TBM
+ATTRIBUTES: AMDONLY
+
 FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ]
 
-PATTERN: XOPV 0x01 VNP W0 VL128  XMAP9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()
-OPERANDS: REG0=GPRy_N():w:y MEM0:r:y
+PATTERN: XOPV 0x01 VNP not64 VL128  XMAP9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()
+OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d
+PATTERN: XOPV 0x01 VNP mode64 VL128  XMAP9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()
+OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y
 
-PATTERN: XOPV 0x01 VNP W0 VL128  XMAP9 MOD[0b11] MOD=3 REG[0b101] RM[nnn]
-OPERANDS: REG0=GPRy_N():w:y REG1=GPRv_B():r:y
+PATTERN: XOPV 0x01 VNP not64 VL128  XMAP9 MOD[0b11] MOD=3 REG[0b101] RM[nnn]
+OPERANDS: REG0=VGPR32_N():w:d REG1=GPR32_B():r:d
+PATTERN: XOPV 0x01 VNP mode64 VL128  XMAP9 MOD[0b11] MOD=3 REG[0b101] RM[nnn]
+OPERANDS: REG0=VGPRy_N():w:y REG1=GPRy_B():r:y
 }
 
 {
@@ -16657,13 +17185,19 @@ CPL: 3
 CATEGORY: TBM
 ISA_SET: TBM
 EXTENSION: TBM
+ATTRIBUTES: AMDONLY
+
 FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ]
 
-PATTERN: XOPV 0x01 VNP W0 VL128  XMAP9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()
-OPERANDS: REG0=GPRy_N():w:y MEM0:r:y
+PATTERN: XOPV 0x01 VNP not64 VL128  XMAP9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()
+OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d
+PATTERN: XOPV 0x01 VNP mode64 VL128  XMAP9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()
+OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y
 
-PATTERN: XOPV 0x01 VNP W0 VL128  XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn]
-OPERANDS: REG0=GPRy_N():w:y REG1=GPRv_B():r:y
+PATTERN: XOPV 0x01 VNP not64 VL128  XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn]
+OPERANDS: REG0=VGPR32_N():w:d REG1=GPR32_B():r:d
+PATTERN: XOPV 0x01 VNP mode64 VL128  XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn]
+OPERANDS: REG0=VGPRy_N():w:y REG1=GPRy_B():r:y
 }
 
 {
@@ -16672,13 +17206,19 @@ CPL: 3
 CATEGORY: TBM
 ISA_SET: TBM
 EXTENSION: TBM
+ATTRIBUTES: AMDONLY
+
 FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ]
 
-PATTERN: XOPV 0x01 VNP W0 VL128  XMAP9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()
-OPERANDS: REG0=GPRy_N():w:y MEM0:r:y
+PATTERN: XOPV 0x01 VNP not64 VL128  XMAP9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()
+OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d
+PATTERN: XOPV 0x01 VNP mode64 VL128  XMAP9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()
+OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y
 
-PATTERN: XOPV 0x01 VNP W0 VL128  XMAP9 MOD[0b11] MOD=3 REG[0b111] RM[nnn]
-OPERANDS: REG0=GPRy_N():w:y REG1=GPRv_B():r:y
+PATTERN: XOPV 0x01 VNP not64 VL128  XMAP9 MOD[0b11] MOD=3 REG[0b111] RM[nnn]
+OPERANDS: REG0=VGPR32_N():w:d REG1=GPR32_B():r:d
+PATTERN: XOPV 0x01 VNP mode64 VL128  XMAP9 MOD[0b11] MOD=3 REG[0b111] RM[nnn]
+OPERANDS: REG0=VGPRy_N():w:y REG1=GPRy_B():r:y
 }
 
 {
@@ -16687,13 +17227,19 @@ CPL: 3
 CATEGORY: TBM
 ISA_SET: TBM
 EXTENSION: TBM
+ATTRIBUTES: AMDONLY
+
 FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ]
 
-PATTERN: XOPV 0x02 VNP W0 VL128  XMAP9 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()
-OPERANDS: REG0=GPRy_N():w:y MEM0:r:y
+PATTERN: XOPV 0x02 VNP not64 VL128  XMAP9 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()
+OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d
+PATTERN: XOPV 0x02 VNP mode64 VL128  XMAP9 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()
+OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y
 
-PATTERN: XOPV 0x02 VNP W0 VL128  XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]
-OPERANDS: REG0=GPRy_N():w:y REG1=GPRv_B():r:y
+PATTERN: XOPV 0x02 VNP not64 VL128  XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]
+OPERANDS: REG0=VGPR32_N():w:d REG1=GPR32_B():r:d
+PATTERN: XOPV 0x02 VNP mode64 VL128  XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]
+OPERANDS: REG0=VGPRy_N():w:y REG1=GPRy_B():r:y
 }
 
 {
@@ -16702,13 +17248,19 @@ CPL: 3
 CATEGORY: TBM
 ISA_SET: TBM
 EXTENSION: TBM
+ATTRIBUTES: AMDONLY
+
 FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ]
 
-PATTERN: XOPV 0x02 VNP W0 VL128  XMAP9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()
-OPERANDS: REG0=GPRy_N():w:y MEM0:r:y
+PATTERN: XOPV 0x02 VNP not64 VL128  XMAP9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()
+OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d
+PATTERN: XOPV 0x02 VNP mode64 VL128  XMAP9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()
+OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y
 
-PATTERN: XOPV 0x02 VNP W0 VL128  XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn]
-OPERANDS: REG0=GPRy_N():w:y REG1=GPRv_B():r:y
+PATTERN: XOPV 0x02 VNP not64 VL128  XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn]
+OPERANDS: REG0=VGPR32_N():w:d REG1=GPR32_B():r:d
+PATTERN: XOPV 0x02 VNP mode64 VL128  XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn]
+OPERANDS: REG0=VGPRy_N():w:y REG1=GPRy_B():r:y
 }
 
 {
@@ -16717,8 +17269,9 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
-PATTERN: XOPV 0x12 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]
+PATTERN: XOPV 0x12 VNP VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]
 OPERANDS: REG0=GPRy_B():w:y
 }
 
@@ -16728,8 +17281,9 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
-PATTERN: XOPV 0x12 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]
+PATTERN: XOPV 0x12 VNP VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]
 OPERANDS: REG0=GPRy_B():w:y
 }
 
@@ -16739,13 +17293,15 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
+
 FLAGS: MUST [ cf-mod ]
 
-PATTERN: XOPV 0x12 VNP W0 VL128  XMAPA MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() UIMM32()
-OPERANDS: REG0=GPRy_N():w:y MEM0:r:d IMM0:r:d
+PATTERN: XOPV 0x12 VNP  VL128  XMAPA MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() UIMM32()
+OPERANDS: REG0=VGPRy_N():w:y MEM0:r:d IMM0:r:d
 
-PATTERN: XOPV 0x12 VNP W0 VL128  XMAPA MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM32()
-OPERANDS: REG0=GPRy_N():w:y REG1=GPRv_B():r:d IMM0:r:d
+PATTERN: XOPV 0x12 VNP  VL128  XMAPA MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM32()
+OPERANDS: REG0=VGPRy_N():w:y REG1=GPR32_B():r:y IMM0:r:d
 }
 
 {
@@ -16754,12 +17310,13 @@ CPL: 3
 CATEGORY: XOP
 ISA_SET: XOP
 EXTENSION: XOP
+ATTRIBUTES: AMDONLY
 
-PATTERN: XOPV 0x12 VNP W0 VL128  XMAPA MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() UIMM32()
-OPERANDS: REG0=GPRy_N():w:y MEM0:r:d IMM0:r:d
+PATTERN: XOPV 0x12 VNP VL128  XMAPA MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() UIMM32()
+OPERANDS: REG0=VGPRy_N():w:y MEM0:r:d IMM0:r:d
 
-PATTERN: XOPV 0x12 VNP W0 VL128  XMAPA MOD[0b11] MOD=3 REG[0b001] RM[nnn] UIMM32()
-OPERANDS: REG0=GPRy_N():w:y REG1=GPRv_B():r:d IMM0:r:d
+PATTERN: XOPV 0x12 VNP VL128  XMAPA MOD[0b11] MOD=3 REG[0b001] RM[nnn] UIMM32()
+OPERANDS: REG0=VGPRy_N():w:y REG1=GPR32_B():r:y IMM0:r:d
 }
 
 
@@ -16767,7 +17324,7 @@ OPERANDS: REG0=GPRy_N():w:y REG1=GPRv_B():r:d IMM0:r:d
 
 #BEGIN_LEGAL
 #
-#Copyright (c) 2016 Intel Corporation
+#Copyright (c) 2018 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -16790,7 +17347,7 @@ CPL: 3
 CATEGORY: FMA4
 ISA_SET: FMA4
 EXTENSION: FMA4
-ATTRIBUTES: MXCSR
+ATTRIBUTES: MXCSR AMDONLY
 
 PATTERN: VV1 0x5C V66 W0 VL128  V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:f32
@@ -16823,7 +17380,7 @@ CPL: 3
 CATEGORY: FMA4
 ISA_SET: FMA4
 EXTENSION: FMA4
-ATTRIBUTES: MXCSR
+ATTRIBUTES: MXCSR AMDONLY
 
 PATTERN: VV1 0x5D V66 W0 VL128  V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:f64
@@ -16856,7 +17413,7 @@ CPL: 3
 CATEGORY: FMA4
 ISA_SET: FMA4
 EXTENSION: FMA4
-ATTRIBUTES: MXCSR
+ATTRIBUTES: MXCSR AMDONLY
 
 PATTERN: VV1 0x5E V66 W0 VL128  V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:f32
@@ -16889,7 +17446,7 @@ CPL: 3
 CATEGORY: FMA4
 ISA_SET: FMA4
 EXTENSION: FMA4
-ATTRIBUTES: MXCSR
+ATTRIBUTES: MXCSR AMDONLY
 
 PATTERN: VV1 0x5F V66 W0 VL128  V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:f64
@@ -16922,7 +17479,7 @@ CPL: 3
 CATEGORY: FMA4
 ISA_SET: FMA4
 EXTENSION: FMA4
-ATTRIBUTES: MXCSR
+ATTRIBUTES: MXCSR AMDONLY
 
 PATTERN: VV1 0x68 V66 W0 VL128  V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:f32
@@ -16955,7 +17512,7 @@ CPL: 3
 CATEGORY: FMA4
 ISA_SET: FMA4
 EXTENSION: FMA4
-ATTRIBUTES: MXCSR
+ATTRIBUTES: MXCSR AMDONLY
 
 PATTERN: VV1 0x69 V66 W0 VL128  V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:f64
@@ -16988,19 +17545,19 @@ CPL: 3
 CATEGORY: FMA4
 ISA_SET: FMA4
 EXTENSION: FMA4
-ATTRIBUTES: SIMD_SCALAR MXCSR
+ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY
 
 PATTERN: VV1 0x6A V66 W0  V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
-OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 REG2=XMM_SE():r:dq:f32
+OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 REG2=XMM_SE():r:d:f32
 
 PATTERN: VV1 0x6A V66 W0  V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
-OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 REG3=XMM_SE():r:dq:f32
+OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 REG3=XMM_SE():r:d:f32
 
 PATTERN: VV1 0x6A V66 W1  V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
-OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:d:f32
+OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_SE():r:d:f32 MEM0:r:d:f32
 
 PATTERN: VV1 0x6A V66 W1  V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
-OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:d:f32
+OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_SE():r:d:f32 REG3=XMM_B():r:d:f32
 }
 
 {
@@ -17009,19 +17566,19 @@ CPL: 3
 CATEGORY: FMA4
 ISA_SET: FMA4
 EXTENSION: FMA4
-ATTRIBUTES: SIMD_SCALAR MXCSR
+ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY
 
 PATTERN: VV1 0x6B V66 W0  V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
-OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 REG2=XMM_SE():r:dq:f64
+OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 REG2=XMM_SE():r:q:f64
 
 PATTERN: VV1 0x6B V66 W0  V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
-OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 REG3=XMM_SE():r:dq:f64
+OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 REG3=XMM_SE():r:q:f64
 
 PATTERN: VV1 0x6B V66 W1  V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
-OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:q:f64
+OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_SE():r:q:f64 MEM0:r:q:f64
 
 PATTERN: VV1 0x6B V66 W1  V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
-OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:q:f64
+OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_SE():r:q:f64 REG3=XMM_B():r:q:f64
 }
 
 {
@@ -17030,7 +17587,7 @@ CPL: 3
 CATEGORY: FMA4
 ISA_SET: FMA4
 EXTENSION: FMA4
-ATTRIBUTES: MXCSR
+ATTRIBUTES: MXCSR AMDONLY
 
 PATTERN: VV1 0x6C V66 W0 VL128  V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:f32
@@ -17063,7 +17620,7 @@ CPL: 3
 CATEGORY: FMA4
 ISA_SET: FMA4
 EXTENSION: FMA4
-ATTRIBUTES: MXCSR
+ATTRIBUTES: MXCSR AMDONLY
 
 PATTERN: VV1 0x6D V66 W0 VL128  V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:f64
@@ -17096,19 +17653,19 @@ CPL: 3
 CATEGORY: FMA4
 ISA_SET: FMA4
 EXTENSION: FMA4
-ATTRIBUTES: SIMD_SCALAR MXCSR
+ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY
 
 PATTERN: VV1 0x6E V66 W0  V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
-OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 REG2=XMM_SE():r:dq:f32
+OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 REG2=XMM_SE():r:d:f32
 
 PATTERN: VV1 0x6E V66 W0  V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
-OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 REG3=XMM_SE():r:dq:f32
+OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 REG3=XMM_SE():r:d:f32
 
 PATTERN: VV1 0x6E V66 W1  V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
-OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:d:f32
+OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_SE():r:d:f32 MEM0:r:d:f32
 
 PATTERN: VV1 0x6E V66 W1  V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
-OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:d:f32
+OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_SE():r:d:f32 REG3=XMM_B():r:d:f32
 }
 
 {
@@ -17117,19 +17674,19 @@ CPL: 3
 CATEGORY: FMA4
 ISA_SET: FMA4
 EXTENSION: FMA4
-ATTRIBUTES: SIMD_SCALAR MXCSR
+ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY
 
 PATTERN: VV1 0x6F V66 W0  V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
-OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 REG2=XMM_SE():r:dq:f64
+OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 REG2=XMM_SE():r:q:f64
 
 PATTERN: VV1 0x6F V66 W0  V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
-OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 REG3=XMM_SE():r:dq:f64
+OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 REG3=XMM_SE():r:q:f64
 
 PATTERN: VV1 0x6F V66 W1  V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
-OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:q:f64
+OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_SE():r:q:f64 MEM0:r:q:f64
 
 PATTERN: VV1 0x6F V66 W1  V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
-OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:q:f64
+OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_SE():r:q:f64 REG3=XMM_B():r:q:f64
 }
 
 {
@@ -17138,7 +17695,7 @@ CPL: 3
 CATEGORY: FMA4
 ISA_SET: FMA4
 EXTENSION: FMA4
-ATTRIBUTES: MXCSR
+ATTRIBUTES: MXCSR AMDONLY
 
 PATTERN: VV1 0x78 V66 W0 VL128  V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:f32
@@ -17171,7 +17728,7 @@ CPL: 3
 CATEGORY: FMA4
 ISA_SET: FMA4
 EXTENSION: FMA4
-ATTRIBUTES: MXCSR
+ATTRIBUTES: MXCSR AMDONLY
 
 PATTERN: VV1 0x79 V66 W0 VL128  V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:f64
@@ -17204,19 +17761,19 @@ CPL: 3
 CATEGORY: FMA4
 ISA_SET: FMA4
 EXTENSION: FMA4
-ATTRIBUTES: SIMD_SCALAR MXCSR
+ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY
 
 PATTERN: VV1 0x7A V66 W0  V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
-OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 REG2=XMM_SE():r:dq:f32
+OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 REG2=XMM_SE():r:d:f32
 
 PATTERN: VV1 0x7A V66 W0  V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
-OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 REG3=XMM_SE():r:dq:f32
+OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 REG3=XMM_SE():r:d:f32
 
 PATTERN: VV1 0x7A V66 W1  V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
-OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:d:f32
+OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_SE():r:d:f32 MEM0:r:d:f32
 
 PATTERN: VV1 0x7A V66 W1  V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
-OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:d:f32
+OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_SE():r:d:f32 REG3=XMM_B():r:d:f32
 }
 
 {
@@ -17225,19 +17782,19 @@ CPL: 3
 CATEGORY: FMA4
 ISA_SET: FMA4
 EXTENSION: FMA4
-ATTRIBUTES: SIMD_SCALAR MXCSR
+ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY
 
 PATTERN: VV1 0x7B V66 W0  V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
-OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 REG2=XMM_SE():r:dq:f64
+OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 REG2=XMM_SE():r:q:f64
 
 PATTERN: VV1 0x7B V66 W0  V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
-OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 REG3=XMM_SE():r:dq:f64
+OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 REG3=XMM_SE():r:q:f64
 
 PATTERN: VV1 0x7B V66 W1  V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
-OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:q:f64
+OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_SE():r:q:f64 MEM0:r:q:f64
 
 PATTERN: VV1 0x7B V66 W1  V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
-OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:q:f64
+OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_SE():r:q:f64 REG3=XMM_B():r:q:f64
 }
 
 {
@@ -17246,7 +17803,7 @@ CPL: 3
 CATEGORY: FMA4
 ISA_SET: FMA4
 EXTENSION: FMA4
-ATTRIBUTES: MXCSR
+ATTRIBUTES: MXCSR AMDONLY
 
 PATTERN: VV1 0x7C V66 W0 VL128  V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:f32
@@ -17279,7 +17836,7 @@ CPL: 3
 CATEGORY: FMA4
 ISA_SET: FMA4
 EXTENSION: FMA4
-ATTRIBUTES: MXCSR
+ATTRIBUTES: MXCSR AMDONLY
 
 PATTERN: VV1 0x7D V66 W0 VL128  V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:f64
@@ -17312,19 +17869,19 @@ CPL: 3
 CATEGORY: FMA4
 ISA_SET: FMA4
 EXTENSION: FMA4
-ATTRIBUTES: SIMD_SCALAR MXCSR
+ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY
 
 PATTERN: VV1 0x7E V66 W0  V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
-OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 REG2=XMM_SE():r:dq:f32
+OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 REG2=XMM_SE():r:d:f32
 
 PATTERN: VV1 0x7E V66 W0  V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
-OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 REG3=XMM_SE():r:dq:f32
+OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 REG3=XMM_SE():r:d:f32
 
 PATTERN: VV1 0x7E V66 W1  V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
-OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:d:f32
+OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_SE():r:d:f32 MEM0:r:d:f32
 
 PATTERN: VV1 0x7E V66 W1  V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
-OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:d:f32
+OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_SE():r:d:f32 REG3=XMM_B():r:d:f32
 }
 
 {
@@ -17333,19 +17890,19 @@ CPL: 3
 CATEGORY: FMA4
 ISA_SET: FMA4
 EXTENSION: FMA4
-ATTRIBUTES: SIMD_SCALAR MXCSR
+ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY
 
 PATTERN: VV1 0x7F V66 W0  V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
-OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 REG2=XMM_SE():r:dq:f64
+OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 REG2=XMM_SE():r:q:f64
 
 PATTERN: VV1 0x7F V66 W0  V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
-OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 REG3=XMM_SE():r:dq:f64
+OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 REG3=XMM_SE():r:q:f64
 
 PATTERN: VV1 0x7F V66 W1  V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
-OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:q:f64
+OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_SE():r:q:f64 MEM0:r:q:f64
 
 PATTERN: VV1 0x7F V66 W1  V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
-OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:q:f64
+OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_SE():r:q:f64 REG3=XMM_B():r:q:f64
 }
 
 
@@ -17353,7 +17910,7 @@ OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG
 
 #BEGIN_LEGAL
 #
-#Copyright (c) 2016 Intel Corporation
+#Copyright (c) 2018 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -17378,6 +17935,7 @@ CPL       : 3
 CATEGORY  : XOP
 EXTENSION : XOP
 ISA_SET   : XOP
+ATTRIBUTES : AMDONLY
 
 # 128b W0
 PATTERN : VV1 0x48 VL128 V66 V0F3A W0  MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
@@ -17417,6 +17975,7 @@ CPL       : 3
 CATEGORY  : XOP
 EXTENSION : XOP
 ISA_SET   : XOP
+ATTRIBUTES : AMDONLY
 
 # 128b W0
 PATTERN : VV1 0x49 VL128 V66 V0F3A W0  MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
@@ -17450,58 +18009,11 @@ OPERANDS  : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 R
 
 
 
-###FILE: ../xed/datafiles/xsaveopt/xsaveopt-isa.txt
-
-#BEGIN_LEGAL
-#
-#Copyright (c) 2016 Intel Corporation
-#
-#  Licensed under the Apache License, Version 2.0 (the "License");
-#  you may not use this file except in compliance with the License.
-#  You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-#  Unless required by applicable law or agreed to in writing, software
-#  distributed under the License is distributed on an "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-#  See the License for the specific language governing permissions and
-#  limitations under the License.
-#
-#END_LEGAL
-INSTRUCTIONS()::
-
-{
-ICLASS    : XSAVEOPT
-CPL       : 3
-CATEGORY  : XSAVEOPT
-EXTENSION : XSAVEOPT
-ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT  x87_mmx_state_r NOTSX
-PATTERN   : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn]  no_refining_prefix norexw_prefix MODRM()
-#FIXME 2007-06-25 need a meaningful width code for XSAVE/XSAVEOPT/XRSTOR
-OPERANDS  : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP
-}
-
-
-{
-ICLASS    : XSAVEOPT64
-CPL       : 3
-CATEGORY  : XSAVEOPT
-EXTENSION : XSAVEOPT
-ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT  x87_mmx_state_r NOTSX
-
-PATTERN   : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] no_refining_prefix rexw_prefix MODRM()
-#FIXME 2007-06-25 need a meaningful width code for XSAVE/XSAVEOPT/XRSTOR
-OPERANDS  : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP
-}
-
-
-
 ###FILE: ../xed/datafiles/mpx/mpx-isa.txt
 
 #BEGIN_LEGAL
 #
-#Copyright (c) 2016 Intel Corporation
+#Copyright (c) 2018 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -17604,7 +18116,7 @@ PATTERN:  0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()  osz_refin
 OPERANDS: REG0=BND_R():w MEM0:r:q:u32
 
 # 32b refs 64b memop (2x32b)
-PATTERN:  0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()  osz_refining_prefix REFINING66() mode32
+PATTERN:  0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()  osz_refining_prefix REFINING66() mode32 eamode32
 OPERANDS: REG0=BND_R():w MEM0:r:q:u32
 
 # 64b refs 128b memop (2x64b)
@@ -17726,11 +18238,425 @@ IFORM     : NOP_GPRv_MEM_0F1B
 
 
 
+###FILE: ../xed/datafiles/cet/cet-nop-remove.xed.txt
+
+#BEGIN_LEGAL
+#
+#Copyright (c) 2018 Intel Corporation
+#
+#  Licensed under the Apache License, Version 2.0 (the "License");
+#  you may not use this file except in compliance with the License.
+#  You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+#  Unless required by applicable law or agreed to in writing, software
+#  distributed under the License is distributed on an "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#  See the License for the specific language governing permissions and
+#  limitations under the License.
+#
+#END_LEGAL
+
+
+INSTRUCTIONS()::
+
+UDELETE: NOP0F1E
+
+{
+ICLASS    : NOP
+#UNAME     : NOP0F1E
+CPL       : 3
+CATEGORY  : WIDENOP
+EXTENSION : BASE
+ATTRIBUTES: NOP
+ISA_SET   : PPRO
+COMMENT   : reg form MODRM.MOD=3 & MODRM.REG=0b001  f3 prefix is RDSSP{D,Q}
+
+# mem forms
+
+PATTERN   : 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : MEM0:r:v REG0=GPRv_R():r
+IFORM     : NOP_MEMv_GPRv_0F1E
+
+
+# reg forms
+
+PATTERN   : 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix
+OPERANDS  : REG0=GPRv_B():r REG1=GPRv_R():r
+IFORM     : NOP_GPRv_GPRv_0F1E
+
+PATTERN   : 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix
+OPERANDS  : REG0=GPRv_B():r REG1=GPRv_R():r
+IFORM     : NOP_GPRv_GPRv_0F1E
+
+PATTERN   : 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix
+OPERANDS  : REG0=GPRv_B():r REG1=GPRv_R():r
+IFORM     : NOP_GPRv_GPRv_0F1E
+
+
+
+
+
+
+PATTERN   : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix
+OPERANDS  : REG0=GPRv_B():r REG1=GPRv_R():r
+IFORM     : NOP_GPRv_GPRv_0F1E
+
+# ...
+# F3 with MODRM.REG=0b001 is for CET for all values of RM.
+# ...
+
+PATTERN   : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix
+OPERANDS  : REG0=GPRv_B():r REG1=GPRv_R():r
+IFORM     : NOP_GPRv_GPRv_0F1E
+PATTERN   : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix
+OPERANDS  : REG0=GPRv_B():r REG1=GPRv_R():r
+IFORM     : NOP_GPRv_GPRv_0F1E
+PATTERN   : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix
+OPERANDS  : REG0=GPRv_B():r REG1=GPRv_R():r
+IFORM     : NOP_GPRv_GPRv_0F1E
+PATTERN   : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix
+OPERANDS  : REG0=GPRv_B():r REG1=GPRv_R():r
+IFORM     : NOP_GPRv_GPRv_0F1E
+PATTERN   : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix
+OPERANDS  : REG0=GPRv_B():r REG1=GPRv_R():r
+IFORM     : NOP_GPRv_GPRv_0F1E
+
+
+PATTERN   : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b000] f3_refining_prefix
+OPERANDS  : REG0=GPRv_B():r REG1=GPRv_R():r
+IFORM     : NOP_GPRv_GPRv_0F1E
+PATTERN   : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b001] f3_refining_prefix
+OPERANDS  : REG0=GPRv_B():r REG1=GPRv_R():r
+IFORM     : NOP_GPRv_GPRv_0F1E
+
+# ...
+# F3 with MODRM.REG=0b111  with RM=2 or RM=3 is for CET
+# ...
+
+PATTERN   : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b100] f3_refining_prefix
+OPERANDS  : REG0=GPRv_B():r REG1=GPRv_R():r
+IFORM     : NOP_GPRv_GPRv_0F1E
+PATTERN   : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b101] f3_refining_prefix
+OPERANDS  : REG0=GPRv_B():r REG1=GPRv_R():r
+IFORM     : NOP_GPRv_GPRv_0F1E
+PATTERN   : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b110] f3_refining_prefix
+OPERANDS  : REG0=GPRv_B():r REG1=GPRv_R():r
+IFORM     : NOP_GPRv_GPRv_0F1E
+PATTERN   : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b111] f3_refining_prefix
+OPERANDS  : REG0=GPRv_B():r REG1=GPRv_R():r
+IFORM     : NOP_GPRv_GPRv_0F1E
+
+
+}
+
+
+# REPLACE CERTAIN NOPS WITH MODAL OPTIONS  basd on CET=0/1
+{
+ICLASS    : NOP
+#UNAME     : NOP0F1E
+CPL       : 3
+CATEGORY  : WIDENOP
+EXTENSION : BASE
+ATTRIBUTES: NOP
+ISA_SET   : PPRO
+
+PATTERN   : 0x0F 0x1E MOD[0b11] MOD=3  REG[0b111] RM[0b010]  f3_refining_prefix CET=0
+OPERANDS  : REG0=GPRv_B():r REG1=GPRv_R():r
+IFORM     : NOP_GPRv_GPRv_0F1E
+
+PATTERN   : 0x0F 0x1E MOD[0b11] MOD=3  REG[0b111] RM[0b011]  f3_refining_prefix CET=0
+OPERANDS  : REG0=GPRv_B():r REG1=GPRv_R():r
+IFORM     : NOP_GPRv_GPRv_0F1E
+}
+
+
+{
+ICLASS    : NOP
+#UNAME     : NOP0F1E
+CPL       : 3
+CATEGORY  : WIDENOP
+EXTENSION : BASE
+ATTRIBUTES: NOP
+ISA_SET   : PPRO
+
+PATTERN   : 0x0F 0x1E MOD[0b11] MOD=3  REG[0b001] RM[nnn]  f3_refining_prefix W0 CET=0
+OPERANDS  : REG0=GPRv_B():r REG1=GPRv_R():r
+IFORM     : NOP_GPRv_GPRv_0F1E
+
+PATTERN   : 0x0F 0x1E MOD[0b11] MOD=3  REG[0b001] RM[nnn]  f3_refining_prefix W1 mode64  CET=0
+OPERANDS  : REG0=GPRv_B():r REG1=GPRv_R():r
+IFORM     : NOP_GPRv_GPRv_0F1E
+}
+
+
+###FILE: ../xed/datafiles/cet/cet-isa.xed.txt
+
+#BEGIN_LEGAL
+#
+#Copyright (c) 2018 Intel Corporation
+#
+#  Licensed under the Apache License, Version 2.0 (the "License");
+#  you may not use this file except in compliance with the License.
+#  You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+#  Unless required by applicable law or agreed to in writing, software
+#  distributed under the License is distributed on an "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#  See the License for the specific language governing permissions and
+#  limitations under the License.
+#
+#END_LEGAL
+#
+#
+#
+#    ***** GENERATED FILE -- DO NOT EDIT! *****
+#    ***** GENERATED FILE -- DO NOT EDIT! *****
+#    ***** GENERATED FILE -- DO NOT EDIT! *****
+#
+#
+#
+INSTRUCTIONS()::
+# EMITTING CLRSSBSY (CLRSSBSY-N/A-1)
+{
+ICLASS:      CLRSSBSY
+CPL:         3
+CATEGORY:    CET
+EXTENSION:   CET
+ISA_SET:     CET
+REAL_OPCODE: Y
+PATTERN:    0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn]   f3_refining_prefix     MODRM()
+OPERANDS:    MEM0:rw:q:u64
+IFORM:       CLRSSBSY_MEMu64
+}
+
+
+# EMITTING ENDBR32 (ENDBR32-N/A-1)
+{
+ICLASS:      ENDBR32
+CPL:         3
+CATEGORY:    CET
+EXTENSION:   CET
+ISA_SET:     CET
+REAL_OPCODE: Y
+PATTERN:    0x0F 0x1E MOD[0b11] MOD=3  REG[0b111] RM[0b011]  f3_refining_prefix     CET=1
+OPERANDS:
+IFORM:       ENDBR32
+}
+
+
+# EMITTING ENDBR64 (ENDBR64-N/A-1)
+{
+ICLASS:      ENDBR64
+CPL:         3
+CATEGORY:    CET
+EXTENSION:   CET
+ISA_SET:     CET
+REAL_OPCODE: Y
+PATTERN:    0x0F 0x1E MOD[0b11] MOD=3  REG[0b111] RM[0b010]  f3_refining_prefix     CET=1
+OPERANDS:
+IFORM:       ENDBR64
+}
+
+
+# EMITTING INCSSPD (INCSSPD-N/A-1)
+{
+ICLASS:      INCSSPD
+CPL:         3
+CATEGORY:    CET
+EXTENSION:   CET
+ISA_SET:     CET
+REAL_OPCODE: Y
+PATTERN:    0x0F 0xAE MOD[0b11] MOD=3  REG[0b101] RM[nnn]  f3_refining_prefix    W0
+OPERANDS:    REG0=GPR32_B():r:d:u8 REG1=XED_REG_SSP:rw:SUPP:u64
+IFORM:       INCSSPD_GPR32u8
+}
+
+
+# EMITTING INCSSPQ (INCSSPQ-N/A-1)
+{
+ICLASS:      INCSSPQ
+CPL:         3
+CATEGORY:    CET
+EXTENSION:   CET
+ISA_SET:     CET
+REAL_OPCODE: Y
+PATTERN:    0x0F 0xAE MOD[0b11] MOD=3  REG[0b101] RM[nnn]  f3_refining_prefix    W1  mode64
+OPERANDS:    REG0=GPR64_B():r:q:u8 REG1=XED_REG_SSP:rw:SUPP:u64
+IFORM:       INCSSPQ_GPR64u8
+}
+
+
+# EMITTING RDSSPD (RDSSPD-N/A-1)
+{
+ICLASS:      RDSSPD
+CPL:         3
+CATEGORY:    CET
+EXTENSION:   CET
+ISA_SET:     CET
+REAL_OPCODE: Y
+PATTERN:    0x0F 0x1E MOD[0b11] MOD=3  REG[0b001] RM[nnn]  f3_refining_prefix    W0 CET=1
+OPERANDS:    REG0=GPR32_B():w:d:u32 REG1=XED_REG_SSP:r:SUPP:u64
+IFORM:       RDSSPD_GPR32u32
+}
+
+
+# EMITTING RDSSPQ (RDSSPQ-N/A-1)
+{
+ICLASS:      RDSSPQ
+CPL:         3
+CATEGORY:    CET
+EXTENSION:   CET
+ISA_SET:     CET
+REAL_OPCODE: Y
+PATTERN:    0x0F 0x1E MOD[0b11] MOD=3  REG[0b001] RM[nnn]  f3_refining_prefix    W1  mode64 CET=1
+OPERANDS:    REG0=GPR64_B():w:q:u64 REG1=XED_REG_SSP:r:SUPP:u64
+IFORM:       RDSSPQ_GPR64u64
+}
+
+
+# EMITTING RSTORSSP (RSTORSSP-N/A-1)
+{
+ICLASS:      RSTORSSP
+CPL:         3
+CATEGORY:    CET
+EXTENSION:   CET
+ISA_SET:     CET
+REAL_OPCODE: Y
+PATTERN:    0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn]  MODRM()  f3_refining_prefix
+OPERANDS:    MEM0:rw:q:u64 REG0=XED_REG_SSP:w:SUPP:u64
+IFORM:       RSTORSSP_MEMu64
+}
+
+
+# EMITTING SAVEPREVSSP (SAVEPREVSSP-N/A-1)
+{
+ICLASS:      SAVEPREVSSP
+CPL:         3
+CATEGORY:    CET
+EXTENSION:   CET
+ISA_SET:     CET
+REAL_OPCODE: Y
+PATTERN:    0x0F 0x01 MOD[0b11] MOD=3  REG[0b101] RM[0b010]  f3_refining_prefix
+OPERANDS:    REG0=XED_REG_SSP:r:SUPP:u64
+IFORM:       SAVEPREVSSP
+}
+
+
+# EMITTING SETSSBSY (SETSSBSY-N/A-1)
+{
+ICLASS:      SETSSBSY
+CPL:         3
+CATEGORY:    CET
+EXTENSION:   CET
+ISA_SET:     CET
+REAL_OPCODE: Y
+PATTERN:    0x0F 0x01 MOD[0b11] MOD=3  REG[0b101] RM[0b000]  f3_refining_prefix
+OPERANDS:
+IFORM:       SETSSBSY
+}
+
+
+# EMITTING WRSSD (WRSSD-N/A-1)
+{
+ICLASS:      WRSSD
+CPL:         3
+CATEGORY:    CET
+EXTENSION:   CET
+ISA_SET:     CET
+REAL_OPCODE: Y
+PATTERN:    0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  no_refining_prefix    W0
+OPERANDS:    MEM0:w:d:u32 REG0=GPR32_R():r:d:u32
+IFORM:       WRSSD_MEMu32_GPR32u32
+}
+
+
+# EMITTING WRSSQ (WRSSQ-N/A-1)
+{
+ICLASS:      WRSSQ
+CPL:         3
+CATEGORY:    CET
+EXTENSION:   CET
+ISA_SET:     CET
+REAL_OPCODE: Y
+PATTERN:    0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  no_refining_prefix    W1  mode64
+OPERANDS:    MEM0:w:q:u64 REG0=GPR64_R():r:q:u64
+IFORM:       WRSSQ_MEMu64_GPR64u64
+}
+
+
+# EMITTING WRUSSD (WRUSSD-N/A-1)
+{
+ICLASS:      WRUSSD
+CPL:         3
+CATEGORY:    CET
+EXTENSION:   CET
+ISA_SET:     CET
+REAL_OPCODE: Y
+PATTERN:    0x0F 0x38 0xF5 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  osz_refining_prefix    W0
+OPERANDS:    MEM0:w:d:u32 REG0=GPR32_R():r:d:u32
+IFORM:       WRUSSD_MEMu32_GPR32u32
+}
+
+
+# EMITTING WRUSSQ (WRUSSQ-N/A-1)
+{
+ICLASS:      WRUSSQ
+CPL:         3
+CATEGORY:    CET
+EXTENSION:   CET
+ISA_SET:     CET
+REAL_OPCODE: Y
+PATTERN:    0x0F 0x38 0xF5 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  osz_refining_prefix    W1  mode64
+OPERANDS:    MEM0:w:q:u64 REG0=GPR64_R():r:q:u64
+IFORM:       WRUSSQ_MEMu64_GPR64u64
+}
+
+
+
+
+###FILE: ../xed/datafiles/rdrand/rdrand-isa.xed.txt
+
+#BEGIN_LEGAL
+#
+#Copyright (c) 2018 Intel Corporation
+#
+#  Licensed under the Apache License, Version 2.0 (the "License");
+#  you may not use this file except in compliance with the License.
+#  You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+#  Unless required by applicable law or agreed to in writing, software
+#  distributed under the License is distributed on an "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#  See the License for the specific language governing permissions and
+#  limitations under the License.
+#
+#END_LEGAL
+INSTRUCTIONS()::
+
+{
+ICLASS    : RDRAND
+CPL       : 3
+CATEGORY  : RDRAND
+EXTENSION : RDRAND
+ISA_SET   : RDRAND
+FLAGS     : MUST [ cf-mod zf-0 of-0 af-0 pf-0 sf-0 ]
+PATTERN   : 0x0F 0xC7  MOD[0b11] MOD=3 REG[0b110] RM[nnn] not_refining
+OPERANDS  : REG0=GPRv_B():w
+}
+
+
+
 ###FILE: ../xed/datafiles/sha/sha-isa.xed.txt
 
 #BEGIN_LEGAL
 #
-#Copyright (c) 2016 Intel Corporation
+#Copyright (c) 2018 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -17960,11 +18886,11 @@ IFORM:       SHA256RNDS2_XMMi32_MEMi32_SHA
 
 
 
-###FILE: ../xed/datafiles/ivbint/ivb-int-isa.txt
+###FILE: ../xed/datafiles/xsaveopt/xsaveopt-isa.txt
 
 #BEGIN_LEGAL
 #
-#Copyright (c) 2016 Intel Corporation
+#Copyright (c) 2018 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -17982,23 +18908,228 @@ IFORM:       SHA256RNDS2_XMMi32_MEMi32_SHA
 INSTRUCTIONS()::
 
 {
-ICLASS    : RDRAND
+ICLASS    : XSAVEOPT
 CPL       : 3
-CATEGORY  : RDRAND
-EXTENSION : RDRAND
-ISA_SET   : RDRAND
+CATEGORY  : XSAVEOPT
+EXTENSION : XSAVEOPT
+ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT  x87_mmx_state_r NOTSX
+COMMENT   :  Variable length Store and conditional reg read. reads/modifies header.
+PATTERN   : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn]  no_refining_prefix norexw_prefix MODRM()
+#FIXME 2007-06-25 need a meaningful width code for XSAVE/XSAVEOPT/XRSTOR
+OPERANDS  : MEM0:rw:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP
+}
+
+
+{
+ICLASS    : XSAVEOPT64
+CPL       : 3
+CATEGORY  : XSAVEOPT
+EXTENSION : XSAVEOPT
+ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT  x87_mmx_state_r NOTSX
+COMMENT   :  Variable length Store and conditional reg read. reads/modifies header.
+PATTERN   : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] no_refining_prefix rexw_prefix MODRM()
+#FIXME 2007-06-25 need a meaningful width code for XSAVE/XSAVEOPT/XRSTOR
+OPERANDS  : MEM0:rw:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP
+}
+
+
+
+###FILE: ../xed/datafiles/xsaves/xsaves-isa.txt
+
+#BEGIN_LEGAL
+#
+#Copyright (c) 2018 Intel Corporation
+#
+#  Licensed under the Apache License, Version 2.0 (the "License");
+#  you may not use this file except in compliance with the License.
+#  You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+#  Unless required by applicable law or agreed to in writing, software
+#  distributed under the License is distributed on an "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#  See the License for the specific language governing permissions and
+#  limitations under the License.
+#
+#END_LEGAL
+INSTRUCTIONS()::
+
+{
+ICLASS    : XSAVES
+CPL       : 0
+CATEGORY  : XSAVE
+EXTENSION : XSAVES
+COMMENT   : variable length store and conditional reg read. does not read header
+ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED
+PATTERN   : 0x0F 0xC7 MOD[mm]  MOD!=3 REG[0b101] RM[nnn] MODRM() norexw_prefix no_refining_prefix
+OPERANDS  : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP
+}
+
+
+{
+ICLASS    : XSAVES64
+CPL       : 0
+CATEGORY  : XSAVE
+EXTENSION : XSAVES
+COMMENT   : variable length store and conditional reg read. does not read header
+ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED
+PATTERN   : 0x0F 0xC7 MOD[mm]  MOD!=3 REG[0b101] RM[nnn] MODRM() rexw_prefix no_refining_prefix
+OPERANDS  : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP
+}
+
+
+
+
+
+{
+ICLASS    : XRSTORS
+CPL       : 0
+CATEGORY  : XSAVE
+EXTENSION : XSAVES
+COMMENT   : variable length load and conditional reg write.
+ATTRIBUTES : xmm_state_w REQUIRES_ALIGNMENT x87_mmx_state_w NOTSX SPECIAL_AGEN_REQUIRED
+PATTERN   : 0x0F 0xC7 MOD[mm]  MOD!=3 REG[0b011] RM[nnn] MODRM() norexw_prefix no_refining_prefix
+OPERANDS  : MEM0:r:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP
+}
+
+
+{
+ICLASS    : XRSTORS64
+CPL       : 0
+CATEGORY  : XSAVE
+EXTENSION : XSAVES
+COMMENT   : variable length load and conditional reg write
+ATTRIBUTES : xmm_state_w REQUIRES_ALIGNMENT x87_mmx_state_w NOTSX SPECIAL_AGEN_REQUIRED
+PATTERN   : 0x0F 0xC7 MOD[mm]  MOD!=3 REG[0b011] RM[nnn] MODRM() rexw_prefix no_refining_prefix
+OPERANDS  : MEM0:r:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP
+}
+
+
+
+###FILE: ../xed/datafiles/xsavec/xsavec-isa.txt
+
+#BEGIN_LEGAL
+#
+#Copyright (c) 2018 Intel Corporation
+#
+#  Licensed under the Apache License, Version 2.0 (the "License");
+#  you may not use this file except in compliance with the License.
+#  You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+#  Unless required by applicable law or agreed to in writing, software
+#  distributed under the License is distributed on an "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#  See the License for the specific language governing permissions and
+#  limitations under the License.
+#
+#END_LEGAL
+INSTRUCTIONS()::
+
+{
+ICLASS    : XSAVEC
+CPL       : 3
+CATEGORY  : XSAVE
+EXTENSION : XSAVEC
+COMMENT   : Variable length store and conditional reg read. does not read header
+ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED
+PATTERN   : 0x0F 0xC7 MOD[mm]  MOD!=3 REG[0b100] RM[nnn] MODRM() norexw_prefix no_refining_prefix
+OPERANDS  : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP
+}
+
+
+
+{
+ICLASS    : XSAVEC64
+CPL       : 3
+CATEGORY  : XSAVE
+EXTENSION : XSAVEC
+COMMENT   : Variable length store and conditional reg read. does not read header
+ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r  NOTSX SPECIAL_AGEN_REQUIRED
+PATTERN   : 0x0F 0xC7 MOD[mm]  MOD!=3 REG[0b100] RM[nnn] MODRM() rexw_prefix no_refining_prefix
+OPERANDS  : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP
+}
+
+
+
+
+###FILE: ../xed/datafiles/clflushopt/clflushopt.xed.txt
+
+#BEGIN_LEGAL
+#
+#Copyright (c) 2018 Intel Corporation
+#
+#  Licensed under the Apache License, Version 2.0 (the "License");
+#  you may not use this file except in compliance with the License.
+#  You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+#  Unless required by applicable law or agreed to in writing, software
+#  distributed under the License is distributed on an "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#  See the License for the specific language governing permissions and
+#  limitations under the License.
+#
+#END_LEGAL
+
+INSTRUCTIONS()::
+
+{
+ICLASS: CLFLUSHOPT
+CPL: 3
+CATEGORY:  CLFLUSHOPT
+EXTENSION: CLFLUSHOPT
+ISA_SET:   CLFLUSHOPT
+ATTRIBUTES: PREFETCH  # check TSX-friendlyness
+PATTERN   : 0x0F 0xAE  MOD[mm] MOD!=3 REG[0b111] RM[nnn]  osz_refining_prefix REFINING66() MODRM()
+OPERANDS  : MEM0:r:mprefetch
+}
+
+
+
+
+###FILE: ../xed/datafiles/rdseed/rdseed-isa.xed.txt
+
+#BEGIN_LEGAL
+#
+#Copyright (c) 2018 Intel Corporation
+#
+#  Licensed under the Apache License, Version 2.0 (the "License");
+#  you may not use this file except in compliance with the License.
+#  You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+#  Unless required by applicable law or agreed to in writing, software
+#  distributed under the License is distributed on an "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#  See the License for the specific language governing permissions and
+#  limitations under the License.
+#
+#END_LEGAL
+INSTRUCTIONS()::
+
+{
+ICLASS    : RDSEED
+CPL       : 3
+CATEGORY  : RDSEED
+EXTENSION : RDSEED
+ISA_SET   : RDSEED
 FLAGS     : MUST [ cf-mod zf-0 of-0 af-0 pf-0 sf-0 ]
-PATTERN   : 0x0F 0xC7  MOD[0b11] MOD=3 REG[0b110] RM[nnn] not_refining
+PATTERN   : 0x0F 0xC7  MOD[0b11] MOD=3 REG[0b111] RM[nnn] not_refining
 OPERANDS  : REG0=GPRv_B():w
 }
 
 
 
-###FILE: ../xed/datafiles/ivbint/fsgsbase-isa.txt
+###FILE: ../xed/datafiles/fsgsbase/fsgsbase-isa.xed.txt
 
 #BEGIN_LEGAL
 #
-#Copyright (c) 2016 Intel Corporation
+#Copyright (c) 2018 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -18022,7 +19153,7 @@ CPL       : 3
 CATEGORY  : RDWRFSGS
 EXTENSION : RDWRFSGS
 
-PATTERN   : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b000] RM[nnn] mode64 f3_refining_prefix  no66_prefix
+PATTERN   : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b000] RM[nnn] mode64 f3_refining_prefix
 OPERANDS  : REG0=GPRy_B():w  REG1=XED_REG_FSBASE:r:SUPP:y
 
 }
@@ -18032,7 +19163,7 @@ CPL       : 3
 CATEGORY  : RDWRFSGS
 EXTENSION : RDWRFSGS
 
-PATTERN   : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b001] RM[nnn] mode64 f3_refining_prefix  no66_prefix
+PATTERN   : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b001] RM[nnn] mode64 f3_refining_prefix
 OPERANDS  : REG0=GPRy_B():w  REG1=XED_REG_GSBASE:r:SUPP:y
 
 }
@@ -18046,7 +19177,7 @@ CATEGORY  : RDWRFSGS
 EXTENSION : RDWRFSGS
 ATTRIBUTES: NOTSX
 
-PATTERN   : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b010] RM[nnn] mode64 f3_refining_prefix  no66_prefix
+PATTERN   : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b010] RM[nnn] mode64 f3_refining_prefix
 OPERANDS  :   REG0=GPRy_B():r   REG1=XED_REG_FSBASE:w:SUPP:y
 
 }
@@ -18057,17 +19188,17 @@ CATEGORY  : RDWRFSGS
 EXTENSION : RDWRFSGS
 ATTRIBUTES: NOTSX
 
-PATTERN   : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b011] RM[nnn] mode64 f3_refining_prefix  no66_prefix
+PATTERN   : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b011] RM[nnn] mode64 f3_refining_prefix
 OPERANDS  :   REG0=GPRy_B():r   REG1=XED_REG_GSBASE:w:SUPP:y
 
 }
 
 
-###FILE: ../xed/datafiles/xsaves/xsaves-isa.txt
+###FILE: ../xed/datafiles/smap/smap-isa.xed.txt
 
 #BEGIN_LEGAL
 #
-#Copyright (c) 2016 Intel Corporation
+#Copyright (c) 2018 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -18082,65 +19213,195 @@ OPERANDS  :   REG0=GPRy_B():r   REG1=XED_REG_GSBASE:w:SUPP:y
 #  limitations under the License.
 #
 #END_LEGAL
+
 INSTRUCTIONS()::
 
 {
-ICLASS    : XSAVES
+ICLASS    : CLAC
 CPL       : 0
-CATEGORY  : XSAVE
-EXTENSION : XSAVES
-COMMENT   : variable length load and conditianal reg write
-ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED
-PATTERN   : 0x0F 0xC7 MOD[mm]  MOD!=3 REG[0b101] RM[nnn] MODRM() norexw_prefix no_refining_prefix
-OPERANDS  : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP
+CATEGORY  : SMAP
+EXTENSION : SMAP
+FLAGS     : MUST [ ac-0 ]
+# 0F 01 CA = 1100_1010 = 11_001_010
+PATTERN   : 0x0F 0x01  MOD[0b11] MOD=3 REG[0b001] RM[0b010] no_refining_prefix
+OPERANDS  :
 }
 
-
 {
-ICLASS    : XSAVES64
+ICLASS    : STAC
 CPL       : 0
-CATEGORY  : XSAVE
-EXTENSION : XSAVES
-COMMENT   : variable length load and conditianal reg write
-ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED
-PATTERN   : 0x0F 0xC7 MOD[mm]  MOD!=3 REG[0b101] RM[nnn] MODRM() rexw_prefix no_refining_prefix
-OPERANDS  : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP
+CATEGORY  : SMAP
+EXTENSION : SMAP
+FLAGS     : MUST [ ac-1 ]
+# 0F 01 CB = 1100_1011 = 11_001_011
+PATTERN   : 0x0F 0x01  MOD[0b11] MOD=3 REG[0b001] RM[0b011] no_refining_prefix
+OPERANDS  :
 }
 
 
 
+###FILE: ../xed/datafiles/sgx/sgx-isa.xed.txt
+
+#BEGIN_LEGAL
+#
+#Copyright (c) 2018 Intel Corporation
+#
+#  Licensed under the Apache License, Version 2.0 (the "License");
+#  you may not use this file except in compliance with the License.
+#  You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+#  Unless required by applicable law or agreed to in writing, software
+#  distributed under the License is distributed on an "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#  See the License for the specific language governing permissions and
+#  limitations under the License.
+#
+#END_LEGAL
+
+INSTRUCTIONS()::
+
+# Both read EAX
+# Both may read or write or r/w  RBX, RCX, RDX
+# ENCLU 0f 01 D7
+# D7 =  1101 0111
+
+# ENCLS 0f 01 CF
+# CF = 1100_1111
+
 
 
 {
-ICLASS    : XRSTORS
-CPL       : 0
-CATEGORY  : XSAVE
-EXTENSION : XSAVES
-COMMENT   : variable length load and conditianal reg write
-ATTRIBUTES : xmm_state_w REQUIRES_ALIGNMENT x87_mmx_state_w NOTSX SPECIAL_AGEN_REQUIRED
-PATTERN   : 0x0F 0xC7 MOD[mm]  MOD!=3 REG[0b011] RM[nnn] MODRM() norexw_prefix no_refining_prefix
-OPERANDS  : MEM0:r:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP
+ICLASS: ENCLU
+CPL: 3
+CATEGORY:  SGX
+EXTENSION: SGX
+ISA_SET:   SGX
+COMMENT:   May set flags
+PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b111] no_refining_prefix
+OPERANDS: REG0=XED_REG_EAX:r:SUPP    \
+          REG1=XED_REG_RBX:crw:SUPP  \
+          REG2=XED_REG_RCX:crw:SUPP  \
+          REG3=XED_REG_RDX:crw:SUPP
 }
 
+{
+
+ICLASS: ENCLS
+CPL: 0
+CATEGORY:  SGX
+EXTENSION: SGX
+ISA_SET:   SGX
+COMMENT:   May set flags
+PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b111] no_refining_prefix
+OPERANDS: REG0=XED_REG_EAX:r:SUPP    \
+          REG1=XED_REG_RBX:crw:SUPP  \
+          REG2=XED_REG_RCX:crw:SUPP  \
+          REG3=XED_REG_RDX:crw:SUPP
 
+}
+
+
+###FILE: ../xed/datafiles/rdpid/rdpid-isa.xed.txt
+
+#BEGIN_LEGAL
+#
+#Copyright (c) 2018 Intel Corporation
+#
+#  Licensed under the Apache License, Version 2.0 (the "License");
+#  you may not use this file except in compliance with the License.
+#  You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+#  Unless required by applicable law or agreed to in writing, software
+#  distributed under the License is distributed on an "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#  See the License for the specific language governing permissions and
+#  limitations under the License.
+#
+#END_LEGAL
+#
+#
+#
+#    ***** GENERATED FILE -- DO NOT EDIT! *****
+#    ***** GENERATED FILE -- DO NOT EDIT! *****
+#    ***** GENERATED FILE -- DO NOT EDIT! *****
+#
+#
+#
+INSTRUCTIONS()::
+# EMITTING RDPID (RDPID-N/A-1-32)
 {
-ICLASS    : XRSTORS64
-CPL       : 0
-CATEGORY  : XSAVE
-EXTENSION : XSAVES
-COMMENT   : variable length load and conditianal reg write
-ATTRIBUTES : xmm_state_w REQUIRES_ALIGNMENT x87_mmx_state_w NOTSX SPECIAL_AGEN_REQUIRED
-PATTERN   : 0x0F 0xC7 MOD[mm]  MOD!=3 REG[0b011] RM[nnn] MODRM() rexw_prefix no_refining_prefix
-OPERANDS  : MEM0:r:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP
+ICLASS:      RDPID
+CPL:         3
+CATEGORY:    RDPID
+EXTENSION:   RDPID
+ISA_SET:     RDPID
+REAL_OPCODE: Y
+PATTERN:     0x0F 0xC7 MOD[0b11] MOD=3  REG[0b111] RM[nnn]  f3_refining_prefix    not64
+OPERANDS:    REG0=GPR32_B():w:d:u32 REG1=XED_REG_TSCAUX:r:SUPP:d:u32
+IFORM:       RDPID_GPR32u32
+}
+
+
+# EMITTING RDPID (RDPID-N/A-1-64)
+{
+ICLASS:      RDPID
+CPL:         3
+CATEGORY:    RDPID
+EXTENSION:   RDPID
+ISA_SET:     RDPID
+REAL_OPCODE: Y
+PATTERN:     0x0F 0xC7 MOD[0b11] MOD=3  REG[0b111] RM[nnn]  f3_refining_prefix   mode64
+OPERANDS:    REG0=GPR64_B():w:q:u64 REG1=XED_REG_TSCAUX:r:SUPP:d:u32
+IFORM:       RDPID_GPR64u64
 }
 
 
 
-###FILE: ../xed/datafiles/xsavec/xsavec-isa.txt
+
+###FILE: ../xed/datafiles/pt/intelpt-isa.xed.txt
+
+#BEGIN_LEGAL
+#
+#Copyright (c) 2018 Intel Corporation
+#
+#  Licensed under the Apache License, Version 2.0 (the "License");
+#  you may not use this file except in compliance with the License.
+#  You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+#  Unless required by applicable law or agreed to in writing, software
+#  distributed under the License is distributed on an "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#  See the License for the specific language governing permissions and
+#  limitations under the License.
+#
+#END_LEGAL
+
+
+INSTRUCTIONS()::
+{
+ICLASS    : PTWRITE
+CPL       : 3
+CATEGORY  : PT
+EXTENSION : PT
+PATTERN   : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b100]  RM[nnn] f3_refining_prefix  no66_prefix
+OPERANDS  : REG0=GPRy_B():r
+PATTERN   : 0x0F 0xAE MOD[mm]   MOD!=3 REG[0b100] RM[nnn] f3_refining_prefix no66_prefix MODRM()
+OPERANDS  : MEM0:r:y
+
+}
+
+
+###FILE: ../xed/datafiles/movdir/movdir-isa.xed.txt
 
 #BEGIN_LEGAL
 #
-#Copyright (c) 2016 Intel Corporation
+#Copyright (c) 2018 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -18155,30 +19416,355 @@ OPERANDS  : MEM0:r:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=X
 #  limitations under the License.
 #
 #END_LEGAL
+#
+#
+#
+#    ***** GENERATED FILE -- DO NOT EDIT! *****
+#    ***** GENERATED FILE -- DO NOT EDIT! *****
+#    ***** GENERATED FILE -- DO NOT EDIT! *****
+#
+#
+#
 INSTRUCTIONS()::
+# EMITTING MOVDIR64B (MOVDIR64B-N/A-1)
+{
+ICLASS:      MOVDIR64B
+CPL:         3
+CATEGORY:    MOVDIR
+EXTENSION:   MOVDIR
+ISA_SET:     MOVDIR
+REAL_OPCODE: Y
+ATTRIBUTES:  REQUIRES_ALIGNMENT
+PATTERN:    0x0F 0x38 0xF8 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  osz_refining_prefix   not64
+OPERANDS:    REG0=A_GPR_R():r MEM0:r:zd:u32 MEM1:w:zd:SUPP BASE1=A_GPR_R():r:SUPP  SEG1=XED_REG_ES:r:SUPP
+IFORM:       MOVDIR64B_GPRa_MEM
+
+PATTERN:    0x0F 0x38 0xF8 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  osz_refining_prefix   mode64
+OPERANDS:    REG0=A_GPR_R():r MEM0:r:zd:u32 MEM1:w:zd:SUPP BASE1=A_GPR_R():r:SUPP
+IFORM:       MOVDIR64B_GPRa_MEM
+}
+
 
+# EMITTING MOVDIRI (MOVDIRI-N/A-1-32)
 {
-ICLASS    : XSAVEC
+ICLASS:      MOVDIRI
+CPL:         3
+CATEGORY:    MOVDIR
+EXTENSION:   MOVDIR
+ISA_SET:     MOVDIR
+REAL_OPCODE: Y
+PATTERN:    0x0F 0x38 0xF9 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  no_refining_prefix      norexw_prefix
+OPERANDS:    MEM0:w:d:u32 REG0=GPR32_R():r:d:u32
+IFORM:       MOVDIRI_MEMu32_GPR32u32
+}
+
+
+# EMITTING MOVDIRI (MOVDIRI-N/A-1-64)
+{
+ICLASS:      MOVDIRI
+CPL:         3
+CATEGORY:    MOVDIR
+EXTENSION:   MOVDIR
+ISA_SET:     MOVDIR
+REAL_OPCODE: Y
+PATTERN:    0x0F 0x38 0xF9 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  no_refining_prefix      mode64 rexw_prefix
+OPERANDS:    MEM0:w:q:u64 REG0=GPR64_R():r:q:u64
+IFORM:       MOVDIRI_MEMu64_GPR64u64
+}
+
+
+
+
+###FILE: ../xed/datafiles/waitpkg/waitpkg-isa.xed.txt
+
+#BEGIN_LEGAL
+#
+#Copyright (c) 2018 Intel Corporation
+#
+#  Licensed under the Apache License, Version 2.0 (the "License");
+#  you may not use this file except in compliance with the License.
+#  You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+#  Unless required by applicable law or agreed to in writing, software
+#  distributed under the License is distributed on an "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#  See the License for the specific language governing permissions and
+#  limitations under the License.
+#
+#END_LEGAL
+#
+#
+#
+#    ***** GENERATED FILE -- DO NOT EDIT! *****
+#    ***** GENERATED FILE -- DO NOT EDIT! *****
+#    ***** GENERATED FILE -- DO NOT EDIT! *****
+#
+#
+#
+INSTRUCTIONS()::
+# EMITTING TPAUSE (TPAUSE-N/A-1-32)
+{
+ICLASS:      TPAUSE
+CPL:         3
+CATEGORY:    WAITPKG
+EXTENSION:   WAITPKG
+ISA_SET:     WAITPKG
+REAL_OPCODE: Y
+FLAGS:       MUST [  cf-mod zf-0 pf-0 af-0 sf-0 of-0  ]
+PATTERN:    0x0F 0xAE MOD[0b11] MOD=3  REG[0b110] RM[nnn]  osz_refining_prefix      norexw_prefix
+OPERANDS:    REG0=GPR32_B():r:d:u32 REG1=XED_REG_EDX:r:SUPP:d:u32 REG2=XED_REG_EAX:r:SUPP:d:u32
+IFORM:       TPAUSE_GPR32u32
+}
+
+
+# EMITTING TPAUSE (TPAUSE-N/A-1-64)
+{
+ICLASS:      TPAUSE
+CPL:         3
+CATEGORY:    WAITPKG
+EXTENSION:   WAITPKG
+ISA_SET:     WAITPKG
+REAL_OPCODE: Y
+FLAGS:       MUST [  cf-mod zf-0 pf-0 af-0 sf-0 of-0  ]
+PATTERN:    0x0F 0xAE MOD[0b11] MOD=3  REG[0b110] RM[nnn]  osz_refining_prefix      mode64 rexw_prefix
+OPERANDS:    REG0=GPR64_B():r:q:u64 REG1=XED_REG_EDX:r:SUPP:d:u32 REG2=XED_REG_EAX:r:SUPP:d:u32
+IFORM:       TPAUSE_GPR64u64
+}
+
+
+# EMITTING UMONITOR (UMONITOR-N/A-1)
+{
+ICLASS:      UMONITOR
+CPL:         3
+CATEGORY:    WAITPKG
+EXTENSION:   WAITPKG
+ISA_SET:     WAITPKG
+REAL_OPCODE: Y
+PATTERN:    0x0F 0xAE MOD[0b11] MOD=3  REG[0b110] RM[nnn]  f3_refining_prefix
+OPERANDS:    REG0=A_GPR_B():r
+IFORM:       UMONITOR_GPRa
+}
+
+
+# EMITTING UMWAIT (UMWAIT-N/A-1-32)
+{
+ICLASS:      UMWAIT
+CPL:         3
+CATEGORY:    WAITPKG
+EXTENSION:   WAITPKG
+ISA_SET:     WAITPKG
+REAL_OPCODE: Y
+FLAGS:       MUST [  cf-mod zf-0 pf-0 af-0 sf-0 of-0  ]
+PATTERN:    0x0F 0xAE MOD[0b11] MOD=3  REG[0b110] RM[nnn]  f2_refining_prefix      norexw_prefix
+OPERANDS:    REG0=GPR32_B():r:d:u32 REG1=XED_REG_EDX:r:SUPP:d:u32 REG2=XED_REG_EAX:r:SUPP:d:u32
+IFORM:       UMWAIT_GPR32
+}
+
+
+# EMITTING UMWAIT (UMWAIT-N/A-1-64)
+{
+ICLASS:      UMWAIT
+CPL:         3
+CATEGORY:    WAITPKG
+EXTENSION:   WAITPKG
+ISA_SET:     WAITPKG
+REAL_OPCODE: Y
+FLAGS:       MUST [  cf-mod zf-0 pf-0 af-0 sf-0 of-0  ]
+PATTERN:    0x0F 0xAE MOD[0b11] MOD=3  REG[0b110] RM[nnn]  f2_refining_prefix      mode64 rexw_prefix
+OPERANDS:    REG0=GPR64_B():r:q:u64 REG1=XED_REG_EDX:r:SUPP:d:u32 REG2=XED_REG_EAX:r:SUPP:d:u32
+IFORM:       UMWAIT_GPR64
+}
+
+
+
+
+###FILE: ../xed/datafiles/cldemote/cldemote-nop-mod.xed.txt
+
+#BEGIN_LEGAL
+#
+#Copyright (c) 2018 Intel Corporation
+#
+#  Licensed under the Apache License, Version 2.0 (the "License");
+#  you may not use this file except in compliance with the License.
+#  You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+#  Unless required by applicable law or agreed to in writing, software
+#  distributed under the License is distributed on an "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#  See the License for the specific language governing permissions and
+#  limitations under the License.
+#
+#END_LEGAL
+
+
+INSTRUCTIONS()::
+
+UDELETE: NOP0F1C
+
+{
+ICLASS    : NOP
+#UNAME     : NOP0F1C
 CPL       : 3
-CATEGORY  : XSAVE
-EXTENSION : XSAVEC
-COMMENT   : variable length store
-ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED
-PATTERN   : 0x0F 0xC7 MOD[mm]  MOD!=3 REG[0b100] RM[nnn] MODRM() norexw_prefix no_refining_prefix
-OPERANDS  : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP
+CATEGORY  : WIDENOP
+EXTENSION : BASE
+ATTRIBUTES: NOP
+ISA_SET   : PPRO
+COMMENT   : memory form with MODRM.REG=0b000 and no refining prefix is CLDEMOTE
+PATTERN   : 0x0F 0x1C MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() f2_refining_prefix
+OPERANDS  : MEM0:r:v REG0=GPRv_R():r
+IFORM     : NOP_MEMv_GPRv_0F1C
+PATTERN   : 0x0F 0x1C MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() f3_refining_prefix
+OPERANDS  : MEM0:r:v REG0=GPRv_R():r
+IFORM     : NOP_MEMv_GPRv_0F1C
+PATTERN   : 0x0F 0x1C MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() osz_refining_prefix
+OPERANDS  : MEM0:r:v REG0=GPRv_R():r
+IFORM     : NOP_MEMv_GPRv_0F1C
+
+
+PATTERN   : 0x0F 0x1C MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()
+OPERANDS  : MEM0:r:v REG0=GPRv_R():r
+IFORM     : NOP_MEMv_GPRv_0F1C
+PATTERN   : 0x0F 0x1C MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()
+OPERANDS  : MEM0:r:v REG0=GPRv_R():r
+IFORM     : NOP_MEMv_GPRv_0F1C
+PATTERN   : 0x0F 0x1C MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()
+OPERANDS  : MEM0:r:v REG0=GPRv_R():r
+IFORM     : NOP_MEMv_GPRv_0F1C
+PATTERN   : 0x0F 0x1C MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()
+OPERANDS  : MEM0:r:v REG0=GPRv_R():r
+IFORM     : NOP_MEMv_GPRv_0F1C
+PATTERN   : 0x0F 0x1C MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()
+OPERANDS  : MEM0:r:v REG0=GPRv_R():r
+IFORM     : NOP_MEMv_GPRv_0F1C
+PATTERN   : 0x0F 0x1C MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()
+OPERANDS  : MEM0:r:v REG0=GPRv_R():r
+IFORM     : NOP_MEMv_GPRv_0F1C
+PATTERN   : 0x0F 0x1C MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()
+OPERANDS  : MEM0:r:v REG0=GPRv_R():r
+IFORM     : NOP_MEMv_GPRv_0F1C
 }
 
+# re-defined by another contemporaneous ISA extension
+{
+ICLASS    : NOP
+UNAME     : NOP0F1C_REG
+CPL       : 3
+CATEGORY  : WIDENOP
+EXTENSION : BASE
+ATTRIBUTES: NOP
+ISA_SET   : PPRO
 
+# reg form
+PATTERN   : 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=GPRv_B():r REG1=GPRv_R():r
+IFORM     : NOP_GPRv_GPRv_0F1C
+}
 
 {
-ICLASS    : XSAVEC64
+ICLASS    : NOP
+UNAME     : NOP0F1C_MEM
 CPL       : 3
-CATEGORY  : XSAVE
-EXTENSION : XSAVEC
-COMMENT   : variable length store
-ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r  NOTSX SPECIAL_AGEN_REQUIRED
-PATTERN   : 0x0F 0xC7 MOD[mm]  MOD!=3 REG[0b100] RM[nnn] MODRM() rexw_prefix no_refining_prefix
-OPERANDS  : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP
+CATEGORY  : WIDENOP
+EXTENSION : BASE
+ATTRIBUTES: NOP
+ISA_SET   : PPRO
+
+PATTERN   : 0x0F 0x1C MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() no_refining_prefix CLDEMOTE=0
+OPERANDS  : MEM0:r:v REG0=GPRv_R():r
+IFORM     : NOP_MEMv_GPRv_0F1C
+}
+
+
+
+###FILE: ../xed/datafiles/cldemote/cldemote-isa.xed.txt
+
+#BEGIN_LEGAL
+#
+#Copyright (c) 2018 Intel Corporation
+#
+#  Licensed under the Apache License, Version 2.0 (the "License");
+#  you may not use this file except in compliance with the License.
+#  You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+#  Unless required by applicable law or agreed to in writing, software
+#  distributed under the License is distributed on an "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#  See the License for the specific language governing permissions and
+#  limitations under the License.
+#
+#END_LEGAL
+#
+#
+#
+#    ***** GENERATED FILE -- DO NOT EDIT! *****
+#    ***** GENERATED FILE -- DO NOT EDIT! *****
+#    ***** GENERATED FILE -- DO NOT EDIT! *****
+#
+#
+#
+INSTRUCTIONS()::
+# EMITTING CLDEMOTE (CLDEMOTE-N/A-1)
+{
+ICLASS:      CLDEMOTE
+CPL:         3
+CATEGORY:    CLDEMOTE
+EXTENSION:   CLDEMOTE
+ISA_SET:     CLDEMOTE
+REAL_OPCODE: Y
+PATTERN:     0x0F 0x1C MOD[mm] MOD!=3 REG[0b000] RM[nnn]  MODRM()  no_refining_prefix     CLDEMOTE=1
+OPERANDS:    MEM0:r:b:u8
+IFORM:       CLDEMOTE_MEMu8
+}
+
+
+
+
+###FILE: ../xed/datafiles/sgx-enclv/sgx-enclv-isa.xed.txt
+
+#BEGIN_LEGAL
+#
+#Copyright (c) 2018 Intel Corporation
+#
+#  Licensed under the Apache License, Version 2.0 (the "License");
+#  you may not use this file except in compliance with the License.
+#  You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+#  Unless required by applicable law or agreed to in writing, software
+#  distributed under the License is distributed on an "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#  See the License for the specific language governing permissions and
+#  limitations under the License.
+#
+#END_LEGAL
+#
+#
+#
+#    ***** GENERATED FILE -- DO NOT EDIT! *****
+#    ***** GENERATED FILE -- DO NOT EDIT! *****
+#    ***** GENERATED FILE -- DO NOT EDIT! *****
+#
+#
+#
+INSTRUCTIONS()::
+# EMITTING ENCLV (ENCLV-N/A-1)
+{
+ICLASS:      ENCLV
+CPL:         3
+CATEGORY:    SGX
+EXTENSION:   SGX_ENCLV
+ISA_SET:     SGX_ENCLV
+REAL_OPCODE: Y
+PATTERN:     0x0F 0x01 MOD[0b11] MOD=3  REG[0b000] RM[0b000]  no_refining_prefix
+OPERANDS:    REG0=XED_REG_EAX:r:SUPP:d:u32 REG1=XED_REG_RBX:crw:SUPP:q:u64 REG2=XED_REG_RCX:crw:SUPP:q:u64 REG3=XED_REG_RDX:crw:SUPP:q:u64
+IFORM:       ENCLV
 }
 
 
@@ -18188,7 +19774,7 @@ OPERANDS  : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=X
 
 #BEGIN_LEGAL
 #
-#Copyright (c) 2016 Intel Corporation
+#Copyright (c) 2018 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -18515,10 +20101,10 @@ EXTENSION : AVX
 
 ATTRIBUTES : simd_scalar MXCSR
 
-PATTERN : VV1 0xC2   VF3 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
+PATTERN : VV1 0xC2   VF3 V0F  MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
 OPERANDS  : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 IMM0:r:b
 
-PATTERN : VV1 0xC2   VF3 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
+PATTERN : VV1 0xC2   VF3 V0F  MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
 OPERANDS  : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 IMM0:r:b
 }
 
@@ -18728,26 +20314,27 @@ CPL       : 3
 CATEGORY  : CONVERT
 EXTENSION : AVX
 ATTRIBUTES : simd_scalar MXCSR
+COMMENT   : SNB/IVB/HSW require VEX.L=128. Later processors are LIG
 
-PATTERN : VV1 0x2D   VF2 V0F VL128 NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+PATTERN : VV1 0x2D   VF2 V0F  NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS  : REG0=GPR32_R():w:d:i32 MEM0:r:q:f64
 
-PATTERN : VV1 0x2D   VF2 V0F VL128 NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+PATTERN : VV1 0x2D   VF2 V0F  NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
 OPERANDS  : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:q:f64
 
 
-PATTERN : VV1 0x2D   VF2 V0F VL128 NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+PATTERN : VV1 0x2D   VF2 V0F  NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS  : REG0=GPR32_R():w:d:i32 MEM0:r:q:f64
 
-PATTERN : VV1 0x2D   VF2 V0F VL128 NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+PATTERN : VV1 0x2D   VF2 V0F  NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
 OPERANDS  : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:q:f64
 
 
 
-PATTERN : VV1 0x2D   VF2 V0F VL128 NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+PATTERN : VV1 0x2D   VF2 V0F  NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS  : REG0=GPR64_R():w:q:i64 MEM0:r:q:f64
 
-PATTERN : VV1 0x2D   VF2 V0F VL128 NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+PATTERN : VV1 0x2D   VF2 V0F  NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
 OPERANDS  : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:q:f64
 }
 
@@ -18758,27 +20345,29 @@ CPL       : 3
 CATEGORY  : CONVERT
 EXTENSION : AVX
 ATTRIBUTES : simd_scalar MXCSR
+COMMENT   : SNB/IVB/HSW require VEX.L=128. Later processors are LIG
+
 
-PATTERN : VV1 0x2C   VF2 V0F VL128 NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+PATTERN : VV1 0x2C   VF2 V0F  NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS  : REG0=GPR32_R():w:d:i32 MEM0:r:q:f64
 
-PATTERN : VV1 0x2C   VF2 V0F VL128 NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+PATTERN : VV1 0x2C   VF2 V0F  NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
 OPERANDS  : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:q:f64
 
 
 
-PATTERN : VV1 0x2C   VF2 V0F VL128 NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+PATTERN : VV1 0x2C   VF2 V0F  NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS  : REG0=GPR32_R():w:d:i32 MEM0:r:q:f64
 
-PATTERN : VV1 0x2C   VF2 V0F VL128 NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+PATTERN : VV1 0x2C   VF2 V0F  NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
 OPERANDS  : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:q:f64
 
 
 
-PATTERN : VV1 0x2C   VF2 V0F VL128 NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+PATTERN : VV1 0x2C   VF2 V0F  NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS  : REG0=GPR64_R():w:q:i64 MEM0:r:q:f64
 
-PATTERN : VV1 0x2C   VF2 V0F VL128 NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+PATTERN : VV1 0x2C   VF2 V0F  NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
 OPERANDS  : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:q:f64
 }
 
@@ -18792,26 +20381,27 @@ CPL       : 3
 CATEGORY  : CONVERT
 EXTENSION : AVX
 ATTRIBUTES : simd_scalar MXCSR
+COMMENT   : SNB/IVB/HSW require VEX.L=128. Later processors are LIG
 
-PATTERN : VV1 0x2D   VF3 V0F VL128 NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+PATTERN : VV1 0x2D   VF3 V0F  NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS  : REG0=GPR32_R():w:d:i32 MEM0:r:d:f32
 
-PATTERN : VV1 0x2D   VF3 V0F VL128 NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+PATTERN : VV1 0x2D   VF3 V0F  NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
 OPERANDS  : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:d:f32
 
 
 
-PATTERN : VV1 0x2D   VF3 V0F VL128 NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+PATTERN : VV1 0x2D   VF3 V0F  NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS  : REG0=GPR32_R():w:d:i32 MEM0:r:d:f32
 
-PATTERN : VV1 0x2D   VF3 V0F VL128 NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+PATTERN : VV1 0x2D   VF3 V0F  NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
 OPERANDS  : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:d:f32
 
 
-PATTERN : VV1 0x2D   VF3 V0F VL128 NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+PATTERN : VV1 0x2D   VF3 V0F  NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS  : REG0=GPR64_R():w:q:i64 MEM0:r:d:f32
 
-PATTERN : VV1 0x2D   VF3 V0F VL128 NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+PATTERN : VV1 0x2D   VF3 V0F  NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
 OPERANDS  : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:d:f32
 }
 
@@ -18822,28 +20412,29 @@ CPL       : 3
 CATEGORY  : CONVERT
 EXTENSION : AVX
 ATTRIBUTES : simd_scalar MXCSR
+COMMENT   : SNB/IVB/HSW require VEX.L=128. Later processors are LIG
 
-PATTERN : VV1 0x2C   VF3 V0F VL128 NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+PATTERN : VV1 0x2C   VF3 V0F  NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS  : REG0=GPR32_R():w:d:i32 MEM0:r:d:f32
 
-PATTERN : VV1 0x2C   VF3 V0F VL128 NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+PATTERN : VV1 0x2C   VF3 V0F  NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
 OPERANDS  : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:d:f32
 
 
 
-PATTERN : VV1 0x2C   VF3 V0F VL128 NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+PATTERN : VV1 0x2C   VF3 V0F  NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS  : REG0=GPR32_R():w:d:i32 MEM0:r:d:f32
 
-PATTERN : VV1 0x2C   VF3 V0F VL128 NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+PATTERN : VV1 0x2C   VF3 V0F  NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
 OPERANDS  : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:d:f32
 
 
 
 
-PATTERN : VV1 0x2C   VF3 V0F VL128 NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+PATTERN : VV1 0x2C   VF3 V0F  NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS  : REG0=GPR64_R():w:q:i64 MEM0:r:d:f32
 
-PATTERN : VV1 0x2C   VF3 V0F VL128 NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+PATTERN : VV1 0x2C   VF3 V0F  NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
 OPERANDS  : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:d:f32
 }
 
@@ -19378,7 +20969,7 @@ EXCEPTIONS: avx-type-6
 CPL       : 3
 CATEGORY  : AVX
 EXTENSION : AVX
-ATTRIBUTES : maskop
+ATTRIBUTES : maskop NONTEMPORAL
 # load  forms
 PATTERN : VV1 0x2C V66 VL128 V0F38 norexw_prefix  MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS  : REG0=XMM_R():w:dq:f32   REG1=XMM_N():r:dq MEM0:r:dq:f32
@@ -22266,9 +23857,9 @@ EXCEPTIONS: avx-type-5
 CPL       : 3
 CATEGORY  : AVX
 EXTENSION : AVX
-PATTERN : VV1 0x16  VL128 V66 V0F3A rexw_prefix mode64  NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
+PATTERN : VV1 0x16  VL128 V66 V0F3A mode64 rexw_prefix  NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
 OPERANDS  : MEM0:w:q              REG0=XMM_R():r:dq:u64 IMM0:r:b
-PATTERN : VV1 0x16  VL128 V66 V0F3A rexw_prefix mode64 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
+PATTERN : VV1 0x16  VL128 V66 V0F3A mode64 rexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
 OPERANDS  : REG0=GPR64_B():w:q    REG1=XMM_R():r:dq:u64 IMM0:r:b
 }
 ############################################################################
@@ -22278,10 +23869,20 @@ EXCEPTIONS: avx-type-5
 CPL       : 3
 CATEGORY  : AVX
 EXTENSION : AVX
-PATTERN : VV1 0x16  VL128 V66 V0F3A norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
-OPERANDS  : MEM0:w:d           REG0=XMM_R():r:dq:u32 IMM0:r:b
-PATTERN : VV1 0x16  VL128 V66 V0F3A norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
+COMMENT   : SNB had an errata where it would #UD of VEX.W=1 outside of 64b mode.  Not modeled.
+
+# 64b mode
+PATTERN   : VV1 0x16 VL128 V66 V0F3A mode64 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
+OPERANDS  : MEM0:w:d REG0=XMM_R():r:dq:u32 IMM0:r:b
+PATTERN   : VV1 0x16 VL128 V66 V0F3A mode64 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
+OPERANDS  : REG0=GPR32_B():w:d REG1=XMM_R():r:dq:u32 IMM0:r:b
+
+# not64b mode
+PATTERN   : VV1 0x16 VL128 V66 V0F3A not64  NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
+OPERANDS  : MEM0:w:d REG0=XMM_R():r:dq:u32 IMM0:r:b
+PATTERN   : VV1 0x16 VL128 V66 V0F3A not64  NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
 OPERANDS  : REG0=GPR32_B():w:d REG1=XMM_R():r:dq:u32 IMM0:r:b
+
 }
 ############################################################################
 
@@ -22323,9 +23924,17 @@ EXCEPTIONS: avx-type-5
 CPL       : 3
 CATEGORY  : AVX
 EXTENSION : AVX
-PATTERN : VV1 0x22  VL128 V66 V0F3A norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
+COMMENT   : SNB had an errata where it would #UD of VEX.W=1 outside of 64b mode. Not modeled
+# 64b mode
+PATTERN : VV1 0x22  VL128 V66 V0F3A mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
 OPERANDS  : REG0=XMM_R():w:dq:u32     REG1=XMM_N():r:dq:u32  MEM0:r:d:u32            IMM0:r:b
-PATTERN : VV1 0x22  VL128 V66 V0F3A norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
+PATTERN : VV1 0x22  VL128 V66 V0F3A mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
+OPERANDS  : REG0=XMM_R():w:dq:u32     REG1=XMM_N():r:dq:u32  REG2=GPR32_B():r:d:u32  IMM0:r:b
+
+# 32b mode
+PATTERN : VV1 0x22  VL128 V66 V0F3A not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
+OPERANDS  : REG0=XMM_R():w:dq:u32     REG1=XMM_N():r:dq:u32  MEM0:r:d:u32            IMM0:r:b
+PATTERN : VV1 0x22  VL128 V66 V0F3A not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
 OPERANDS  : REG0=XMM_R():w:dq:u32     REG1=XMM_N():r:dq:u32  REG2=GPR32_B():r:d:u32  IMM0:r:b
 }
 {
@@ -22334,9 +23943,9 @@ EXCEPTIONS: avx-type-5
 CPL       : 3
 CATEGORY  : AVX
 EXTENSION : AVX
-PATTERN : VV1 0x22  VL128 V66 V0F3A rexw_prefix mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
+PATTERN : VV1 0x22  VL128 V66 V0F3A mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
 OPERANDS  : REG0=XMM_R():w:dq:u64     REG1=XMM_N():r:dq:u64  MEM0:r:q:u64            IMM0:r:b
-PATTERN : VV1 0x22  VL128 V66 V0F3A rexw_prefix mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
+PATTERN : VV1 0x22  VL128 V66 V0F3A mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
 OPERANDS  : REG0=XMM_R():w:dq:u64     REG1=XMM_N():r:dq:u64  REG2=GPR64_B():r:q:u64  IMM0:r:b
 }
 
@@ -22361,14 +23970,23 @@ PATTERN : VV1 0x61  VL128 V66 V0F3A NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
 OPERANDS  : REG0=XMM_R():r:dq     REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_ECX:w:SUPP
 
 # in 64b mode, vex.w changes the behavior for GPRs
-PATTERN : VV1 0x61  VL128 V66 V0F3A NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
+PATTERN : VV1 0x61  VL128 V66 V0F3A NOVSR mode64 EOSZ=2 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
 OPERANDS  : REG0=XMM_R():r:dq     MEM0:r:dq         IMM0:r:b REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_EDX:r:SUPP REG3=XED_REG_ECX:w:SUPP
-PATTERN : VV1 0x61  VL128 V66 V0F3A NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
+PATTERN : VV1 0x61  VL128 V66 V0F3A NOVSR mode64 EOSZ=2 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
 OPERANDS  : REG0=XMM_R():r:dq     REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_ECX:w:SUPP
+}
+{
+ICLASS    : VPCMPESTRI
+
+EXCEPTIONS: avx-type-4
+CPL       : 3
+CATEGORY  : STTNI
+EXTENSION : AVX
+FLAGS     : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ]
 
-PATTERN : VV1 0x61  VL128 V66 V0F3A NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
+PATTERN : VV1 0x61  VL128 V66 V0F3A NOVSR mode64 EOSZ=3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
 OPERANDS  : REG0=XMM_R():r:dq     MEM0:r:dq         IMM0:r:b REG1=XED_REG_RAX:r:SUPP REG2=XED_REG_RDX:r:SUPP REG3=XED_REG_RCX:w:SUPP
-PATTERN : VV1 0x61  VL128 V66 V0F3A NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
+PATTERN : VV1 0x61  VL128 V66 V0F3A NOVSR mode64 EOSZ=3 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
 OPERANDS  : REG0=XMM_R():r:dq     REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_RAX:r:SUPP REG3=XED_REG_RDX:r:SUPP REG4=XED_REG_RCX:w:SUPP
 }
 {
@@ -22386,14 +24004,22 @@ PATTERN : VV1 0x63  VL128 V66 V0F3A NOVSR  not64  MOD[0b11] MOD=3 REG[rrr] RM[nn
 OPERANDS  : REG0=XMM_R():r:dq     REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_ECX:w:SUPP
 
 # in 64b mode, vex.w changes the behavior for GPRs
-PATTERN : VV1 0x63  VL128 V66 V0F3A NOVSR mode64 norexw_prefix  MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
+PATTERN : VV1 0x63  VL128 V66 V0F3A NOVSR mode64 EOSZ=2  MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
 OPERANDS  : REG0=XMM_R():r:dq     MEM0:r:dq         IMM0:r:b REG1=XED_REG_ECX:w:SUPP
-PATTERN : VV1 0x63  VL128 V66 V0F3A NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
+PATTERN : VV1 0x63  VL128 V66 V0F3A NOVSR mode64 EOSZ=2 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
 OPERANDS  : REG0=XMM_R():r:dq     REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_ECX:w:SUPP
+}
+{
+ICLASS    : VPCMPISTRI
+EXCEPTIONS: avx-type-4
+CPL       : 3
+CATEGORY  : STTNI
+EXTENSION : AVX
+FLAGS     : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ]
 
-PATTERN : VV1 0x63  VL128 V66 V0F3A NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
+PATTERN : VV1 0x63  VL128 V66 V0F3A NOVSR mode64 EOSZ=3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
 OPERANDS  : REG0=XMM_R():r:dq     MEM0:r:dq         IMM0:r:b REG1=XED_REG_RCX:w:SUPP
-PATTERN : VV1 0x63  VL128 V66 V0F3A NOVSR mode64 rexw_prefix  MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
+PATTERN : VV1 0x63  VL128 V66 V0F3A NOVSR mode64 EOSZ=3  MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
 OPERANDS  : REG0=XMM_R():r:dq     REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_RCX:w:SUPP
 }
 
@@ -22412,14 +24038,23 @@ PATTERN : VV1 0x60  VL128 V66 V0F3A NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
 OPERANDS  : REG0=XMM_R():r:dq     REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_XMM0:w:dq:SUPP
 
 # in 64b mode, vex.w changes the behavior for GPRs
-PATTERN : VV1 0x60  VL128 V66 V0F3A NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
+PATTERN : VV1 0x60  VL128 V66 V0F3A NOVSR mode64 EOSZ=2 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
 OPERANDS  : REG0=XMM_R():r:dq     MEM0:r:dq         IMM0:r:b REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_EDX:r:SUPP REG3=XED_REG_XMM0:w:dq:SUPP
-PATTERN : VV1 0x60  VL128 V66 V0F3A NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
+PATTERN : VV1 0x60  VL128 V66 V0F3A NOVSR mode64 EOSZ=2 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
 OPERANDS  : REG0=XMM_R():r:dq     REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_XMM0:w:dq:SUPP
+}
+
+{
+ICLASS    : VPCMPESTRM
+EXCEPTIONS: avx-type-4
+CPL       : 3
+CATEGORY  : STTNI
+EXTENSION : AVX
+FLAGS     : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ]
 
-PATTERN : VV1 0x60  VL128 V66 V0F3A NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
+PATTERN : VV1 0x60  VL128 V66 V0F3A NOVSR mode64 EOSZ=3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
 OPERANDS  : REG0=XMM_R():r:dq     MEM0:r:dq         IMM0:r:b REG1=XED_REG_RAX:r:SUPP REG2=XED_REG_RDX:r:SUPP REG3=XED_REG_XMM0:w:dq:SUPP
-PATTERN : VV1 0x60  VL128 V66 V0F3A NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
+PATTERN : VV1 0x60  VL128 V66 V0F3A NOVSR mode64 EOSZ=3 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
 OPERANDS  : REG0=XMM_R():r:dq     REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_RAX:r:SUPP REG3=XED_REG_RDX:r:SUPP REG4=XED_REG_XMM0:w:dq:SUPP
 }
 
@@ -22444,9 +24079,10 @@ OPERANDS  : REG0=XMM_R():r:dq     REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_XMM0:w
 ICLASS    : VMASKMOVDQU
 EXCEPTIONS: avx-type-4
 CPL       : 3
+
 CATEGORY  : AVX
 EXTENSION : AVX
-ATTRIBUTES : maskop fixed_base0 NOTSX
+ATTRIBUTES : maskop fixed_base0 NOTSX NONTEMPORAL
 PATTERN : VV1 0xF7 V0F V66 VL128  NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
 OPERANDS  : REG0=XMM_R():r:dq:u8 REG1=XMM_B():r:dq:u8 MEM0:w:SUPP:dq:u8 BASE0=ArDI():r:SUPP SEG0=FINAL_DSEG():r:SUPP
 }
@@ -22459,7 +24095,7 @@ CPL       : 3
 CATEGORY  : AVX
 EXTENSION : AVX
 ATTRIBUTES: MXCSR
-PATTERN   : VV1 0xAE VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[0b010] RM[nnn] no_refining_prefix MODRM()
+PATTERN   : VV1 0xAE VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()
 OPERANDS  : MEM0:r:d REG0=XED_REG_MXCSR:w:SUPP
 }
 {
@@ -22469,7 +24105,7 @@ CPL       : 3
 CATEGORY  : AVX
 EXTENSION : AVX
 ATTRIBUTES: MXCSR_RD
-PATTERN   : VV1 0xAE VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[0b011] RM[nnn] no_refining_prefix MODRM()
+PATTERN   : VV1 0xAE VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()
 OPERANDS  : MEM0:w:d REG0=XED_REG_MXCSR:r:SUPP
 }
 #######################################################################################
@@ -22544,7 +24180,7 @@ EXCEPTIONS: avx-type-1
 CPL       : 3
 CATEGORY  : DATAXFER
 EXTENSION : AVX
-ATTRIBUTES :  REQUIRES_ALIGNMENT NOTSX
+ATTRIBUTES :  REQUIRES_ALIGNMENT NOTSX  NONTEMPORAL
 
 PATTERN : VV1 0x2A  V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS  : REG0=XMM_R():w:dq MEM0:r:dq
@@ -22560,7 +24196,7 @@ EXCEPTIONS: avx-type-1
 CPL       : 3
 CATEGORY  : DATAXFER
 EXTENSION : AVX
-ATTRIBUTES :  REQUIRES_ALIGNMENT NOTSX
+ATTRIBUTES :  REQUIRES_ALIGNMENT NOTSX NONTEMPORAL
 PATTERN : VV1 0xE7  V66 V0F VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS : MEM0:w:dq:i32  REG0=XMM_R():r:dq:i32
 
@@ -22571,7 +24207,7 @@ EXCEPTIONS: avx-type-1
 CPL       : 3
 CATEGORY  : DATAXFER
 EXTENSION : AVX
-ATTRIBUTES :  REQUIRES_ALIGNMENT NOTSX
+ATTRIBUTES :  REQUIRES_ALIGNMENT NOTSX NONTEMPORAL
 PATTERN : VV1 0x2B  V66 V0F VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS : MEM0:w:dq:f64  REG0=XMM_R():r:dq:f64
 
@@ -22582,7 +24218,7 @@ EXCEPTIONS: avx-type-1
 CPL       : 3
 CATEGORY  : DATAXFER
 EXTENSION : AVX
-ATTRIBUTES :  REQUIRES_ALIGNMENT NOTSX
+ATTRIBUTES :  REQUIRES_ALIGNMENT NOTSX NONTEMPORAL
 PATTERN : VV1 0x2B  VNP V0F VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS : MEM0:w:dq:f32  REG0=XMM_R():r:dq:f32
 
@@ -22594,7 +24230,7 @@ OPERANDS : MEM0:w:dq:f32  REG0=XMM_R():r:dq:f32
 
 #BEGIN_LEGAL
 #
-#Copyright (c) 2016 Intel Corporation
+#Copyright (c) 2018 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -22618,7 +24254,7 @@ EXCEPTIONS: avx-type-1
 CPL       : 3
 CATEGORY  : DATAXFER
 EXTENSION : AVX
-ATTRIBUTES :  REQUIRES_ALIGNMENT NOTSX
+ATTRIBUTES :  REQUIRES_ALIGNMENT NOTSX NONTEMPORAL
 PATTERN : VV1 0xE7  V66 V0F VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS : MEM0:w:qq:i32  REG0=YMM_R():r:qq:i32
 
@@ -22629,7 +24265,7 @@ EXCEPTIONS: avx-type-1
 CPL       : 3
 CATEGORY  : DATAXFER
 EXTENSION : AVX
-ATTRIBUTES :  REQUIRES_ALIGNMENT NOTSX
+ATTRIBUTES :  REQUIRES_ALIGNMENT NOTSX NONTEMPORAL
 PATTERN : VV1 0x2B  V66 V0F VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS : MEM0:w:qq:f64  REG0=YMM_R():r:qq:f64
 
@@ -22640,7 +24276,7 @@ EXCEPTIONS: avx-type-1
 CPL       : 3
 CATEGORY  : DATAXFER
 EXTENSION : AVX
-ATTRIBUTES :  REQUIRES_ALIGNMENT NOTSX
+ATTRIBUTES :  REQUIRES_ALIGNMENT NOTSX NONTEMPORAL
 PATTERN : VV1 0x2B  VNP V0F VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
 OPERANDS : MEM0:w:qq:f32  REG0=YMM_R():r:qq:f32
 
@@ -22652,7 +24288,7 @@ OPERANDS : MEM0:w:qq:f32  REG0=YMM_R():r:qq:f32
 
 #BEGIN_LEGAL
 #
-#Copyright (c) 2016 Intel Corporation
+#Copyright (c) 2018 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -22742,7 +24378,7 @@ OPERANDS  : REG0=XMM_R():w:dq  MEM0:r:dq
 
 #BEGIN_LEGAL
 #
-#Copyright (c) 2016 Intel Corporation
+#Copyright (c) 2018 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -22775,7 +24411,7 @@ OPERANDS  : REG0=XMM_R():w:dq:u128  REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 IMM0:r:b
 
 #BEGIN_LEGAL
 #
-#Copyright (c) 2016 Intel Corporation
+#Copyright (c) 2018 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -22846,11 +24482,1272 @@ OPERANDS  : REG0=XMM_B():w:dq:f16 REG1=YMM_R():r:qq:f32    IMM0:r:b
 
 
 
-###FILE: ../xed/datafiles/avxhsw/gather-isa.txt
+###FILE: ../xed/datafiles/hswavx/avx-fma-isa.xed.txt
+
+#BEGIN_LEGAL
+#
+#Copyright (c) 2018 Intel Corporation
+#
+#  Licensed under the Apache License, Version 2.0 (the "License");
+#  you may not use this file except in compliance with the License.
+#  You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+#  Unless required by applicable law or agreed to in writing, software
+#  distributed under the License is distributed on an "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#  See the License for the specific language governing permissions and
+#  limitations under the License.
+#
+#END_LEGAL
+AVX_INSTRUCTIONS()::
+
+# Issues: encoder is at a loss for vmaddps xmm0,xmm0,xmm0,xmm0.
+# Encoder must enforce equality between two parameters. Never had to do this before.
+#   Extra check?
+# Decoder must rip off suffixes _DDMR, _DDRM, _DRMD  in disassembly (eventually)
+#############################################################################################
+# Operand orders:
+#             A  =  B   *  C     +  D
+#Type 1)   reg0  reg0  mem/reg1  reg2          DDMR  312 or 132
+#Type 2)   reg0  reg0  reg1      mem/reg2      DDRM  123 or 213
+#Type 3)   reg0  reg1  mem/reg2  reg0          DRMD  321 or 231
+
+# dst is in MODRM.REG
+# regsrc is in VEX.vvvv
+# memop is in MODRM.RM
+############################################################################################
+
+
+
+
+
+
+
+
+
+
+
+
+##########################################################
+
+
+
+
+
+
+
+
+
+
+
+
+##################################################################
+
+
+
+
+
+
+
+
+
+
+
+
+
+##################################################################
+{
+ICLASS    : VFMADD132PD
+EXCEPTIONS: avx-type-2
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR
+# R/M 128
+PATTERN : VV1 0x98 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64
+# R/R 128
+PATTERN : VV1 0x98 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
+
+
+# R/M 256
+PATTERN : VV1 0x98 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64
+# R/R 256
+PATTERN : VV1 0x98 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
+}
+{
+ICLASS    : VFMADD132PS
+EXCEPTIONS: avx-type-2
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR
+# R/M 128
+PATTERN : VV1 0x98 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
+# R/R 128
+PATTERN : VV1 0x98 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
+
+
+# R/M 256
+PATTERN : VV1 0x98 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
+# R/R 256
+PATTERN : VV1 0x98 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
+}
+{
+ICLASS    : VFMADD132SD
+EXCEPTIONS: avx-type-3
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR simd_scalar
+# R/M 128
+PATTERN : VV1 0x99 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64
+# R/R 128
+PATTERN : VV1 0x99 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64
+}
+{
+ICLASS    : VFMADD132SS
+EXCEPTIONS: avx-type-3
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR simd_scalar
+# R/M 128
+PATTERN : VV1 0x99  V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32
+# R/R 128
+PATTERN : VV1 0x99  V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32
+
+}
+
+{
+ICLASS    : VFMADD213PD
+EXCEPTIONS: avx-type-2
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR
+# R/M 128
+PATTERN : VV1 0xA8 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64    MEM0:r:dq:f64
+# R/R 128
+PATTERN : VV1 0xA8 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
+
+
+# R/M 256
+PATTERN : VV1 0xA8 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64    MEM0:r:qq:f64
+# R/R 256
+PATTERN : VV1 0xA8 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
+}
+{
+ICLASS    : VFMADD213PS
+EXCEPTIONS: avx-type-2
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR
+# R/M 128
+PATTERN : VV1 0xA8 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
+# R/R 128
+PATTERN : VV1 0xA8 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
+
+
+# R/M 256
+PATTERN : VV1 0xA8 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
+# R/R 256
+PATTERN : VV1 0xA8 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
+}
+{
+ICLASS    : VFMADD213SD
+EXCEPTIONS: avx-type-3
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR simd_scalar
+# R/M 128
+PATTERN : VV1 0xA9  V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64     MEM0:r:q:f64
+# R/R 128
+PATTERN : VV1 0xA9  V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64
+
+}
+{
+ICLASS    : VFMADD213SS
+EXCEPTIONS: avx-type-3
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR simd_scalar
+# R/M 128
+PATTERN : VV1 0xA9  V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32     MEM0:r:d:f32
+# R/R 128
+PATTERN : VV1 0xA9  V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32
+}
+
+{
+ICLASS    : VFMADD231PD
+EXCEPTIONS: avx-type-2
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR
+# R/M 128
+PATTERN : VV1 0xB8 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64
+# R/R 128
+PATTERN : VV1 0xB8 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
+
+
+# R/M 256
+PATTERN : VV1 0xB8 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64
+# R/R 256
+PATTERN : VV1 0xB8 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
+
+}
+{
+ICLASS    : VFMADD231PS
+EXCEPTIONS: avx-type-2
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR
+# R/M 128
+PATTERN : VV1 0xB8 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
+# R/R 128
+PATTERN : VV1 0xB8 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
+
+# R/M 256
+PATTERN : VV1 0xB8 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
+# R/R 256
+PATTERN : VV1 0xB8 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
+
+}
+{
+ICLASS    : VFMADD231SD
+EXCEPTIONS: avx-type-3
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR simd_scalar
+# R/M 128
+PATTERN : VV1 0xB9 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64
+# R/R 128
+PATTERN : VV1 0xB9 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64
+
+}
+{
+ICLASS    : VFMADD231SS
+EXCEPTIONS: avx-type-3
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR simd_scalar
+# R/M 128
+PATTERN : VV1 0xB9 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32
+# R/R 128
+PATTERN : VV1 0xB9 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32
+
+}
+
+
+###################################################
+{
+ICLASS    : VFMADDSUB132PD
+EXCEPTIONS: avx-type-2
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR
+# R/M 128
+PATTERN : VV1 0x96 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64
+# R/R 128
+PATTERN : VV1 0x96 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
+
+
+# R/M 256
+PATTERN : VV1 0x96 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64
+# R/R 256
+PATTERN : VV1 0x96 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
+}
+{
+ICLASS    : VFMADDSUB213PD
+EXCEPTIONS: avx-type-2
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR
+# R/M 128
+PATTERN : VV1 0xA6 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64    MEM0:r:dq:f64
+# R/R 128
+PATTERN : VV1 0xA6 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
+
+
+# R/M 256
+PATTERN : VV1 0xA6 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64    MEM0:r:qq:f64
+# R/R 256
+PATTERN : VV1 0xA6 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
+}
+{
+ICLASS    : VFMADDSUB231PD
+EXCEPTIONS: avx-type-2
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR
+# R/M 128
+PATTERN : VV1 0xB6 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64
+# R/R 128
+PATTERN : VV1 0xB6 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
+
+
+# R/M 256
+PATTERN : VV1 0xB6 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64
+# R/R 256
+PATTERN : VV1 0xB6 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
+
+}
+
+{
+ICLASS    : VFMADDSUB132PS
+EXCEPTIONS: avx-type-2
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR
+# R/M 128
+PATTERN : VV1 0x96 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
+# R/R 128
+PATTERN : VV1 0x96 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
+
+
+# R/M 256
+PATTERN : VV1 0x96 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
+# R/R 256
+PATTERN : VV1 0x96 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
+}
+{
+ICLASS    : VFMADDSUB213PS
+EXCEPTIONS: avx-type-2
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR
+# R/M 128
+PATTERN : VV1 0xA6 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
+# R/R 128
+PATTERN : VV1 0xA6 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
+
+
+# R/M 256
+PATTERN : VV1 0xA6 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
+# R/R 256
+PATTERN : VV1 0xA6 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
+}
+{
+ICLASS    : VFMADDSUB231PS
+EXCEPTIONS: avx-type-2
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR
+# R/M 128
+PATTERN : VV1 0xB6 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
+# R/R 128
+PATTERN : VV1 0xB6 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
+
+# R/M 256
+PATTERN : VV1 0xB6 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
+# R/R 256
+PATTERN : VV1 0xB6 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
+
+}
+###################################################
+
+{
+ICLASS    : VFMSUBADD132PD
+EXCEPTIONS: avx-type-2
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR
+# R/M 128
+PATTERN : VV1 0x97 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64
+# R/R 128
+PATTERN : VV1 0x97 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
+
+
+# R/M 256
+PATTERN : VV1 0x97 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64
+# R/R 256
+PATTERN : VV1 0x97 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
+}
+{
+ICLASS    : VFMSUBADD213PD
+EXCEPTIONS: avx-type-2
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR
+# R/M 128
+PATTERN : VV1 0xA7 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64    MEM0:r:dq:f64
+# R/R 128
+PATTERN : VV1 0xA7 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
+
+
+# R/M 256
+PATTERN : VV1 0xA7 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64    MEM0:r:qq:f64
+# R/R 256
+PATTERN : VV1 0xA7 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
+}
+{
+ICLASS    : VFMSUBADD231PD
+EXCEPTIONS: avx-type-2
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR
+# R/M 128
+PATTERN : VV1 0xB7 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64
+# R/R 128
+PATTERN : VV1 0xB7 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
+
+
+# R/M 256
+PATTERN : VV1 0xB7 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64
+# R/R 256
+PATTERN : VV1 0xB7 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
+
+}
+
+{
+ICLASS    : VFMSUBADD132PS
+EXCEPTIONS: avx-type-2
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR
+# R/M 128
+PATTERN : VV1 0x97 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
+# R/R 128
+PATTERN : VV1 0x97 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
+
+
+# R/M 256
+PATTERN : VV1 0x97 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
+# R/R 256
+PATTERN : VV1 0x97 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
+}
+{
+ICLASS    : VFMSUBADD213PS
+EXCEPTIONS: avx-type-2
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR
+# R/M 128
+PATTERN : VV1 0xA7 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
+# R/R 128
+PATTERN : VV1 0xA7 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
+
+
+# R/M 256
+PATTERN : VV1 0xA7 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
+# R/R 256
+PATTERN : VV1 0xA7 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
+}
+{
+ICLASS    : VFMSUBADD231PS
+EXCEPTIONS: avx-type-2
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR
+# R/M 128
+PATTERN : VV1 0xB7 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
+# R/R 128
+PATTERN : VV1 0xB7 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
+
+# R/M 256
+PATTERN : VV1 0xB7 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
+# R/R 256
+PATTERN : VV1 0xB7 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
+
+}
+
+
+###################################################
+
+{
+ICLASS    : VFMSUB132PD
+EXCEPTIONS: avx-type-2
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR
+# R/M 128
+PATTERN : VV1 0x9A VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64
+# R/R 128
+PATTERN : VV1 0x9A VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
+
+
+# R/M 256
+PATTERN : VV1 0x9A VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64
+# R/R 256
+PATTERN : VV1 0x9A VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
+}
+{
+ICLASS    : VFMSUB132PS
+EXCEPTIONS: avx-type-2
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR
+# R/M 128
+PATTERN : VV1 0x9A VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
+# R/R 128
+PATTERN : VV1 0x9A VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
+
+
+# R/M 256
+PATTERN : VV1 0x9A VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
+# R/R 256
+PATTERN : VV1 0x9A VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
+}
+{
+ICLASS    : VFMSUB132SD
+EXCEPTIONS: avx-type-3
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR simd_scalar
+# R/M 128
+PATTERN : VV1 0x9B V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64
+# R/R 128
+PATTERN : VV1 0x9B V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64
+}
+{
+ICLASS    : VFMSUB132SS
+EXCEPTIONS: avx-type-3
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR simd_scalar
+# R/M 128
+PATTERN : VV1 0x9B  V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32
+# R/R 128
+PATTERN : VV1 0x9B  V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32
+
+}
+
+{
+ICLASS    : VFMSUB213PD
+EXCEPTIONS: avx-type-2
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR
+# R/M 128
+PATTERN : VV1 0xAA VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64    MEM0:r:dq:f64
+# R/R 128
+PATTERN : VV1 0xAA VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
+
+
+# R/M 256
+PATTERN : VV1 0xAA VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64    MEM0:r:qq:f64
+# R/R 256
+PATTERN : VV1 0xAA VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
+}
+{
+ICLASS    : VFMSUB213PS
+EXCEPTIONS: avx-type-2
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR
+# R/M 128
+PATTERN : VV1 0xAA VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
+# R/R 128
+PATTERN : VV1 0xAA VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
+
+
+# R/M 256
+PATTERN : VV1 0xAA VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
+# R/R 256
+PATTERN : VV1 0xAA VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
+}
+{
+ICLASS    : VFMSUB213SD
+EXCEPTIONS: avx-type-3
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR simd_scalar
+# R/M 128
+PATTERN : VV1 0xAB  V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64     MEM0:r:q:f64
+# R/R 128
+PATTERN : VV1 0xAB  V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64
+
+}
+{
+ICLASS    : VFMSUB213SS
+EXCEPTIONS: avx-type-3
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR simd_scalar
+# R/M 128
+PATTERN : VV1 0xAB  V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32     MEM0:r:d:f32
+# R/R 128
+PATTERN : VV1 0xAB  V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32
+}
+
+{
+ICLASS    : VFMSUB231PD
+EXCEPTIONS: avx-type-2
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR
+# R/M 128
+PATTERN : VV1 0xBA VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64
+# R/R 128
+PATTERN : VV1 0xBA VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
+
+
+# R/M 256
+PATTERN : VV1 0xBA VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64
+# R/R 256
+PATTERN : VV1 0xBA VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
+
+}
+{
+ICLASS    : VFMSUB231PS
+EXCEPTIONS: avx-type-2
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR
+# R/M 128
+PATTERN : VV1 0xBA VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
+# R/R 128
+PATTERN : VV1 0xBA VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
+
+# R/M 256
+PATTERN : VV1 0xBA VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
+# R/R 256
+PATTERN : VV1 0xBA VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
+
+}
+{
+ICLASS    : VFMSUB231SD
+EXCEPTIONS: avx-type-3
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR simd_scalar
+# R/M 128
+PATTERN : VV1 0xBB V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64
+# R/R 128
+PATTERN : VV1 0xBB V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64
+
+}
+{
+ICLASS    : VFMSUB231SS
+EXCEPTIONS: avx-type-3
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR simd_scalar
+# R/M 128
+PATTERN : VV1 0xBB V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32
+# R/R 128
+PATTERN : VV1 0xBB V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32
+
+}
+
+###################################################
+
+
+{
+ICLASS    : VFNMADD132PD
+EXCEPTIONS: avx-type-2
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR
+# R/M 128
+PATTERN : VV1 0x9C VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64
+# R/R 128
+PATTERN : VV1 0x9C VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
+
+
+# R/M 256
+PATTERN : VV1 0x9C VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64
+# R/R 256
+PATTERN : VV1 0x9C VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
+}
+{
+ICLASS    : VFNMADD132PS
+EXCEPTIONS: avx-type-2
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR
+# R/M 128
+PATTERN : VV1 0x9C VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
+# R/R 128
+PATTERN : VV1 0x9C VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
+
+
+# R/M 256
+PATTERN : VV1 0x9C VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
+# R/R 256
+PATTERN : VV1 0x9C VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
+}
+{
+ICLASS    : VFNMADD132SD
+EXCEPTIONS: avx-type-3
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR simd_scalar
+# R/M 128
+PATTERN : VV1 0x9D V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64
+# R/R 128
+PATTERN : VV1 0x9D V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64
+}
+{
+ICLASS    : VFNMADD132SS
+EXCEPTIONS: avx-type-3
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR simd_scalar
+# R/M 128
+PATTERN : VV1 0x9D  V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32
+# R/R 128
+PATTERN : VV1 0x9D  V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32
+
+}
+
+{
+ICLASS    : VFNMADD213PD
+EXCEPTIONS: avx-type-2
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR
+# R/M 128
+PATTERN : VV1 0xAC VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64    MEM0:r:dq:f64
+# R/R 128
+PATTERN : VV1 0xAC VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
+
+
+# R/M 256
+PATTERN : VV1 0xAC VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64    MEM0:r:qq:f64
+# R/R 256
+PATTERN : VV1 0xAC VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
+}
+{
+ICLASS    : VFNMADD213PS
+EXCEPTIONS: avx-type-2
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR
+# R/M 128
+PATTERN : VV1 0xAC VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
+# R/R 128
+PATTERN : VV1 0xAC VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
+
+
+# R/M 256
+PATTERN : VV1 0xAC VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
+# R/R 256
+PATTERN : VV1 0xAC VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
+}
+{
+ICLASS    : VFNMADD213SD
+EXCEPTIONS: avx-type-3
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR simd_scalar
+# R/M 128
+PATTERN : VV1 0xAD  V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64     MEM0:r:q:f64
+# R/R 128
+PATTERN : VV1 0xAD  V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64
+
+}
+{
+ICLASS    : VFNMADD213SS
+EXCEPTIONS: avx-type-3
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR simd_scalar
+# R/M 128
+PATTERN : VV1 0xAD  V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32     MEM0:r:d:f32
+# R/R 128
+PATTERN : VV1 0xAD  V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32
+}
+
+{
+ICLASS    : VFNMADD231PD
+EXCEPTIONS: avx-type-2
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR
+# R/M 128
+PATTERN : VV1 0xBC VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64
+# R/R 128
+PATTERN : VV1 0xBC VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
+
+
+# R/M 256
+PATTERN : VV1 0xBC VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64
+# R/R 256
+PATTERN : VV1 0xBC VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
+
+}
+{
+ICLASS    : VFNMADD231PS
+EXCEPTIONS: avx-type-2
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR
+# R/M 128
+PATTERN : VV1 0xBC VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
+# R/R 128
+PATTERN : VV1 0xBC VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
+
+# R/M 256
+PATTERN : VV1 0xBC VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
+# R/R 256
+PATTERN : VV1 0xBC VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
+
+}
+{
+ICLASS    : VFNMADD231SD
+EXCEPTIONS: avx-type-3
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR simd_scalar
+# R/M 128
+PATTERN : VV1 0xBD V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64
+# R/R 128
+PATTERN : VV1 0xBD V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64
+
+}
+{
+ICLASS    : VFNMADD231SS
+EXCEPTIONS: avx-type-3
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR simd_scalar
+# R/M 128
+PATTERN : VV1 0xBD V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32
+# R/R 128
+PATTERN : VV1 0xBD V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32
+
+}
+
+###################################################
+
+
+{
+ICLASS    : VFNMSUB132PD
+EXCEPTIONS: avx-type-2
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR
+# R/M 128
+PATTERN : VV1 0x9E VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64
+# R/R 128
+PATTERN : VV1 0x9E VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
+
+
+# R/M 256
+PATTERN : VV1 0x9E VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64
+# R/R 256
+PATTERN : VV1 0x9E VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
+}
+{
+ICLASS    : VFNMSUB132PS
+EXCEPTIONS: avx-type-2
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR
+# R/M 128
+PATTERN : VV1 0x9E VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
+# R/R 128
+PATTERN : VV1 0x9E VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
+
+
+# R/M 256
+PATTERN : VV1 0x9E VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
+# R/R 256
+PATTERN : VV1 0x9E VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
+}
+{
+ICLASS    : VFNMSUB132SD
+EXCEPTIONS: avx-type-3
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR simd_scalar
+# R/M 128
+PATTERN : VV1 0x9F V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64
+# R/R 128
+PATTERN : VV1 0x9F V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64
+}
+{
+ICLASS    : VFNMSUB132SS
+EXCEPTIONS: avx-type-3
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR simd_scalar
+# R/M 128
+PATTERN : VV1 0x9F  V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32
+# R/R 128
+PATTERN : VV1 0x9F  V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32
+
+}
+
+{
+ICLASS    : VFNMSUB213PD
+EXCEPTIONS: avx-type-2
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR
+# R/M 128
+PATTERN : VV1 0xAE VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64    MEM0:r:dq:f64
+# R/R 128
+PATTERN : VV1 0xAE VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
+
+
+# R/M 256
+PATTERN : VV1 0xAE VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64    MEM0:r:qq:f64
+# R/R 256
+PATTERN : VV1 0xAE VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
+}
+{
+ICLASS    : VFNMSUB213PS
+EXCEPTIONS: avx-type-2
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR
+# R/M 128
+PATTERN : VV1 0xAE VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
+# R/R 128
+PATTERN : VV1 0xAE VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
+
+
+# R/M 256
+PATTERN : VV1 0xAE VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
+# R/R 256
+PATTERN : VV1 0xAE VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
+}
+{
+ICLASS    : VFNMSUB213SD
+EXCEPTIONS: avx-type-3
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR simd_scalar
+# R/M 128
+PATTERN : VV1 0xAF  V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64     MEM0:r:q:f64
+# R/R 128
+PATTERN : VV1 0xAF  V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64
+
+}
+{
+ICLASS    : VFNMSUB213SS
+EXCEPTIONS: avx-type-3
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR simd_scalar
+# R/M 128
+PATTERN : VV1 0xAF  V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32     MEM0:r:d:f32
+# R/R 128
+PATTERN : VV1 0xAF  V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32
+}
+
+{
+ICLASS    : VFNMSUB231PD
+EXCEPTIONS: avx-type-2
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR
+# R/M 128
+PATTERN : VV1 0xBE VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64
+# R/R 128
+PATTERN : VV1 0xBE VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
+
+
+# R/M 256
+PATTERN : VV1 0xBE VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64
+# R/R 256
+PATTERN : VV1 0xBE VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
+
+}
+{
+ICLASS    : VFNMSUB231PS
+EXCEPTIONS: avx-type-2
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR
+# R/M 128
+PATTERN : VV1 0xBE VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
+# R/R 128
+PATTERN : VV1 0xBE VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
+
+# R/M 256
+PATTERN : VV1 0xBE VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
+# R/R 256
+PATTERN : VV1 0xBE VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
+
+}
+{
+ICLASS    : VFNMSUB231SD
+EXCEPTIONS: avx-type-3
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR simd_scalar
+# R/M 128
+PATTERN : VV1 0xBF V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64
+# R/R 128
+PATTERN : VV1 0xBF V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64
+
+}
+{
+ICLASS    : VFNMSUB231SS
+EXCEPTIONS: avx-type-3
+CPL       : 3
+CATEGORY  : VFMA
+EXTENSION : FMA
+ATTRIBUTES: MXCSR simd_scalar
+# R/M 128
+PATTERN : VV1 0xBF V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32
+# R/R 128
+PATTERN : VV1 0xBF V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32
+
+}
+
+###################################################
+
+
+
+
+
+
+###FILE: ../xed/datafiles/hswavx/gather-isa.txt
 
 #BEGIN_LEGAL
 #
-#Copyright (c) 2016 Intel Corporation
+#Copyright (c) 2018 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -22893,13 +25790,13 @@ EXCEPTIONS: avx-type-12
 
 # VL = 256 - when data/mask differ from index size see asterisks in above chart.
 PATTERN : VV1 0x92   VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16
-OPERANDS  : REG0=YMM_R():crw:qq:f64   MEM0:r:qq:f64 REG1=YMM_N():rw:qq:i64
-IFORM: VGATHERDPD_YMMf64_MEMqq_YMMi64_VL256
+OPERANDS  : REG0=YMM_R():crw:qq:f64   MEM0:r:q:f64 REG1=YMM_N():rw:qq:i64
+IFORM: VGATHERDPD_YMMf64_MEMf64_YMMi64_VL256
 
 # VL = 128 - index, mask and dest are all XMMs
 PATTERN : VV1 0x92   VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16
-OPERANDS  : REG0=XMM_R():crw:dq:f64   MEM0:r:dq:f64 REG1=XMM_N():rw:dq:i64
-IFORM: VGATHERDPD_XMMf64_MEMdq_XMMi64_VL128
+OPERANDS  : REG0=XMM_R():crw:dq:f64   MEM0:r:q:f64 REG1=XMM_N():rw:dq:i64
+IFORM: VGATHERDPD_XMMf64_MEMf64_XMMi64_VL128
 
 COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz
 }
@@ -22914,13 +25811,13 @@ EXCEPTIONS: avx-type-12
 
 # VL = 256 - when data/mask differ from index size see asterisks in above chart.
 PATTERN : VV1 0x92   VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16
-OPERANDS  : REG0=YMM_R():crw:qq:f32   MEM0:r:qq:f32 REG1=YMM_N():rw:qq:i32
-IFORM: VGATHERDPS_YMMf32_MEMqq_YMMi32_VL256
+OPERANDS  : REG0=YMM_R():crw:qq:f32   MEM0:r:d:f32 REG1=YMM_N():rw:qq:i32
+IFORM: VGATHERDPS_YMMf32_MEMf32_YMMi32_VL256
 
 # VL = 128 - index, mask and dest are all XMMs
 PATTERN : VV1 0x92   VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16
-OPERANDS  : REG0=XMM_R():crw:dq:f32   MEM0:r:dq:f32 REG1=XMM_N():rw:dq:i32
-IFORM: VGATHERDPS_XMMf32_MEMdq_XMMi32_VL128
+OPERANDS  : REG0=XMM_R():crw:dq:f32   MEM0:r:d:f32 REG1=XMM_N():rw:dq:i32
+IFORM: VGATHERDPS_XMMf32_MEMf32_XMMi32_VL128
 
 COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz
 }
@@ -22934,13 +25831,13 @@ EXCEPTIONS: avx-type-12
 
 # VL = 256 - when data/mask differ from index size see asterisks in above chart.
 PATTERN : VV1 0x93   VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16
-OPERANDS  : REG0=YMM_R():crw:qq:f64   MEM0:r:qq:f64 REG1=YMM_N():rw:qq:i64
-IFORM: VGATHERQPD_YMMf64_MEMqq_YMMi64_VL256
+OPERANDS  : REG0=YMM_R():crw:qq:f64   MEM0:r:q:f64 REG1=YMM_N():rw:qq:i64
+IFORM: VGATHERQPD_YMMf64_MEMf64_YMMi64_VL256
 
 # VL = 128 - index, mask and dest are all XMMs
 PATTERN : VV1 0x93   VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16
-OPERANDS  : REG0=XMM_R():crw:dq:f64   MEM0:r:dq:f64 REG1=XMM_N():rw:dq:i64
-IFORM: VGATHERQPD_XMMf64_MEMdq_XMMi64_VL128
+OPERANDS  : REG0=XMM_R():crw:dq:f64   MEM0:r:q:f64 REG1=XMM_N():rw:dq:i64
+IFORM: VGATHERQPD_XMMf64_MEMf64_XMMi64_VL128
 
 COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz
 }
@@ -22955,13 +25852,13 @@ EXCEPTIONS: avx-type-12
 
 # VL = 256 - when data/mask differ from index size see asterisks in above chart.
 PATTERN : VV1 0x93   VL256 V66 V0F38   W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16
-OPERANDS  : REG0=XMM_R():crw:dq:f32   MEM0:r:dq:f32 REG1=XMM_N():rw:dq:i32
-IFORM: VGATHERQPS_XMMf32_MEMdq_XMMi32_VL256
+OPERANDS  : REG0=XMM_R():crw:dq:f32   MEM0:r:d:f32 REG1=XMM_N():rw:dq:i32
+IFORM: VGATHERQPS_XMMf32_MEMf32_XMMi32_VL256
 
 # VL = 128 - index, mask and dest are all XMMs
 PATTERN : VV1 0x93   VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16
-OPERANDS  : REG0=XMM_R():crw:q:f32   MEM0:r:q:f32 REG1=XMM_N():rw:q:i32
-IFORM: VGATHERQPS_XMMf32_MEMq_XMMi32_VL128
+OPERANDS  : REG0=XMM_R():crw:q:f32   MEM0:r:d:f32 REG1=XMM_N():rw:q:i32
+IFORM: VGATHERQPS_XMMf32_MEMf32_XMMi32_VL128
 
 COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz
 }
@@ -22976,13 +25873,13 @@ EXCEPTIONS: avx-type-12
 
 # VL = 256 - when data/mask differ from index size see asterisks in above chart.
 PATTERN : VV1 0x90   VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16
-OPERANDS  : REG0=YMM_R():crw:qq:u64   MEM0:r:qq:u64 REG1=YMM_N():rw:qq:i64
-IFORM: VPGATHERDQ_YMMu64_MEMqq_YMMi64_VL256
+OPERANDS  : REG0=YMM_R():crw:qq:u64   MEM0:r:q:u64 REG1=YMM_N():rw:qq:i64
+IFORM: VPGATHERDQ_YMMu64_MEMq_YMMi64_VL256
 
 # VL = 128 - index, mask and dest are all XMMs
 PATTERN : VV1 0x90   VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16
-OPERANDS  : REG0=XMM_R():crw:dq:u64   MEM0:r:dq:u64 REG1=XMM_N():rw:dq:i64
-IFORM: VPGATHERDQ_XMMu64_MEMdq_XMMi64_VL128
+OPERANDS  : REG0=XMM_R():crw:dq:u64   MEM0:r:q:u64 REG1=XMM_N():rw:dq:i64
+IFORM: VPGATHERDQ_XMMu64_MEMq_XMMi64_VL128
 
 COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz
 }
@@ -22996,13 +25893,13 @@ EXCEPTIONS: avx-type-12
 
 # VL = 256 - when data/mask differ from index size see asterisks in above chart.
 PATTERN : VV1 0x90   VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16
-OPERANDS  : REG0=YMM_R():crw:qq:u32   MEM0:r:qq:u32 REG1=YMM_N():rw:qq:i32
-IFORM: VPGATHERDD_YMMu32_MEMqq_YMMi32_VL256
+OPERANDS  : REG0=YMM_R():crw:qq:u32   MEM0:r:d:u32 REG1=YMM_N():rw:qq:i32
+IFORM: VPGATHERDD_YMMu32_MEMd_YMMi32_VL256
 
 # VL = 128 - index, mask and dest are all XMMs
 PATTERN : VV1 0x90   VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16
-OPERANDS  : REG0=XMM_R():crw:dq:u32   MEM0:r:dq:u32 REG1=XMM_N():rw:dq:i32
-IFORM: VPGATHERDD_XMMu32_MEMdq_XMMi32_VL128
+OPERANDS  : REG0=XMM_R():crw:dq:u32   MEM0:r:d:u32 REG1=XMM_N():rw:dq:i32
+IFORM: VPGATHERDD_XMMu32_MEMd_XMMi32_VL128
 
 COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz
 }
@@ -23016,13 +25913,13 @@ EXCEPTIONS: avx-type-12
 
 # VL = 256 - when data/mask differ from index size see asterisks in above chart.
 PATTERN : VV1 0x91   VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16
-OPERANDS  : REG0=YMM_R():crw:qq:u64   MEM0:r:qq:u64 REG1=YMM_N():rw:qq:i64
-IFORM: VPGATHERQQ_YMMu64_MEMqq_YMMi64_VL256
+OPERANDS  : REG0=YMM_R():crw:qq:u64   MEM0:r:q:u64 REG1=YMM_N():rw:qq:i64
+IFORM: VPGATHERQQ_YMMu64_MEMq_YMMi64_VL256
 
 # VL = 128 - index, mask and dest are all XMMs
 PATTERN : VV1 0x91   VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16
-OPERANDS  : REG0=XMM_R():crw:dq:u64   MEM0:r:dq:u64 REG1=XMM_N():rw:dq:i64
-IFORM: VPGATHERQQ_XMMu64_MEMdq_XMMi64_VL128
+OPERANDS  : REG0=XMM_R():crw:dq:u64   MEM0:r:q:u64 REG1=XMM_N():rw:dq:i64
+IFORM: VPGATHERQQ_XMMu64_MEMq_XMMi64_VL128
 
 COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz
 }
@@ -23036,24 +25933,24 @@ EXCEPTIONS: avx-type-12
 
 # VL = 256 - when data/mask differ from index size see asterisks in above chart.
 PATTERN : VV1 0x91   VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16
-OPERANDS  : REG0=XMM_R():crw:dq:u32   MEM0:r:dq:u32 REG1=XMM_N():rw:dq:i32
-IFORM: VPGATHERQD_XMMu32_MEMdq_XMMi32_VL256
+OPERANDS  : REG0=XMM_R():crw:dq:u32   MEM0:r:d:u32 REG1=XMM_N():rw:dq:i32
+IFORM: VPGATHERQD_XMMu32_MEMd_XMMi32_VL256
 
 # VL = 128 - index, mask and dest are all XMMs
 PATTERN : VV1 0x91   VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16
-OPERANDS  : REG0=XMM_R():crw:q:u32   MEM0:r:q:u32 REG1=XMM_N():rw:q:i32
-IFORM: VPGATHERQD_XMMu32_MEMq_XMMi32_VL128
+OPERANDS  : REG0=XMM_R():crw:q:u32   MEM0:r:d:u32 REG1=XMM_N():rw:q:i32
+IFORM: VPGATHERQD_XMMu32_MEMd_XMMi32_VL128
 
 COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz
 }
 
 
 
-###FILE: ../xed/datafiles/avxhsw/hsw-int256-isa.txt
+###FILE: ../xed/datafiles/hswavx/hsw-int256-isa.txt
 
 #BEGIN_LEGAL
 #
-#Copyright (c) 2016 Intel Corporation
+#Copyright (c) 2018 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -23107,19 +26004,6 @@ OPERANDS  : REG0=YMM_R():w:qq:u32 MEM0:r:qq:i32
 PATTERN : VV1 0x1E   VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
 OPERANDS  : REG0=YMM_R():w:qq:u32  REG1=YMM_B():r:qq:i32
 }
-{
-ICLASS    : VPHMINPOSUW
-CPL       : 3
-CATEGORY  : AVX2
-EXTENSION : AVX2
-EXCEPTIONS: avx-type-4
-PATTERN : VV1 0x41   VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=YMM_R():w:qq:u16 MEM0:r:qq:u16
-
-PATTERN : VV1 0x41   VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=YMM_R():w:qq:u16  REG1=YMM_B():r:qq:u16
-}
-
 
 
 
@@ -24871,11 +27755,11 @@ OPERANDS  : REG0=YMM_R():w:qq:u128  MEM0:r:dq:u128 EMX_BROADCAST_2TO4_64
 }
 
 
-###FILE: ../xed/datafiles/avxhsw/hsw-isa.txt
+###FILE: ../xed/datafiles/hswavx/hsw-vshift-isa.txt
 
 #BEGIN_LEGAL
 #
-#Copyright (c) 2016 Intel Corporation
+#Copyright (c) 2018 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -24890,64 +27774,117 @@ OPERANDS  : REG0=YMM_R():w:qq:u128  MEM0:r:dq:u128 EMX_BROADCAST_2TO4_64
 #  limitations under the License.
 #
 #END_LEGAL
-INSTRUCTIONS()::
+AVX_INSTRUCTIONS()::
+
+
+
 
 {
-ICLASS    : TZCNT
+ICLASS    : VPSLLVD
 CPL       : 3
-CATEGORY  : BMI1
-EXTENSION : BMI1
-FLAGS     : MUST [ of-u sf-u zf-mod af-u pf-u cf-mod ]
-PATTERN   : 0x0F 0xBC refining_f3  TZCNT=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=GPRv_R():w MEM0:r:v
+CATEGORY  : AVX2
+EXTENSION : AVX2
+EXCEPTIONS: avx-type-4
+PATTERN : VV1 0x47  VL128 V0F38 V66  W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq
+
+PATTERN : VV1 0x47  VL128 V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq
+
+PATTERN : VV1 0x47  VL256 V0F38 V66  W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq
+
+PATTERN : VV1 0x47  VL256 V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq
+
+}
+{
+ICLASS    : VPSLLVQ
+CPL       : 3
+CATEGORY  : AVX2
+EXTENSION : AVX2
+EXCEPTIONS: avx-type-4
+PATTERN : VV1 0x47  VL128 V0F38 V66  W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq
+
+PATTERN : VV1 0x47  VL128 V0F38 V66 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq
+
+PATTERN : VV1 0x47  VL256 V0F38 V66  W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq
+
+PATTERN : VV1 0x47  VL256 V0F38 V66 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq
 
-PATTERN   : 0x0F 0xBC refining_f3 TZCNT=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=GPRv_R():w  REG1=GPRv_B():r
 }
 
 {
-ICLASS    : BSF
-VERSION   : 1
-COMMENT   : AMD reused 0FBC for TZCNT and made BSF not have a refining prefix.  This version replaces the normal version of BSF
+ICLASS    : VPSRLVD
 CPL       : 3
-CATEGORY  : BITBYTE
-EXTENSION : BASE
-ISA_SET   : I386
-FLAGS     : MUST [ of-u sf-u zf-mod af-u pf-u cf-u ]
+CATEGORY  : AVX2
+EXTENSION : AVX2
+EXCEPTIONS: avx-type-4
+PATTERN : VV1 0x45  VL128 V0F38 V66  W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq
 
-PATTERN   : 0x0F 0xBC not_refining_f3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=GPRv_R():cw MEM0:r:v
+PATTERN : VV1 0x45  VL128 V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq
 
-PATTERN   : 0x0F 0xBC not_refining_f3 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=GPRv_R():cw REG1=GPRv_B():r
+PATTERN : VV1 0x45  VL256 V0F38 V66  W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq
 
-PATTERN   : 0x0F 0xBC refining_f3 TZCNT=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=GPRv_R():cw MEM0:r:v
+PATTERN : VV1 0x45  VL256 V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq
+
+}
+{
+ICLASS    : VPSRLVQ
+CPL       : 3
+CATEGORY  : AVX2
+EXTENSION : AVX2
+EXCEPTIONS: avx-type-4
+PATTERN : VV1 0x45  VL128 V0F38 V66  W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq
+
+PATTERN : VV1 0x45  VL128 V0F38 V66 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq
+
+PATTERN : VV1 0x45  VL256 V0F38 V66  W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq
+
+PATTERN : VV1 0x45  VL256 V0F38 V66 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq
 
-PATTERN   : 0x0F 0xBC refining_f3 TZCNT=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=GPRv_R():cw REG1=GPRv_B():r
 }
 
 {
-ICLASS    : INVPCID
-CPL       : 0
-CATEGORY  : MISC
-EXTENSION : INVPCID
-ISA_SET   : INVPCID
-ATTRIBUTES : RING0 NOTSX
-PATTERN   : 0x0F 0x38 0x82 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() mode64 MODRM() CR_WIDTH()
-OPERANDS  : REG0=GPR64_R():r MEM0:r:dq
-PATTERN   : 0x0F 0x38 0x82 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() mode32 MODRM() CR_WIDTH()
-OPERANDS  : REG0=GPR32_R():r MEM0:r:dq
-COMMENT   :
+ICLASS    : VPSRAVD
+CPL       : 3
+CATEGORY  : AVX2
+EXTENSION : AVX2
+EXCEPTIONS: avx-type-4
+PATTERN : VV1 0x46  VL128 V0F38 V66  W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq
+
+PATTERN : VV1 0x46  VL128 V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq
+
+PATTERN : VV1 0x46  VL256 V0F38 V66  W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq
+
+PATTERN : VV1 0x46  VL256 V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq
+
 }
 
 
-###FILE: ../xed/datafiles/avxhsw/hsw-lzcnt.txt
+
+
+###FILE: ../xed/datafiles/hswavx/movnt-load-isa.txt
 
 #BEGIN_LEGAL
 #
-#Copyright (c) 2016 Intel Corporation
+#Copyright (c) 2018 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -24962,56 +27899,30 @@ COMMENT   :
 #  limitations under the License.
 #
 #END_LEGAL
-INSTRUCTIONS()::
+AVX_INSTRUCTIONS()::
 
-# LZCNT reg16, reg/mem16 F30FBD /r
-# LZCNT reg32, reg/mem32 F30FBD /r
-# LZCNT reg64, reg/mem64 F30FBD /r
 
 {
-ICLASS    : LZCNT
-# This replace the AMD version in LZCNT builds
-VERSION   : 2
+ICLASS    : VMOVNTDQA
 CPL       : 3
-CATEGORY  : LZCNT
-EXTENSION : LZCNT
-COMMENT:  : These next one WAS introduced first by AMD circa SSE4a.
-FLAGS     : MUST [ cf-mod zf-mod of-u af-u pf-u sf-u ]
-PATTERN   : 0x0F 0xBD f3_refining_prefix LZCNT=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=GPRv_R():w:v     MEM0:r:v
-PATTERN   : 0x0F 0xBD f3_refining_prefix LZCNT=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=GPRv_R():w:v     REG1=GPRv_B():r:v
-}
-
+CATEGORY  : DATAXFER
+EXTENSION : AVX2
+EXCEPTIONS: avx-type-1
+ATTRIBUTES :  REQUIRES_ALIGNMENT NOTSX NONTEMPORAL
 
-{
-ICLASS    : BSR
-VERSION   : 2
-COMMENT   : AMD reused 0FBD for LZCNT and made BSR not have a refining prefix.  This version replaces the normal version of BSR
-CPL       : 3
-CATEGORY  : BITBYTE
-EXTENSION : BASE
-ISA_SET   : I386
-FLAGS     : MUST [ of-u sf-u zf-mod af-u pf-u cf-u ]
-PATTERN   : 0x0F 0xBD not_refining_f3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=GPRv_R():cw MEM0:r:v
+PATTERN : VV1 0x2A  V66 V0F38 VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  :  REG0=YMM_R():w:qq MEM0:r:qq
+}
 
-PATTERN   : 0x0F 0xBD not_refining_f3 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=GPRv_R():cw REG1=GPRv_B():r
 
-PATTERN   : 0x0F 0xBD  refining_f3 LZCNT=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=GPRv_R():cw MEM0:r:v
 
-PATTERN   : 0x0F 0xBD  refining_f3 LZCNT=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=GPRv_R():cw REG1=GPRv_B():r
-}
 
 
-###FILE: ../xed/datafiles/avxhsw/hsw-vex-gpr-isa.txt
+###FILE: ../xed/datafiles/hswbmi/hsw-bmi-vex-isa.xed.txt
 
 #BEGIN_LEGAL
 #
-#Copyright (c) 2016 Intel Corporation
+#Copyright (c) 2018 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -25034,27 +27945,26 @@ ICLASS    : PDEP
 CPL       : 3
 CATEGORY  : BMI2
 EXTENSION : BMI2
-FLAGS     : MUST [ of-u sf-u zf-mod af-u pf-u cf-mod ]
 
 #32b
 PATTERN   : VV1 0xF5 V0F38 VF2 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d MEM0:r:d
+OPERANDS  : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d MEM0:r:d
 
 PATTERN   : VV1 0xF5 V0F38 VF2 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d MEM0:r:d
+OPERANDS  : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d MEM0:r:d
 
 PATTERN   : VV1 0xF5 V0F38 VF2 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d
+OPERANDS  : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d
 
 PATTERN   : VV1 0xF5 V0F38 VF2 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d
+OPERANDS  : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d
 
 # 64b
 PATTERN   : VV1 0xF5 V0F38 VF2 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=VGPR64_R():rw:q REG1=VGPR64_N():r:q MEM0:r:q
+OPERANDS  : REG0=VGPR64_R():w:q REG1=VGPR64_N():r:q MEM0:r:q
 
 PATTERN   : VV1 0xF5 V0F38 VF2 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=VGPR64_R():rw:q REG1=VGPR64_N():r:q REG2=VGPR64_B():r:q
+OPERANDS  : REG0=VGPR64_R():w:q REG1=VGPR64_N():r:q REG2=VGPR64_B():r:q
 }
 
 {
@@ -25062,28 +27972,27 @@ ICLASS    : PEXT
 CPL       : 3
 CATEGORY  : BMI2
 EXTENSION : BMI2
-FLAGS     : MUST [ of-u sf-u zf-mod af-u pf-u cf-mod ]
 
 
 #32b
 PATTERN   : VV1 0xF5 V0F38 VF3 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d MEM0:r:d
+OPERANDS  : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d MEM0:r:d
 
 PATTERN   : VV1 0xF5 V0F38 VF3 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d MEM0:r:d
+OPERANDS  : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d MEM0:r:d
 
 PATTERN   : VV1 0xF5 V0F38 VF3 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d
+OPERANDS  : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d
 
 PATTERN   : VV1 0xF5 V0F38 VF3 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d
+OPERANDS  : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d
 
 # 64b
 PATTERN   : VV1 0xF5 V0F38 VF3 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=VGPR64_R():rw:q REG1=VGPR64_N():r:q MEM0:r:q
+OPERANDS  : REG0=VGPR64_R():w:q REG1=VGPR64_N():r:q MEM0:r:q
 
 PATTERN   : VV1 0xF5 V0F38 VF3 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=VGPR64_R():rw:q REG1=VGPR64_N():r:q REG2=VGPR64_B():r:q
+OPERANDS  : REG0=VGPR64_R():w:q REG1=VGPR64_N():r:q REG2=VGPR64_B():r:q
 }
 
 
@@ -25092,27 +28001,27 @@ ICLASS    : ANDN
 CPL       : 3
 CATEGORY  : BMI1
 EXTENSION : BMI1
-FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
+FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-u cf-0 ]
 
 # 32b
 PATTERN   : VV1 0xF2 V0F38 VNP  not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d MEM0:r:d
+OPERANDS  : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d MEM0:r:d
 
 PATTERN   : VV1 0xF2 V0F38 VNP  W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d MEM0:r:d
+OPERANDS  : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d MEM0:r:d
 
 PATTERN   : VV1 0xF2 V0F38 VNP  not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d
+OPERANDS  : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d
 
 PATTERN   : VV1 0xF2 V0F38 VNP  W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d
+OPERANDS  : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d
 
 # 64b
 PATTERN   : VV1 0xF2 V0F38 VNP W1 VL128  mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=VGPR64_R():rw:q REG1=VGPR64_N():r:q MEM0:r:q
+OPERANDS  : REG0=VGPR64_R():w:q REG1=VGPR64_N():r:q MEM0:r:q
 
 PATTERN   : VV1 0xF2 V0F38 VNP W1 VL128  mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=VGPR64_R():rw:q REG1=VGPR64_N():r:q REG2=VGPR64_B():r:q
+OPERANDS  : REG0=VGPR64_R():w:q REG1=VGPR64_N():r:q REG2=VGPR64_B():r:q
 }
 
 {
@@ -25205,7 +28114,7 @@ ICLASS    : BZHI
 CPL       : 3
 CATEGORY  : BMI2
 EXTENSION : BMI2
-FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-mod ]
+FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-u cf-mod ]
 
 # 32b
 PATTERN   : VV1 0xF5 V0F38 VNP not64 VL128  MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
@@ -25393,11 +28302,11 @@ OPERANDS  : REG0=VGPR64_R():w:q MEM0:r:q IMM0:r:b
 }
 
 
-###FILE: ../xed/datafiles/avxhsw/hsw-vshift-isa.txt
+###FILE: ../xed/datafiles/hswbmi/tzcnt-isa.xed.txt
 
 #BEGIN_LEGAL
 #
-#Copyright (c) 2016 Intel Corporation
+#Copyright (c) 2018 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -25412,117 +28321,83 @@ OPERANDS  : REG0=VGPR64_R():w:q MEM0:r:q IMM0:r:b
 #  limitations under the License.
 #
 #END_LEGAL
-AVX_INSTRUCTIONS()::
-
-
-
-
-{
-ICLASS    : VPSLLVD
-CPL       : 3
-CATEGORY  : AVX2
-EXTENSION : AVX2
-EXCEPTIONS: avx-type-4
-PATTERN : VV1 0x47  VL128 V0F38 V66  W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq
-
-PATTERN : VV1 0x47  VL128 V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq
-
-PATTERN : VV1 0x47  VL256 V0F38 V66  W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq
-
-PATTERN : VV1 0x47  VL256 V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq
+INSTRUCTIONS()::
 
-}
 {
-ICLASS    : VPSLLVQ
+ICLASS    : TZCNT
 CPL       : 3
-CATEGORY  : AVX2
-EXTENSION : AVX2
-EXCEPTIONS: avx-type-4
-PATTERN : VV1 0x47  VL128 V0F38 V66  W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq
-
-PATTERN : VV1 0x47  VL128 V0F38 V66 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq
-
-PATTERN : VV1 0x47  VL256 V0F38 V66  W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq
-
-PATTERN : VV1 0x47  VL256 V0F38 V66 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq
+CATEGORY  : BMI1
+EXTENSION : BMI1
+FLAGS     : MUST [ of-u sf-u zf-mod af-u pf-u cf-mod ]
+PATTERN   : 0x0F 0xBC refining_f3  TZCNT=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=GPRv_R():w MEM0:r:v
 
+PATTERN   : 0x0F 0xBC refining_f3 TZCNT=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=GPRv_R():w  REG1=GPRv_B():r
 }
 
 {
-ICLASS    : VPSRLVD
+ICLASS    : BSF
+VERSION   : 1
+COMMENT   : AMD reused 0FBC for TZCNT and made BSF not have a refining prefix.  This version replaces the normal version of BSF
 CPL       : 3
-CATEGORY  : AVX2
-EXTENSION : AVX2
-EXCEPTIONS: avx-type-4
-PATTERN : VV1 0x45  VL128 V0F38 V66  W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq
+CATEGORY  : BITBYTE
+EXTENSION : BASE
+ISA_SET   : I386
+FLAGS     : MUST [ of-u sf-u zf-mod af-u pf-u cf-u ]
 
-PATTERN : VV1 0x45  VL128 V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq
+PATTERN   : 0x0F 0xBC not_refining_f3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=GPRv_R():cw MEM0:r:v
 
-PATTERN : VV1 0x45  VL256 V0F38 V66  W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq
+PATTERN   : 0x0F 0xBC not_refining_f3 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=GPRv_R():cw REG1=GPRv_B():r
 
-PATTERN : VV1 0x45  VL256 V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq
+PATTERN   : 0x0F 0xBC refining_f3 TZCNT=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=GPRv_R():cw MEM0:r:v
 
+PATTERN   : 0x0F 0xBC refining_f3 TZCNT=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=GPRv_R():cw REG1=GPRv_B():r
 }
-{
-ICLASS    : VPSRLVQ
-CPL       : 3
-CATEGORY  : AVX2
-EXTENSION : AVX2
-EXCEPTIONS: avx-type-4
-PATTERN : VV1 0x45  VL128 V0F38 V66  W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq
 
-PATTERN : VV1 0x45  VL128 V0F38 V66 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq
-
-PATTERN : VV1 0x45  VL256 V0F38 V66  W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq
 
-PATTERN : VV1 0x45  VL256 V0F38 V66 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq
+###FILE: ../xed/datafiles/hsw/vmfunc-isa.xed.txt
 
-}
+#BEGIN_LEGAL
+#
+#Copyright (c) 2018 Intel Corporation
+#
+#  Licensed under the Apache License, Version 2.0 (the "License");
+#  you may not use this file except in compliance with the License.
+#  You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+#  Unless required by applicable law or agreed to in writing, software
+#  distributed under the License is distributed on an "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#  See the License for the specific language governing permissions and
+#  limitations under the License.
+#
+#END_LEGAL
+INSTRUCTIONS()::
 
 {
-ICLASS    : VPSRAVD
+ICLASS    : VMFUNC
 CPL       : 3
-CATEGORY  : AVX2
-EXTENSION : AVX2
-EXCEPTIONS: avx-type-4
-PATTERN : VV1 0x46  VL128 V0F38 V66  W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq
-
-PATTERN : VV1 0x46  VL128 V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq
-
-PATTERN : VV1 0x46  VL256 V0F38 V66  W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq
-
-PATTERN : VV1 0x46  VL256 V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq
-
+CATEGORY  : VTX
+EXTENSION : VMFUNC
+ISA_SET   : VMFUNC
+ATTRIBUTES :
+PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b100] no_refining_prefix
+OPERANDS  : REG0=XED_REG_EAX:r:SUPP
 }
 
 
-
-
-###FILE: ../xed/datafiles/avxhsw/movnt-load-isa.txt
+###FILE: ../xed/datafiles/hsw/invpcid-isa.xed.txt
 
 #BEGIN_LEGAL
 #
-#Copyright (c) 2016 Intel Corporation
+#Copyright (c) 2018 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -25537,30 +28412,29 @@ OPERANDS  : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq
 #  limitations under the License.
 #
 #END_LEGAL
-AVX_INSTRUCTIONS()::
+INSTRUCTIONS()::
 
 
 {
-ICLASS    : VMOVNTDQA
-CPL       : 3
-CATEGORY  : DATAXFER
-EXTENSION : AVX2
-EXCEPTIONS: avx-type-1
-ATTRIBUTES :  REQUIRES_ALIGNMENT NOTSX
-
-PATTERN : VV1 0x2A  V66 V0F38 VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  :  REG0=YMM_R():w:qq MEM0:r:qq
+ICLASS    : INVPCID
+CPL       : 0
+CATEGORY  : MISC
+EXTENSION : INVPCID
+ISA_SET   : INVPCID
+ATTRIBUTES : RING0 NOTSX
+PATTERN   : 0x0F 0x38 0x82 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() mode64 MODRM() CR_WIDTH()
+OPERANDS  : REG0=GPR64_R():r MEM0:r:dq
+PATTERN   : 0x0F 0x38 0x82 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() not64 MODRM() CR_WIDTH()
+OPERANDS  : REG0=GPR32_R():r MEM0:r:dq
+COMMENT   :
 }
 
 
-
-
-
-###FILE: ../xed/datafiles/avxhsw/vmfunc-isa.txt
+###FILE: ../xed/datafiles/hsw/lzcnt-isa.xed.txt
 
 #BEGIN_LEGAL
 #
-#Copyright (c) 2016 Intel Corporation
+#Copyright (c) 2018 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -25577,23 +28451,54 @@ OPERANDS  :  REG0=YMM_R():w:qq MEM0:r:qq
 #END_LEGAL
 INSTRUCTIONS()::
 
+# LZCNT reg16, reg/mem16 F30FBD /r
+# LZCNT reg32, reg/mem32 F30FBD /r
+# LZCNT reg64, reg/mem64 F30FBD /r
+
 {
-ICLASS    : VMFUNC
+ICLASS    : LZCNT
+# This replace the AMD version in LZCNT builds
+VERSION   : 2
 CPL       : 3
-CATEGORY  : VTX
-EXTENSION : VMFUNC
-ISA_SET   : VMFUNC
-ATTRIBUTES :
-PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b100] no_refining_prefix
-OPERANDS  :
+CATEGORY  : LZCNT
+EXTENSION : LZCNT
+COMMENT:  : These next one WAS introduced first by AMD circa SSE4a.
+FLAGS     : MUST [ cf-mod zf-mod of-u af-u pf-u sf-u ]
+PATTERN   : 0x0F 0xBD f3_refining_prefix LZCNT=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=GPRv_R():w:v     MEM0:r:v
+PATTERN   : 0x0F 0xBD f3_refining_prefix LZCNT=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=GPRv_R():w:v     REG1=GPRv_B():r:v
 }
 
 
-###FILE: ../xed/datafiles/avxhsw/rtm.xed
+{
+ICLASS    : BSR
+VERSION   : 2
+COMMENT   : AMD reused 0FBD for LZCNT and made BSR not have a refining prefix.  This version replaces the normal version of BSR
+CPL       : 3
+CATEGORY  : BITBYTE
+EXTENSION : BASE
+ISA_SET   : I386
+FLAGS     : MUST [ of-u sf-u zf-mod af-u pf-u cf-u ]
+PATTERN   : 0x0F 0xBD not_refining_f3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=GPRv_R():cw MEM0:r:v
+
+PATTERN   : 0x0F 0xBD not_refining_f3 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=GPRv_R():cw REG1=GPRv_B():r
+
+PATTERN   : 0x0F 0xBD  refining_f3 LZCNT=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
+OPERANDS  : REG0=GPRv_R():cw MEM0:r:v
+
+PATTERN   : 0x0F 0xBD  refining_f3 LZCNT=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
+OPERANDS  : REG0=GPRv_R():cw REG1=GPRv_B():r
+}
+
+
+###FILE: ../xed/datafiles/hsw/rtm-isa.xed.txt
 
 #BEGIN_LEGAL
 #
-#Copyright (c) 2016 Intel Corporation
+#Copyright (c) 2018 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -25654,1272 +28559,11 @@ OPERANDS  :
 }
 
 
-###FILE: ../xed/datafiles/avx/avx-fma-isa.txt
-
-#BEGIN_LEGAL
-#
-#Copyright (c) 2016 Intel Corporation
-#
-#  Licensed under the Apache License, Version 2.0 (the "License");
-#  you may not use this file except in compliance with the License.
-#  You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-#  Unless required by applicable law or agreed to in writing, software
-#  distributed under the License is distributed on an "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-#  See the License for the specific language governing permissions and
-#  limitations under the License.
-#
-#END_LEGAL
-AVX_INSTRUCTIONS()::
-
-# Issues: encoder is at a loss for vmaddps xmm0,xmm0,xmm0,xmm0.
-# Encoder must enforce equality between two parameters. Never had to do this before.
-#   Extra check?
-# Decoder must rip off suffixes _DDMR, _DDRM, _DRMD  in disassembly (eventually)
-#############################################################################################
-# Operand orders:
-#             A  =  B   *  C     +  D
-#Type 1)   reg0  reg0  mem/reg1  reg2          DDMR  312 or 132
-#Type 2)   reg0  reg0  reg1      mem/reg2      DDRM  123 or 213
-#Type 3)   reg0  reg1  mem/reg2  reg0          DRMD  321 or 231
-
-# dst is in MODRM.REG
-# regsrc is in VEX.vvvv
-# memop is in MODRM.RM
-############################################################################################
-
-
-
-
-
-
-
-
-
-
-
-
-##########################################################
-
-
-
-
-
-
-
-
-
-
-
-
-##################################################################
-
-
-
-
-
-
-
-
-
-
-
-
-
-##################################################################
-{
-ICLASS    : VFMADD132PD
-EXCEPTIONS: avx-type-2
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR
-# R/M 128
-PATTERN : VV1 0x98 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64
-# R/R 128
-PATTERN : VV1 0x98 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
-
-
-# R/M 256
-PATTERN : VV1 0x98 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64
-# R/R 256
-PATTERN : VV1 0x98 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
-}
-{
-ICLASS    : VFMADD132PS
-EXCEPTIONS: avx-type-2
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR
-# R/M 128
-PATTERN : VV1 0x98 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
-# R/R 128
-PATTERN : VV1 0x98 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
-
-
-# R/M 256
-PATTERN : VV1 0x98 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
-# R/R 256
-PATTERN : VV1 0x98 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
-}
-{
-ICLASS    : VFMADD132SD
-EXCEPTIONS: avx-type-3
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR simd_scalar
-# R/M 128
-PATTERN : VV1 0x99 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64
-# R/R 128
-PATTERN : VV1 0x99 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64
-}
-{
-ICLASS    : VFMADD132SS
-EXCEPTIONS: avx-type-3
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR simd_scalar
-# R/M 128
-PATTERN : VV1 0x99  V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32
-# R/R 128
-PATTERN : VV1 0x99  V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32
-
-}
-
-{
-ICLASS    : VFMADD213PD
-EXCEPTIONS: avx-type-2
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR
-# R/M 128
-PATTERN : VV1 0xA8 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64    MEM0:r:dq:f64
-# R/R 128
-PATTERN : VV1 0xA8 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
-
-
-# R/M 256
-PATTERN : VV1 0xA8 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64    MEM0:r:qq:f64
-# R/R 256
-PATTERN : VV1 0xA8 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
-}
-{
-ICLASS    : VFMADD213PS
-EXCEPTIONS: avx-type-2
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR
-# R/M 128
-PATTERN : VV1 0xA8 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
-# R/R 128
-PATTERN : VV1 0xA8 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
-
-
-# R/M 256
-PATTERN : VV1 0xA8 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
-# R/R 256
-PATTERN : VV1 0xA8 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
-}
-{
-ICLASS    : VFMADD213SD
-EXCEPTIONS: avx-type-3
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR simd_scalar
-# R/M 128
-PATTERN : VV1 0xA9  V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64     MEM0:r:q:f64
-# R/R 128
-PATTERN : VV1 0xA9  V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64
-
-}
-{
-ICLASS    : VFMADD213SS
-EXCEPTIONS: avx-type-3
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR simd_scalar
-# R/M 128
-PATTERN : VV1 0xA9  V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32     MEM0:r:d:f32
-# R/R 128
-PATTERN : VV1 0xA9  V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32
-}
-
-{
-ICLASS    : VFMADD231PD
-EXCEPTIONS: avx-type-2
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR
-# R/M 128
-PATTERN : VV1 0xB8 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64
-# R/R 128
-PATTERN : VV1 0xB8 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
-
-
-# R/M 256
-PATTERN : VV1 0xB8 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64
-# R/R 256
-PATTERN : VV1 0xB8 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
-
-}
-{
-ICLASS    : VFMADD231PS
-EXCEPTIONS: avx-type-2
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR
-# R/M 128
-PATTERN : VV1 0xB8 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
-# R/R 128
-PATTERN : VV1 0xB8 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
-
-# R/M 256
-PATTERN : VV1 0xB8 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
-# R/R 256
-PATTERN : VV1 0xB8 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
-
-}
-{
-ICLASS    : VFMADD231SD
-EXCEPTIONS: avx-type-3
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR simd_scalar
-# R/M 128
-PATTERN : VV1 0xB9 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64
-# R/R 128
-PATTERN : VV1 0xB9 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64
-
-}
-{
-ICLASS    : VFMADD231SS
-EXCEPTIONS: avx-type-3
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR simd_scalar
-# R/M 128
-PATTERN : VV1 0xB9 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32
-# R/R 128
-PATTERN : VV1 0xB9 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32
-
-}
-
-
-###################################################
-{
-ICLASS    : VFMADDSUB132PD
-EXCEPTIONS: avx-type-2
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR
-# R/M 128
-PATTERN : VV1 0x96 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64
-# R/R 128
-PATTERN : VV1 0x96 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
-
-
-# R/M 256
-PATTERN : VV1 0x96 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64
-# R/R 256
-PATTERN : VV1 0x96 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
-}
-{
-ICLASS    : VFMADDSUB213PD
-EXCEPTIONS: avx-type-2
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR
-# R/M 128
-PATTERN : VV1 0xA6 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64    MEM0:r:dq:f64
-# R/R 128
-PATTERN : VV1 0xA6 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
-
-
-# R/M 256
-PATTERN : VV1 0xA6 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64    MEM0:r:qq:f64
-# R/R 256
-PATTERN : VV1 0xA6 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
-}
-{
-ICLASS    : VFMADDSUB231PD
-EXCEPTIONS: avx-type-2
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR
-# R/M 128
-PATTERN : VV1 0xB6 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64
-# R/R 128
-PATTERN : VV1 0xB6 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
-
-
-# R/M 256
-PATTERN : VV1 0xB6 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64
-# R/R 256
-PATTERN : VV1 0xB6 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
-
-}
-
-{
-ICLASS    : VFMADDSUB132PS
-EXCEPTIONS: avx-type-2
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR
-# R/M 128
-PATTERN : VV1 0x96 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
-# R/R 128
-PATTERN : VV1 0x96 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
-
-
-# R/M 256
-PATTERN : VV1 0x96 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
-# R/R 256
-PATTERN : VV1 0x96 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
-}
-{
-ICLASS    : VFMADDSUB213PS
-EXCEPTIONS: avx-type-2
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR
-# R/M 128
-PATTERN : VV1 0xA6 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
-# R/R 128
-PATTERN : VV1 0xA6 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
-
-
-# R/M 256
-PATTERN : VV1 0xA6 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
-# R/R 256
-PATTERN : VV1 0xA6 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
-}
-{
-ICLASS    : VFMADDSUB231PS
-EXCEPTIONS: avx-type-2
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR
-# R/M 128
-PATTERN : VV1 0xB6 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
-# R/R 128
-PATTERN : VV1 0xB6 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
-
-# R/M 256
-PATTERN : VV1 0xB6 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
-# R/R 256
-PATTERN : VV1 0xB6 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
-
-}
-###################################################
-
-{
-ICLASS    : VFMSUBADD132PD
-EXCEPTIONS: avx-type-2
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR
-# R/M 128
-PATTERN : VV1 0x97 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64
-# R/R 128
-PATTERN : VV1 0x97 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
-
-
-# R/M 256
-PATTERN : VV1 0x97 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64
-# R/R 256
-PATTERN : VV1 0x97 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
-}
-{
-ICLASS    : VFMSUBADD213PD
-EXCEPTIONS: avx-type-2
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR
-# R/M 128
-PATTERN : VV1 0xA7 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64    MEM0:r:dq:f64
-# R/R 128
-PATTERN : VV1 0xA7 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
-
-
-# R/M 256
-PATTERN : VV1 0xA7 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64    MEM0:r:qq:f64
-# R/R 256
-PATTERN : VV1 0xA7 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
-}
-{
-ICLASS    : VFMSUBADD231PD
-EXCEPTIONS: avx-type-2
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR
-# R/M 128
-PATTERN : VV1 0xB7 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64
-# R/R 128
-PATTERN : VV1 0xB7 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
-
-
-# R/M 256
-PATTERN : VV1 0xB7 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64
-# R/R 256
-PATTERN : VV1 0xB7 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
-
-}
-
-{
-ICLASS    : VFMSUBADD132PS
-EXCEPTIONS: avx-type-2
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR
-# R/M 128
-PATTERN : VV1 0x97 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
-# R/R 128
-PATTERN : VV1 0x97 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
-
-
-# R/M 256
-PATTERN : VV1 0x97 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
-# R/R 256
-PATTERN : VV1 0x97 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
-}
-{
-ICLASS    : VFMSUBADD213PS
-EXCEPTIONS: avx-type-2
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR
-# R/M 128
-PATTERN : VV1 0xA7 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
-# R/R 128
-PATTERN : VV1 0xA7 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
-
-
-# R/M 256
-PATTERN : VV1 0xA7 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
-# R/R 256
-PATTERN : VV1 0xA7 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
-}
-{
-ICLASS    : VFMSUBADD231PS
-EXCEPTIONS: avx-type-2
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR
-# R/M 128
-PATTERN : VV1 0xB7 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
-# R/R 128
-PATTERN : VV1 0xB7 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
-
-# R/M 256
-PATTERN : VV1 0xB7 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
-# R/R 256
-PATTERN : VV1 0xB7 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
-
-}
-
-
-###################################################
-
-{
-ICLASS    : VFMSUB132PD
-EXCEPTIONS: avx-type-2
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR
-# R/M 128
-PATTERN : VV1 0x9A VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64
-# R/R 128
-PATTERN : VV1 0x9A VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
-
-
-# R/M 256
-PATTERN : VV1 0x9A VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64
-# R/R 256
-PATTERN : VV1 0x9A VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
-}
-{
-ICLASS    : VFMSUB132PS
-EXCEPTIONS: avx-type-2
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR
-# R/M 128
-PATTERN : VV1 0x9A VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
-# R/R 128
-PATTERN : VV1 0x9A VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
-
-
-# R/M 256
-PATTERN : VV1 0x9A VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
-# R/R 256
-PATTERN : VV1 0x9A VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
-}
-{
-ICLASS    : VFMSUB132SD
-EXCEPTIONS: avx-type-3
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR simd_scalar
-# R/M 128
-PATTERN : VV1 0x9B V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64
-# R/R 128
-PATTERN : VV1 0x9B V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64
-}
-{
-ICLASS    : VFMSUB132SS
-EXCEPTIONS: avx-type-3
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR simd_scalar
-# R/M 128
-PATTERN : VV1 0x9B  V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32
-# R/R 128
-PATTERN : VV1 0x9B  V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32
-
-}
-
-{
-ICLASS    : VFMSUB213PD
-EXCEPTIONS: avx-type-2
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR
-# R/M 128
-PATTERN : VV1 0xAA VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64    MEM0:r:dq:f64
-# R/R 128
-PATTERN : VV1 0xAA VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
-
-
-# R/M 256
-PATTERN : VV1 0xAA VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64    MEM0:r:qq:f64
-# R/R 256
-PATTERN : VV1 0xAA VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
-}
-{
-ICLASS    : VFMSUB213PS
-EXCEPTIONS: avx-type-2
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR
-# R/M 128
-PATTERN : VV1 0xAA VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
-# R/R 128
-PATTERN : VV1 0xAA VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
-
-
-# R/M 256
-PATTERN : VV1 0xAA VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
-# R/R 256
-PATTERN : VV1 0xAA VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
-}
-{
-ICLASS    : VFMSUB213SD
-EXCEPTIONS: avx-type-3
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR simd_scalar
-# R/M 128
-PATTERN : VV1 0xAB  V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64     MEM0:r:q:f64
-# R/R 128
-PATTERN : VV1 0xAB  V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64
-
-}
-{
-ICLASS    : VFMSUB213SS
-EXCEPTIONS: avx-type-3
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR simd_scalar
-# R/M 128
-PATTERN : VV1 0xAB  V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32     MEM0:r:d:f32
-# R/R 128
-PATTERN : VV1 0xAB  V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32
-}
-
-{
-ICLASS    : VFMSUB231PD
-EXCEPTIONS: avx-type-2
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR
-# R/M 128
-PATTERN : VV1 0xBA VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64
-# R/R 128
-PATTERN : VV1 0xBA VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
-
-
-# R/M 256
-PATTERN : VV1 0xBA VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64
-# R/R 256
-PATTERN : VV1 0xBA VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
-
-}
-{
-ICLASS    : VFMSUB231PS
-EXCEPTIONS: avx-type-2
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR
-# R/M 128
-PATTERN : VV1 0xBA VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
-# R/R 128
-PATTERN : VV1 0xBA VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
-
-# R/M 256
-PATTERN : VV1 0xBA VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
-# R/R 256
-PATTERN : VV1 0xBA VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
-
-}
-{
-ICLASS    : VFMSUB231SD
-EXCEPTIONS: avx-type-3
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR simd_scalar
-# R/M 128
-PATTERN : VV1 0xBB V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64
-# R/R 128
-PATTERN : VV1 0xBB V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64
-
-}
-{
-ICLASS    : VFMSUB231SS
-EXCEPTIONS: avx-type-3
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR simd_scalar
-# R/M 128
-PATTERN : VV1 0xBB V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32
-# R/R 128
-PATTERN : VV1 0xBB V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32
-
-}
-
-###################################################
-
-
-{
-ICLASS    : VFNMADD132PD
-EXCEPTIONS: avx-type-2
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR
-# R/M 128
-PATTERN : VV1 0x9C VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64
-# R/R 128
-PATTERN : VV1 0x9C VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
-
-
-# R/M 256
-PATTERN : VV1 0x9C VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64
-# R/R 256
-PATTERN : VV1 0x9C VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
-}
-{
-ICLASS    : VFNMADD132PS
-EXCEPTIONS: avx-type-2
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR
-# R/M 128
-PATTERN : VV1 0x9C VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
-# R/R 128
-PATTERN : VV1 0x9C VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
-
-
-# R/M 256
-PATTERN : VV1 0x9C VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
-# R/R 256
-PATTERN : VV1 0x9C VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
-}
-{
-ICLASS    : VFNMADD132SD
-EXCEPTIONS: avx-type-3
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR simd_scalar
-# R/M 128
-PATTERN : VV1 0x9D V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64
-# R/R 128
-PATTERN : VV1 0x9D V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64
-}
-{
-ICLASS    : VFNMADD132SS
-EXCEPTIONS: avx-type-3
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR simd_scalar
-# R/M 128
-PATTERN : VV1 0x9D  V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32
-# R/R 128
-PATTERN : VV1 0x9D  V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32
-
-}
-
-{
-ICLASS    : VFNMADD213PD
-EXCEPTIONS: avx-type-2
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR
-# R/M 128
-PATTERN : VV1 0xAC VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64    MEM0:r:dq:f64
-# R/R 128
-PATTERN : VV1 0xAC VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
-
-
-# R/M 256
-PATTERN : VV1 0xAC VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64    MEM0:r:qq:f64
-# R/R 256
-PATTERN : VV1 0xAC VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
-}
-{
-ICLASS    : VFNMADD213PS
-EXCEPTIONS: avx-type-2
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR
-# R/M 128
-PATTERN : VV1 0xAC VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
-# R/R 128
-PATTERN : VV1 0xAC VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
-
-
-# R/M 256
-PATTERN : VV1 0xAC VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
-# R/R 256
-PATTERN : VV1 0xAC VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
-}
-{
-ICLASS    : VFNMADD213SD
-EXCEPTIONS: avx-type-3
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR simd_scalar
-# R/M 128
-PATTERN : VV1 0xAD  V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64     MEM0:r:q:f64
-# R/R 128
-PATTERN : VV1 0xAD  V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64
-
-}
-{
-ICLASS    : VFNMADD213SS
-EXCEPTIONS: avx-type-3
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR simd_scalar
-# R/M 128
-PATTERN : VV1 0xAD  V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32     MEM0:r:d:f32
-# R/R 128
-PATTERN : VV1 0xAD  V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32
-}
-
-{
-ICLASS    : VFNMADD231PD
-EXCEPTIONS: avx-type-2
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR
-# R/M 128
-PATTERN : VV1 0xBC VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64
-# R/R 128
-PATTERN : VV1 0xBC VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
-
-
-# R/M 256
-PATTERN : VV1 0xBC VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64
-# R/R 256
-PATTERN : VV1 0xBC VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
-
-}
-{
-ICLASS    : VFNMADD231PS
-EXCEPTIONS: avx-type-2
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR
-# R/M 128
-PATTERN : VV1 0xBC VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
-# R/R 128
-PATTERN : VV1 0xBC VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
-
-# R/M 256
-PATTERN : VV1 0xBC VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
-# R/R 256
-PATTERN : VV1 0xBC VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
-
-}
-{
-ICLASS    : VFNMADD231SD
-EXCEPTIONS: avx-type-3
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR simd_scalar
-# R/M 128
-PATTERN : VV1 0xBD V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64
-# R/R 128
-PATTERN : VV1 0xBD V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64
-
-}
-{
-ICLASS    : VFNMADD231SS
-EXCEPTIONS: avx-type-3
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR simd_scalar
-# R/M 128
-PATTERN : VV1 0xBD V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32
-# R/R 128
-PATTERN : VV1 0xBD V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32
-
-}
-
-###################################################
-
-
-{
-ICLASS    : VFNMSUB132PD
-EXCEPTIONS: avx-type-2
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR
-# R/M 128
-PATTERN : VV1 0x9E VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64
-# R/R 128
-PATTERN : VV1 0x9E VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
-
-
-# R/M 256
-PATTERN : VV1 0x9E VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64
-# R/R 256
-PATTERN : VV1 0x9E VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
-}
-{
-ICLASS    : VFNMSUB132PS
-EXCEPTIONS: avx-type-2
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR
-# R/M 128
-PATTERN : VV1 0x9E VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
-# R/R 128
-PATTERN : VV1 0x9E VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
-
-
-# R/M 256
-PATTERN : VV1 0x9E VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
-# R/R 256
-PATTERN : VV1 0x9E VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
-}
-{
-ICLASS    : VFNMSUB132SD
-EXCEPTIONS: avx-type-3
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR simd_scalar
-# R/M 128
-PATTERN : VV1 0x9F V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64
-# R/R 128
-PATTERN : VV1 0x9F V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64
-}
-{
-ICLASS    : VFNMSUB132SS
-EXCEPTIONS: avx-type-3
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR simd_scalar
-# R/M 128
-PATTERN : VV1 0x9F  V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32
-# R/R 128
-PATTERN : VV1 0x9F  V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32
-
-}
-
-{
-ICLASS    : VFNMSUB213PD
-EXCEPTIONS: avx-type-2
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR
-# R/M 128
-PATTERN : VV1 0xAE VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64    MEM0:r:dq:f64
-# R/R 128
-PATTERN : VV1 0xAE VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
-
-
-# R/M 256
-PATTERN : VV1 0xAE VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64    MEM0:r:qq:f64
-# R/R 256
-PATTERN : VV1 0xAE VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
-}
-{
-ICLASS    : VFNMSUB213PS
-EXCEPTIONS: avx-type-2
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR
-# R/M 128
-PATTERN : VV1 0xAE VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
-# R/R 128
-PATTERN : VV1 0xAE VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
-
-
-# R/M 256
-PATTERN : VV1 0xAE VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
-# R/R 256
-PATTERN : VV1 0xAE VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
-}
-{
-ICLASS    : VFNMSUB213SD
-EXCEPTIONS: avx-type-3
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR simd_scalar
-# R/M 128
-PATTERN : VV1 0xAF  V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64     MEM0:r:q:f64
-# R/R 128
-PATTERN : VV1 0xAF  V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64
-
-}
-{
-ICLASS    : VFNMSUB213SS
-EXCEPTIONS: avx-type-3
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR simd_scalar
-# R/M 128
-PATTERN : VV1 0xAF  V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32     MEM0:r:d:f32
-# R/R 128
-PATTERN : VV1 0xAF  V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32
-}
-
-{
-ICLASS    : VFNMSUB231PD
-EXCEPTIONS: avx-type-2
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR
-# R/M 128
-PATTERN : VV1 0xBE VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64
-# R/R 128
-PATTERN : VV1 0xBE VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
-
-
-# R/M 256
-PATTERN : VV1 0xBE VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64
-# R/R 256
-PATTERN : VV1 0xBE VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
-
-}
-{
-ICLASS    : VFNMSUB231PS
-EXCEPTIONS: avx-type-2
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR
-# R/M 128
-PATTERN : VV1 0xBE VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
-# R/R 128
-PATTERN : VV1 0xBE VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
-
-# R/M 256
-PATTERN : VV1 0xBE VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
-# R/R 256
-PATTERN : VV1 0xBE VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
-
-}
-{
-ICLASS    : VFNMSUB231SD
-EXCEPTIONS: avx-type-3
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR simd_scalar
-# R/M 128
-PATTERN : VV1 0xBF V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64
-# R/R 128
-PATTERN : VV1 0xBF V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64
-
-}
-{
-ICLASS    : VFNMSUB231SS
-EXCEPTIONS: avx-type-3
-CPL       : 3
-CATEGORY  : VFMA
-EXTENSION : FMA
-ATTRIBUTES: MXCSR simd_scalar
-# R/M 128
-PATTERN : VV1 0xBF V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32
-# R/R 128
-PATTERN : VV1 0xBF V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
-OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32
-
-}
-
-###################################################
-
-
-
-
-
-
-###FILE: ../xed/datafiles/bdw/lin2.xed.txt
+###FILE: ../xed/datafiles/bdw/adox-adcx-isa.xed.txt
 
 #BEGIN_LEGAL
 #
-#Copyright (c) 2016 Intel Corporation
+#Copyright (c) 2018 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -26939,9 +28583,12 @@ INSTRUCTIONS()::
 {
 ICLASS    : ADCX
 CPL       : 3
-CATEGORY  : BDW
-EXTENSION : BDW
+CATEGORY  : ADOX_ADCX
+EXTENSION : ADOX_ADCX
+ISA_SET   : ADOX_ADCX
+
 FLAGS     : MUST [ cf-tst cf-mod ]
+
 # reg:rw rm:r
 # 32b
 PATTERN   : 0x0F 0x38 0xF6  MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix W0  IMMUNE66()
@@ -26961,9 +28608,12 @@ OPERANDS  : REG0=GPR64_R():rw:q  MEM0:r:q
 {
 ICLASS    : ADOX
 CPL       : 3
-CATEGORY  : BDW
-EXTENSION : BDW
+CATEGORY  : ADOX_ADCX
+EXTENSION : ADOX_ADCX
+ISA_SET   : ADOX_ADCX
+
 FLAGS     : MUST [ of-tst of-mod ]
+
 # reg:rw rm:r
 # 32b
 PATTERN   : 0x0F 0x38 0xF6  MOD[0b11] MOD=3 REG[rrr] RM[nnn] refining_f3  W0 IMMUNE66()
@@ -26980,11 +28630,11 @@ OPERANDS  : REG0=GPR64_R():rw:q  MEM0:r:q
 
 
 
-###FILE: ../xed/datafiles/bdw/rdseed.xed.txt
+###FILE: ../xed/datafiles/pku/pku-isa.xed.txt
 
 #BEGIN_LEGAL
 #
-#Copyright (c) 2016 Intel Corporation
+#Copyright (c) 2018 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -26999,26 +28649,40 @@ OPERANDS  : REG0=GPR64_R():rw:q  MEM0:r:q
 #  limitations under the License.
 #
 #END_LEGAL
+
+
 INSTRUCTIONS()::
 
 {
-ICLASS    : RDSEED
-CPL       : 3
-CATEGORY  : RDSEED
-EXTENSION : RDSEED
-ISA_SET   : RDSEED
-FLAGS     : MUST [ cf-mod zf-0 of-0 af-0 pf-0 sf-0 ]
-PATTERN   : 0x0F 0xC7  MOD[0b11] MOD=3 REG[0b111] RM[nnn] not_refining
-OPERANDS  : REG0=GPRv_B():w
+ICLASS:      RDPKRU
+CPL:         3
+CATEGORY:    PKU
+EXTENSION:   PKU
+ISA_SET:     PKU
+ATTRIBUTES:
+PATTERN:    0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b110]  no_refining_prefix
+OPERANDS:    REG0=XED_REG_EDX:w:SUPP REG1=XED_REG_EAX:w:SUPP REG2=XED_REG_ECX:r:SUPP
 }
 
 
+{
+ICLASS:      WRPKRU
+CPL:         3
+CATEGORY:    PKU
+EXTENSION:   PKU
+ISA_SET:     PKU
+ATTRIBUTES:
+PATTERN:    0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b111]  no_refining_prefix
+OPERANDS:    REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_ECX:r:SUPP
+}
 
-###FILE: ../xed/datafiles/bdw/smap.xed.txt
+
+
+###FILE: ../xed/datafiles/clwb/clwb.xed.txt
 
 #BEGIN_LEGAL
 #
-#Copyright (c) 2016 Intel Corporation
+#Copyright (c) 2018 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -27037,34 +28701,24 @@ OPERANDS  : REG0=GPRv_B():w
 INSTRUCTIONS()::
 
 {
-ICLASS    : CLAC
-CPL       : 0
-CATEGORY  : SMAP
-EXTENSION : SMAP
-FLAGS     : MUST [ ac-0 ]
-# 0F 01 CA = 1100_1010 = 11_001_010
-PATTERN   : 0x0F 0x01  MOD[0b11] MOD=3 REG[0b001] RM[0b010] no_refining_prefix
-OPERANDS  :
+ICLASS: CLWB
+CPL: 3
+CATEGORY:  CLWB
+EXTENSION: CLWB
+ISA_SET:   CLWB
+ATTRIBUTES: PREFETCH  # check TSX-friendlyness
+PATTERN   : 0x0F 0xAE  MOD[mm] MOD!=3 REG[0b110] RM[nnn]  osz_refining_prefix REFINING66() MODRM()
+OPERANDS  : MEM0:r:mprefetch
 }
 
-{
-ICLASS    : STAC
-CPL       : 0
-CATEGORY  : SMAP
-EXTENSION : SMAP
-FLAGS     : MUST [ ac-1 ]
-# 0F 01 CB = 1100_1011 = 11_001_011
-PATTERN   : 0x0F 0x01  MOD[0b11] MOD=3 REG[0b001] RM[0b011] no_refining_prefix
-OPERANDS  :
-}
 
 
 
-###FILE: ../xed/datafiles/sgx/sgx-isa.xed.txt
+###FILE: ../xed/datafiles/vnni/vnni-isa.xed.txt
 
 #BEGIN_LEGAL
 #
-#Copyright (c) 2016 Intel Corporation
+#Copyright (c) 2018 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -27079,210 +28733,383 @@ OPERANDS  :
 #  limitations under the License.
 #
 #END_LEGAL
+#
+#
+#
+#    ***** GENERATED FILE -- DO NOT EDIT! *****
+#    ***** GENERATED FILE -- DO NOT EDIT! *****
+#    ***** GENERATED FILE -- DO NOT EDIT! *****
+#
+#
+#
+EVEX_INSTRUCTIONS()::
+# EMITTING VPDPBUSD (VPDPBUSD-128-1)
+{
+ICLASS:      VPDPBUSD
+CPL:         3
+CATEGORY:    AVX512
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VNNI_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x50 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0
+OPERANDS:    REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u32
+IFORM:       VPDPBUSD_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512
+}
 
-INSTRUCTIONS()::
+{
+ICLASS:      VPDPBUSD
+CPL:         3
+CATEGORY:    AVX512
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VNNI_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+PATTERN:    EVV 0x50 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_32_BITS() NELEM_FULL()
+OPERANDS:    REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:vv:u32:TXT=BCASTSTR
+IFORM:       VPDPBUSD_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512
+}
 
-# Both read EAX
-# Both may read or write or r/w  RBX, RCX, RDX
-# ENCLU 0f 01 D7
-# D7 =  1101 0111
 
-# ENCLS 0f 01 CF
-# CF = 1100_1111
+# EMITTING VPDPBUSD (VPDPBUSD-256-1)
+{
+ICLASS:      VPDPBUSD
+CPL:         3
+CATEGORY:    AVX512
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VNNI_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x50 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0
+OPERANDS:    REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u32
+IFORM:       VPDPBUSD_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512
+}
 
+{
+ICLASS:      VPDPBUSD
+CPL:         3
+CATEGORY:    AVX512
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VNNI_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+PATTERN:    EVV 0x50 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_32_BITS() NELEM_FULL()
+OPERANDS:    REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:vv:u32:TXT=BCASTSTR
+IFORM:       VPDPBUSD_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512
+}
 
 
+# EMITTING VPDPBUSD (VPDPBUSD-512-1)
 {
-ICLASS: ENCLU
-CPL: 3
-CATEGORY:  SGX
-EXTENSION: SGX
-ISA_SET:   SGX
-COMMENT:   May set flags
-PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b111] no_refining_prefix
-OPERANDS: REG0=XED_REG_EAX:r:SUPP    \
-          REG1=XED_REG_RBX:crw:SUPP  \
-          REG2=XED_REG_RCX:crw:SUPP  \
-          REG3=XED_REG_RDX:crw:SUPP
+ICLASS:      VPDPBUSD
+CPL:         3
+CATEGORY:    AVX512
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VNNI_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x50 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0
+OPERANDS:    REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu32
+IFORM:       VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512
 }
 
 {
-
-ICLASS: ENCLS
-CPL: 0
-CATEGORY:  SGX
-EXTENSION: SGX
-ISA_SET:   SGX
-COMMENT:   May set flags
-PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b111] no_refining_prefix
-OPERANDS: REG0=XED_REG_EAX:r:SUPP    \
-          REG1=XED_REG_RBX:crw:SUPP  \
-          REG2=XED_REG_RCX:crw:SUPP  \
-          REG3=XED_REG_RDX:crw:SUPP
-
+ICLASS:      VPDPBUSD
+CPL:         3
+CATEGORY:    AVX512
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VNNI_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+PATTERN:    EVV 0x50 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
+OPERANDS:    REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:vv:u32:TXT=BCASTSTR
+IFORM:       VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512
 }
 
 
-###FILE: ../xed/datafiles/pku/pku-isa.xed.txt
+# EMITTING VPDPBUSDS (VPDPBUSDS-128-1)
+{
+ICLASS:      VPDPBUSDS
+CPL:         3
+CATEGORY:    AVX512
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VNNI_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x51 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0
+OPERANDS:    REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u32
+IFORM:       VPDPBUSDS_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512
+}
 
-#BEGIN_LEGAL
-#
-#Copyright (c) 2016 Intel Corporation
-#
-#  Licensed under the Apache License, Version 2.0 (the "License");
-#  you may not use this file except in compliance with the License.
-#  You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-#  Unless required by applicable law or agreed to in writing, software
-#  distributed under the License is distributed on an "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-#  See the License for the specific language governing permissions and
-#  limitations under the License.
-#
-#END_LEGAL
+{
+ICLASS:      VPDPBUSDS
+CPL:         3
+CATEGORY:    AVX512
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VNNI_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+PATTERN:    EVV 0x51 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_32_BITS() NELEM_FULL()
+OPERANDS:    REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:vv:u32:TXT=BCASTSTR
+IFORM:       VPDPBUSDS_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512
+}
 
 
-INSTRUCTIONS()::
+# EMITTING VPDPBUSDS (VPDPBUSDS-256-1)
+{
+ICLASS:      VPDPBUSDS
+CPL:         3
+CATEGORY:    AVX512
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VNNI_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x51 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0
+OPERANDS:    REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u32
+IFORM:       VPDPBUSDS_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512
+}
 
 {
-ICLASS:      RDPKRU
+ICLASS:      VPDPBUSDS
 CPL:         3
-CATEGORY:    PKU
-EXTENSION:   PKU
-ISA_SET:     PKU
-ATTRIBUTES:
-PATTERN:    0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b110]
-OPERANDS:    REG0=XED_REG_EDX:w:SUPP REG1=XED_REG_EAX:w:SUPP REG2=XED_REG_ECX:r:SUPP
+CATEGORY:    AVX512
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VNNI_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+PATTERN:    EVV 0x51 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_32_BITS() NELEM_FULL()
+OPERANDS:    REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:vv:u32:TXT=BCASTSTR
+IFORM:       VPDPBUSDS_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512
 }
 
 
+# EMITTING VPDPBUSDS (VPDPBUSDS-512-1)
 {
-ICLASS:      WRPKRU
+ICLASS:      VPDPBUSDS
 CPL:         3
-CATEGORY:    PKU
-EXTENSION:   PKU
-ISA_SET:     PKU
-ATTRIBUTES:
-PATTERN:    0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b111]
-OPERANDS:    REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_ECX:r:SUPP
+CATEGORY:    AVX512
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VNNI_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x51 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0
+OPERANDS:    REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu32
+IFORM:       VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512
 }
 
+{
+ICLASS:      VPDPBUSDS
+CPL:         3
+CATEGORY:    AVX512
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VNNI_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+PATTERN:    EVV 0x51 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
+OPERANDS:    REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:vv:u32:TXT=BCASTSTR
+IFORM:       VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512
+}
 
 
-###FILE: ../xed/datafiles/memory/clwb.xed.txt
+# EMITTING VPDPWSSD (VPDPWSSD-128-1)
+{
+ICLASS:      VPDPWSSD
+CPL:         3
+CATEGORY:    AVX512
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VNNI_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x52 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0
+OPERANDS:    REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:u32
+IFORM:       VPDPWSSD_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512
+}
 
-#BEGIN_LEGAL
-#
-#Copyright (c) 2016 Intel Corporation
-#
-#  Licensed under the Apache License, Version 2.0 (the "License");
-#  you may not use this file except in compliance with the License.
-#  You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-#  Unless required by applicable law or agreed to in writing, software
-#  distributed under the License is distributed on an "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-#  See the License for the specific language governing permissions and
-#  limitations under the License.
-#
-#END_LEGAL
+{
+ICLASS:      VPDPWSSD
+CPL:         3
+CATEGORY:    AVX512
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VNNI_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+PATTERN:    EVV 0x52 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_32_BITS() NELEM_FULL()
+OPERANDS:    REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:vv:u32:TXT=BCASTSTR
+IFORM:       VPDPWSSD_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512
+}
 
-INSTRUCTIONS()::
 
+# EMITTING VPDPWSSD (VPDPWSSD-256-1)
 {
-ICLASS: CLWB
-CPL: 3
-CATEGORY:  CLWB
-EXTENSION: CLWB
-ISA_SET:   CLWB
-ATTRIBUTES: PREFETCH  # check TSX-friendlyness
-PATTERN   : 0x0F 0xAE  MOD[mm] MOD!=3 REG[0b110] RM[nnn]  osz_refining_prefix REFINING66() MODRM()
-OPERANDS  : MEM0:r:mprefetch
+ICLASS:      VPDPWSSD
+CPL:         3
+CATEGORY:    AVX512
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VNNI_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x52 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0
+OPERANDS:    REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:u32
+IFORM:       VPDPWSSD_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512
 }
 
+{
+ICLASS:      VPDPWSSD
+CPL:         3
+CATEGORY:    AVX512
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VNNI_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+PATTERN:    EVV 0x52 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_32_BITS() NELEM_FULL()
+OPERANDS:    REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:vv:u32:TXT=BCASTSTR
+IFORM:       VPDPWSSD_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512
+}
 
 
+# EMITTING VPDPWSSD (VPDPWSSD-512-1)
+{
+ICLASS:      VPDPWSSD
+CPL:         3
+CATEGORY:    AVX512
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VNNI_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x52 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0
+OPERANDS:    REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zu32
+IFORM:       VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512
+}
 
-###FILE: ../xed/datafiles/memory/clflushopt.xed.txt
-
-#BEGIN_LEGAL
-#
-#Copyright (c) 2016 Intel Corporation
-#
-#  Licensed under the Apache License, Version 2.0 (the "License");
-#  you may not use this file except in compliance with the License.
-#  You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-#  Unless required by applicable law or agreed to in writing, software
-#  distributed under the License is distributed on an "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-#  See the License for the specific language governing permissions and
-#  limitations under the License.
-#
-#END_LEGAL
+{
+ICLASS:      VPDPWSSD
+CPL:         3
+CATEGORY:    AVX512
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VNNI_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+PATTERN:    EVV 0x52 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
+OPERANDS:    REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:vv:u32:TXT=BCASTSTR
+IFORM:       VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512
+}
 
-INSTRUCTIONS()::
 
+# EMITTING VPDPWSSDS (VPDPWSSDS-128-1)
 {
-ICLASS: CLFLUSHOPT
-CPL: 3
-CATEGORY:  CLFLUSHOPT
-EXTENSION: CLFLUSHOPT
-ISA_SET:   CLFLUSHOPT
-ATTRIBUTES: PREFETCH  # check TSX-friendlyness
-PATTERN   : 0x0F 0xAE  MOD[mm] MOD!=3 REG[0b111] RM[nnn]  osz_refining_prefix REFINING66() MODRM()
-OPERANDS  : MEM0:r:mprefetch
+ICLASS:      VPDPWSSDS
+CPL:         3
+CATEGORY:    AVX512
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VNNI_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x53 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0
+OPERANDS:    REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:u32
+IFORM:       VPDPWSSDS_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512
 }
 
+{
+ICLASS:      VPDPWSSDS
+CPL:         3
+CATEGORY:    AVX512
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VNNI_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+PATTERN:    EVV 0x53 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_32_BITS() NELEM_FULL()
+OPERANDS:    REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:vv:u32:TXT=BCASTSTR
+IFORM:       VPDPWSSDS_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512
+}
 
 
+# EMITTING VPDPWSSDS (VPDPWSSDS-256-1)
+{
+ICLASS:      VPDPWSSDS
+CPL:         3
+CATEGORY:    AVX512
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VNNI_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x53 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0
+OPERANDS:    REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:u32
+IFORM:       VPDPWSSDS_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512
+}
 
-###FILE: ../xed/datafiles/pt/intelpt-isa.xed.txt
-
-#BEGIN_LEGAL
-#
-#Copyright (c) 2016 Intel Corporation
-#
-#  Licensed under the Apache License, Version 2.0 (the "License");
-#  you may not use this file except in compliance with the License.
-#  You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-#  Unless required by applicable law or agreed to in writing, software
-#  distributed under the License is distributed on an "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-#  See the License for the specific language governing permissions and
-#  limitations under the License.
-#
-#END_LEGAL
+{
+ICLASS:      VPDPWSSDS
+CPL:         3
+CATEGORY:    AVX512
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VNNI_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+PATTERN:    EVV 0x53 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_32_BITS() NELEM_FULL()
+OPERANDS:    REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:vv:u32:TXT=BCASTSTR
+IFORM:       VPDPWSSDS_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512
+}
 
 
-INSTRUCTIONS()::
+# EMITTING VPDPWSSDS (VPDPWSSDS-512-1)
 {
-ICLASS    : PTWRITE
-CPL       : 3
-CATEGORY  : PT
-EXTENSION : PT
-PATTERN   : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b100]  RM[nnn] f3_refining_prefix  no66_prefix
-OPERANDS  : REG0=GPRy_B():r
-PATTERN   : 0x0F 0xAE MOD[mm]   MOD!=3 REG[0b100] RM[nnn] f3_refining_prefix no66_prefix MODRM()
-OPERANDS  : MEM0:r:y
+ICLASS:      VPDPWSSDS
+CPL:         3
+CATEGORY:    AVX512
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VNNI_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x53 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0
+OPERANDS:    REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zu32
+IFORM:       VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512
+}
 
+{
+ICLASS:      VPDPWSSDS
+CPL:         3
+CATEGORY:    AVX512
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VNNI_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+PATTERN:    EVV 0x53 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
+OPERANDS:    REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:vv:u32:TXT=BCASTSTR
+IFORM:       VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512
 }
 
 
+
+
 ###FILE: ../xed/datafiles/knl/knl-fixup.txt
 
 #BEGIN_LEGAL
 #
-#Copyright (c) 2016 Intel Corporation
+#Copyright (c) 2018 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -27306,7 +29133,7 @@ UDELETE     : PREFETCH_RESERVED_0F0Dr2
 
 #BEGIN_LEGAL
 #
-#Copyright (c) 2016 Intel Corporation
+#Copyright (c) 2018 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -28032,7 +29859,7 @@ INSTRUCTIONS()::
 {
 ICLASS:      PREFETCHWT1
 CPL:         3
-CATEGORY:    AVX512
+CATEGORY:    PREFETCHWT1
 EXTENSION:   PREFETCHWT1
 ISA_SET:     PREFETCHWT1
 REAL_OPCODE: Y
@@ -28049,7 +29876,7 @@ IFORM:       PREFETCHWT1_MEMu8
 
 #BEGIN_LEGAL
 #
-#Copyright (c) 2016 Intel Corporation
+#Copyright (c) 2018 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -28144,7 +29971,7 @@ IFORM:       V4FNMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
 
 #BEGIN_LEGAL
 #
-#Copyright (c) 2016 Intel Corporation
+#Copyright (c) 2018 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -28179,7 +30006,7 @@ ISA_SET:     AVX512_4VNNIW_512
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MULTISOURCE4 DISP8_TUPLE1_4X MASKOP_EVEX
-PATTERN:    EVV 0x52 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_TUPLE1_4X()
+PATTERN:    EVV 0x52 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0  VL512  W0    ESIZE_32_BITS() NELEM_TUPLE1_4X()
 OPERANDS:    REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16:MULTISOURCE4 MEM0:r:dq:u32
 IFORM:       VP4DPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512
 }
@@ -28195,7 +30022,7 @@ ISA_SET:     AVX512_4VNNIW_512
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MULTISOURCE4 DISP8_TUPLE1_4X MASKOP_EVEX
-PATTERN:    EVV 0x53 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_TUPLE1_4X()
+PATTERN:    EVV 0x53 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0  VL512  W0    ESIZE_32_BITS() NELEM_TUPLE1_4X()
 OPERANDS:    REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16:MULTISOURCE4 MEM0:r:dq:u32
 IFORM:       VP4DPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512
 }
@@ -28207,7 +30034,7 @@ IFORM:       VP4DPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512
 
 #BEGIN_LEGAL
 #
-#Copyright (c) 2016 Intel Corporation
+#Copyright (c) 2018 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -28298,7 +30125,7 @@ IFORM:       VPOPCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512
 
 #BEGIN_LEGAL
 #
-#Copyright (c) 2016 Intel Corporation
+#Copyright (c) 2018 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -28332,7 +30159,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x58 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1
 OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
 IFORM:       VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
@@ -28346,7 +30173,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x58 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1
 OPERANDS:    REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
 IFORM:       VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
@@ -28360,7 +30187,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x58 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VADDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
@@ -28376,7 +30203,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x58 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0
 OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
 IFORM:       VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
@@ -28390,7 +30217,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x58 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0
 OPERANDS:    REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
 IFORM:       VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
@@ -28404,7 +30231,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x58 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
@@ -28420,7 +30247,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x58 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -28434,7 +30261,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x58 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1
 OPERANDS:    REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -28448,7 +30275,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0x58 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ESIZE_64_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
 IFORM:       VADDSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
@@ -28464,7 +30291,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x58 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -28478,7 +30305,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x58 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0
 OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -28492,7 +30319,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0x58 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ESIZE_32_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
 IFORM:       VADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
@@ -28582,7 +30409,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL
 PATTERN:    EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
@@ -28612,7 +30439,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL
 PATTERN:    EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
@@ -28756,7 +30583,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xC2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1    ZEROING=0 UIMM8()
 OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b
 IFORM:       VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512
@@ -28770,7 +30597,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xC2 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W1    ZEROING=0 UIMM8()
 OPERANDS:    REG0=MASK_R():w:mskw:TXT=SAESTR REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b
 IFORM:       VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512
@@ -28784,7 +30611,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xC2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ZEROING=0 UIMM8()  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
 IFORM:       VCMPPD_MASKmskw_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512
@@ -28800,7 +30627,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xC2 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0    ZEROING=0 UIMM8()
 OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b
 IFORM:       VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512
@@ -28814,7 +30641,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xC2 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W0    ZEROING=0 UIMM8()
 OPERANDS:    REG0=MASK_R():w:mskw:TXT=SAESTR REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b
 IFORM:       VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512
@@ -28828,7 +30655,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xC2 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ZEROING=0 UIMM8()  ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
 IFORM:       VCMPPS_MASKmskw_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512
@@ -28844,7 +30671,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0xC2 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1    ZEROING=0 UIMM8()
 OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
 IFORM:       VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
@@ -28858,7 +30685,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0xC2 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W1    ZEROING=0 UIMM8()
 OPERANDS:    REG0=MASK_R():w:mskw:TXT=SAESTR REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
 IFORM:       VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
@@ -28872,7 +30699,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0xC2 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ZEROING=0 UIMM8()  ESIZE_64_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b
 IFORM:       VCMPSD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512
@@ -28888,7 +30715,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0xC2 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0    ZEROING=0 UIMM8()
 OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
 IFORM:       VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
@@ -28902,7 +30729,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0xC2 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W0    ZEROING=0 UIMM8()
 OPERANDS:    REG0=MASK_R():w:mskw:TXT=SAESTR REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
 IFORM:       VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
@@ -28916,7 +30743,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0xC2 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ZEROING=0 UIMM8()  ESIZE_32_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b
 IFORM:       VCMPSS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512
@@ -29026,7 +30853,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
 PATTERN:    EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W1  NOEVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
 OPERANDS:    MEM0:w:zd:f64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf64
 IFORM:       VCOMPRESSPD_MEMf64_MASKmskw_ZMMf64_AVX512
@@ -29058,7 +30885,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
 PATTERN:    EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
 OPERANDS:    MEM0:w:zd:f32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32
 IFORM:       VCOMPRESSPS_MEMf32_MASKmskw_ZMMf32_AVX512
@@ -29120,7 +30947,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR
 OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi32
 IFORM:       VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512
@@ -29134,7 +30961,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0  NOEVSR
 OPERANDS:    REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi32
 IFORM:       VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512
@@ -29148,7 +30975,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR
 IFORM:       VCVTDQ2PS_ZMMf32_MASKmskw_MEMi32_AVX512
@@ -29164,7 +30991,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xE6 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR
 OPERANDS:    REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
 IFORM:       VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512
@@ -29178,7 +31005,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xE6 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1  NOEVSR
 OPERANDS:    REG0=YMM_R3():w:qq:i32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
 IFORM:       VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512
@@ -29192,7 +31019,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xE6 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512
@@ -29208,7 +31035,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR
 OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
 IFORM:       VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512
@@ -29222,7 +31049,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5A V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1  NOEVSR
 OPERANDS:    REG0=YMM_R3():w:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
 IFORM:       VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512
@@ -29236,7 +31063,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x5A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512
@@ -29252,7 +31079,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR
 OPERANDS:    REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
 IFORM:       VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512
@@ -29266,7 +31093,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1  NOEVSR
 OPERANDS:    REG0=YMM_R3():w:qq:u32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
 IFORM:       VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512
@@ -29280,7 +31107,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512
@@ -29296,7 +31123,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E11
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR
 OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
 IFORM:       VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512
@@ -29310,7 +31137,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E11
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W0  NOEVSR
 OPERANDS:    REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
 IFORM:       VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512
@@ -29324,7 +31151,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E11
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR DISP8_HALFMEM
 PATTERN:    EVV 0x13 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ESIZE_16_BITS() NELEM_HALFMEM()
 OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f16
 IFORM:       VCVTPH2PS_ZMMf32_MASKmskw_MEMf16_AVX512
@@ -29340,7 +31167,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR
 OPERANDS:    REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
 IFORM:       VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512
@@ -29354,7 +31181,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0  NOEVSR
 OPERANDS:    REG0=ZMM_R3():w:zi32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
 IFORM:       VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512
@@ -29368,7 +31195,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x5B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VCVTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512
@@ -29384,7 +31211,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5A VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR
 OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
 IFORM:       VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512
@@ -29398,7 +31225,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5A VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W0  NOEVSR
 OPERANDS:    REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
 IFORM:       VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512
@@ -29412,7 +31239,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x5A VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_HALF()
 OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VCVTPS2PD_ZMMf64_MASKmskw_MEMf32_AVX512
@@ -29428,7 +31255,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E11NF
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR UIMM8()
 OPERANDS:    REG0=YMM_B3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 IMM0:r:b
 IFORM:       VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512
@@ -29442,7 +31269,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E11NF
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W0  NOEVSR UIMM8()
 OPERANDS:    REG0=YMM_B3():w:qq:f16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 IMM0:r:b
 IFORM:       VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512
@@ -29456,9 +31283,9 @@ CPL:         3
 CATEGORY:    CONVERT
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
-EXCEPTIONS:     AVX512-E11NF
+EXCEPTIONS:     AVX512-E11
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR DISP8_HALFMEM
 PATTERN:    EVV 0x1D V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ZEROING=0 UIMM8()  ESIZE_16_BITS() NELEM_HALFMEM()
 OPERANDS:    MEM0:w:qq:f16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32 IMM0:r:b
 IFORM:       VCVTPS2PH_MEMf16_MASKmskw_ZMMf32_IMM8_AVX512
@@ -29474,7 +31301,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR
 OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
 IFORM:       VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512
@@ -29488,7 +31315,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0  NOEVSR
 OPERANDS:    REG0=ZMM_R3():w:zu32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
 IFORM:       VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512
@@ -29502,7 +31329,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512
@@ -29519,7 +31346,10 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR
-PATTERN:    EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0  NOEVSR  ZEROING=0 MASK=0
+PATTERN:    EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  not64  NOEVSR  ZEROING=0 MASK=0
+OPERANDS:    REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f64
+IFORM:       VCVTSD2SI_GPR32i32_XMMf64_AVX512
+PATTERN:    EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  mode64 W0  NOEVSR  ZEROING=0 MASK=0 EVEXRR_ONE
 OPERANDS:    REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f64
 IFORM:       VCVTSD2SI_GPR32i32_XMMf64_AVX512
 }
@@ -29533,7 +31363,10 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR
-PATTERN:    EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0  NOEVSR  ZEROING=0 MASK=0
+PATTERN:    EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  not64  NOEVSR  ZEROING=0 MASK=0
+OPERANDS:    REG0=GPR32_R():w:d:i32:TXT=ROUNDC REG1=XMM_B3():r:dq:f64
+IFORM:       VCVTSD2SI_GPR32i32_XMMf64_AVX512
+PATTERN:    EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  mode64 W0  NOEVSR  ZEROING=0 MASK=0 EVEXRR_ONE
 OPERANDS:    REG0=GPR32_R():w:d:i32:TXT=ROUNDC REG1=XMM_B3():r:dq:f64
 IFORM:       VCVTSD2SI_GPR32i32_XMMf64_AVX512
 }
@@ -29547,7 +31380,10 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q
-PATTERN:    EVV 0x2D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0  NOEVSR  ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q()
+PATTERN:    EVV 0x2D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  not64  NOEVSR  ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q()
+OPERANDS:    REG0=GPR32_R():w:d:i32 MEM0:r:q:f64
+IFORM:       VCVTSD2SI_GPR32i32_MEMf64_AVX512
+PATTERN:    EVV 0x2D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  mode64 W0  NOEVSR  ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE
 OPERANDS:    REG0=GPR32_R():w:d:i32 MEM0:r:q:f64
 IFORM:       VCVTSD2SI_GPR32i32_MEMf64_AVX512
 }
@@ -29563,7 +31399,7 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR
-PATTERN:    EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1  mode64  NOEVSR  ZEROING=0 MASK=0
+PATTERN:    EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  mode64  W1  NOEVSR  ZEROING=0 MASK=0  EVEXRR_ONE
 OPERANDS:    REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f64
 IFORM:       VCVTSD2SI_GPR64i64_XMMf64_AVX512
 }
@@ -29577,7 +31413,7 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR
-PATTERN:    EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1  mode64  NOEVSR  ZEROING=0 MASK=0
+PATTERN:    EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  mode64  W1  NOEVSR  ZEROING=0 MASK=0  EVEXRR_ONE
 OPERANDS:    REG0=GPR64_R():w:q:i64:TXT=ROUNDC REG1=XMM_B3():r:dq:f64
 IFORM:       VCVTSD2SI_GPR64i64_XMMf64_AVX512
 }
@@ -29591,7 +31427,7 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q
-PATTERN:    EVV 0x2D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1  mode64  NOEVSR  ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q()
+PATTERN:    EVV 0x2D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  mode64  W1  NOEVSR  ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE
 OPERANDS:    REG0=GPR64_R():w:q:i64 MEM0:r:q:f64
 IFORM:       VCVTSD2SI_GPR64i64_MEMf64_AVX512
 }
@@ -29606,7 +31442,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512
@@ -29620,7 +31456,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1
 OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512
@@ -29634,7 +31470,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ESIZE_64_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
 IFORM:       VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512
@@ -29651,7 +31487,10 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR
-PATTERN:    EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0  NOEVSR  ZEROING=0 MASK=0
+PATTERN:    EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  not64  NOEVSR  ZEROING=0 MASK=0
+OPERANDS:    REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f64
+IFORM:       VCVTSD2USI_GPR32u32_XMMf64_AVX512
+PATTERN:    EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  mode64 W0  NOEVSR  ZEROING=0 MASK=0 EVEXRR_ONE
 OPERANDS:    REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f64
 IFORM:       VCVTSD2USI_GPR32u32_XMMf64_AVX512
 }
@@ -29665,7 +31504,10 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR
-PATTERN:    EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0  NOEVSR  ZEROING=0 MASK=0
+PATTERN:    EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  not64  NOEVSR  ZEROING=0 MASK=0
+OPERANDS:    REG0=GPR32_R():w:d:u32:TXT=ROUNDC REG1=XMM_B3():r:dq:f64
+IFORM:       VCVTSD2USI_GPR32u32_XMMf64_AVX512
+PATTERN:    EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  mode64 W0  NOEVSR  ZEROING=0 MASK=0 EVEXRR_ONE
 OPERANDS:    REG0=GPR32_R():w:d:u32:TXT=ROUNDC REG1=XMM_B3():r:dq:f64
 IFORM:       VCVTSD2USI_GPR32u32_XMMf64_AVX512
 }
@@ -29679,7 +31521,10 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q
-PATTERN:    EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0  NOEVSR  ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q()
+PATTERN:    EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  not64  NOEVSR  ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q()
+OPERANDS:    REG0=GPR32_R():w:d:u32 MEM0:r:q:f64
+IFORM:       VCVTSD2USI_GPR32u32_MEMf64_AVX512
+PATTERN:    EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  mode64 W0  NOEVSR  ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE
 OPERANDS:    REG0=GPR32_R():w:d:u32 MEM0:r:q:f64
 IFORM:       VCVTSD2USI_GPR32u32_MEMf64_AVX512
 }
@@ -29695,7 +31540,7 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR
-PATTERN:    EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1  mode64  NOEVSR  ZEROING=0 MASK=0
+PATTERN:    EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  mode64  W1  NOEVSR  ZEROING=0 MASK=0  EVEXRR_ONE
 OPERANDS:    REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f64
 IFORM:       VCVTSD2USI_GPR64u64_XMMf64_AVX512
 }
@@ -29709,7 +31554,7 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR
-PATTERN:    EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1  mode64  NOEVSR  ZEROING=0 MASK=0
+PATTERN:    EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  mode64  W1  NOEVSR  ZEROING=0 MASK=0  EVEXRR_ONE
 OPERANDS:    REG0=GPR64_R():w:q:u64:TXT=ROUNDC REG1=XMM_B3():r:dq:f64
 IFORM:       VCVTSD2USI_GPR64u64_XMMf64_AVX512
 }
@@ -29723,7 +31568,7 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q
-PATTERN:    EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1  mode64  NOEVSR  ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q()
+PATTERN:    EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  mode64  W1  NOEVSR  ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE
 OPERANDS:    REG0=GPR64_R():w:q:u64 MEM0:r:q:f64
 IFORM:       VCVTSD2USI_GPR64u64_MEMf64_AVX512
 }
@@ -29739,7 +31584,11 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E10NF
 REAL_OPCODE: Y
 ATTRIBUTES:  SIMD_SCALAR
-PATTERN:    EVV 0x2A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0    ZEROING=0 MASK=0
+COMMENT: Ignores rounding controls: 32b-INT-to-FP64 does not need rounding
+PATTERN:    EVV 0x2A VF2 V0F MOD[0b11] MOD=3  REG[rrr] RM[nnn]  not64    ZEROING=0 MASK=0
+OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR32_B():r:d:i32
+IFORM:       VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512
+PATTERN:    EVV 0x2A VF2 V0F MOD[0b11] MOD=3  REG[rrr] RM[nnn]  mode64 W0    ZEROING=0 MASK=0
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR32_B():r:d:i32
 IFORM:       VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512
 }
@@ -29753,7 +31602,10 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E10NF
 REAL_OPCODE: Y
 ATTRIBUTES:  SIMD_SCALAR DISP8_GPR_READER
-PATTERN:    EVV 0x2A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_GPR_READER()
+PATTERN:    EVV 0x2A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  not64 ZEROING=0 MASK=0 BCRC=0  ESIZE_32_BITS() NELEM_GPR_READER()
+OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:d:i32
+IFORM:       VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512
+PATTERN:    EVV 0x2A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  mode64 W0 ZEROING=0 MASK=0 BCRC=0  ESIZE_32_BITS() NELEM_GPR_READER()
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:d:i32
 IFORM:       VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512
 }
@@ -29769,7 +31621,7 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR
-PATTERN:    EVV 0x2A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1  mode64    ZEROING=0 MASK=0
+PATTERN:    EVV 0x2A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=0
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR64_B():r:q:i64
 IFORM:       VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512
 }
@@ -29783,7 +31635,7 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR
-PATTERN:    EVV 0x2A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1  mode64    ZEROING=0 MASK=0
+PATTERN:    EVV 0x2A VF2 V0F MOD[0b11] MOD=3  REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=1 FIX_ROUND_LEN128() AVX512_ROUND()
 OPERANDS:    REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=XMM_N3():r:dq:f64 REG2=GPR64_B():r:q:i64
 IFORM:       VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512
 }
@@ -29797,7 +31649,7 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR DISP8_GPR_READER
-PATTERN:    EVV 0x2A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1  mode64    ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_GPR_READER()
+PATTERN:    EVV 0x2A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM() mode64 W1 ZEROING=0 MASK=0 BCRC=0  ESIZE_64_BITS() NELEM_GPR_READER()
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:q:i64
 IFORM:       VCVTSI2SD_XMMf64_XMMf64_MEMi64_AVX512
 }
@@ -29813,7 +31665,10 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR
-PATTERN:    EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0    ZEROING=0 MASK=0
+PATTERN:    EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  not64    ZEROING=0 MASK=0
+OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:i32
+IFORM:       VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512
+PATTERN:    EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  mode64 W0    ZEROING=0 MASK=0
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:i32
 IFORM:       VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512
 }
@@ -29827,7 +31682,10 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR
-PATTERN:    EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0    ZEROING=0 MASK=0
+PATTERN:    EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  not64    ZEROING=0 MASK=0
+OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:i32
+IFORM:       VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512
+PATTERN:    EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  mode64 W0    ZEROING=0 MASK=0
 OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:i32
 IFORM:       VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512
 }
@@ -29841,7 +31699,10 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR DISP8_GPR_READER
-PATTERN:    EVV 0x2A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_GPR_READER()
+PATTERN:    EVV 0x2A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  not64    ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_GPR_READER()
+OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:d:i32
+IFORM:       VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512
+PATTERN:    EVV 0x2A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  mode64 W0    ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_GPR_READER()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:d:i32
 IFORM:       VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512
 }
@@ -29857,7 +31718,7 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR
-PATTERN:    EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1  mode64    ZEROING=0 MASK=0
+PATTERN:    EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  mode64  W1    ZEROING=0 MASK=0
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR64_B():r:q:i64
 IFORM:       VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512
 }
@@ -29871,7 +31732,7 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR
-PATTERN:    EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1  mode64    ZEROING=0 MASK=0
+PATTERN:    EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  mode64  W1    ZEROING=0 MASK=0
 OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR64_B():r:q:i64
 IFORM:       VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512
 }
@@ -29885,12 +31746,10 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR DISP8_GPR_READER
-PATTERN:    EVV 0x2A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1  mode64    ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_GPR_READER()
+PATTERN:    EVV 0x2A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  mode64  W1    ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_GPR_READER()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:q:i64
 IFORM:       VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512
 }
-
-
 # EMITTING VCVTSS2SD (VCVTSS2SD-128-1)
 {
 ICLASS:      VCVTSS2SD
@@ -29900,7 +31759,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512
@@ -29914,7 +31773,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W0
 OPERANDS:    REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512
@@ -29928,7 +31787,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ESIZE_32_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
 IFORM:       VCVTSS2SD_XMMf64_MASKmskw_XMMf32_MEMf32_AVX512
@@ -29945,7 +31804,10 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR
-PATTERN:    EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0  NOEVSR  ZEROING=0 MASK=0
+PATTERN:    EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  not64  NOEVSR  ZEROING=0 MASK=0
+OPERANDS:    REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f32
+IFORM:       VCVTSS2SI_GPR32i32_XMMf32_AVX512
+PATTERN:    EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  mode64 W0  NOEVSR  ZEROING=0 MASK=0  EVEXRR_ONE
 OPERANDS:    REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f32
 IFORM:       VCVTSS2SI_GPR32i32_XMMf32_AVX512
 }
@@ -29959,7 +31821,10 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR
-PATTERN:    EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0  NOEVSR  ZEROING=0 MASK=0
+PATTERN:    EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  not64  NOEVSR  ZEROING=0 MASK=0
+OPERANDS:    REG0=GPR32_R():w:d:i32:TXT=ROUNDC REG1=XMM_B3():r:dq:f32
+IFORM:       VCVTSS2SI_GPR32i32_XMMf32_AVX512
+PATTERN:    EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  mode64 W0  NOEVSR  ZEROING=0 MASK=0  EVEXRR_ONE
 OPERANDS:    REG0=GPR32_R():w:d:i32:TXT=ROUNDC REG1=XMM_B3():r:dq:f32
 IFORM:       VCVTSS2SI_GPR32i32_XMMf32_AVX512
 }
@@ -29972,8 +31837,11 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_D
-PATTERN:    EVV 0x2D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0  NOEVSR  ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D()
+ATTRIBUTES:  DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR
+PATTERN:    EVV 0x2D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  not64  NOEVSR  ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D()
+OPERANDS:    REG0=GPR32_R():w:d:i32 MEM0:r:d:f32
+IFORM:       VCVTSS2SI_GPR32i32_MEMf32_AVX512
+PATTERN:    EVV 0x2D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  mode64 W0  NOEVSR  ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE
 OPERANDS:    REG0=GPR32_R():w:d:i32 MEM0:r:d:f32
 IFORM:       VCVTSS2SI_GPR32i32_MEMf32_AVX512
 }
@@ -29989,7 +31857,7 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR
-PATTERN:    EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1  mode64  NOEVSR  ZEROING=0 MASK=0
+PATTERN:    EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  mode64  W1  NOEVSR  ZEROING=0 MASK=0  EVEXRR_ONE
 OPERANDS:    REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f32
 IFORM:       VCVTSS2SI_GPR64i64_XMMf32_AVX512
 }
@@ -30003,7 +31871,7 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR
-PATTERN:    EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1  mode64  NOEVSR  ZEROING=0 MASK=0
+PATTERN:    EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  mode64  W1  NOEVSR  ZEROING=0 MASK=0  EVEXRR_ONE
 OPERANDS:    REG0=GPR64_R():w:q:i64:TXT=ROUNDC REG1=XMM_B3():r:dq:f32
 IFORM:       VCVTSS2SI_GPR64i64_XMMf32_AVX512
 }
@@ -30016,8 +31884,8 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_D
-PATTERN:    EVV 0x2D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1  mode64  NOEVSR  ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D()
+ATTRIBUTES:  DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR
+PATTERN:    EVV 0x2D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  mode64  W1  NOEVSR  ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE
 OPERANDS:    REG0=GPR64_R():w:q:i64 MEM0:r:d:f32
 IFORM:       VCVTSS2SI_GPR64i64_MEMf32_AVX512
 }
@@ -30033,7 +31901,10 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR
-PATTERN:    EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0  NOEVSR  ZEROING=0 MASK=0
+PATTERN:    EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  not64  NOEVSR  ZEROING=0 MASK=0
+OPERANDS:    REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f32
+IFORM:       VCVTSS2USI_GPR32u32_XMMf32_AVX512
+PATTERN:    EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  mode64 W0  NOEVSR  ZEROING=0 MASK=0  EVEXRR_ONE
 OPERANDS:    REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f32
 IFORM:       VCVTSS2USI_GPR32u32_XMMf32_AVX512
 }
@@ -30047,7 +31918,10 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR
-PATTERN:    EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0  NOEVSR  ZEROING=0 MASK=0
+PATTERN:    EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  not64  NOEVSR  ZEROING=0 MASK=0
+OPERANDS:    REG0=GPR32_R():w:d:u32:TXT=ROUNDC REG1=XMM_B3():r:dq:f32
+IFORM:       VCVTSS2USI_GPR32u32_XMMf32_AVX512
+PATTERN:    EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  mode64 W0  NOEVSR  ZEROING=0 MASK=0  EVEXRR_ONE
 OPERANDS:    REG0=GPR32_R():w:d:u32:TXT=ROUNDC REG1=XMM_B3():r:dq:f32
 IFORM:       VCVTSS2USI_GPR32u32_XMMf32_AVX512
 }
@@ -30060,8 +31934,11 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_D
-PATTERN:    EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0  NOEVSR  ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D()
+ATTRIBUTES:  DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR
+PATTERN:    EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  not64  NOEVSR  ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D()
+OPERANDS:    REG0=GPR32_R():w:d:u32 MEM0:r:d:f32
+IFORM:       VCVTSS2USI_GPR32u32_MEMf32_AVX512
+PATTERN:    EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  mode64 W0  NOEVSR  ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE
 OPERANDS:    REG0=GPR32_R():w:d:u32 MEM0:r:d:f32
 IFORM:       VCVTSS2USI_GPR32u32_MEMf32_AVX512
 }
@@ -30077,7 +31954,7 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR
-PATTERN:    EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1  mode64  NOEVSR  ZEROING=0 MASK=0
+PATTERN:    EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  mode64  W1  NOEVSR  ZEROING=0 MASK=0  EVEXRR_ONE
 OPERANDS:    REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f32
 IFORM:       VCVTSS2USI_GPR64u64_XMMf32_AVX512
 }
@@ -30091,7 +31968,7 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR
-PATTERN:    EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1  mode64  NOEVSR  ZEROING=0 MASK=0
+PATTERN:    EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  mode64  W1  NOEVSR  ZEROING=0 MASK=0  EVEXRR_ONE
 OPERANDS:    REG0=GPR64_R():w:q:u64:TXT=ROUNDC REG1=XMM_B3():r:dq:f32
 IFORM:       VCVTSS2USI_GPR64u64_XMMf32_AVX512
 }
@@ -30104,8 +31981,8 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_D
-PATTERN:    EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1  mode64  NOEVSR  ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D()
+ATTRIBUTES:  DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR
+PATTERN:    EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  mode64  W1  NOEVSR  ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE
 OPERANDS:    REG0=GPR64_R():w:q:u64 MEM0:r:d:f32
 IFORM:       VCVTSS2USI_GPR64u64_MEMf32_AVX512
 }
@@ -30120,7 +31997,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xE6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR
 OPERANDS:    REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
 IFORM:       VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512
@@ -30134,7 +32011,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xE6 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W1  NOEVSR
 OPERANDS:    REG0=YMM_R3():w:qq:i32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
 IFORM:       VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512
@@ -30148,7 +32025,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xE6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512
@@ -30164,7 +32041,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR
 OPERANDS:    REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
 IFORM:       VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512
@@ -30178,7 +32055,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W1  NOEVSR
 OPERANDS:    REG0=YMM_R3():w:qq:u32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
 IFORM:       VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512
@@ -30192,7 +32069,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512
@@ -30208,7 +32085,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR
 OPERANDS:    REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
 IFORM:       VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512
@@ -30222,7 +32099,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W0  NOEVSR
 OPERANDS:    REG0=ZMM_R3():w:zi32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
 IFORM:       VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512
@@ -30236,7 +32113,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x5B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VCVTTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512
@@ -30252,7 +32129,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR
 OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
 IFORM:       VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512
@@ -30266,7 +32143,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W0  NOEVSR
 OPERANDS:    REG0=ZMM_R3():w:zu32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
 IFORM:       VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512
@@ -30280,7 +32157,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512
@@ -30297,7 +32174,10 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR
-PATTERN:    EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0  NOEVSR  ZEROING=0 MASK=0
+PATTERN:    EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  not64  NOEVSR  ZEROING=0 MASK=0
+OPERANDS:    REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f64
+IFORM:       VCVTTSD2SI_GPR32i32_XMMf64_AVX512
+PATTERN:    EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  mode64 W0  NOEVSR  ZEROING=0 MASK=0  EVEXRR_ONE
 OPERANDS:    REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f64
 IFORM:       VCVTTSD2SI_GPR32i32_XMMf64_AVX512
 }
@@ -30311,7 +32191,10 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR
-PATTERN:    EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W0  NOEVSR  ZEROING=0 MASK=0
+PATTERN:    EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  not64  NOEVSR  ZEROING=0 MASK=0
+OPERANDS:    REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f64
+IFORM:       VCVTTSD2SI_GPR32i32_XMMf64_AVX512
+PATTERN:    EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  mode64 W0  NOEVSR  ZEROING=0 MASK=0  EVEXRR_ONE
 OPERANDS:    REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f64
 IFORM:       VCVTTSD2SI_GPR32i32_XMMf64_AVX512
 }
@@ -30325,7 +32208,10 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q
-PATTERN:    EVV 0x2C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0  NOEVSR  ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q()
+PATTERN:    EVV 0x2C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  not64  NOEVSR  ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q()
+OPERANDS:    REG0=GPR32_R():w:d:i32 MEM0:r:q:f64
+IFORM:       VCVTTSD2SI_GPR32i32_MEMf64_AVX512
+PATTERN:    EVV 0x2C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  mode64 W0  NOEVSR  ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE
 OPERANDS:    REG0=GPR32_R():w:d:i32 MEM0:r:q:f64
 IFORM:       VCVTTSD2SI_GPR32i32_MEMf64_AVX512
 }
@@ -30341,7 +32227,7 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR
-PATTERN:    EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1  mode64  NOEVSR  ZEROING=0 MASK=0
+PATTERN:    EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  mode64  W1  NOEVSR  ZEROING=0 MASK=0  EVEXRR_ONE
 OPERANDS:    REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f64
 IFORM:       VCVTTSD2SI_GPR64i64_XMMf64_AVX512
 }
@@ -30355,7 +32241,7 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR
-PATTERN:    EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W1  mode64  NOEVSR  ZEROING=0 MASK=0
+PATTERN:    EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  mode64  W1  NOEVSR  ZEROING=0 MASK=0  EVEXRR_ONE
 OPERANDS:    REG0=GPR64_R():w:q:i64:TXT=SAESTR REG1=XMM_B3():r:dq:f64
 IFORM:       VCVTTSD2SI_GPR64i64_XMMf64_AVX512
 }
@@ -30369,7 +32255,7 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q
-PATTERN:    EVV 0x2C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1  mode64  NOEVSR  ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q()
+PATTERN:    EVV 0x2C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  mode64  W1  NOEVSR  ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE
 OPERANDS:    REG0=GPR64_R():w:q:i64 MEM0:r:q:f64
 IFORM:       VCVTTSD2SI_GPR64i64_MEMf64_AVX512
 }
@@ -30385,7 +32271,10 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR
-PATTERN:    EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0  NOEVSR  ZEROING=0 MASK=0
+PATTERN:    EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  not64  NOEVSR  ZEROING=0 MASK=0
+OPERANDS:    REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f64
+IFORM:       VCVTTSD2USI_GPR32u32_XMMf64_AVX512
+PATTERN:    EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  mode64 W0  NOEVSR  ZEROING=0 MASK=0  EVEXRR_ONE
 OPERANDS:    REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f64
 IFORM:       VCVTTSD2USI_GPR32u32_XMMf64_AVX512
 }
@@ -30399,7 +32288,10 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR
-PATTERN:    EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W0  NOEVSR  ZEROING=0 MASK=0
+PATTERN:    EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  not64  NOEVSR  ZEROING=0 MASK=0
+OPERANDS:    REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f64
+IFORM:       VCVTTSD2USI_GPR32u32_XMMf64_AVX512
+PATTERN:    EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  mode64 W0  NOEVSR  ZEROING=0 MASK=0  EVEXRR_ONE
 OPERANDS:    REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f64
 IFORM:       VCVTTSD2USI_GPR32u32_XMMf64_AVX512
 }
@@ -30413,7 +32305,10 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q
-PATTERN:    EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0  NOEVSR  ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q()
+PATTERN:    EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  not64  NOEVSR  ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q()
+OPERANDS:    REG0=GPR32_R():w:d:u32 MEM0:r:q:f64
+IFORM:       VCVTTSD2USI_GPR32u32_MEMf64_AVX512
+PATTERN:    EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  mode64 W0  NOEVSR  ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE
 OPERANDS:    REG0=GPR32_R():w:d:u32 MEM0:r:q:f64
 IFORM:       VCVTTSD2USI_GPR32u32_MEMf64_AVX512
 }
@@ -30429,7 +32324,7 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR
-PATTERN:    EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1  mode64  NOEVSR  ZEROING=0 MASK=0
+PATTERN:    EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  mode64  W1  NOEVSR  ZEROING=0 MASK=0  EVEXRR_ONE
 OPERANDS:    REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f64
 IFORM:       VCVTTSD2USI_GPR64u64_XMMf64_AVX512
 }
@@ -30443,7 +32338,7 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR
-PATTERN:    EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W1  mode64  NOEVSR  ZEROING=0 MASK=0
+PATTERN:    EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  mode64  W1  NOEVSR  ZEROING=0 MASK=0  EVEXRR_ONE
 OPERANDS:    REG0=GPR64_R():w:q:u64:TXT=SAESTR REG1=XMM_B3():r:dq:f64
 IFORM:       VCVTTSD2USI_GPR64u64_XMMf64_AVX512
 }
@@ -30457,7 +32352,7 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q
-PATTERN:    EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1  mode64  NOEVSR  ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q()
+PATTERN:    EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  mode64  W1  NOEVSR  ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE
 OPERANDS:    REG0=GPR64_R():w:q:u64 MEM0:r:q:f64
 IFORM:       VCVTTSD2USI_GPR64u64_MEMf64_AVX512
 }
@@ -30473,7 +32368,10 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR
-PATTERN:    EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0  NOEVSR  ZEROING=0 MASK=0
+PATTERN:    EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  not64  NOEVSR  ZEROING=0 MASK=0
+OPERANDS:    REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f32
+IFORM:       VCVTTSS2SI_GPR32i32_XMMf32_AVX512
+PATTERN:    EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  mode64 W0  NOEVSR  ZEROING=0 MASK=0  EVEXRR_ONE
 OPERANDS:    REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f32
 IFORM:       VCVTTSS2SI_GPR32i32_XMMf32_AVX512
 }
@@ -30487,7 +32385,10 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR
-PATTERN:    EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W0  NOEVSR  ZEROING=0 MASK=0
+PATTERN:    EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  not64  NOEVSR  ZEROING=0 MASK=0
+OPERANDS:    REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f32
+IFORM:       VCVTTSS2SI_GPR32i32_XMMf32_AVX512
+PATTERN:    EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  mode64 W0  NOEVSR  ZEROING=0 MASK=0  EVEXRR_ONE
 OPERANDS:    REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f32
 IFORM:       VCVTTSS2SI_GPR32i32_XMMf32_AVX512
 }
@@ -30500,8 +32401,11 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_D
-PATTERN:    EVV 0x2C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0  NOEVSR  ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D()
+ATTRIBUTES:  DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR
+PATTERN:    EVV 0x2C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  not64  NOEVSR  ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D()
+OPERANDS:    REG0=GPR32_R():w:d:i32 MEM0:r:d:f32
+IFORM:       VCVTTSS2SI_GPR32i32_MEMf32_AVX512
+PATTERN:    EVV 0x2C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  mode64 W0  NOEVSR  ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE
 OPERANDS:    REG0=GPR32_R():w:d:i32 MEM0:r:d:f32
 IFORM:       VCVTTSS2SI_GPR32i32_MEMf32_AVX512
 }
@@ -30517,7 +32421,7 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR
-PATTERN:    EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1  mode64  NOEVSR  ZEROING=0 MASK=0
+PATTERN:    EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  mode64  W1  NOEVSR  ZEROING=0 MASK=0  EVEXRR_ONE
 OPERANDS:    REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f32
 IFORM:       VCVTTSS2SI_GPR64i64_XMMf32_AVX512
 }
@@ -30531,7 +32435,7 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR
-PATTERN:    EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W1  mode64  NOEVSR  ZEROING=0 MASK=0
+PATTERN:    EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  mode64  W1  NOEVSR  ZEROING=0 MASK=0  EVEXRR_ONE
 OPERANDS:    REG0=GPR64_R():w:q:i64:TXT=SAESTR REG1=XMM_B3():r:dq:f32
 IFORM:       VCVTTSS2SI_GPR64i64_XMMf32_AVX512
 }
@@ -30544,8 +32448,8 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_D
-PATTERN:    EVV 0x2C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1  mode64  NOEVSR  ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D()
+ATTRIBUTES:  DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR
+PATTERN:    EVV 0x2C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  mode64  W1  NOEVSR  ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE
 OPERANDS:    REG0=GPR64_R():w:q:i64 MEM0:r:d:f32
 IFORM:       VCVTTSS2SI_GPR64i64_MEMf32_AVX512
 }
@@ -30561,7 +32465,10 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR
-PATTERN:    EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0  NOEVSR  ZEROING=0 MASK=0
+PATTERN:    EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  not64  NOEVSR  ZEROING=0 MASK=0
+OPERANDS:    REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f32
+IFORM:       VCVTTSS2USI_GPR32u32_XMMf32_AVX512
+PATTERN:    EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  mode64 W0  NOEVSR  ZEROING=0 MASK=0  EVEXRR_ONE
 OPERANDS:    REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f32
 IFORM:       VCVTTSS2USI_GPR32u32_XMMf32_AVX512
 }
@@ -30575,7 +32482,10 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR
-PATTERN:    EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W0  NOEVSR  ZEROING=0 MASK=0
+PATTERN:    EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  not64  NOEVSR  ZEROING=0 MASK=0
+OPERANDS:    REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f32
+IFORM:       VCVTTSS2USI_GPR32u32_XMMf32_AVX512
+PATTERN:    EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  mode64 W0  NOEVSR  ZEROING=0 MASK=0  EVEXRR_ONE
 OPERANDS:    REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f32
 IFORM:       VCVTTSS2USI_GPR32u32_XMMf32_AVX512
 }
@@ -30588,8 +32498,11 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_D
-PATTERN:    EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0  NOEVSR  ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D()
+ATTRIBUTES:  DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR
+PATTERN:    EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  not64  NOEVSR  ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D()
+OPERANDS:    REG0=GPR32_R():w:d:u32 MEM0:r:d:f32
+IFORM:       VCVTTSS2USI_GPR32u32_MEMf32_AVX512
+PATTERN:    EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  mode64 W0  NOEVSR  ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE
 OPERANDS:    REG0=GPR32_R():w:d:u32 MEM0:r:d:f32
 IFORM:       VCVTTSS2USI_GPR32u32_MEMf32_AVX512
 }
@@ -30605,7 +32518,7 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR
-PATTERN:    EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1  mode64  NOEVSR  ZEROING=0 MASK=0
+PATTERN:    EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  mode64  W1  NOEVSR  ZEROING=0 MASK=0  EVEXRR_ONE
 OPERANDS:    REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f32
 IFORM:       VCVTTSS2USI_GPR64u64_XMMf32_AVX512
 }
@@ -30619,7 +32532,7 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR
-PATTERN:    EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W1  mode64  NOEVSR  ZEROING=0 MASK=0
+PATTERN:    EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  mode64  W1  NOEVSR  ZEROING=0 MASK=0  EVEXRR_ONE
 OPERANDS:    REG0=GPR64_R():w:q:u64:TXT=SAESTR REG1=XMM_B3():r:dq:f32
 IFORM:       VCVTTSS2USI_GPR64u64_XMMf32_AVX512
 }
@@ -30632,8 +32545,8 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_D
-PATTERN:    EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1  mode64  NOEVSR  ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D()
+ATTRIBUTES:  DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR
+PATTERN:    EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  mode64  W1  NOEVSR  ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE
 OPERANDS:    REG0=GPR64_R():w:q:u64 MEM0:r:d:f32
 IFORM:       VCVTTSS2USI_GPR64u64_MEMf32_AVX512
 }
@@ -30678,7 +32591,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR
 OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32
 IFORM:       VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512
@@ -30692,7 +32605,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0  NOEVSR
 OPERANDS:    REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32
 IFORM:       VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512
@@ -30706,7 +32619,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR
 IFORM:       VCVTUDQ2PS_ZMMf32_MASKmskw_MEMu32_AVX512
@@ -30723,7 +32636,10 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E10NF
 REAL_OPCODE: Y
 ATTRIBUTES:  SIMD_SCALAR
-PATTERN:    EVV 0x7B VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0    ZEROING=0 MASK=0
+PATTERN:    EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0
+OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR32_B():r:d:u32
+IFORM:       VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512
+PATTERN:    EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR32_B():r:d:u32
 IFORM:       VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512
 }
@@ -30737,7 +32653,10 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E10NF
 REAL_OPCODE: Y
 ATTRIBUTES:  SIMD_SCALAR DISP8_GPR_READER
-PATTERN:    EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_GPR_READER()
+PATTERN:    EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  not64    ZEROING=0 MASK=0 BCRC=0  ESIZE_32_BITS() NELEM_GPR_READER()
+OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:d:u32
+IFORM:       VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512
+PATTERN:    EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  mode64 W0    ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER()
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:d:u32
 IFORM:       VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512
 }
@@ -30753,7 +32672,7 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR
-PATTERN:    EVV 0x7B VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1  mode64    ZEROING=0 MASK=0
+PATTERN:    EVV 0x7B VF2 V0F MOD[0b11] MOD=3  REG[rrr] RM[nnn]  mode64 W1 ZEROING=0 MASK=0 BCRC=0
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR64_B():r:q:u64
 IFORM:       VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512
 }
@@ -30767,7 +32686,7 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR
-PATTERN:    EVV 0x7B VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1  mode64    ZEROING=0 MASK=0
+PATTERN:    EVV 0x7B VF2 V0F MOD[0b11] MOD=3  REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=1 FIX_ROUND_LEN128() AVX512_ROUND()
 OPERANDS:    REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=XMM_N3():r:dq:f64 REG2=GPR64_B():r:q:u64
 IFORM:       VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512
 }
@@ -30781,7 +32700,7 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR DISP8_GPR_READER
-PATTERN:    EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1  mode64    ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_GPR_READER()
+PATTERN:    EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM() mode64 W1 ZEROING=0 MASK=0 BCRC=0  ESIZE_64_BITS() NELEM_GPR_READER()
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:q:u64
 IFORM:       VCVTUSI2SD_XMMf64_XMMf64_MEMu64_AVX512
 }
@@ -30797,7 +32716,10 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR
-PATTERN:    EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0    ZEROING=0 MASK=0
+PATTERN:    EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  not64    ZEROING=0 MASK=0
+OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:u32
+IFORM:       VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512
+PATTERN:    EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  mode64 W0    ZEROING=0 MASK=0
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:u32
 IFORM:       VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512
 }
@@ -30811,7 +32733,10 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR
-PATTERN:    EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0    ZEROING=0 MASK=0
+PATTERN:    EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  not64    ZEROING=0 MASK=0
+OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:u32
+IFORM:       VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512
+PATTERN:    EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  mode64 W0    ZEROING=0 MASK=0
 OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:u32
 IFORM:       VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512
 }
@@ -30825,7 +32750,10 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR DISP8_GPR_READER
-PATTERN:    EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_GPR_READER()
+PATTERN:    EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  not64    ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_GPR_READER()
+OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:d:u32
+IFORM:       VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512
+PATTERN:    EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  mode64 W0    ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_GPR_READER()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:d:u32
 IFORM:       VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512
 }
@@ -30841,7 +32769,7 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR
-PATTERN:    EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1  mode64    ZEROING=0 MASK=0
+PATTERN:    EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  mode64  W1    ZEROING=0 MASK=0
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR64_B():r:q:u64
 IFORM:       VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512
 }
@@ -30855,7 +32783,7 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR
-PATTERN:    EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1  mode64    ZEROING=0 MASK=0
+PATTERN:    EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  mode64  W1    ZEROING=0 MASK=0
 OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR64_B():r:q:u64
 IFORM:       VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512
 }
@@ -30869,7 +32797,7 @@ ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MXCSR SIMD_SCALAR DISP8_GPR_READER
-PATTERN:    EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1  mode64    ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_GPR_READER()
+PATTERN:    EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  mode64  W1    ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_GPR_READER()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:q:u64
 IFORM:       VCVTUSI2SS_XMMf32_XMMf32_MEMu64_AVX512
 }
@@ -30884,7 +32812,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1
 OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
 IFORM:       VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
@@ -30898,7 +32826,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5E V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1
 OPERANDS:    REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
 IFORM:       VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
@@ -30912,7 +32840,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x5E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VDIVPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
@@ -30928,7 +32856,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5E VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0
 OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
 IFORM:       VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
@@ -30942,7 +32870,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5E VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0
 OPERANDS:    REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
 IFORM:       VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
@@ -30956,7 +32884,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x5E VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VDIVPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
@@ -30972,7 +32900,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x5E VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -30986,7 +32914,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x5E VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1
 OPERANDS:    REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -31000,7 +32928,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0x5E VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ESIZE_64_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
 IFORM:       VDIVSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
@@ -31016,7 +32944,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x5E VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -31030,7 +32958,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x5E VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0
 OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -31044,7 +32972,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0x5E VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ESIZE_32_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
 IFORM:       VDIVSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
@@ -31060,7 +32988,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
 PATTERN:    EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W1  NOEVSR  ESIZE_64_BITS() NELEM_GSCAT()
 OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f64
 IFORM:       VEXPANDPD_ZMMf64_MASKmskw_MEMf64_AVX512
@@ -31092,7 +33020,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
 PATTERN:    EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_GSCAT()
 OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f32
 IFORM:       VEXPANDPS_ZMMf32_MASKmskw_MEMf32_AVX512
@@ -31281,7 +33209,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   UIMM8()
 OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b
 IFORM:       VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512
@@ -31295,7 +33223,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W1   UIMM8()
 OPERANDS:    REG0=ZMM_R3():rw:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b
 IFORM:       VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512
@@ -31309,7 +33237,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1   UIMM8()  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
 IFORM:       VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512
@@ -31325,7 +33253,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   UIMM8()
 OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b
 IFORM:       VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512
@@ -31339,7 +33267,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W0   UIMM8()
 OPERANDS:    REG0=ZMM_R3():rw:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b
 IFORM:       VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512
@@ -31353,7 +33281,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0   UIMM8()  ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
 IFORM:       VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512
@@ -31369,7 +33297,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x55 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1   UIMM8()
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
 IFORM:       VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
@@ -31383,7 +33311,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x55 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W1   UIMM8()
 OPERANDS:    REG0=XMM_R3():rw:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
 IFORM:       VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
@@ -31397,7 +33325,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0x55 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1   UIMM8()  ESIZE_64_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b
 IFORM:       VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512
@@ -31413,7 +33341,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x55 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0   UIMM8()
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
 IFORM:       VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
@@ -31427,7 +33355,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x55 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W0   UIMM8()
 OPERANDS:    REG0=XMM_R3():rw:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
 IFORM:       VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
@@ -31441,7 +33369,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0x55 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0   UIMM8()  ESIZE_32_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b
 IFORM:       VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512
@@ -31457,7 +33385,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1
 OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
 IFORM:       VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
@@ -31471,7 +33399,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1
 OPERANDS:    REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
 IFORM:       VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
@@ -31485,7 +33413,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
@@ -31501,7 +33429,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0
 OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
 IFORM:       VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
@@ -31515,7 +33443,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0
 OPERANDS:    REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
 IFORM:       VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
@@ -31529,7 +33457,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
@@ -31545,7 +33473,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x99 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -31559,7 +33487,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x99 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1
 OPERANDS:    REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -31573,7 +33501,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0x99 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ESIZE_64_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
 IFORM:       VFMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
@@ -31589,7 +33517,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x99 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -31603,7 +33531,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x99 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0
 OPERANDS:    REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -31617,7 +33545,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0x99 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ESIZE_32_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
 IFORM:       VFMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
@@ -31633,7 +33561,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1
 OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
 IFORM:       VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
@@ -31647,7 +33575,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1
 OPERANDS:    REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
 IFORM:       VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
@@ -31661,7 +33589,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
@@ -31677,7 +33605,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0
 OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
 IFORM:       VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
@@ -31691,7 +33619,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0
 OPERANDS:    REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
 IFORM:       VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
@@ -31705,7 +33633,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
@@ -31721,7 +33649,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0xA9 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -31735,7 +33663,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0xA9 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1
 OPERANDS:    REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -31749,7 +33677,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0xA9 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ESIZE_64_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
 IFORM:       VFMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
@@ -31765,7 +33693,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0xA9 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -31779,7 +33707,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0xA9 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0
 OPERANDS:    REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -31793,7 +33721,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0xA9 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ESIZE_32_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
 IFORM:       VFMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
@@ -31809,7 +33737,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1
 OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
 IFORM:       VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
@@ -31823,7 +33751,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1
 OPERANDS:    REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
 IFORM:       VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
@@ -31837,7 +33765,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
@@ -31853,7 +33781,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0
 OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
 IFORM:       VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
@@ -31867,7 +33795,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0
 OPERANDS:    REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
 IFORM:       VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
@@ -31881,7 +33809,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
@@ -31897,7 +33825,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0xB9 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -31911,7 +33839,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0xB9 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1
 OPERANDS:    REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -31925,7 +33853,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0xB9 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ESIZE_64_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
 IFORM:       VFMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
@@ -31941,7 +33869,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0xB9 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -31955,7 +33883,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0xB9 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0
 OPERANDS:    REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -31969,7 +33897,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0xB9 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ESIZE_32_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
 IFORM:       VFMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
@@ -31985,7 +33913,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1
 OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
 IFORM:       VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
@@ -31999,7 +33927,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1
 OPERANDS:    REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
 IFORM:       VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
@@ -32013,7 +33941,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
@@ -32029,7 +33957,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0
 OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
 IFORM:       VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
@@ -32043,7 +33971,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0
 OPERANDS:    REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
 IFORM:       VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
@@ -32057,7 +33985,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
@@ -32073,7 +34001,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1
 OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
 IFORM:       VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
@@ -32087,7 +34015,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1
 OPERANDS:    REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
 IFORM:       VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
@@ -32101,7 +34029,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
@@ -32117,7 +34045,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0
 OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
 IFORM:       VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
@@ -32131,7 +34059,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0
 OPERANDS:    REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
 IFORM:       VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
@@ -32145,7 +34073,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
@@ -32161,7 +34089,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1
 OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
 IFORM:       VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
@@ -32175,7 +34103,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1
 OPERANDS:    REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
 IFORM:       VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
@@ -32189,7 +34117,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
@@ -32205,7 +34133,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0
 OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
 IFORM:       VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
@@ -32219,7 +34147,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0
 OPERANDS:    REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
 IFORM:       VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
@@ -32233,7 +34161,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
@@ -32249,7 +34177,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1
 OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
 IFORM:       VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
@@ -32263,7 +34191,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1
 OPERANDS:    REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
 IFORM:       VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
@@ -32277,7 +34205,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
@@ -32293,7 +34221,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0
 OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
 IFORM:       VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
@@ -32307,7 +34235,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0
 OPERANDS:    REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
 IFORM:       VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
@@ -32321,7 +34249,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
@@ -32337,7 +34265,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x9B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -32351,7 +34279,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x9B V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1
 OPERANDS:    REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -32365,7 +34293,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0x9B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ESIZE_64_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
 IFORM:       VFMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
@@ -32381,7 +34309,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x9B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -32395,7 +34323,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x9B V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0
 OPERANDS:    REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -32409,7 +34337,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0x9B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ESIZE_32_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
 IFORM:       VFMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
@@ -32425,7 +34353,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1
 OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
 IFORM:       VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
@@ -32439,7 +34367,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1
 OPERANDS:    REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
 IFORM:       VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
@@ -32453,7 +34381,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
@@ -32469,7 +34397,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0
 OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
 IFORM:       VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
@@ -32483,7 +34411,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0
 OPERANDS:    REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
 IFORM:       VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
@@ -32497,7 +34425,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
@@ -32513,7 +34441,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0xAB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -32527,7 +34455,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0xAB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1
 OPERANDS:    REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -32541,7 +34469,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0xAB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ESIZE_64_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
 IFORM:       VFMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
@@ -32557,7 +34485,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0xAB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -32571,7 +34499,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0xAB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0
 OPERANDS:    REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -32585,7 +34513,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0xAB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ESIZE_32_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
 IFORM:       VFMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
@@ -32601,7 +34529,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1
 OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
 IFORM:       VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
@@ -32615,7 +34543,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1
 OPERANDS:    REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
 IFORM:       VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
@@ -32629,7 +34557,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
@@ -32645,7 +34573,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0
 OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
 IFORM:       VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
@@ -32659,7 +34587,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0
 OPERANDS:    REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
 IFORM:       VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
@@ -32673,7 +34601,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
@@ -32689,7 +34617,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0xBB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -32703,7 +34631,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0xBB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1
 OPERANDS:    REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -32717,7 +34645,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0xBB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ESIZE_64_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
 IFORM:       VFMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
@@ -32733,7 +34661,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0xBB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -32747,7 +34675,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0xBB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0
 OPERANDS:    REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -32761,7 +34689,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0xBB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ESIZE_32_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
 IFORM:       VFMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
@@ -32777,7 +34705,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1
 OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
 IFORM:       VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
@@ -32791,7 +34719,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1
 OPERANDS:    REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
 IFORM:       VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
@@ -32805,7 +34733,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
@@ -32821,7 +34749,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0
 OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
 IFORM:       VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
@@ -32835,7 +34763,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0
 OPERANDS:    REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
 IFORM:       VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
@@ -32849,7 +34777,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
@@ -32865,7 +34793,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1
 OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
 IFORM:       VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
@@ -32879,7 +34807,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1
 OPERANDS:    REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
 IFORM:       VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
@@ -32893,7 +34821,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
@@ -32909,7 +34837,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0
 OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
 IFORM:       VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
@@ -32923,7 +34851,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0
 OPERANDS:    REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
 IFORM:       VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
@@ -32937,7 +34865,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
@@ -32953,7 +34881,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1
 OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
 IFORM:       VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
@@ -32967,7 +34895,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1
 OPERANDS:    REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
 IFORM:       VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
@@ -32981,7 +34909,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
@@ -32997,7 +34925,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0
 OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
 IFORM:       VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
@@ -33011,7 +34939,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0
 OPERANDS:    REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
 IFORM:       VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
@@ -33025,7 +34953,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
@@ -33041,7 +34969,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1
 OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
 IFORM:       VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
@@ -33055,7 +34983,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1
 OPERANDS:    REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
 IFORM:       VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
@@ -33069,7 +34997,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
@@ -33085,7 +35013,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0
 OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
 IFORM:       VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
@@ -33099,7 +35027,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0
 OPERANDS:    REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
 IFORM:       VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
@@ -33113,7 +35041,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
@@ -33129,7 +35057,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x9D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -33143,7 +35071,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x9D V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1
 OPERANDS:    REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -33157,7 +35085,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0x9D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ESIZE_64_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
 IFORM:       VFNMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
@@ -33173,7 +35101,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x9D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -33187,7 +35115,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x9D V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0
 OPERANDS:    REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -33201,7 +35129,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0x9D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ESIZE_32_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
 IFORM:       VFNMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
@@ -33217,7 +35145,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1
 OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
 IFORM:       VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
@@ -33231,7 +35159,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1
 OPERANDS:    REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
 IFORM:       VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
@@ -33245,7 +35173,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
@@ -33261,7 +35189,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0
 OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
 IFORM:       VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
@@ -33275,7 +35203,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0
 OPERANDS:    REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
 IFORM:       VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
@@ -33289,7 +35217,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
@@ -33305,7 +35233,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0xAD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -33319,7 +35247,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0xAD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1
 OPERANDS:    REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -33333,7 +35261,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0xAD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ESIZE_64_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
 IFORM:       VFNMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
@@ -33349,7 +35277,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0xAD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -33363,7 +35291,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0xAD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0
 OPERANDS:    REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -33377,7 +35305,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0xAD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ESIZE_32_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
 IFORM:       VFNMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
@@ -33393,7 +35321,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1
 OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
 IFORM:       VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
@@ -33407,7 +35335,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1
 OPERANDS:    REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
 IFORM:       VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
@@ -33421,7 +35349,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
@@ -33437,7 +35365,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0
 OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
 IFORM:       VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
@@ -33451,7 +35379,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0
 OPERANDS:    REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
 IFORM:       VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
@@ -33465,7 +35393,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
@@ -33481,7 +35409,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0xBD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -33495,7 +35423,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0xBD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1
 OPERANDS:    REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -33509,7 +35437,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0xBD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ESIZE_64_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
 IFORM:       VFNMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
@@ -33525,7 +35453,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0xBD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -33539,7 +35467,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0xBD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0
 OPERANDS:    REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -33553,7 +35481,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0xBD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ESIZE_32_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
 IFORM:       VFNMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
@@ -33569,7 +35497,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1
 OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
 IFORM:       VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
@@ -33583,7 +35511,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1
 OPERANDS:    REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
 IFORM:       VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
@@ -33597,7 +35525,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
@@ -33613,7 +35541,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0
 OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
 IFORM:       VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
@@ -33627,7 +35555,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0
 OPERANDS:    REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
 IFORM:       VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
@@ -33641,7 +35569,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
@@ -33657,7 +35585,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x9F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -33671,7 +35599,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x9F V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1
 OPERANDS:    REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -33685,7 +35613,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0x9F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ESIZE_64_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
 IFORM:       VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
@@ -33701,7 +35629,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x9F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -33715,7 +35643,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x9F V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0
 OPERANDS:    REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -33729,7 +35657,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0x9F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ESIZE_32_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
 IFORM:       VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
@@ -33745,7 +35673,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1
 OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
 IFORM:       VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
@@ -33759,7 +35687,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1
 OPERANDS:    REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
 IFORM:       VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
@@ -33773,7 +35701,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
@@ -33789,7 +35717,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0
 OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
 IFORM:       VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
@@ -33803,7 +35731,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0
 OPERANDS:    REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
 IFORM:       VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
@@ -33817,7 +35745,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
@@ -33833,7 +35761,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0xAF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -33847,7 +35775,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0xAF V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1
 OPERANDS:    REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -33861,7 +35789,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0xAF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ESIZE_64_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
 IFORM:       VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
@@ -33877,7 +35805,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0xAF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -33891,7 +35819,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0xAF V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0
 OPERANDS:    REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -33905,7 +35833,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0xAF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ESIZE_32_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
 IFORM:       VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
@@ -33921,7 +35849,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1
 OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
 IFORM:       VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
@@ -33935,7 +35863,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1
 OPERANDS:    REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
 IFORM:       VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
@@ -33949,7 +35877,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
@@ -33965,7 +35893,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0
 OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
 IFORM:       VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
@@ -33979,7 +35907,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0
 OPERANDS:    REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
 IFORM:       VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
@@ -33993,7 +35921,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
@@ -34009,7 +35937,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0xBF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -34023,7 +35951,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0xBF V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1
 OPERANDS:    REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -34037,7 +35965,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0xBF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ESIZE_64_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
 IFORM:       VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
@@ -34053,7 +35981,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0xBF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -34067,7 +35995,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0xBF V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0
 OPERANDS:    REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -34081,7 +36009,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0xBF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ESIZE_32_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
 IFORM:       VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
@@ -34097,9 +36025,9 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E12
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT
-PATTERN:    EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL512  W1 RM=4 UISA_VMODRM_YMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
-OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASKNOT0():rw:mskw MEM0:r:zd:f64
+ATTRIBUTES:  DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED
+PATTERN:    EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0   VL512  W1 UISA_VMODRM_YMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
+OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASKNOT0():rw:mskw MEM0:r:q:f64
 IFORM:       VGATHERDPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512
 }
 
@@ -34113,9 +36041,9 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E12
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT
-PATTERN:    EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL512  W0 RM=4 UISA_VMODRM_ZMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
-OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASKNOT0():rw:mskw MEM0:r:zd:f32
+ATTRIBUTES:  DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED
+PATTERN:    EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0   VL512  W0 UISA_VMODRM_ZMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
+OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASKNOT0():rw:mskw MEM0:r:d:f32
 IFORM:       VGATHERDPS_ZMMf32_MASKmskw_MEMf32_AVX512_VL512
 }
 
@@ -34129,9 +36057,9 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E12
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT
-PATTERN:    EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL512  W1 RM=4 UISA_VMODRM_ZMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
-OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASKNOT0():rw:mskw MEM0:r:zd:f64
+ATTRIBUTES:  GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED
+PATTERN:    EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0   VL512  W1 UISA_VMODRM_ZMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
+OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASKNOT0():rw:mskw MEM0:r:q:f64
 IFORM:       VGATHERQPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512
 }
 
@@ -34145,9 +36073,9 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E12
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT
-PATTERN:    EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL512  W0 RM=4 UISA_VMODRM_ZMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
-OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASKNOT0():rw:mskw MEM0:r:qq:f32
+ATTRIBUTES:  GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED
+PATTERN:    EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0   VL512  W0 UISA_VMODRM_ZMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
+OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASKNOT0():rw:mskw MEM0:r:d:f32
 IFORM:       VGATHERQPS_YMMf32_MASKmskw_MEMf32_AVX512_VL512
 }
 
@@ -34161,7 +36089,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR
 OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
 IFORM:       VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512
@@ -34175,7 +36103,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W1  NOEVSR
 OPERANDS:    REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
 IFORM:       VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512
@@ -34189,7 +36117,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VGETEXPPD_ZMMf64_MASKmskw_MEMf64_AVX512
@@ -34205,7 +36133,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR
 OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
 IFORM:       VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512
@@ -34219,7 +36147,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W0  NOEVSR
 OPERANDS:    REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
 IFORM:       VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512
@@ -34233,7 +36161,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VGETEXPPS_ZMMf32_MASKmskw_MEMf32_AVX512
@@ -34249,7 +36177,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x43 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -34263,7 +36191,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x43 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W1
 OPERANDS:    REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -34277,7 +36205,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0x43 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ESIZE_64_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
 IFORM:       VGETEXPSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
@@ -34293,7 +36221,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x43 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -34307,7 +36235,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x43 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W0
 OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -34321,7 +36249,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0x43 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ESIZE_32_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
 IFORM:       VGETEXPSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
@@ -34337,7 +36265,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR UIMM8()
 OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b
 IFORM:       VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512
@@ -34351,7 +36279,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W1  NOEVSR UIMM8()
 OPERANDS:    REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b
 IFORM:       VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512
@@ -34365,7 +36293,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1  NOEVSR UIMM8()  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
 IFORM:       VGETMANTPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512
@@ -34381,7 +36309,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR UIMM8()
 OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b
 IFORM:       VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512
@@ -34395,7 +36323,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W0  NOEVSR UIMM8()
 OPERANDS:    REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b
 IFORM:       VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512
@@ -34409,7 +36337,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR UIMM8()  ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
 IFORM:       VGETMANTPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512
@@ -34425,7 +36353,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x27 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1   UIMM8()
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
 IFORM:       VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
@@ -34439,7 +36367,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x27 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W1   UIMM8()
 OPERANDS:    REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
 IFORM:       VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
@@ -34453,7 +36381,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0x27 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1   UIMM8()  ESIZE_64_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b
 IFORM:       VGETMANTSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512
@@ -34469,7 +36397,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x27 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0   UIMM8()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
 IFORM:       VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
@@ -34483,7 +36411,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x27 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W0   UIMM8()
 OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
 IFORM:       VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
@@ -34497,7 +36425,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0x27 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0   UIMM8()  ESIZE_32_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b
 IFORM:       VGETMANTSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512
@@ -34662,7 +36590,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1
 OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
 IFORM:       VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
@@ -34676,7 +36604,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5F V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W1
 OPERANDS:    REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
 IFORM:       VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
@@ -34690,7 +36618,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x5F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
@@ -34706,7 +36634,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5F VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0
 OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
 IFORM:       VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
@@ -34720,7 +36648,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5F VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W0
 OPERANDS:    REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
 IFORM:       VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
@@ -34734,7 +36662,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x5F VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
@@ -34750,7 +36678,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x5F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -34764,7 +36692,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x5F VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W1
 OPERANDS:    REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -34778,7 +36706,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0x5F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ESIZE_64_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
 IFORM:       VMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
@@ -34794,7 +36722,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x5F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -34808,7 +36736,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x5F VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W0
 OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -34822,7 +36750,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0x5F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ESIZE_32_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
 IFORM:       VMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
@@ -34838,7 +36766,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1
 OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
 IFORM:       VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
@@ -34852,7 +36780,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5D V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W1
 OPERANDS:    REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
 IFORM:       VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
@@ -34866,7 +36794,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x5D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VMINPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
@@ -34882,7 +36810,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5D VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0
 OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
 IFORM:       VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
@@ -34896,7 +36824,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5D VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W0
 OPERANDS:    REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
 IFORM:       VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
@@ -34910,7 +36838,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x5D VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VMINPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
@@ -34926,7 +36854,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x5D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -34940,7 +36868,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x5D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W1
 OPERANDS:    REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -34954,7 +36882,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0x5D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ESIZE_64_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
 IFORM:       VMINSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
@@ -34970,7 +36898,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x5D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -34984,7 +36912,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x5D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W0
 OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -34998,7 +36926,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0x5D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ESIZE_32_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
 IFORM:       VMINSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
@@ -35028,7 +36956,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E1
 REAL_OPCODE: Y
-ATTRIBUTES:   REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM
 PATTERN:    EVV 0x28 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULLMEM()
 OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f64
 IFORM:       VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512
@@ -35060,7 +36988,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E1
 REAL_OPCODE: Y
-ATTRIBUTES:   REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM
 PATTERN:    EVV 0x29 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W1  NOEVSR  ZEROING=0  ESIZE_64_BITS() NELEM_FULLMEM()
 OPERANDS:    MEM0:w:zd:f64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf64
 IFORM:       VMOVAPD_MEMf64_MASKmskw_ZMMf64_AVX512
@@ -35090,7 +37018,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E1
 REAL_OPCODE: Y
-ATTRIBUTES:   REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM
 PATTERN:    EVV 0x28 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULLMEM()
 OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f32
 IFORM:       VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512
@@ -35122,7 +37050,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E1
 REAL_OPCODE: Y
-ATTRIBUTES:   REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM
 PATTERN:    EVV 0x29 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ZEROING=0  ESIZE_32_BITS() NELEM_FULLMEM()
 OPERANDS:    MEM0:w:zd:f32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32
 IFORM:       VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512
@@ -35138,7 +37066,10 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128N
 EXCEPTIONS:     AVX512-E9NF
 REAL_OPCODE: Y
-PATTERN:    EVV 0x6E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0  NOEVSR  ZEROING=0 MASK=0
+PATTERN:    EVV 0x6E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  not64  NOEVSR  ZEROING=0 MASK=0
+OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=GPR32_B():r:d:u32
+IFORM:       VMOVD_XMMu32_GPR32u32_AVX512
+PATTERN:    EVV 0x6E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  mode64 W0  NOEVSR  ZEROING=0 MASK=0
 OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=GPR32_B():r:d:u32
 IFORM:       VMOVD_XMMu32_GPR32u32_AVX512
 }
@@ -35152,7 +37083,10 @@ ISA_SET:     AVX512F_128N
 EXCEPTIONS:     AVX512-E9NF
 REAL_OPCODE: Y
 ATTRIBUTES:  DISP8_GPR_READER
-PATTERN:    EVV 0x6E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0  NOEVSR  ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_GPR_READER()
+PATTERN:    EVV 0x6E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  not64  NOEVSR  ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_GPR_READER()
+OPERANDS:    REG0=XMM_R3():w:dq:u32 MEM0:r:d:u32
+IFORM:       VMOVD_XMMu32_MEMu32_AVX512
+PATTERN:    EVV 0x6E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  mode64 W0  NOEVSR  ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_GPR_READER()
 OPERANDS:    REG0=XMM_R3():w:dq:u32 MEM0:r:d:u32
 IFORM:       VMOVD_XMMu32_MEMu32_AVX512
 }
@@ -35167,7 +37101,10 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128N
 EXCEPTIONS:     AVX512-E9NF
 REAL_OPCODE: Y
-PATTERN:    EVV 0x7E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0  NOEVSR  ZEROING=0 MASK=0
+PATTERN:    EVV 0x7E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  not64  NOEVSR  ZEROING=0 MASK=0
+OPERANDS:    REG0=GPR32_B():w:d:u32 REG1=XMM_R3():r:dq:u32
+IFORM:       VMOVD_GPR32u32_XMMu32_AVX512
+PATTERN:    EVV 0x7E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  mode64 W0  NOEVSR  ZEROING=0 MASK=0
 OPERANDS:    REG0=GPR32_B():w:d:u32 REG1=XMM_R3():r:dq:u32
 IFORM:       VMOVD_GPR32u32_XMMu32_AVX512
 }
@@ -35181,7 +37118,10 @@ ISA_SET:     AVX512F_128N
 EXCEPTIONS:     AVX512-E9NF
 REAL_OPCODE: Y
 ATTRIBUTES:  DISP8_GPR_WRITER_STORE
-PATTERN:    EVV 0x7E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0  NOEVSR  ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_GPR_WRITER_STORE()
+PATTERN:    EVV 0x7E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  not64  NOEVSR  ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_GPR_WRITER_STORE()
+OPERANDS:    MEM0:w:d:u32 REG0=XMM_R3():r:dq:u32
+IFORM:       VMOVD_MEMu32_XMMu32_AVX512
+PATTERN:    EVV 0x7E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  mode64 W0  NOEVSR  ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_GPR_WRITER_STORE()
 OPERANDS:    MEM0:w:d:u32 REG0=XMM_R3():r:dq:u32
 IFORM:       VMOVD_MEMu32_XMMu32_AVX512
 }
@@ -35240,7 +37180,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E1
 REAL_OPCODE: Y
-ATTRIBUTES:   REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM
 PATTERN:    EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULLMEM()
 OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u32
 IFORM:       VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512
@@ -35272,7 +37212,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E1
 REAL_OPCODE: Y
-ATTRIBUTES:   REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM
 PATTERN:    EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ZEROING=0  ESIZE_32_BITS() NELEM_FULLMEM()
 OPERANDS:    MEM0:w:zd:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32
 IFORM:       VMOVDQA32_MEMu32_MASKmskw_ZMMu32_AVX512
@@ -35302,7 +37242,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E1
 REAL_OPCODE: Y
-ATTRIBUTES:   REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM
 PATTERN:    EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULLMEM()
 OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u64
 IFORM:       VMOVDQA64_ZMMu64_MASKmskw_MEMu64_AVX512
@@ -35334,7 +37274,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E1
 REAL_OPCODE: Y
-ATTRIBUTES:   REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM
 PATTERN:    EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W1  NOEVSR  ZEROING=0  ESIZE_64_BITS() NELEM_FULLMEM()
 OPERANDS:    MEM0:w:zd:u64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64
 IFORM:       VMOVDQA64_MEMu64_MASKmskw_ZMMu64_AVX512
@@ -35490,7 +37430,7 @@ ISA_SET:     AVX512F_128N
 EXCEPTIONS:     AVX512-E9NF
 REAL_OPCODE: Y
 ATTRIBUTES:  DISP8_SCALAR
-PATTERN:    EVV 0x16 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_SCALAR()
+PATTERN:    EVV 0x16 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128 W1    ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:q:f64 MEM0:r:q:f64
 IFORM:       VMOVHPD_XMMf64_XMMf64_MEMf64_AVX512
 }
@@ -35506,7 +37446,7 @@ ISA_SET:     AVX512F_128N
 EXCEPTIONS:     AVX512-E9NF
 REAL_OPCODE: Y
 ATTRIBUTES:  DISP8_SCALAR
-PATTERN:    EVV 0x17 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1  NOEVSR  ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_SCALAR()
+PATTERN:    EVV 0x17 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128  W1  NOEVSR  ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_SCALAR()
 OPERANDS:    MEM0:w:q:f64 REG0=XMM_R3():r:dq:f64
 IFORM:       VMOVHPD_MEMf64_XMMf64_AVX512
 }
@@ -35569,7 +37509,7 @@ ISA_SET:     AVX512F_128N
 EXCEPTIONS:     AVX512-E9NF
 REAL_OPCODE: Y
 ATTRIBUTES:  DISP8_SCALAR
-PATTERN:    EVV 0x12 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_SCALAR()
+PATTERN:    EVV 0x12 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128  W1    ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:q:f64
 IFORM:       VMOVLPD_XMMf64_XMMf64_MEMf64_AVX512
 }
@@ -35585,7 +37525,7 @@ ISA_SET:     AVX512F_128N
 EXCEPTIONS:     AVX512-E9NF
 REAL_OPCODE: Y
 ATTRIBUTES:  DISP8_SCALAR
-PATTERN:    EVV 0x13 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1  NOEVSR  ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_SCALAR()
+PATTERN:    EVV 0x13 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1  NOEVSR  ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_SCALAR()
 OPERANDS:    MEM0:w:q:f64 REG0=XMM_R3():r:q:f64
 IFORM:       VMOVLPD_MEMf64_XMMf64_AVX512
 }
@@ -35632,7 +37572,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E1NF
 REAL_OPCODE: Y
-ATTRIBUTES:  NOTSX  REQUIRES_ALIGNMENT DISP8_FULLMEM
+ATTRIBUTES:  NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM
 PATTERN:    EVV 0xE7 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_FULLMEM()
 OPERANDS:    MEM0:w:zd:u32 REG0=ZMM_R3():r:zu32
 IFORM:       VMOVNTDQ_MEMu32_ZMMu32_AVX512
@@ -35648,7 +37588,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E1NF
 REAL_OPCODE: Y
-ATTRIBUTES:  NOTSX  REQUIRES_ALIGNMENT DISP8_FULLMEM
+ATTRIBUTES:  NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM
 PATTERN:    EVV 0x2A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_FULLMEM()
 OPERANDS:    REG0=ZMM_R3():w:zu32 MEM0:r:zd:u32
 IFORM:       VMOVNTDQA_ZMMu32_MEMu32_AVX512
@@ -35664,7 +37604,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E1NF
 REAL_OPCODE: Y
-ATTRIBUTES:  NOTSX  REQUIRES_ALIGNMENT DISP8_FULLMEM
+ATTRIBUTES:  NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM
 PATTERN:    EVV 0x2B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W1  NOEVSR  ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_FULLMEM()
 OPERANDS:    MEM0:w:zd:f64 REG0=ZMM_R3():r:zf64
 IFORM:       VMOVNTPD_MEMf64_ZMMf64_AVX512
@@ -35680,7 +37620,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E1NF
 REAL_OPCODE: Y
-ATTRIBUTES:  NOTSX  REQUIRES_ALIGNMENT DISP8_FULLMEM
+ATTRIBUTES:  NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM
 PATTERN:    EVV 0x2B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_FULLMEM()
 OPERANDS:    MEM0:w:zd:f32 REG0=ZMM_R3():r:zf32
 IFORM:       VMOVNTPS_MEMf32_ZMMf32_AVX512
@@ -35754,7 +37694,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128N
 EXCEPTIONS:     AVX512-E9NF
 REAL_OPCODE: Y
-PATTERN:    EVV 0x7E VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1  NOEVSR  ZEROING=0 MASK=0
+PATTERN:    EVV 0x7E VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1  NOEVSR  ZEROING=0 MASK=0
 OPERANDS:    REG0=XMM_R3():w:dq:u64 REG1=XMM_B3():r:dq:u64
 IFORM:       VMOVQ_XMMu64_XMMu64_AVX512
 }
@@ -35768,7 +37708,7 @@ ISA_SET:     AVX512F_128N
 EXCEPTIONS:     AVX512-E9NF
 REAL_OPCODE: Y
 ATTRIBUTES:  DISP8_SCALAR
-PATTERN:    EVV 0x7E VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1  NOEVSR  ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_SCALAR()
+PATTERN:    EVV 0x7E VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128 W1  NOEVSR  ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():w:dq:u64 MEM0:r:q:u64
 IFORM:       VMOVQ_XMMu64_MEMu64_AVX512
 }
@@ -35783,7 +37723,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128N
 EXCEPTIONS:     AVX512-E9NF
 REAL_OPCODE: Y
-PATTERN:    EVV 0xD6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1  NOEVSR  ZEROING=0 MASK=0
+PATTERN:    EVV 0xD6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128 W1  NOEVSR  ZEROING=0 MASK=0
 OPERANDS:    REG0=XMM_B3():w:dq:u64 REG1=XMM_R3():r:dq:u64
 IFORM:       VMOVQ_XMMu64_XMMu64_AVX512
 }
@@ -35797,7 +37737,7 @@ ISA_SET:     AVX512F_128N
 EXCEPTIONS:     AVX512-E9NF
 REAL_OPCODE: Y
 ATTRIBUTES:  DISP8_SCALAR
-PATTERN:    EVV 0xD6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1  NOEVSR  ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_SCALAR()
+PATTERN:    EVV 0xD6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128 W1  NOEVSR  ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_SCALAR()
 OPERANDS:    MEM0:w:q:u64 REG0=XMM_R3():r:dq:u64
 IFORM:       VMOVQ_MEMu64_XMMu64_AVX512
 }
@@ -35812,7 +37752,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E5
 REAL_OPCODE: Y
-ATTRIBUTES:  SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0x10 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1  NOEVSR  ESIZE_64_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f64
 IFORM:       VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512
@@ -35828,7 +37768,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E5
 REAL_OPCODE: Y
-ATTRIBUTES:  SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0x11 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1  NOEVSR  ZEROING=0  ESIZE_64_BITS() NELEM_SCALAR()
 OPERANDS:    MEM0:w:q:f64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f64
 IFORM:       VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512
@@ -35844,7 +37784,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E5
 REAL_OPCODE: Y
-ATTRIBUTES:  SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX SIMD_SCALAR
 PATTERN:    EVV 0x10 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -35860,7 +37800,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E5
 REAL_OPCODE: Y
-ATTRIBUTES:  SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX SIMD_SCALAR
 PATTERN:    EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1
 OPERANDS:    REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_R3():r:dq:f64
 IFORM:       VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -35936,7 +37876,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E5
 REAL_OPCODE: Y
-ATTRIBUTES:  SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0x10 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0  NOEVSR  ESIZE_32_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:f32
 IFORM:       VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512
@@ -35952,7 +37892,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E5
 REAL_OPCODE: Y
-ATTRIBUTES:  SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0x11 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0  NOEVSR  ZEROING=0  ESIZE_32_BITS() NELEM_SCALAR()
 OPERANDS:    MEM0:w:d:f32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f32
 IFORM:       VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512
@@ -35968,7 +37908,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E5
 REAL_OPCODE: Y
-ATTRIBUTES:  SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX SIMD_SCALAR
 PATTERN:    EVV 0x10 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -35984,7 +37924,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E5
 REAL_OPCODE: Y
-ATTRIBUTES:  SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX SIMD_SCALAR
 PATTERN:    EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0
 OPERANDS:    REG0=XMM_B3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_R3():r:dq:f32
 IFORM:       VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -36124,7 +38064,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x59 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1
 OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
 IFORM:       VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
@@ -36138,7 +38078,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x59 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1
 OPERANDS:    REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
 IFORM:       VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
@@ -36152,7 +38092,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x59 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VMULPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
@@ -36168,7 +38108,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x59 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0
 OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
 IFORM:       VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
@@ -36182,7 +38122,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x59 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0
 OPERANDS:    REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
 IFORM:       VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
@@ -36196,7 +38136,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x59 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VMULPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
@@ -36212,7 +38152,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x59 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -36226,7 +38166,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x59 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1
 OPERANDS:    REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -36240,7 +38180,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0x59 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ESIZE_64_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
 IFORM:       VMULSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
@@ -36256,7 +38196,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x59 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -36270,7 +38210,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x59 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0
 OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -36284,7 +38224,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0x59 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ESIZE_32_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
 IFORM:       VMULSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
@@ -36554,7 +38494,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL
 PATTERN:    EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
 IFORM:       VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
@@ -36584,7 +38524,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL
 PATTERN:    EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
 IFORM:       VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
@@ -36633,7 +38573,10 @@ ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E7NM
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX
-PATTERN:    EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR
+PATTERN:    EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  not64  NOEVSR
+OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO16_32
+IFORM:       VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512
+PATTERN:    EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  mode64 W0  NOEVSR
 OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO16_32
 IFORM:       VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512
 }
@@ -36681,7 +38624,7 @@ ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E7NM
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX
-PATTERN:    EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  mode64  NOEVSR
+PATTERN:    EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  mode64  W1  NOEVSR
 OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR64_B():r:q:u64 EMX_BROADCAST_1TO8_64
 IFORM:       VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512
 }
@@ -36936,7 +38879,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
 PATTERN:    EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
 OPERANDS:    MEM0:w:zd:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32
 IFORM:       VPCOMPRESSD_MEMu32_MASKmskw_ZMMu32_AVX512
@@ -36968,7 +38911,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
 PATTERN:    EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W1  NOEVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
 OPERANDS:    MEM0:w:zd:u64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64
 IFORM:       VPCOMPRESSQ_MEMu64_MASKmskw_ZMMu64_AVX512
@@ -37540,7 +39483,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
 PATTERN:    EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_GSCAT()
 OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u32
 IFORM:       VPEXPANDD_ZMMu32_MASKmskw_MEMu32_AVX512
@@ -37572,7 +39515,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
 PATTERN:    EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W1  NOEVSR  ESIZE_64_BITS() NELEM_GSCAT()
 OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u64
 IFORM:       VPEXPANDQ_ZMMu64_MASKmskw_MEMu64_AVX512
@@ -37604,9 +39547,9 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E12
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT
-PATTERN:    EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL512  W0 RM=4 UISA_VMODRM_ZMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
-OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASKNOT0():rw:mskw MEM0:r:zd:u32
+ATTRIBUTES:  DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED
+PATTERN:    EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0   VL512  W0 UISA_VMODRM_ZMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
+OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASKNOT0():rw:mskw MEM0:r:d:u32
 IFORM:       VPGATHERDD_ZMMu32_MASKmskw_MEMu32_AVX512_VL512
 }
 
@@ -37620,9 +39563,9 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E12
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT
-PATTERN:    EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL512  W1 RM=4 UISA_VMODRM_YMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
-OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASKNOT0():rw:mskw MEM0:r:zd:u64
+ATTRIBUTES:  DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED
+PATTERN:    EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0   VL512  W1 UISA_VMODRM_YMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
+OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASKNOT0():rw:mskw MEM0:r:q:u64
 IFORM:       VPGATHERDQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512
 }
 
@@ -37636,9 +39579,9 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E12
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT
-PATTERN:    EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL512  W0 RM=4 UISA_VMODRM_ZMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
-OPERANDS:    REG0=YMM_R3():w:qq:u32 REG1=MASKNOT0():rw:mskw MEM0:r:qq:u32
+ATTRIBUTES:  GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED
+PATTERN:    EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0   VL512  W0 UISA_VMODRM_ZMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
+OPERANDS:    REG0=YMM_R3():w:qq:u32 REG1=MASKNOT0():rw:mskw MEM0:r:d:u32
 IFORM:       VPGATHERQD_YMMu32_MASKmskw_MEMu32_AVX512_VL512
 }
 
@@ -37652,9 +39595,9 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E12
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT
-PATTERN:    EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL512  W1 RM=4 UISA_VMODRM_ZMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
-OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASKNOT0():rw:mskw MEM0:r:zd:u64
+ATTRIBUTES:  GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED
+PATTERN:    EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0   VL512  W1 UISA_VMODRM_ZMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
+OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASKNOT0():rw:mskw MEM0:r:q:u64
 IFORM:       VPGATHERQQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512
 }
 
@@ -37922,7 +39865,7 @@ CPL:         3
 CATEGORY:    DATAXFER
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
-EXCEPTIONS:     AVX512-E6NF
+EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
 PATTERN:    EVV 0x31 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ZEROING=0  ESIZE_8_BITS() NELEM_QUARTERMEM()
@@ -37954,7 +39897,7 @@ CPL:         3
 CATEGORY:    DATAXFER
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
-EXCEPTIONS:     AVX512-E6NF
+EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
 PATTERN:    EVV 0x33 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ZEROING=0  ESIZE_16_BITS() NELEM_HALFMEM()
@@ -37986,7 +39929,7 @@ CPL:         3
 CATEGORY:    DATAXFER
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
-EXCEPTIONS:     AVX512-E6NF
+EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM
 PATTERN:    EVV 0x32 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ZEROING=0  ESIZE_8_BITS() NELEM_EIGHTHMEM()
@@ -38018,7 +39961,7 @@ CPL:         3
 CATEGORY:    DATAXFER
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
-EXCEPTIONS:     AVX512-E6NF
+EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
 PATTERN:    EVV 0x35 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ZEROING=0  ESIZE_32_BITS() NELEM_HALFMEM()
@@ -38050,7 +39993,7 @@ CPL:         3
 CATEGORY:    DATAXFER
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
-EXCEPTIONS:     AVX512-E6NF
+EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
 PATTERN:    EVV 0x34 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ZEROING=0  ESIZE_16_BITS() NELEM_QUARTERMEM()
@@ -38082,7 +40025,7 @@ CPL:         3
 CATEGORY:    DATAXFER
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
-EXCEPTIONS:     AVX512-E6NF
+EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
 PATTERN:    EVV 0x21 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ZEROING=0  ESIZE_8_BITS() NELEM_QUARTERMEM()
@@ -38114,7 +40057,7 @@ CPL:         3
 CATEGORY:    DATAXFER
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
-EXCEPTIONS:     AVX512-E6NF
+EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
 PATTERN:    EVV 0x23 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ZEROING=0  ESIZE_16_BITS() NELEM_HALFMEM()
@@ -38146,7 +40089,7 @@ CPL:         3
 CATEGORY:    DATAXFER
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
-EXCEPTIONS:     AVX512-E6NF
+EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM
 PATTERN:    EVV 0x22 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ZEROING=0  ESIZE_8_BITS() NELEM_EIGHTHMEM()
@@ -38178,7 +40121,7 @@ CPL:         3
 CATEGORY:    DATAXFER
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
-EXCEPTIONS:     AVX512-E6NF
+EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
 PATTERN:    EVV 0x25 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ZEROING=0  ESIZE_32_BITS() NELEM_HALFMEM()
@@ -38210,7 +40153,7 @@ CPL:         3
 CATEGORY:    DATAXFER
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
-EXCEPTIONS:     AVX512-E6NF
+EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
 PATTERN:    EVV 0x24 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ZEROING=0  ESIZE_16_BITS() NELEM_QUARTERMEM()
@@ -38392,7 +40335,7 @@ CPL:         3
 CATEGORY:    DATAXFER
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
-EXCEPTIONS:     AVX512-E6NF
+EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
 PATTERN:    EVV 0x11 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ZEROING=0  ESIZE_8_BITS() NELEM_QUARTERMEM()
@@ -38424,7 +40367,7 @@ CPL:         3
 CATEGORY:    DATAXFER
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
-EXCEPTIONS:     AVX512-E6NF
+EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
 PATTERN:    EVV 0x13 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ZEROING=0  ESIZE_16_BITS() NELEM_HALFMEM()
@@ -38456,7 +40399,7 @@ CPL:         3
 CATEGORY:    DATAXFER
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
-EXCEPTIONS:     AVX512-E6NF
+EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM
 PATTERN:    EVV 0x12 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ZEROING=0  ESIZE_8_BITS() NELEM_EIGHTHMEM()
@@ -38488,7 +40431,7 @@ CPL:         3
 CATEGORY:    DATAXFER
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
-EXCEPTIONS:     AVX512-E6NF
+EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
 PATTERN:    EVV 0x15 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ZEROING=0  ESIZE_32_BITS() NELEM_HALFMEM()
@@ -38520,7 +40463,7 @@ CPL:         3
 CATEGORY:    DATAXFER
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
-EXCEPTIONS:     AVX512-E6NF
+EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
 PATTERN:    EVV 0x14 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ZEROING=0  ESIZE_16_BITS() NELEM_QUARTERMEM()
@@ -38688,9 +40631,10 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
+COMMENT:     Strange instruction that uses 32b of each 64b input element
 ATTRIBUTES:  MASKOP_EVEX
 PATTERN:    EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1
-OPERANDS:    REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 REG3=ZMM_B3():r:zi32
+OPERANDS:    REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi64 REG3=ZMM_B3():r:zi64
 IFORM:       VPMULDQ_ZMMi64_MASKmskw_ZMMi32_ZMMi32_AVX512
 }
 
@@ -38702,9 +40646,10 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+COMMENT:     Strange instruction that uses 32b of each 64b input element
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP DISP8_FULL BROADCAST_ENABLED MASKOP_EVEX
 PATTERN:    EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
-OPERANDS:    REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 MEM0:r:vv:i32:TXT=BCASTSTR
+OPERANDS:    REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi64 MEM0:r:vv:i64:TXT=BCASTSTR
 IFORM:       VPMULDQ_ZMMi64_MASKmskw_ZMMi32_MEMi32_AVX512
 }
 
@@ -38748,9 +40693,10 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
+COMMENT:     Strange instruction that uses 32b of each 64b input element
 ATTRIBUTES:  MASKOP_EVEX
 PATTERN:    EVV 0xF4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1
-OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
+OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
 IFORM:       VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_ZMMu32_AVX512
 }
 
@@ -38762,9 +40708,10 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+COMMENT:     Strange instruction that uses 32b of each 64b input element
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP DISP8_FULL BROADCAST_ENABLED MASKOP_EVEX
 PATTERN:    EVV 0xF4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
-OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
+OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
 IFORM:       VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_MEMu32_AVX512
 }
 
@@ -39078,9 +41025,9 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E12
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT
-PATTERN:    EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL512  W0 RM=4 UISA_VMODRM_ZMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
-OPERANDS:    MEM0:w:zd:u32 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zu32
+ATTRIBUTES:  DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER
+PATTERN:    EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0   VL512  W0 UISA_VMODRM_ZMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
+OPERANDS:    MEM0:w:d:u32 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zu32
 IFORM:       VPSCATTERDD_MEMu32_MASKmskw_ZMMu32_AVX512_VL512
 }
 
@@ -39094,9 +41041,9 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E12
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT
-PATTERN:    EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL512  W1 RM=4 UISA_VMODRM_YMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
-OPERANDS:    MEM0:w:zd:u64 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zu64
+ATTRIBUTES:  DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER
+PATTERN:    EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0   VL512  W1 UISA_VMODRM_YMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
+OPERANDS:    MEM0:w:q:u64 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zu64
 IFORM:       VPSCATTERDQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512
 }
 
@@ -39110,9 +41057,9 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E12
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT
-PATTERN:    EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL512  W0 RM=4 UISA_VMODRM_ZMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
-OPERANDS:    MEM0:w:qq:u32 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:u32
+ATTRIBUTES:  QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER
+PATTERN:    EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0   VL512  W0 UISA_VMODRM_ZMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
+OPERANDS:    MEM0:w:d:u32 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:u32
 IFORM:       VPSCATTERQD_MEMu32_MASKmskw_YMMu32_AVX512_VL512
 }
 
@@ -39126,9 +41073,9 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E12
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT
-PATTERN:    EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL512  W1 RM=4 UISA_VMODRM_ZMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
-OPERANDS:    MEM0:w:zd:u64 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zu64
+ATTRIBUTES:  QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER
+PATTERN:    EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0   VL512  W1 UISA_VMODRM_ZMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
+OPERANDS:    MEM0:w:q:u64 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zu64
 IFORM:       VPSCATTERQQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512
 }
 
@@ -40132,7 +42079,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR
 OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
 IFORM:       VRCP14PD_ZMMf64_MASKmskw_ZMMf64_AVX512
@@ -40146,7 +42093,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VRCP14PD_ZMMf64_MASKmskw_MEMf64_AVX512
@@ -40162,7 +42109,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR
 OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
 IFORM:       VRCP14PS_ZMMf32_MASKmskw_ZMMf32_AVX512
@@ -40176,7 +42123,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VRCP14PS_ZMMf32_MASKmskw_MEMf32_AVX512
@@ -40192,7 +42139,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E10
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x4D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VRCP14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -40206,7 +42153,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E10
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0x4D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ESIZE_64_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
 IFORM:       VRCP14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
@@ -40222,7 +42169,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E10
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x4D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -40236,7 +42183,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E10
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0x4D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ESIZE_32_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
 IFORM:       VRCP14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
@@ -40252,7 +42199,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x09 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR UIMM8()
 OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b
 IFORM:       VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512
@@ -40266,7 +42213,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x09 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W1  NOEVSR UIMM8()
 OPERANDS:    REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b
 IFORM:       VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512
@@ -40280,7 +42227,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x09 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1  NOEVSR UIMM8()  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
 IFORM:       VRNDSCALEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512
@@ -40296,7 +42243,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x08 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR UIMM8()
 OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b
 IFORM:       VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512
@@ -40310,7 +42257,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x08 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W0  NOEVSR UIMM8()
 OPERANDS:    REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b
 IFORM:       VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512
@@ -40324,7 +42271,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x08 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR UIMM8()  ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
 IFORM:       VRNDSCALEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512
@@ -40340,7 +42287,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x0B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1   UIMM8()
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
 IFORM:       VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
@@ -40354,7 +42301,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x0B V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W1   UIMM8()
 OPERANDS:    REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
 IFORM:       VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
@@ -40368,7 +42315,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0x0B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1   UIMM8()  ESIZE_64_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b
 IFORM:       VRNDSCALESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512
@@ -40384,7 +42331,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x0A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0   UIMM8()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
 IFORM:       VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
@@ -40398,7 +42345,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x0A V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W0   UIMM8()
 OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
 IFORM:       VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
@@ -40412,7 +42359,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0x0A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0   UIMM8()  ESIZE_32_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b
 IFORM:       VRNDSCALESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512
@@ -40428,7 +42375,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR
 OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
 IFORM:       VRSQRT14PD_ZMMf64_MASKmskw_ZMMf64_AVX512
@@ -40442,7 +42389,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VRSQRT14PD_ZMMf64_MASKmskw_MEMf64_AVX512
@@ -40458,7 +42405,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR
 OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
 IFORM:       VRSQRT14PS_ZMMf32_MASKmskw_ZMMf32_AVX512
@@ -40472,7 +42419,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VRSQRT14PS_ZMMf32_MASKmskw_MEMf32_AVX512
@@ -40488,7 +42435,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E10
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x4F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VRSQRT14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -40502,7 +42449,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E10
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0x4F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ESIZE_64_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
 IFORM:       VRSQRT14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
@@ -40518,7 +42465,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E10
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x4F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -40532,7 +42479,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E10
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0x4F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ESIZE_32_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
 IFORM:       VRSQRT14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
@@ -40548,7 +42495,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1
 OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
 IFORM:       VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
@@ -40562,7 +42509,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1
 OPERANDS:    REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
 IFORM:       VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
@@ -40576,7 +42523,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
@@ -40592,7 +42539,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0
 OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
 IFORM:       VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
@@ -40606,7 +42553,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0
 OPERANDS:    REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
 IFORM:       VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
@@ -40620,7 +42567,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
@@ -40636,7 +42583,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x2D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -40650,7 +42597,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x2D V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1
 OPERANDS:    REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -40664,7 +42611,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0x2D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ESIZE_64_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
 IFORM:       VSCALEFSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
@@ -40680,7 +42627,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x2D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -40694,7 +42641,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x2D V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0
 OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -40708,7 +42655,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0x2D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ESIZE_32_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
 IFORM:       VSCALEFSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
@@ -40724,9 +42671,9 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E12
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT
-PATTERN:    EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL512  W1 RM=4 UISA_VMODRM_YMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
-OPERANDS:    MEM0:w:zd:f64 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zf64
+ATTRIBUTES:  DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER
+PATTERN:    EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0   VL512  W1 UISA_VMODRM_YMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
+OPERANDS:    MEM0:w:q:f64 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zf64
 IFORM:       VSCATTERDPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512
 }
 
@@ -40740,9 +42687,9 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E12
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT
-PATTERN:    EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL512  W0 RM=4 UISA_VMODRM_ZMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
-OPERANDS:    MEM0:w:zd:f32 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zf32
+ATTRIBUTES:  DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER
+PATTERN:    EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0   VL512  W0 UISA_VMODRM_ZMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
+OPERANDS:    MEM0:w:d:f32 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zf32
 IFORM:       VSCATTERDPS_MEMf32_MASKmskw_ZMMf32_AVX512_VL512
 }
 
@@ -40756,9 +42703,9 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E12
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT
-PATTERN:    EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL512  W1 RM=4 UISA_VMODRM_ZMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
-OPERANDS:    MEM0:w:zd:f64 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zf64
+ATTRIBUTES:  QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER
+PATTERN:    EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0   VL512  W1 UISA_VMODRM_ZMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
+OPERANDS:    MEM0:w:q:f64 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zf64
 IFORM:       VSCATTERQPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512
 }
 
@@ -40772,9 +42719,9 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E12
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT
-PATTERN:    EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL512  W0 RM=4 UISA_VMODRM_ZMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
-OPERANDS:    MEM0:w:qq:f32 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:f32
+ATTRIBUTES:  QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER
+PATTERN:    EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0   VL512  W0 UISA_VMODRM_ZMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
+OPERANDS:    MEM0:w:d:f32 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:f32
 IFORM:       VSCATTERQPS_MEMf32_MASKmskw_YMMf32_AVX512_VL512
 }
 
@@ -40968,7 +42915,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x51 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR
 OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
 IFORM:       VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512
@@ -40982,7 +42929,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x51 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1  NOEVSR
 OPERANDS:    REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
 IFORM:       VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512
@@ -40996,7 +42943,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x51 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VSQRTPD_ZMMf64_MASKmskw_MEMf64_AVX512
@@ -41012,7 +42959,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x51 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR
 OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
 IFORM:       VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512
@@ -41026,7 +42973,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x51 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0  NOEVSR
 OPERANDS:    REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
 IFORM:       VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512
@@ -41040,7 +42987,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x51 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VSQRTPS_ZMMf32_MASKmskw_MEMf32_AVX512
@@ -41056,7 +43003,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -41070,7 +43017,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1
 OPERANDS:    REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -41084,7 +43031,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ESIZE_64_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
 IFORM:       VSQRTSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
@@ -41100,7 +43047,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -41114,7 +43061,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0
 OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -41128,7 +43075,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ESIZE_32_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
 IFORM:       VSQRTSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
@@ -41144,7 +43091,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1
 OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
 IFORM:       VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
@@ -41158,7 +43105,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5C V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1
 OPERANDS:    REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
 IFORM:       VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
@@ -41172,7 +43119,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x5C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VSUBPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
@@ -41188,7 +43135,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5C VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0
 OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
 IFORM:       VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
@@ -41202,7 +43149,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5C VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0
 OPERANDS:    REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
 IFORM:       VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
@@ -41216,7 +43163,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x5C VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VSUBPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
@@ -41232,7 +43179,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x5C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -41246,7 +43193,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x5C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1
 OPERANDS:    REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -41260,7 +43207,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0x5C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ESIZE_64_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
 IFORM:       VSUBSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
@@ -41276,7 +43223,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x5C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -41290,7 +43237,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x5C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0
 OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -41304,7 +43251,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0x5C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ESIZE_32_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
 IFORM:       VSUBSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
@@ -41771,7 +43718,7 @@ IFORM:       KXORW_MASKmskw_MASKmskw_MASKmskw_AVX512
 
 #BEGIN_LEGAL
 #
-#Copyright (c) 2016 Intel Corporation
+#Copyright (c) 2018 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -41833,7 +43780,7 @@ CPL:         3
 CATEGORY:    CONFLICT
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512CD_512
-EXCEPTIONS:     AVX512-E4
+EXCEPTIONS:     AVX512-E4NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX
 PATTERN:    EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR
@@ -41847,7 +43794,7 @@ CPL:         3
 CATEGORY:    CONFLICT
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512CD_512
-EXCEPTIONS:     AVX512-E4
+EXCEPTIONS:     AVX512-E4NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
 PATTERN:    EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL()
@@ -41863,7 +43810,7 @@ CPL:         3
 CATEGORY:    CONFLICT
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512CD_512
-EXCEPTIONS:     AVX512-E4
+EXCEPTIONS:     AVX512-E4NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX
 PATTERN:    EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR
@@ -41877,7 +43824,7 @@ CPL:         3
 CATEGORY:    CONFLICT
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512CD_512
-EXCEPTIONS:     AVX512-E4
+EXCEPTIONS:     AVX512-E4NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
 PATTERN:    EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
@@ -41952,7 +43899,7 @@ IFORM:       VPLZCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD
 
 #BEGIN_LEGAL
 #
-#Copyright (c) 2016 Intel Corporation
+#Copyright (c) 2018 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -41986,7 +43933,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x58 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -42000,7 +43947,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x58 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VADDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
@@ -42016,7 +43963,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x58 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1
 OPERANDS:    REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
 IFORM:       VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
@@ -42030,7 +43977,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x58 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VADDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
@@ -42046,7 +43993,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x58 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -42060,7 +44007,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x58 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VADDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
@@ -42076,7 +44023,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x58 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0
 OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
 IFORM:       VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
@@ -42090,7 +44037,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x58 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VADDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
@@ -42228,8 +44175,8 @@ EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX
 PATTERN:    EVV 0x55 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1
-OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
-IFORM:       VANDNPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
+OPERANDS:    REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
+IFORM:       VANDNPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
 }
 
 {
@@ -42242,8 +44189,8 @@ EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
 PATTERN:    EVV 0x55 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1    ESIZE_64_BITS() NELEM_FULL()
-OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
-IFORM:       VANDNPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
+OPERANDS:    REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
+IFORM:       VANDNPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
 }
 
 
@@ -42258,8 +44205,8 @@ EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX
 PATTERN:    EVV 0x55 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1
-OPERANDS:    REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
-IFORM:       VANDNPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
+OPERANDS:    REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
+IFORM:       VANDNPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
 }
 
 {
@@ -42272,8 +44219,8 @@ EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
 PATTERN:    EVV 0x55 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1    ESIZE_64_BITS() NELEM_FULL()
-OPERANDS:    REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
-IFORM:       VANDNPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
+OPERANDS:    REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
+IFORM:       VANDNPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
 }
 
 
@@ -42288,8 +44235,8 @@ EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX
 PATTERN:    EVV 0x55 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1
-OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
-IFORM:       VANDNPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
+OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
+IFORM:       VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
 }
 
 {
@@ -42302,8 +44249,8 @@ EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
 PATTERN:    EVV 0x55 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
-OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
-IFORM:       VANDNPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
+OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
+IFORM:       VANDNPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
 }
 
 
@@ -42318,8 +44265,8 @@ EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX
 PATTERN:    EVV 0x55 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0
-OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
-IFORM:       VANDNPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
+OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
+IFORM:       VANDNPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
 }
 
 {
@@ -42332,8 +44279,8 @@ EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
 PATTERN:    EVV 0x55 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_32_BITS() NELEM_FULL()
-OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
-IFORM:       VANDNPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
+OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
+IFORM:       VANDNPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
 }
 
 
@@ -42348,8 +44295,8 @@ EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX
 PATTERN:    EVV 0x55 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0
-OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
-IFORM:       VANDNPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
+OPERANDS:    REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
+IFORM:       VANDNPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
 }
 
 {
@@ -42362,8 +44309,8 @@ EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
 PATTERN:    EVV 0x55 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_32_BITS() NELEM_FULL()
-OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
-IFORM:       VANDNPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
+OPERANDS:    REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
+IFORM:       VANDNPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
 }
 
 
@@ -42378,8 +44325,8 @@ EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX
 PATTERN:    EVV 0x55 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0
-OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
-IFORM:       VANDNPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
+OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
+IFORM:       VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
 }
 
 {
@@ -42392,8 +44339,8 @@ EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
 PATTERN:    EVV 0x55 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
-OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
-IFORM:       VANDNPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
+OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
+IFORM:       VANDNPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
 }
 
 
@@ -42408,8 +44355,8 @@ EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX
 PATTERN:    EVV 0x54 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1
-OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
-IFORM:       VANDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
+OPERANDS:    REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
+IFORM:       VANDPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
 }
 
 {
@@ -42422,8 +44369,8 @@ EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
 PATTERN:    EVV 0x54 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1    ESIZE_64_BITS() NELEM_FULL()
-OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
-IFORM:       VANDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
+OPERANDS:    REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
+IFORM:       VANDPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
 }
 
 
@@ -42438,8 +44385,8 @@ EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX
 PATTERN:    EVV 0x54 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1
-OPERANDS:    REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
-IFORM:       VANDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
+OPERANDS:    REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
+IFORM:       VANDPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
 }
 
 {
@@ -42452,8 +44399,8 @@ EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
 PATTERN:    EVV 0x54 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1    ESIZE_64_BITS() NELEM_FULL()
-OPERANDS:    REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
-IFORM:       VANDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
+OPERANDS:    REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
+IFORM:       VANDPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
 }
 
 
@@ -42468,8 +44415,8 @@ EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX
 PATTERN:    EVV 0x54 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1
-OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
-IFORM:       VANDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
+OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
+IFORM:       VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
 }
 
 {
@@ -42482,8 +44429,8 @@ EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
 PATTERN:    EVV 0x54 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
-OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
-IFORM:       VANDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
+OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
+IFORM:       VANDPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
 }
 
 
@@ -42498,8 +44445,8 @@ EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX
 PATTERN:    EVV 0x54 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0
-OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
-IFORM:       VANDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
+OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
+IFORM:       VANDPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
 }
 
 {
@@ -42512,8 +44459,8 @@ EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
 PATTERN:    EVV 0x54 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_32_BITS() NELEM_FULL()
-OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
-IFORM:       VANDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
+OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
+IFORM:       VANDPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
 }
 
 
@@ -42528,8 +44475,8 @@ EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX
 PATTERN:    EVV 0x54 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0
-OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
-IFORM:       VANDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
+OPERANDS:    REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
+IFORM:       VANDPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
 }
 
 {
@@ -42542,8 +44489,8 @@ EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
 PATTERN:    EVV 0x54 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_32_BITS() NELEM_FULL()
-OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
-IFORM:       VANDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
+OPERANDS:    REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
+IFORM:       VANDPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
 }
 
 
@@ -42558,8 +44505,8 @@ EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX
 PATTERN:    EVV 0x54 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0
-OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
-IFORM:       VANDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
+OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
+IFORM:       VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
 }
 
 {
@@ -42572,8 +44519,8 @@ EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
 PATTERN:    EVV 0x54 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
-OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
-IFORM:       VANDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
+OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
+IFORM:       VANDPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
 }
 
 
@@ -42600,7 +44547,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL
 PATTERN:    EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VBLENDMPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
@@ -42630,7 +44577,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL
 PATTERN:    EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VBLENDMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
@@ -42660,7 +44607,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL
 PATTERN:    EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VBLENDMPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
@@ -42690,7 +44637,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL
 PATTERN:    EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VBLENDMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
@@ -43080,7 +45027,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xC2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1    ZEROING=0 UIMM8()
 OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
 IFORM:       VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
@@ -43094,7 +45041,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xC2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1    ZEROING=0 UIMM8()  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
 IFORM:       VCMPPD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512
@@ -43110,7 +45057,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xC2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1    ZEROING=0 UIMM8()
 OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 IMM0:r:b
 IFORM:       VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512
@@ -43124,7 +45071,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xC2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1    ZEROING=0 UIMM8()  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
 IFORM:       VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512
@@ -43140,7 +45087,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xC2 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0    ZEROING=0 UIMM8()
 OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
 IFORM:       VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
@@ -43154,7 +45101,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xC2 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ZEROING=0 UIMM8()  ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
 IFORM:       VCMPPS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512
@@ -43170,7 +45117,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xC2 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0    ZEROING=0 UIMM8()
 OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 IMM0:r:b
 IFORM:       VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512
@@ -43184,7 +45131,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xC2 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ZEROING=0 UIMM8()  ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
 IFORM:       VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512
@@ -43200,7 +45147,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
 PATTERN:    EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W1  NOEVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
 OPERANDS:    MEM0:w:dq:f64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f64
 IFORM:       VCOMPRESSPD_MEMf64_MASKmskw_XMMf64_AVX512
@@ -43232,7 +45179,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
 PATTERN:    EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W1  NOEVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
 OPERANDS:    MEM0:w:qq:f64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f64
 IFORM:       VCOMPRESSPD_MEMf64_MASKmskw_YMMf64_AVX512
@@ -43264,7 +45211,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
 PATTERN:    EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0  NOEVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
 OPERANDS:    MEM0:w:dq:f32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f32
 IFORM:       VCOMPRESSPS_MEMf32_MASKmskw_XMMf32_AVX512
@@ -43296,7 +45243,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
 PATTERN:    EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W0  NOEVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
 OPERANDS:    MEM0:w:qq:f32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f32
 IFORM:       VCOMPRESSPS_MEMf32_MASKmskw_YMMf32_AVX512
@@ -43388,7 +45335,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0  NOEVSR
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32
 IFORM:       VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512
@@ -43402,7 +45349,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR
 IFORM:       VCVTDQ2PS_XMMf32_MASKmskw_MEMi32_AVX512
@@ -43418,7 +45365,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0  NOEVSR
 OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32
 IFORM:       VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512
@@ -43432,7 +45379,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR
 IFORM:       VCVTDQ2PS_YMMf32_MASKmskw_MEMi32_AVX512
@@ -43448,7 +45395,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xE6 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1  NOEVSR
 OPERANDS:    REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
 IFORM:       VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128
@@ -43462,7 +45409,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xE6 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128
@@ -43478,7 +45425,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xE6 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1  NOEVSR
 OPERANDS:    REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
 IFORM:       VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256
@@ -43492,7 +45439,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xE6 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256
@@ -43508,7 +45455,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1  NOEVSR
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
 IFORM:       VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128
@@ -43522,7 +45469,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x5A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128
@@ -43538,7 +45485,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1  NOEVSR
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
 IFORM:       VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256
@@ -43552,7 +45499,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x5A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256
@@ -43568,7 +45515,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1  NOEVSR
 OPERANDS:    REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
 IFORM:       VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512
@@ -43582,7 +45529,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512
@@ -43598,7 +45545,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1  NOEVSR
 OPERANDS:    REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
 IFORM:       VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512
@@ -43612,7 +45559,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512
@@ -43628,7 +45575,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR
 OPERANDS:    REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
 IFORM:       VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512
@@ -43642,7 +45589,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1  NOEVSR
 OPERANDS:    REG0=ZMM_R3():w:zi64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
 IFORM:       VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512
@@ -43656,7 +45603,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512
@@ -43672,7 +45619,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1  NOEVSR
 OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
 IFORM:       VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128
@@ -43686,7 +45633,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128
@@ -43702,7 +45649,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1  NOEVSR
 OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
 IFORM:       VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256
@@ -43716,7 +45663,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256
@@ -43732,7 +45679,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1  NOEVSR
 OPERANDS:    REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
 IFORM:       VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512
@@ -43746,7 +45693,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512
@@ -43762,7 +45709,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1  NOEVSR
 OPERANDS:    REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
 IFORM:       VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512
@@ -43776,7 +45723,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512
@@ -43792,7 +45739,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR
 OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
 IFORM:       VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512
@@ -43806,7 +45753,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1  NOEVSR
 OPERANDS:    REG0=ZMM_R3():w:zu64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
 IFORM:       VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512
@@ -43820,14 +45767,14 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512
 }
 
 
-# EMITTING VCVTPH2PS (VCVTPH2PS-128-1)
+# EMITTING VCVTPH2PS (VCVTPH2PS-128-2)
 {
 ICLASS:      VCVTPH2PS
 CPL:         3
@@ -43836,7 +45783,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E11
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0  NOEVSR
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
 IFORM:       VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512
@@ -43850,14 +45797,14 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E11
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR DISP8_HALFMEM
 PATTERN:    EVV 0x13 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0  NOEVSR  ESIZE_16_BITS() NELEM_HALFMEM()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f16
 IFORM:       VCVTPH2PS_XMMf32_MASKmskw_MEMf16_AVX512
 }
 
 
-# EMITTING VCVTPH2PS (VCVTPH2PS-256-1)
+# EMITTING VCVTPH2PS (VCVTPH2PS-256-2)
 {
 ICLASS:      VCVTPH2PS
 CPL:         3
@@ -43866,7 +45813,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E11
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0  NOEVSR
 OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
 IFORM:       VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512
@@ -43880,7 +45827,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E11
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR DISP8_HALFMEM
 PATTERN:    EVV 0x13 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W0  NOEVSR  ESIZE_16_BITS() NELEM_HALFMEM()
 OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f16
 IFORM:       VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512
@@ -43896,7 +45843,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0  NOEVSR
 OPERANDS:    REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
 IFORM:       VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512
@@ -43910,7 +45857,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x5B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VCVTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512
@@ -43926,7 +45873,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0  NOEVSR
 OPERANDS:    REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
 IFORM:       VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512
@@ -43940,7 +45887,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x5B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512
@@ -43956,7 +45903,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5A VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0  NOEVSR
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
 IFORM:       VCVTPS2PD_XMMf64_MASKmskw_XMMf32_AVX512
@@ -43970,7 +45917,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x5A VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0  NOEVSR  ESIZE_32_BITS() NELEM_HALF()
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512
@@ -43986,7 +45933,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5A VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0  NOEVSR
 OPERANDS:    REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
 IFORM:       VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512
@@ -44000,14 +45947,14 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x5A VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0  NOEVSR  ESIZE_32_BITS() NELEM_HALF()
 OPERANDS:    REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512
 }
 
 
-# EMITTING VCVTPS2PH (VCVTPS2PH-128-1)
+# EMITTING VCVTPS2PH (VCVTPS2PH-128-2)
 {
 ICLASS:      VCVTPS2PH
 CPL:         3
@@ -44016,30 +45963,30 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E11NF
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0  NOEVSR UIMM8()
 OPERANDS:    REG0=XMM_B3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f32 IMM0:r:b
 IFORM:       VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512
 }
 
 
-# EMITTING VCVTPS2PH (VCVTPS2PH-128-2)
+# EMITTING VCVTPS2PH (VCVTPS2PH-128-3)
 {
 ICLASS:      VCVTPS2PH
 CPL:         3
 CATEGORY:    CONVERT
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
-EXCEPTIONS:     AVX512-E11NF
+EXCEPTIONS:     AVX512-E11
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR DISP8_HALFMEM
 PATTERN:    EVV 0x1D V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0  NOEVSR  ZEROING=0 UIMM8()  ESIZE_16_BITS() NELEM_HALFMEM()
 OPERANDS:    MEM0:w:q:f16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f32 IMM0:r:b
 IFORM:       VCVTPS2PH_MEMf16_MASKmskw_XMMf32_IMM8_AVX512
 }
 
 
-# EMITTING VCVTPS2PH (VCVTPS2PH-256-1)
+# EMITTING VCVTPS2PH (VCVTPS2PH-256-2)
 {
 ICLASS:      VCVTPS2PH
 CPL:         3
@@ -44048,23 +45995,23 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E11NF
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0  NOEVSR UIMM8()
 OPERANDS:    REG0=XMM_B3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f32 IMM0:r:b
 IFORM:       VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512
 }
 
 
-# EMITTING VCVTPS2PH (VCVTPS2PH-256-2)
+# EMITTING VCVTPS2PH (VCVTPS2PH-256-3)
 {
 ICLASS:      VCVTPS2PH
 CPL:         3
 CATEGORY:    CONVERT
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
-EXCEPTIONS:     AVX512-E11NF
+EXCEPTIONS:     AVX512-E11
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR DISP8_HALFMEM
 PATTERN:    EVV 0x1D V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W0  NOEVSR  ZEROING=0 UIMM8()  ESIZE_16_BITS() NELEM_HALFMEM()
 OPERANDS:    MEM0:w:dq:f16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f32 IMM0:r:b
 IFORM:       VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512
@@ -44080,7 +46027,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_128
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0  NOEVSR
 OPERANDS:    REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
 IFORM:       VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512
@@ -44094,7 +46041,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_128
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0  NOEVSR  ESIZE_32_BITS() NELEM_HALF()
 OPERANDS:    REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512
@@ -44110,7 +46057,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_256
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0  NOEVSR
 OPERANDS:    REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
 IFORM:       VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512
@@ -44124,7 +46071,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_256
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0  NOEVSR  ESIZE_32_BITS() NELEM_HALF()
 OPERANDS:    REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512
@@ -44140,7 +46087,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_512
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR
 OPERANDS:    REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
 IFORM:       VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512
@@ -44154,7 +46101,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_512
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0  NOEVSR
 OPERANDS:    REG0=ZMM_R3():w:zi64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
 IFORM:       VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512
@@ -44168,7 +46115,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_512
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_HALF()
 OPERANDS:    REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512
@@ -44184,7 +46131,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0  NOEVSR
 OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
 IFORM:       VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512
@@ -44198,7 +46145,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512
@@ -44214,7 +46161,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0  NOEVSR
 OPERANDS:    REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
 IFORM:       VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512
@@ -44228,7 +46175,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512
@@ -44244,7 +46191,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_128
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0  NOEVSR
 OPERANDS:    REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
 IFORM:       VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512
@@ -44258,7 +46205,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_128
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0  NOEVSR  ESIZE_32_BITS() NELEM_HALF()
 OPERANDS:    REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512
@@ -44274,7 +46221,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_256
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0  NOEVSR
 OPERANDS:    REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
 IFORM:       VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512
@@ -44288,7 +46235,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_256
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0  NOEVSR  ESIZE_32_BITS() NELEM_HALF()
 OPERANDS:    REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512
@@ -44304,7 +46251,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_512
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR
 OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
 IFORM:       VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512
@@ -44318,7 +46265,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_512
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0  NOEVSR
 OPERANDS:    REG0=ZMM_R3():w:zu64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
 IFORM:       VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512
@@ -44332,7 +46279,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_512
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_HALF()
 OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512
@@ -44348,7 +46295,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1  NOEVSR
 OPERANDS:    REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
 IFORM:       VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512
@@ -44362,7 +46309,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VCVTQQ2PD_XMMi64_MASKmskw_MEMf64_AVX512
@@ -44378,7 +46325,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1  NOEVSR
 OPERANDS:    REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
 IFORM:       VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512
@@ -44392,7 +46339,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VCVTQQ2PD_YMMi64_MASKmskw_MEMf64_AVX512
@@ -44408,7 +46355,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR
 OPERANDS:    REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
 IFORM:       VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512
@@ -44422,7 +46369,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1  NOEVSR
 OPERANDS:    REG0=ZMM_R3():w:zi64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
 IFORM:       VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512
@@ -44436,7 +46383,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VCVTQQ2PD_ZMMi64_MASKmskw_MEMf64_AVX512
@@ -44452,7 +46399,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1  NOEVSR
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64
 IFORM:       VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128
@@ -44466,7 +46413,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
 IFORM:       VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128
@@ -44482,7 +46429,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1  NOEVSR
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64
 IFORM:       VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256
@@ -44496,7 +46443,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
 IFORM:       VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256
@@ -44512,7 +46459,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR
 OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64
 IFORM:       VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512
@@ -44526,7 +46473,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1  NOEVSR
 OPERANDS:    REG0=YMM_R3():w:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64
 IFORM:       VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512
@@ -44540,7 +46487,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
 IFORM:       VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512
@@ -44556,7 +46503,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xE6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1  NOEVSR
 OPERANDS:    REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
 IFORM:       VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128
@@ -44570,7 +46517,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xE6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128
@@ -44586,7 +46533,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xE6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1  NOEVSR
 OPERANDS:    REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
 IFORM:       VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256
@@ -44600,7 +46547,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xE6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256
@@ -44616,7 +46563,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1  NOEVSR
 OPERANDS:    REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
 IFORM:       VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512
@@ -44630,7 +46577,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512
@@ -44646,7 +46593,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1  NOEVSR
 OPERANDS:    REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
 IFORM:       VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512
@@ -44660,7 +46607,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512
@@ -44676,7 +46623,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR
 OPERANDS:    REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
 IFORM:       VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512
@@ -44690,7 +46637,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W1  NOEVSR
 OPERANDS:    REG0=ZMM_R3():w:zi64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
 IFORM:       VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512
@@ -44704,7 +46651,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512
@@ -44720,7 +46667,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1  NOEVSR
 OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
 IFORM:       VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128
@@ -44734,7 +46681,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128
@@ -44750,7 +46697,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1  NOEVSR
 OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
 IFORM:       VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256
@@ -44764,7 +46711,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256
@@ -44780,7 +46727,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1  NOEVSR
 OPERANDS:    REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
 IFORM:       VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512
@@ -44794,7 +46741,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512
@@ -44810,7 +46757,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1  NOEVSR
 OPERANDS:    REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
 IFORM:       VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512
@@ -44824,7 +46771,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512
@@ -44840,7 +46787,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR
 OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
 IFORM:       VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512
@@ -44854,7 +46801,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W1  NOEVSR
 OPERANDS:    REG0=ZMM_R3():w:zu64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
 IFORM:       VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512
@@ -44868,7 +46815,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512
@@ -44884,7 +46831,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0  NOEVSR
 OPERANDS:    REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
 IFORM:       VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512
@@ -44898,7 +46845,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x5B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VCVTTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512
@@ -44914,7 +46861,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0  NOEVSR
 OPERANDS:    REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
 IFORM:       VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512
@@ -44928,7 +46875,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x5B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512
@@ -44944,7 +46891,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_128
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0  NOEVSR
 OPERANDS:    REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
 IFORM:       VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512
@@ -44958,7 +46905,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_128
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0  NOEVSR  ESIZE_32_BITS() NELEM_HALF()
 OPERANDS:    REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512
@@ -44974,7 +46921,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_256
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0  NOEVSR
 OPERANDS:    REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
 IFORM:       VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512
@@ -44988,7 +46935,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_256
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0  NOEVSR  ESIZE_32_BITS() NELEM_HALF()
 OPERANDS:    REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512
@@ -45004,7 +46951,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_512
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR
 OPERANDS:    REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
 IFORM:       VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512
@@ -45018,7 +46965,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_512
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W0  NOEVSR
 OPERANDS:    REG0=ZMM_R3():w:zi64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
 IFORM:       VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512
@@ -45032,7 +46979,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_512
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_HALF()
 OPERANDS:    REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512
@@ -45048,7 +46995,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0  NOEVSR
 OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
 IFORM:       VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512
@@ -45062,7 +47009,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512
@@ -45078,7 +47025,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0  NOEVSR
 OPERANDS:    REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
 IFORM:       VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512
@@ -45092,7 +47039,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512
@@ -45108,7 +47055,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_128
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0  NOEVSR
 OPERANDS:    REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
 IFORM:       VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512
@@ -45122,7 +47069,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_128
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0  NOEVSR  ESIZE_32_BITS() NELEM_HALF()
 OPERANDS:    REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VCVTTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512
@@ -45138,7 +47085,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_256
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0  NOEVSR
 OPERANDS:    REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
 IFORM:       VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512
@@ -45152,7 +47099,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_256
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0  NOEVSR  ESIZE_32_BITS() NELEM_HALF()
 OPERANDS:    REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VCVTTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512
@@ -45168,7 +47115,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_512
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR
 OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
 IFORM:       VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512
@@ -45182,7 +47129,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_512
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W0  NOEVSR
 OPERANDS:    REG0=ZMM_R3():w:zu64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
 IFORM:       VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512
@@ -45196,7 +47143,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_512
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_HALF()
 OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VCVTTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512
@@ -45272,7 +47219,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0  NOEVSR
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32
 IFORM:       VCVTUDQ2PS_XMMf32_MASKmskw_XMMu32_AVX512
@@ -45286,7 +47233,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR
 IFORM:       VCVTUDQ2PS_XMMf32_MASKmskw_MEMu32_AVX512
@@ -45302,7 +47249,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0  NOEVSR
 OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32
 IFORM:       VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512
@@ -45316,7 +47263,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR
 IFORM:       VCVTUDQ2PS_YMMf32_MASKmskw_MEMu32_AVX512
@@ -45332,7 +47279,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1  NOEVSR
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64
 IFORM:       VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512
@@ -45346,7 +47293,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
 IFORM:       VCVTUQQ2PD_XMMf64_MASKmskw_MEMu64_AVX512
@@ -45362,7 +47309,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1  NOEVSR
 OPERANDS:    REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64
 IFORM:       VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512
@@ -45376,7 +47323,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
 IFORM:       VCVTUQQ2PD_YMMf64_MASKmskw_MEMu64_AVX512
@@ -45392,7 +47339,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR
 OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64
 IFORM:       VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512
@@ -45406,7 +47353,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1  NOEVSR
 OPERANDS:    REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64
 IFORM:       VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512
@@ -45420,7 +47367,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
 IFORM:       VCVTUQQ2PD_ZMMf64_MASKmskw_MEMu64_AVX512
@@ -45436,7 +47383,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1  NOEVSR
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64
 IFORM:       VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128
@@ -45450,7 +47397,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
 IFORM:       VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128
@@ -45466,7 +47413,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1  NOEVSR
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64
 IFORM:       VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256
@@ -45480,7 +47427,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
 IFORM:       VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256
@@ -45496,7 +47443,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR
 OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64
 IFORM:       VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512
@@ -45510,7 +47457,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1  NOEVSR
 OPERANDS:    REG0=YMM_R3():w:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64
 IFORM:       VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512
@@ -45524,7 +47471,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
 IFORM:       VCVTUQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512
@@ -45630,7 +47577,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -45644,7 +47591,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x5E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VDIVPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
@@ -45660,7 +47607,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1
 OPERANDS:    REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
 IFORM:       VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
@@ -45674,7 +47621,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x5E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VDIVPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
@@ -45690,7 +47637,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5E VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -45704,7 +47651,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x5E VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VDIVPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
@@ -45720,7 +47667,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5E VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0
 OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
 IFORM:       VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
@@ -45734,7 +47681,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x5E VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VDIVPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
@@ -45750,7 +47697,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
 PATTERN:    EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W1  NOEVSR  ESIZE_64_BITS() NELEM_GSCAT()
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f64
 IFORM:       VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512
@@ -45782,7 +47729,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
 PATTERN:    EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W1  NOEVSR  ESIZE_64_BITS() NELEM_GSCAT()
 OPERANDS:    REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f64
 IFORM:       VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512
@@ -45814,7 +47761,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
 PATTERN:    EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0  NOEVSR  ESIZE_32_BITS() NELEM_GSCAT()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32
 IFORM:       VEXPANDPS_XMMf32_MASKmskw_MEMf32_AVX512
@@ -45846,7 +47793,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
 PATTERN:    EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W0  NOEVSR  ESIZE_32_BITS() NELEM_GSCAT()
 OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32
 IFORM:       VEXPANDPS_YMMf32_MASKmskw_MEMf32_AVX512
@@ -46134,7 +48081,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1   UIMM8()
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
 IFORM:       VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
@@ -46148,7 +48095,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1   UIMM8()  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
 IFORM:       VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512
@@ -46164,7 +48111,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1   UIMM8()
 OPERANDS:    REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 IMM0:r:b
 IFORM:       VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512
@@ -46178,7 +48125,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1   UIMM8()  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
 IFORM:       VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512
@@ -46194,7 +48141,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0   UIMM8()
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
 IFORM:       VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
@@ -46208,7 +48155,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0   UIMM8()  ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
 IFORM:       VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512
@@ -46224,7 +48171,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0   UIMM8()
 OPERANDS:    REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 IMM0:r:b
 IFORM:       VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512
@@ -46238,7 +48185,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0   UIMM8()  ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
 IFORM:       VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512
@@ -46254,7 +48201,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -46268,7 +48215,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VFMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
@@ -46284,7 +48231,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1
 OPERANDS:    REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
 IFORM:       VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
@@ -46298,7 +48245,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VFMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
@@ -46314,7 +48261,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -46328,7 +48275,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VFMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
@@ -46344,7 +48291,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0
 OPERANDS:    REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
 IFORM:       VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
@@ -46358,7 +48305,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VFMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
@@ -46374,7 +48321,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -46388,7 +48335,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VFMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
@@ -46404,7 +48351,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1
 OPERANDS:    REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
 IFORM:       VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
@@ -46418,7 +48365,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VFMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
@@ -46434,7 +48381,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -46448,7 +48395,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VFMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
@@ -46464,7 +48411,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0
 OPERANDS:    REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
 IFORM:       VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
@@ -46478,7 +48425,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VFMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
@@ -46494,7 +48441,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -46508,7 +48455,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VFMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
@@ -46524,7 +48471,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1
 OPERANDS:    REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
 IFORM:       VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
@@ -46538,7 +48485,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VFMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
@@ -46554,7 +48501,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -46568,7 +48515,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VFMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
@@ -46584,7 +48531,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0
 OPERANDS:    REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
 IFORM:       VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
@@ -46598,7 +48545,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VFMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
@@ -46614,7 +48561,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -46628,7 +48575,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
@@ -46644,7 +48591,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1
 OPERANDS:    REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
 IFORM:       VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
@@ -46658,7 +48605,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
@@ -46674,7 +48621,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -46688,7 +48635,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
@@ -46704,7 +48651,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0
 OPERANDS:    REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
 IFORM:       VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
@@ -46718,7 +48665,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
@@ -46734,7 +48681,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -46748,7 +48695,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
@@ -46764,7 +48711,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1
 OPERANDS:    REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
 IFORM:       VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
@@ -46778,7 +48725,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
@@ -46794,7 +48741,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -46808,7 +48755,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
@@ -46824,7 +48771,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0
 OPERANDS:    REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
 IFORM:       VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
@@ -46838,7 +48785,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
@@ -46854,7 +48801,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -46868,7 +48815,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
@@ -46884,7 +48831,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1
 OPERANDS:    REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
 IFORM:       VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
@@ -46898,7 +48845,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
@@ -46914,7 +48861,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -46928,7 +48875,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
@@ -46944,7 +48891,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0
 OPERANDS:    REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
 IFORM:       VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
@@ -46958,7 +48905,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
@@ -46974,7 +48921,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -46988,7 +48935,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VFMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
@@ -47004,7 +48951,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1
 OPERANDS:    REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
 IFORM:       VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
@@ -47018,7 +48965,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VFMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
@@ -47034,7 +48981,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -47048,7 +48995,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VFMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
@@ -47064,7 +49011,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0
 OPERANDS:    REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
 IFORM:       VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
@@ -47078,7 +49025,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VFMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
@@ -47094,7 +49041,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -47108,7 +49055,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VFMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
@@ -47124,7 +49071,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1
 OPERANDS:    REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
 IFORM:       VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
@@ -47138,7 +49085,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VFMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
@@ -47154,7 +49101,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -47168,7 +49115,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VFMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
@@ -47184,7 +49131,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0
 OPERANDS:    REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
 IFORM:       VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
@@ -47198,7 +49145,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VFMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
@@ -47214,7 +49161,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -47228,7 +49175,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VFMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
@@ -47244,7 +49191,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1
 OPERANDS:    REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
 IFORM:       VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
@@ -47258,7 +49205,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VFMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
@@ -47274,7 +49221,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -47288,7 +49235,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VFMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
@@ -47304,7 +49251,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0
 OPERANDS:    REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
 IFORM:       VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
@@ -47318,7 +49265,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VFMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
@@ -47334,7 +49281,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -47348,7 +49295,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
@@ -47364,7 +49311,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1
 OPERANDS:    REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
 IFORM:       VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
@@ -47378,7 +49325,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
@@ -47394,7 +49341,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -47408,7 +49355,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
@@ -47424,7 +49371,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0
 OPERANDS:    REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
 IFORM:       VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
@@ -47438,7 +49385,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
@@ -47454,7 +49401,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -47468,7 +49415,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
@@ -47484,7 +49431,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1
 OPERANDS:    REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
 IFORM:       VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
@@ -47498,7 +49445,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
@@ -47514,7 +49461,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -47528,7 +49475,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
@@ -47544,7 +49491,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0
 OPERANDS:    REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
 IFORM:       VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
@@ -47558,7 +49505,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
@@ -47574,7 +49521,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -47588,7 +49535,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
@@ -47604,7 +49551,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1
 OPERANDS:    REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
 IFORM:       VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
@@ -47618,7 +49565,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
@@ -47634,7 +49581,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -47648,7 +49595,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
@@ -47664,7 +49611,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0
 OPERANDS:    REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
 IFORM:       VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
@@ -47678,7 +49625,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
@@ -47694,7 +49641,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -47708,7 +49655,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VFNMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
@@ -47724,7 +49671,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1
 OPERANDS:    REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
 IFORM:       VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
@@ -47738,7 +49685,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VFNMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
@@ -47754,7 +49701,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -47768,7 +49715,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VFNMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
@@ -47784,7 +49731,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0
 OPERANDS:    REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
 IFORM:       VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
@@ -47798,7 +49745,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VFNMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
@@ -47814,7 +49761,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -47828,7 +49775,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VFNMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
@@ -47844,7 +49791,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1
 OPERANDS:    REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
 IFORM:       VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
@@ -47858,7 +49805,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VFNMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
@@ -47874,7 +49821,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -47888,7 +49835,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VFNMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
@@ -47904,7 +49851,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0
 OPERANDS:    REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
 IFORM:       VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
@@ -47918,7 +49865,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VFNMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
@@ -47934,7 +49881,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -47948,7 +49895,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VFNMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
@@ -47964,7 +49911,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1
 OPERANDS:    REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
 IFORM:       VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
@@ -47978,7 +49925,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VFNMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
@@ -47994,7 +49941,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -48008,7 +49955,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VFNMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
@@ -48024,7 +49971,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0
 OPERANDS:    REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
 IFORM:       VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
@@ -48038,7 +49985,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VFNMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
@@ -48054,7 +50001,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -48068,7 +50015,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
@@ -48084,7 +50031,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1
 OPERANDS:    REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
 IFORM:       VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
@@ -48098,7 +50045,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
@@ -48114,7 +50061,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -48128,7 +50075,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
@@ -48144,7 +50091,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0
 OPERANDS:    REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
 IFORM:       VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
@@ -48158,7 +50105,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
@@ -48174,7 +50121,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -48188,7 +50135,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
@@ -48204,7 +50151,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1
 OPERANDS:    REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
 IFORM:       VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
@@ -48218,7 +50165,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
@@ -48234,7 +50181,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -48248,7 +50195,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
@@ -48264,7 +50211,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0
 OPERANDS:    REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
 IFORM:       VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
@@ -48278,7 +50225,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
@@ -48294,7 +50241,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -48308,7 +50255,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
@@ -48324,7 +50271,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1
 OPERANDS:    REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
 IFORM:       VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
@@ -48338,7 +50285,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
@@ -48354,7 +50301,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -48368,7 +50315,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
@@ -48384,7 +50331,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0
 OPERANDS:    REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
 IFORM:       VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
@@ -48398,7 +50345,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
@@ -48414,7 +50361,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_128
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1  NOEVSR  ZEROING=0 UIMM8()
 OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_B3():r:dq:f64 IMM0:r:b
 IFORM:       VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512
@@ -48428,10 +50375,10 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_128
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1  NOEVSR  ZEROING=0 UIMM8()  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
-IFORM:       VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512
+IFORM:       VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL128
 }
 
 
@@ -48444,7 +50391,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_256
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1  NOEVSR  ZEROING=0 UIMM8()
 OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_B3():r:qq:f64 IMM0:r:b
 IFORM:       VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512
@@ -48458,10 +50405,10 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_256
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1  NOEVSR  ZEROING=0 UIMM8()  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
-IFORM:       VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512
+IFORM:       VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256
 }
 
 
@@ -48474,7 +50421,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_512
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR  ZEROING=0 UIMM8()
 OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf64 IMM0:r:b
 IFORM:       VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512
@@ -48488,10 +50435,10 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_512
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1  NOEVSR  ZEROING=0 UIMM8()  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
-IFORM:       VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512
+IFORM:       VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL512
 }
 
 
@@ -48504,7 +50451,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_128
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0  NOEVSR  ZEROING=0 UIMM8()
 OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_B3():r:dq:f32 IMM0:r:b
 IFORM:       VFPCLASSPS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512
@@ -48518,10 +50465,10 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_128
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0  NOEVSR  ZEROING=0 UIMM8()  ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
-IFORM:       VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512
+IFORM:       VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL128
 }
 
 
@@ -48534,7 +50481,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_256
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0  NOEVSR  ZEROING=0 UIMM8()
 OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_B3():r:qq:f32 IMM0:r:b
 IFORM:       VFPCLASSPS_MASKmskw_MASKmskw_YMMf32_IMM8_AVX512
@@ -48548,10 +50495,10 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_256
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0  NOEVSR  ZEROING=0 UIMM8()  ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
-IFORM:       VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512
+IFORM:       VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL256
 }
 
 
@@ -48564,7 +50511,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_512
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR  ZEROING=0 UIMM8()
 OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf32 IMM0:r:b
 IFORM:       VFPCLASSPS_MASKmskw_MASKmskw_ZMMf32_IMM8_AVX512
@@ -48578,10 +50525,10 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_512
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ZEROING=0 UIMM8()  ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
-IFORM:       VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512
+IFORM:       VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL512
 }
 
 
@@ -48594,7 +50541,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_SCALAR
 EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x67 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1  NOEVSR  ZEROING=0 UIMM8()
 OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_B3():r:dq:f64 IMM0:r:b
 IFORM:       VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512
@@ -48608,7 +50555,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_SCALAR
 EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0x67 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1  NOEVSR  ZEROING=0 UIMM8()  ESIZE_64_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:q:f64 IMM0:r:b
 IFORM:       VFPCLASSSD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512
@@ -48624,7 +50571,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_SCALAR
 EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x67 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0  NOEVSR  ZEROING=0 UIMM8()
 OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_B3():r:dq:f32 IMM0:r:b
 IFORM:       VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512
@@ -48638,14 +50585,14 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_SCALAR
 EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0x67 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0  NOEVSR  ZEROING=0 UIMM8()  ESIZE_32_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:d:f32 IMM0:r:b
 IFORM:       VFPCLASSSS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512
 }
 
 
-# EMITTING VGATHERDPD (VGATHERDPD-128-1)
+# EMITTING VGATHERDPD (VGATHERDPD-128-2)
 {
 ICLASS:      VGATHERDPD
 CPL:         3
@@ -48654,14 +50601,14 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E12
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT
-PATTERN:    EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL128  W1 RM=4 UISA_VMODRM_XMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
-OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASKNOT0():rw:mskw MEM0:r:dq:f64
+ATTRIBUTES:  DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED
+PATTERN:    EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0   VL128  W1 UISA_VMODRM_XMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
+OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASKNOT0():rw:mskw MEM0:r:q:f64
 IFORM:       VGATHERDPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128
 }
 
 
-# EMITTING VGATHERDPD (VGATHERDPD-256-1)
+# EMITTING VGATHERDPD (VGATHERDPD-256-2)
 {
 ICLASS:      VGATHERDPD
 CPL:         3
@@ -48670,14 +50617,14 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E12
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT
-PATTERN:    EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL256  W1 RM=4 UISA_VMODRM_XMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
-OPERANDS:    REG0=YMM_R3():w:qq:f64 REG1=MASKNOT0():rw:mskw MEM0:r:qq:f64
+ATTRIBUTES:  DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED
+PATTERN:    EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0   VL256  W1 UISA_VMODRM_XMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
+OPERANDS:    REG0=YMM_R3():w:qq:f64 REG1=MASKNOT0():rw:mskw MEM0:r:q:f64
 IFORM:       VGATHERDPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256
 }
 
 
-# EMITTING VGATHERDPS (VGATHERDPS-128-1)
+# EMITTING VGATHERDPS (VGATHERDPS-128-2)
 {
 ICLASS:      VGATHERDPS
 CPL:         3
@@ -48686,14 +50633,14 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E12
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT
-PATTERN:    EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL128  W0 RM=4 UISA_VMODRM_XMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
-OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASKNOT0():rw:mskw MEM0:r:dq:f32
+ATTRIBUTES:  DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED
+PATTERN:    EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0   VL128  W0 UISA_VMODRM_XMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
+OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASKNOT0():rw:mskw MEM0:r:d:f32
 IFORM:       VGATHERDPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128
 }
 
 
-# EMITTING VGATHERDPS (VGATHERDPS-256-1)
+# EMITTING VGATHERDPS (VGATHERDPS-256-2)
 {
 ICLASS:      VGATHERDPS
 CPL:         3
@@ -48702,14 +50649,14 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E12
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT
-PATTERN:    EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL256  W0 RM=4 UISA_VMODRM_YMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
-OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASKNOT0():rw:mskw MEM0:r:qq:f32
+ATTRIBUTES:  DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED
+PATTERN:    EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0   VL256  W0 UISA_VMODRM_YMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
+OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASKNOT0():rw:mskw MEM0:r:d:f32
 IFORM:       VGATHERDPS_YMMf32_MASKmskw_MEMf32_AVX512_VL256
 }
 
 
-# EMITTING VGATHERQPD (VGATHERQPD-128-1)
+# EMITTING VGATHERQPD (VGATHERQPD-128-2)
 {
 ICLASS:      VGATHERQPD
 CPL:         3
@@ -48718,14 +50665,14 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E12
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT
-PATTERN:    EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL128  W1 RM=4 UISA_VMODRM_XMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
-OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASKNOT0():rw:mskw MEM0:r:dq:f64
+ATTRIBUTES:  GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED
+PATTERN:    EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0   VL128  W1 UISA_VMODRM_XMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
+OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASKNOT0():rw:mskw MEM0:r:q:f64
 IFORM:       VGATHERQPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128
 }
 
 
-# EMITTING VGATHERQPD (VGATHERQPD-256-1)
+# EMITTING VGATHERQPD (VGATHERQPD-256-2)
 {
 ICLASS:      VGATHERQPD
 CPL:         3
@@ -48734,14 +50681,14 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E12
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT
-PATTERN:    EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL256  W1 RM=4 UISA_VMODRM_YMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
-OPERANDS:    REG0=YMM_R3():w:qq:f64 REG1=MASKNOT0():rw:mskw MEM0:r:qq:f64
+ATTRIBUTES:  GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED
+PATTERN:    EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0   VL256  W1 UISA_VMODRM_YMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
+OPERANDS:    REG0=YMM_R3():w:qq:f64 REG1=MASKNOT0():rw:mskw MEM0:r:q:f64
 IFORM:       VGATHERQPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256
 }
 
 
-# EMITTING VGATHERQPS (VGATHERQPS-128-1)
+# EMITTING VGATHERQPS (VGATHERQPS-128-2)
 {
 ICLASS:      VGATHERQPS
 CPL:         3
@@ -48750,14 +50697,14 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E12
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT
-PATTERN:    EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL128  W0 RM=4 UISA_VMODRM_XMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
-OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASKNOT0():rw:mskw MEM0:r:q:f32
+ATTRIBUTES:  GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED
+PATTERN:    EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0   VL128  W0 UISA_VMODRM_XMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
+OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASKNOT0():rw:mskw MEM0:r:d:f32
 IFORM:       VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128
 }
 
 
-# EMITTING VGATHERQPS (VGATHERQPS-256-1)
+# EMITTING VGATHERQPS (VGATHERQPS-256-2)
 {
 ICLASS:      VGATHERQPS
 CPL:         3
@@ -48766,9 +50713,9 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E12
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT
-PATTERN:    EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL256  W0 RM=4 UISA_VMODRM_YMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
-OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASKNOT0():rw:mskw MEM0:r:dq:f32
+ATTRIBUTES:  GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED
+PATTERN:    EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0   VL256  W0 UISA_VMODRM_YMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
+OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASKNOT0():rw:mskw MEM0:r:d:f32
 IFORM:       VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL256
 }
 
@@ -48782,7 +50729,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1  NOEVSR
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
 IFORM:       VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512
@@ -48796,7 +50743,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VGETEXPPD_XMMf64_MASKmskw_MEMf64_AVX512
@@ -48812,7 +50759,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1  NOEVSR
 OPERANDS:    REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
 IFORM:       VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512
@@ -48826,7 +50773,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VGETEXPPD_YMMf64_MASKmskw_MEMf64_AVX512
@@ -48842,7 +50789,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0  NOEVSR
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
 IFORM:       VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512
@@ -48856,7 +50803,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VGETEXPPS_XMMf32_MASKmskw_MEMf32_AVX512
@@ -48872,7 +50819,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0  NOEVSR
 OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
 IFORM:       VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512
@@ -48886,7 +50833,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VGETEXPPS_YMMf32_MASKmskw_MEMf32_AVX512
@@ -48902,7 +50849,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1  NOEVSR UIMM8()
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 IMM0:r:b
 IFORM:       VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512
@@ -48916,7 +50863,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1  NOEVSR UIMM8()  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
 IFORM:       VGETMANTPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512
@@ -48932,7 +50879,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1  NOEVSR UIMM8()
 OPERANDS:    REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 IMM0:r:b
 IFORM:       VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512
@@ -48946,7 +50893,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1  NOEVSR UIMM8()  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
 IFORM:       VGETMANTPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512
@@ -48962,7 +50909,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0  NOEVSR UIMM8()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 IMM0:r:b
 IFORM:       VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512
@@ -48976,7 +50923,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0  NOEVSR UIMM8()  ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
 IFORM:       VGETMANTPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512
@@ -48992,7 +50939,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0  NOEVSR UIMM8()
 OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 IMM0:r:b
 IFORM:       VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512
@@ -49006,7 +50953,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0  NOEVSR UIMM8()  ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
 IFORM:       VGETMANTPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512
@@ -49262,7 +51209,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -49276,7 +51223,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x5F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
@@ -49292,7 +51239,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1
 OPERANDS:    REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
 IFORM:       VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
@@ -49306,7 +51253,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x5F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
@@ -49322,7 +51269,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5F VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -49336,7 +51283,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x5F VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
@@ -49352,7 +51299,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5F VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0
 OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
 IFORM:       VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
@@ -49366,7 +51313,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x5F VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
@@ -49382,7 +51329,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -49396,7 +51343,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x5D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VMINPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
@@ -49412,7 +51359,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1
 OPERANDS:    REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
 IFORM:       VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
@@ -49426,7 +51373,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x5D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VMINPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
@@ -49442,7 +51389,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5D VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -49456,7 +51403,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x5D VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VMINPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
@@ -49472,7 +51419,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5D VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0
 OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
 IFORM:       VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
@@ -49486,7 +51433,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x5D VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VMINPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
@@ -49516,7 +51463,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E1
 REAL_OPCODE: Y
-ATTRIBUTES:   REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM
 PATTERN:    EVV 0x28 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULLMEM()
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f64
 IFORM:       VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512
@@ -49548,7 +51495,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E1
 REAL_OPCODE: Y
-ATTRIBUTES:   REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM
 PATTERN:    EVV 0x29 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W1  NOEVSR  ZEROING=0  ESIZE_64_BITS() NELEM_FULLMEM()
 OPERANDS:    MEM0:w:dq:f64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f64
 IFORM:       VMOVAPD_MEMf64_MASKmskw_XMMf64_AVX512
@@ -49578,7 +51525,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E1
 REAL_OPCODE: Y
-ATTRIBUTES:   REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM
 PATTERN:    EVV 0x28 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULLMEM()
 OPERANDS:    REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f64
 IFORM:       VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512
@@ -49610,7 +51557,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E1
 REAL_OPCODE: Y
-ATTRIBUTES:   REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM
 PATTERN:    EVV 0x29 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W1  NOEVSR  ZEROING=0  ESIZE_64_BITS() NELEM_FULLMEM()
 OPERANDS:    MEM0:w:qq:f64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f64
 IFORM:       VMOVAPD_MEMf64_MASKmskw_YMMf64_AVX512
@@ -49640,7 +51587,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E1
 REAL_OPCODE: Y
-ATTRIBUTES:   REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM
 PATTERN:    EVV 0x28 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULLMEM()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32
 IFORM:       VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512
@@ -49672,7 +51619,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E1
 REAL_OPCODE: Y
-ATTRIBUTES:   REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM
 PATTERN:    EVV 0x29 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0  NOEVSR  ZEROING=0  ESIZE_32_BITS() NELEM_FULLMEM()
 OPERANDS:    MEM0:w:dq:f32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f32
 IFORM:       VMOVAPS_MEMf32_MASKmskw_XMMf32_AVX512
@@ -49702,7 +51649,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E1
 REAL_OPCODE: Y
-ATTRIBUTES:   REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM
 PATTERN:    EVV 0x28 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULLMEM()
 OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32
 IFORM:       VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512
@@ -49734,7 +51681,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E1
 REAL_OPCODE: Y
-ATTRIBUTES:   REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM
 PATTERN:    EVV 0x29 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W0  NOEVSR  ZEROING=0  ESIZE_32_BITS() NELEM_FULLMEM()
 OPERANDS:    MEM0:w:qq:f32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f32
 IFORM:       VMOVAPS_MEMf32_MASKmskw_YMMf32_AVX512
@@ -49824,7 +51771,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E1
 REAL_OPCODE: Y
-ATTRIBUTES:   REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM
 PATTERN:    EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULLMEM()
 OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u32
 IFORM:       VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512
@@ -49856,7 +51803,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E1
 REAL_OPCODE: Y
-ATTRIBUTES:   REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM
 PATTERN:    EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0  NOEVSR  ZEROING=0  ESIZE_32_BITS() NELEM_FULLMEM()
 OPERANDS:    MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32
 IFORM:       VMOVDQA32_MEMu32_MASKmskw_XMMu32_AVX512
@@ -49886,7 +51833,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E1
 REAL_OPCODE: Y
-ATTRIBUTES:   REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM
 PATTERN:    EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULLMEM()
 OPERANDS:    REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u32
 IFORM:       VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512
@@ -49918,7 +51865,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E1
 REAL_OPCODE: Y
-ATTRIBUTES:   REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM
 PATTERN:    EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W0  NOEVSR  ZEROING=0  ESIZE_32_BITS() NELEM_FULLMEM()
 OPERANDS:    MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32
 IFORM:       VMOVDQA32_MEMu32_MASKmskw_YMMu32_AVX512
@@ -49948,7 +51895,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E1
 REAL_OPCODE: Y
-ATTRIBUTES:   REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM
 PATTERN:    EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULLMEM()
 OPERANDS:    REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u64
 IFORM:       VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512
@@ -49980,7 +51927,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E1
 REAL_OPCODE: Y
-ATTRIBUTES:   REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM
 PATTERN:    EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W1  NOEVSR  ZEROING=0  ESIZE_64_BITS() NELEM_FULLMEM()
 OPERANDS:    MEM0:w:dq:u64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64
 IFORM:       VMOVDQA64_MEMu64_MASKmskw_XMMu64_AVX512
@@ -50010,7 +51957,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E1
 REAL_OPCODE: Y
-ATTRIBUTES:   REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM
 PATTERN:    EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULLMEM()
 OPERANDS:    REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u64
 IFORM:       VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512
@@ -50042,7 +51989,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E1
 REAL_OPCODE: Y
-ATTRIBUTES:   REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM
 PATTERN:    EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W1  NOEVSR  ZEROING=0  ESIZE_64_BITS() NELEM_FULLMEM()
 OPERANDS:    MEM0:w:qq:u64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64
 IFORM:       VMOVDQA64_MEMu64_MASKmskw_YMMu64_AVX512
@@ -50678,7 +52625,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E1NF
 REAL_OPCODE: Y
-ATTRIBUTES:  NOTSX  REQUIRES_ALIGNMENT DISP8_FULLMEM
+ATTRIBUTES:  NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM
 PATTERN:    EVV 0xE7 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0  NOEVSR  ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_FULLMEM()
 OPERANDS:    MEM0:w:dq:u32 REG0=XMM_R3():r:dq:u32
 IFORM:       VMOVNTDQ_MEMu32_XMMu32_AVX512
@@ -50694,7 +52641,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E1NF
 REAL_OPCODE: Y
-ATTRIBUTES:  NOTSX  REQUIRES_ALIGNMENT DISP8_FULLMEM
+ATTRIBUTES:  NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM
 PATTERN:    EVV 0xE7 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W0  NOEVSR  ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_FULLMEM()
 OPERANDS:    MEM0:w:qq:u32 REG0=YMM_R3():r:qq:u32
 IFORM:       VMOVNTDQ_MEMu32_YMMu32_AVX512
@@ -50710,7 +52657,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E1NF
 REAL_OPCODE: Y
-ATTRIBUTES:  NOTSX  REQUIRES_ALIGNMENT DISP8_FULLMEM
+ATTRIBUTES:  NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM
 PATTERN:    EVV 0x2A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0  NOEVSR  ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_FULLMEM()
 OPERANDS:    REG0=XMM_R3():w:dq:u32 MEM0:r:dq:u32
 IFORM:       VMOVNTDQA_XMMu32_MEMu32_AVX512
@@ -50726,7 +52673,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E1NF
 REAL_OPCODE: Y
-ATTRIBUTES:  NOTSX  REQUIRES_ALIGNMENT DISP8_FULLMEM
+ATTRIBUTES:  NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM
 PATTERN:    EVV 0x2A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W0  NOEVSR  ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_FULLMEM()
 OPERANDS:    REG0=YMM_R3():w:qq:u32 MEM0:r:qq:u32
 IFORM:       VMOVNTDQA_YMMu32_MEMu32_AVX512
@@ -50742,7 +52689,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E1NF
 REAL_OPCODE: Y
-ATTRIBUTES:  NOTSX  REQUIRES_ALIGNMENT DISP8_FULLMEM
+ATTRIBUTES:  NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM
 PATTERN:    EVV 0x2B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W1  NOEVSR  ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_FULLMEM()
 OPERANDS:    MEM0:w:dq:f64 REG0=XMM_R3():r:dq:f64
 IFORM:       VMOVNTPD_MEMf64_XMMf64_AVX512
@@ -50758,7 +52705,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E1NF
 REAL_OPCODE: Y
-ATTRIBUTES:  NOTSX  REQUIRES_ALIGNMENT DISP8_FULLMEM
+ATTRIBUTES:  NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM
 PATTERN:    EVV 0x2B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W1  NOEVSR  ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_FULLMEM()
 OPERANDS:    MEM0:w:qq:f64 REG0=YMM_R3():r:qq:f64
 IFORM:       VMOVNTPD_MEMf64_YMMf64_AVX512
@@ -50774,7 +52721,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E1NF
 REAL_OPCODE: Y
-ATTRIBUTES:  NOTSX  REQUIRES_ALIGNMENT DISP8_FULLMEM
+ATTRIBUTES:  NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM
 PATTERN:    EVV 0x2B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0  NOEVSR  ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_FULLMEM()
 OPERANDS:    MEM0:w:dq:f32 REG0=XMM_R3():r:dq:f32
 IFORM:       VMOVNTPS_MEMf32_XMMf32_AVX512
@@ -50790,7 +52737,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E1NF
 REAL_OPCODE: Y
-ATTRIBUTES:  NOTSX  REQUIRES_ALIGNMENT DISP8_FULLMEM
+ATTRIBUTES:  NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM
 PATTERN:    EVV 0x2B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W0  NOEVSR  ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_FULLMEM()
 OPERANDS:    MEM0:w:qq:f32 REG0=YMM_R3():r:qq:f32
 IFORM:       VMOVNTPS_MEMf32_YMMf32_AVX512
@@ -51174,7 +53121,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x59 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -51188,7 +53135,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x59 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VMULPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
@@ -51204,7 +53151,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x59 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1
 OPERANDS:    REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
 IFORM:       VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
@@ -51218,7 +53165,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x59 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VMULPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
@@ -51234,7 +53181,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x59 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -51248,7 +53195,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x59 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VMULPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
@@ -51264,7 +53211,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x59 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0
 OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
 IFORM:       VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
@@ -51278,7 +53225,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x59 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VMULPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
@@ -51296,8 +53243,8 @@ EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX
 PATTERN:    EVV 0x56 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1
-OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
-IFORM:       VORPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
+OPERANDS:    REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
+IFORM:       VORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
 }
 
 {
@@ -51310,8 +53257,8 @@ EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
 PATTERN:    EVV 0x56 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1    ESIZE_64_BITS() NELEM_FULL()
-OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
-IFORM:       VORPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
+OPERANDS:    REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
+IFORM:       VORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
 }
 
 
@@ -51326,8 +53273,8 @@ EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX
 PATTERN:    EVV 0x56 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1
-OPERANDS:    REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
-IFORM:       VORPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
+OPERANDS:    REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
+IFORM:       VORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
 }
 
 {
@@ -51340,8 +53287,8 @@ EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
 PATTERN:    EVV 0x56 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1    ESIZE_64_BITS() NELEM_FULL()
-OPERANDS:    REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
-IFORM:       VORPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
+OPERANDS:    REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
+IFORM:       VORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
 }
 
 
@@ -51356,8 +53303,8 @@ EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX
 PATTERN:    EVV 0x56 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1
-OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
-IFORM:       VORPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
+OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
+IFORM:       VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
 }
 
 {
@@ -51370,8 +53317,8 @@ EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
 PATTERN:    EVV 0x56 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
-OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
-IFORM:       VORPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
+OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
+IFORM:       VORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
 }
 
 
@@ -51386,8 +53333,8 @@ EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX
 PATTERN:    EVV 0x56 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0
-OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
-IFORM:       VORPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
+OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
+IFORM:       VORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
 }
 
 {
@@ -51400,8 +53347,8 @@ EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
 PATTERN:    EVV 0x56 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_32_BITS() NELEM_FULL()
-OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
-IFORM:       VORPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
+OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
+IFORM:       VORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
 }
 
 
@@ -51416,8 +53363,8 @@ EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX
 PATTERN:    EVV 0x56 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0
-OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
-IFORM:       VORPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
+OPERANDS:    REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
+IFORM:       VORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
 }
 
 {
@@ -51430,8 +53377,8 @@ EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
 PATTERN:    EVV 0x56 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_32_BITS() NELEM_FULL()
-OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
-IFORM:       VORPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
+OPERANDS:    REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
+IFORM:       VORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
 }
 
 
@@ -51446,8 +53393,8 @@ EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX
 PATTERN:    EVV 0x56 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0
-OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
-IFORM:       VORPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
+OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
+IFORM:       VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
 }
 
 {
@@ -51460,8 +53407,8 @@ EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
 PATTERN:    EVV 0x56 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
-OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
-IFORM:       VORPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
+OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
+IFORM:       VORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
 }
 
 
@@ -53318,7 +55265,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512BW_128
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULLMEM
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM MASK_AS_CONTROL
 PATTERN:    EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0    ESIZE_8_BITS() NELEM_FULLMEM()
 OPERANDS:    REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8
 IFORM:       VPBLENDMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512
@@ -53348,7 +55295,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512BW_256
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULLMEM
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM MASK_AS_CONTROL
 PATTERN:    EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W0    ESIZE_8_BITS() NELEM_FULLMEM()
 OPERANDS:    REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8
 IFORM:       VPBLENDMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512
@@ -53378,7 +55325,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512BW_512
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULLMEM
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM MASK_AS_CONTROL
 PATTERN:    EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0    ESIZE_8_BITS() NELEM_FULLMEM()
 OPERANDS:    REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8
 IFORM:       VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512
@@ -53408,7 +55355,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL
 PATTERN:    EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
 IFORM:       VPBLENDMD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
@@ -53438,7 +55385,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL
 PATTERN:    EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
 IFORM:       VPBLENDMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
@@ -53468,7 +55415,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL
 PATTERN:    EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
 IFORM:       VPBLENDMQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
@@ -53498,7 +55445,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL
 PATTERN:    EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
 IFORM:       VPBLENDMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
@@ -53528,7 +55475,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512BW_128
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULLMEM
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM MASK_AS_CONTROL
 PATTERN:    EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W1    ESIZE_16_BITS() NELEM_FULLMEM()
 OPERANDS:    REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
 IFORM:       VPBLENDMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
@@ -53558,7 +55505,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512BW_256
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULLMEM
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM MASK_AS_CONTROL
 PATTERN:    EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W1    ESIZE_16_BITS() NELEM_FULLMEM()
 OPERANDS:    REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
 IFORM:       VPBLENDMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
@@ -53588,7 +55535,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512BW_512
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULLMEM
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM MASK_AS_CONTROL
 PATTERN:    EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W1    ESIZE_16_BITS() NELEM_FULLMEM()
 OPERANDS:    REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
 IFORM:       VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
@@ -53775,7 +55722,10 @@ ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E7NM
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX
-PATTERN:    EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0  NOEVSR
+PATTERN:    EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  not64  NOEVSR
+OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO4_32
+IFORM:       VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512
+PATTERN:    EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  mode64 W0  NOEVSR
 OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO4_32
 IFORM:       VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512
 }
@@ -53823,7 +55773,10 @@ ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E7NM
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX
-PATTERN:    EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0  NOEVSR
+PATTERN:    EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  not64  NOEVSR
+OPERANDS:    REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO8_32
+IFORM:       VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512
+PATTERN:    EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  mode64 W0  NOEVSR
 OPERANDS:    REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO8_32
 IFORM:       VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512
 }
@@ -55332,7 +57285,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
 PATTERN:    EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0  NOEVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
 OPERANDS:    MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32
 IFORM:       VPCOMPRESSD_MEMu32_MASKmskw_XMMu32_AVX512
@@ -55364,7 +57317,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
 PATTERN:    EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W0  NOEVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
 OPERANDS:    MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32
 IFORM:       VPCOMPRESSD_MEMu32_MASKmskw_YMMu32_AVX512
@@ -55396,7 +57349,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
 PATTERN:    EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W1  NOEVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
 OPERANDS:    MEM0:w:dq:u64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64
 IFORM:       VPCOMPRESSQ_MEMu64_MASKmskw_XMMu64_AVX512
@@ -55428,7 +57381,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
 PATTERN:    EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W1  NOEVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
 OPERANDS:    MEM0:w:qq:u64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64
 IFORM:       VPCOMPRESSQ_MEMu64_MASKmskw_YMMu64_AVX512
@@ -55458,7 +57411,7 @@ CPL:         3
 CATEGORY:    CONFLICT
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512CD_128
-EXCEPTIONS:     AVX512-E4
+EXCEPTIONS:     AVX512-E4NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX
 PATTERN:    EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0  NOEVSR
@@ -55472,7 +57425,7 @@ CPL:         3
 CATEGORY:    CONFLICT
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512CD_128
-EXCEPTIONS:     AVX512-E4
+EXCEPTIONS:     AVX512-E4NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
 PATTERN:    EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL()
@@ -55488,7 +57441,7 @@ CPL:         3
 CATEGORY:    CONFLICT
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512CD_256
-EXCEPTIONS:     AVX512-E4
+EXCEPTIONS:     AVX512-E4NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX
 PATTERN:    EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0  NOEVSR
@@ -55502,7 +57455,7 @@ CPL:         3
 CATEGORY:    CONFLICT
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512CD_256
-EXCEPTIONS:     AVX512-E4
+EXCEPTIONS:     AVX512-E4NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
 PATTERN:    EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL()
@@ -55518,7 +57471,7 @@ CPL:         3
 CATEGORY:    CONFLICT
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512CD_128
-EXCEPTIONS:     AVX512-E4
+EXCEPTIONS:     AVX512-E4NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX
 PATTERN:    EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1  NOEVSR
@@ -55532,7 +57485,7 @@ CPL:         3
 CATEGORY:    CONFLICT
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512CD_128
-EXCEPTIONS:     AVX512-E4
+EXCEPTIONS:     AVX512-E4NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
 PATTERN:    EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
@@ -55548,7 +57501,7 @@ CPL:         3
 CATEGORY:    CONFLICT
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512CD_256
-EXCEPTIONS:     AVX512-E4
+EXCEPTIONS:     AVX512-E4NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX
 PATTERN:    EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1  NOEVSR
@@ -55562,7 +57515,7 @@ CPL:         3
 CATEGORY:    CONFLICT
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512CD_256
-EXCEPTIONS:     AVX512-E4
+EXCEPTIONS:     AVX512-E4NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
 PATTERN:    EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
@@ -56750,7 +58703,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
 PATTERN:    EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0  NOEVSR  ESIZE_32_BITS() NELEM_GSCAT()
 OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u32
 IFORM:       VPEXPANDD_XMMu32_MASKmskw_MEMu32_AVX512
@@ -56782,7 +58735,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
 PATTERN:    EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W0  NOEVSR  ESIZE_32_BITS() NELEM_GSCAT()
 OPERANDS:    REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u32
 IFORM:       VPEXPANDD_YMMu32_MASKmskw_MEMu32_AVX512
@@ -56814,7 +58767,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
 PATTERN:    EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W1  NOEVSR  ESIZE_64_BITS() NELEM_GSCAT()
 OPERANDS:    REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u64
 IFORM:       VPEXPANDQ_XMMu64_MASKmskw_MEMu64_AVX512
@@ -56846,7 +58799,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
 PATTERN:    EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W1  NOEVSR  ESIZE_64_BITS() NELEM_GSCAT()
 OPERANDS:    REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u64
 IFORM:       VPEXPANDQ_YMMu64_MASKmskw_MEMu64_AVX512
@@ -56907,7 +58860,10 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_128N
 EXCEPTIONS:     AVX512-E9NF
 REAL_OPCODE: Y
-PATTERN:    EVV 0x16 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0  NOEVSR  ZEROING=0 MASK=0 UIMM8()
+PATTERN:    EVV 0x16 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  not64  NOEVSR  ZEROING=0 MASK=0 UIMM8()
+OPERANDS:    REG0=GPR32_B():w:d:u32 REG1=XMM_R3():r:dq:u32 IMM0:r:b
+IFORM:       VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512
+PATTERN:    EVV 0x16 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  mode64 W0  NOEVSR  ZEROING=0 MASK=0 UIMM8()
 OPERANDS:    REG0=GPR32_B():w:d:u32 REG1=XMM_R3():r:dq:u32 IMM0:r:b
 IFORM:       VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512
 }
@@ -56921,7 +58877,10 @@ ISA_SET:     AVX512DQ_128N
 EXCEPTIONS:     AVX512-E9NF
 REAL_OPCODE: Y
 ATTRIBUTES:  DISP8_GPR_WRITER_STORE
-PATTERN:    EVV 0x16 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0  NOEVSR  ZEROING=0 MASK=0 UIMM8()  ESIZE_32_BITS() NELEM_GPR_WRITER_STORE()
+PATTERN:    EVV 0x16 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  not64  NOEVSR  ZEROING=0 MASK=0 UIMM8()  ESIZE_32_BITS() NELEM_GPR_WRITER_STORE()
+OPERANDS:    MEM0:w:d:u32 REG0=XMM_R3():r:dq:u32 IMM0:r:b
+IFORM:       VPEXTRD_MEMu32_XMMu32_IMM8_AVX512
+PATTERN:    EVV 0x16 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  mode64 W0  NOEVSR  ZEROING=0 MASK=0 UIMM8()  ESIZE_32_BITS() NELEM_GPR_WRITER_STORE()
 OPERANDS:    MEM0:w:d:u32 REG0=XMM_R3():r:dq:u32 IMM0:r:b
 IFORM:       VPEXTRD_MEMu32_XMMu32_IMM8_AVX512
 }
@@ -56987,20 +58946,26 @@ IFORM:       VPEXTRW_MEMu16_XMMu16_IMM8_AVX512
 
 # EMITTING VPEXTRW (VPEXTRW-128-2)
 {
-ICLASS:      VPEXTRW
+ICLASS:      VPEXTRW_C5
+DISASM:      vpextrw
 CPL:         3
 CATEGORY:    AVX512
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512BW_128N
 EXCEPTIONS:     AVX512-E9NF
 REAL_OPCODE: Y
-PATTERN:    EVV 0xC5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128    NOEVSR  ZEROING=0 MASK=0 UIMM8()
+
+PATTERN:    EVV 0xC5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128    NOEVSR  ZEROING=0 MASK=0 UIMM8() not64
 OPERANDS:    REG0=GPR32_R():w:d:u16 REG1=XMM_B3():r:dq:u16 IMM0:r:b
-IFORM:       VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512
+IFORM:       VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_C5
+
+PATTERN:    EVV 0xC5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128    NOEVSR  ZEROING=0 MASK=0 UIMM8() mode64 EVEXRR_ONE
+OPERANDS:    REG0=GPR32_R():w:d:u16 REG1=XMM_B3():r:dq:u16 IMM0:r:b
+IFORM:       VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_C5
 }
 
 
-# EMITTING VPGATHERDD (VPGATHERDD-128-1)
+# EMITTING VPGATHERDD (VPGATHERDD-128-2)
 {
 ICLASS:      VPGATHERDD
 CPL:         3
@@ -57009,14 +58974,14 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E12
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT
-PATTERN:    EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL128  W0 RM=4 UISA_VMODRM_XMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
-OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=MASKNOT0():rw:mskw MEM0:r:dq:u32
+ATTRIBUTES:  DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED
+PATTERN:    EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0   VL128  W0 UISA_VMODRM_XMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
+OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=MASKNOT0():rw:mskw MEM0:r:d:u32
 IFORM:       VPGATHERDD_XMMu32_MASKmskw_MEMu32_AVX512_VL128
 }
 
 
-# EMITTING VPGATHERDD (VPGATHERDD-256-1)
+# EMITTING VPGATHERDD (VPGATHERDD-256-2)
 {
 ICLASS:      VPGATHERDD
 CPL:         3
@@ -57025,14 +58990,14 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E12
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT
-PATTERN:    EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL256  W0 RM=4 UISA_VMODRM_YMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
-OPERANDS:    REG0=YMM_R3():w:qq:u32 REG1=MASKNOT0():rw:mskw MEM0:r:qq:u32
+ATTRIBUTES:  DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED
+PATTERN:    EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0   VL256  W0 UISA_VMODRM_YMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
+OPERANDS:    REG0=YMM_R3():w:qq:u32 REG1=MASKNOT0():rw:mskw MEM0:r:d:u32
 IFORM:       VPGATHERDD_YMMu32_MASKmskw_MEMu32_AVX512_VL256
 }
 
 
-# EMITTING VPGATHERDQ (VPGATHERDQ-128-1)
+# EMITTING VPGATHERDQ (VPGATHERDQ-128-2)
 {
 ICLASS:      VPGATHERDQ
 CPL:         3
@@ -57041,14 +59006,14 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E12
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT
-PATTERN:    EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL128  W1 RM=4 UISA_VMODRM_XMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
-OPERANDS:    REG0=XMM_R3():w:dq:u64 REG1=MASKNOT0():rw:mskw MEM0:r:dq:u64
+ATTRIBUTES:  DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED
+PATTERN:    EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0   VL128  W1 UISA_VMODRM_XMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
+OPERANDS:    REG0=XMM_R3():w:dq:u64 REG1=MASKNOT0():rw:mskw MEM0:r:q:u64
 IFORM:       VPGATHERDQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128
 }
 
 
-# EMITTING VPGATHERDQ (VPGATHERDQ-256-1)
+# EMITTING VPGATHERDQ (VPGATHERDQ-256-2)
 {
 ICLASS:      VPGATHERDQ
 CPL:         3
@@ -57057,14 +59022,14 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E12
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT
-PATTERN:    EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL256  W1 RM=4 UISA_VMODRM_XMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
-OPERANDS:    REG0=YMM_R3():w:qq:u64 REG1=MASKNOT0():rw:mskw MEM0:r:qq:u64
+ATTRIBUTES:  DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED
+PATTERN:    EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0   VL256  W1 UISA_VMODRM_XMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
+OPERANDS:    REG0=YMM_R3():w:qq:u64 REG1=MASKNOT0():rw:mskw MEM0:r:q:u64
 IFORM:       VPGATHERDQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256
 }
 
 
-# EMITTING VPGATHERQD (VPGATHERQD-128-1)
+# EMITTING VPGATHERQD (VPGATHERQD-128-2)
 {
 ICLASS:      VPGATHERQD
 CPL:         3
@@ -57073,14 +59038,14 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E12
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT
-PATTERN:    EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL128  W0 RM=4 UISA_VMODRM_XMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
-OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=MASKNOT0():rw:mskw MEM0:r:q:u32
+ATTRIBUTES:  GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED
+PATTERN:    EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0   VL128  W0 UISA_VMODRM_XMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
+OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=MASKNOT0():rw:mskw MEM0:r:d:u32
 IFORM:       VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL128
 }
 
 
-# EMITTING VPGATHERQD (VPGATHERQD-256-1)
+# EMITTING VPGATHERQD (VPGATHERQD-256-2)
 {
 ICLASS:      VPGATHERQD
 CPL:         3
@@ -57089,14 +59054,14 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E12
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT
-PATTERN:    EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL256  W0 RM=4 UISA_VMODRM_YMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
-OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=MASKNOT0():rw:mskw MEM0:r:dq:u32
+ATTRIBUTES:  GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED
+PATTERN:    EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0   VL256  W0 UISA_VMODRM_YMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
+OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=MASKNOT0():rw:mskw MEM0:r:d:u32
 IFORM:       VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL256
 }
 
 
-# EMITTING VPGATHERQQ (VPGATHERQQ-128-1)
+# EMITTING VPGATHERQQ (VPGATHERQQ-128-2)
 {
 ICLASS:      VPGATHERQQ
 CPL:         3
@@ -57105,14 +59070,14 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E12
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT
-PATTERN:    EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL128  W1 RM=4 UISA_VMODRM_XMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
-OPERANDS:    REG0=XMM_R3():w:dq:u64 REG1=MASKNOT0():rw:mskw MEM0:r:dq:u64
+ATTRIBUTES:  GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED
+PATTERN:    EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0   VL128  W1 UISA_VMODRM_XMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
+OPERANDS:    REG0=XMM_R3():w:dq:u64 REG1=MASKNOT0():rw:mskw MEM0:r:q:u64
 IFORM:       VPGATHERQQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128
 }
 
 
-# EMITTING VPGATHERQQ (VPGATHERQQ-256-1)
+# EMITTING VPGATHERQQ (VPGATHERQQ-256-2)
 {
 ICLASS:      VPGATHERQQ
 CPL:         3
@@ -57121,9 +59086,9 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E12
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT
-PATTERN:    EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL256  W1 RM=4 UISA_VMODRM_YMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
-OPERANDS:    REG0=YMM_R3():w:qq:u64 REG1=MASKNOT0():rw:mskw MEM0:r:qq:u64
+ATTRIBUTES:  GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED
+PATTERN:    EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0   VL256  W1 UISA_VMODRM_YMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
+OPERANDS:    REG0=YMM_R3():w:qq:u64 REG1=MASKNOT0():rw:mskw MEM0:r:q:u64
 IFORM:       VPGATHERQQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256
 }
 
@@ -57166,7 +59131,10 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_128N
 EXCEPTIONS:     AVX512-E9NF
 REAL_OPCODE: Y
-PATTERN:    EVV 0x22 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0    ZEROING=0 MASK=0 UIMM8()
+PATTERN:    EVV 0x22 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  not64    ZEROING=0 MASK=0 UIMM8()
+OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=XMM_N3():r:dq:u32 REG2=GPR32_B():r:d:u32 IMM0:r:b
+IFORM:       VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512
+PATTERN:    EVV 0x22 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  mode64 W0    ZEROING=0 MASK=0 UIMM8()
 OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=XMM_N3():r:dq:u32 REG2=GPR32_B():r:d:u32 IMM0:r:b
 IFORM:       VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512
 }
@@ -57180,7 +59148,10 @@ ISA_SET:     AVX512DQ_128N
 EXCEPTIONS:     AVX512-E9NF
 REAL_OPCODE: Y
 ATTRIBUTES:  DISP8_GPR_READER
-PATTERN:    EVV 0x22 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0    ZEROING=0 MASK=0 UIMM8()  ESIZE_32_BITS() NELEM_GPR_READER()
+PATTERN:    EVV 0x22 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  not64    ZEROING=0 MASK=0 UIMM8()  ESIZE_32_BITS() NELEM_GPR_READER()
+OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=XMM_N3():r:dq:u32 MEM0:r:d:u32 IMM0:r:b
+IFORM:       VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512
+PATTERN:    EVV 0x22 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  mode64 W0    ZEROING=0 MASK=0 UIMM8()  ESIZE_32_BITS() NELEM_GPR_READER()
 OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=XMM_N3():r:dq:u32 MEM0:r:d:u32 IMM0:r:b
 IFORM:       VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512
 }
@@ -58857,7 +60828,7 @@ CPL:         3
 CATEGORY:    DATAXFER
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
-EXCEPTIONS:     AVX512-E6NF
+EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
 PATTERN:    EVV 0x31 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0  NOEVSR  ZEROING=0  ESIZE_8_BITS() NELEM_QUARTERMEM()
@@ -58889,7 +60860,7 @@ CPL:         3
 CATEGORY:    DATAXFER
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
-EXCEPTIONS:     AVX512-E6NF
+EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
 PATTERN:    EVV 0x31 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W0  NOEVSR  ZEROING=0  ESIZE_8_BITS() NELEM_QUARTERMEM()
@@ -58921,7 +60892,7 @@ CPL:         3
 CATEGORY:    DATAXFER
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
-EXCEPTIONS:     AVX512-E6NF
+EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
 PATTERN:    EVV 0x33 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0  NOEVSR  ZEROING=0  ESIZE_16_BITS() NELEM_HALFMEM()
@@ -58953,7 +60924,7 @@ CPL:         3
 CATEGORY:    DATAXFER
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
-EXCEPTIONS:     AVX512-E6NF
+EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
 PATTERN:    EVV 0x33 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W0  NOEVSR  ZEROING=0  ESIZE_16_BITS() NELEM_HALFMEM()
@@ -59210,7 +61181,7 @@ CPL:         3
 CATEGORY:    DATAXFER
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
-EXCEPTIONS:     AVX512-E6NF
+EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM
 PATTERN:    EVV 0x32 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0  NOEVSR  ZEROING=0  ESIZE_8_BITS() NELEM_EIGHTHMEM()
@@ -59242,7 +61213,7 @@ CPL:         3
 CATEGORY:    DATAXFER
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
-EXCEPTIONS:     AVX512-E6NF
+EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM
 PATTERN:    EVV 0x32 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W0  NOEVSR  ZEROING=0  ESIZE_8_BITS() NELEM_EIGHTHMEM()
@@ -59274,7 +61245,7 @@ CPL:         3
 CATEGORY:    DATAXFER
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
-EXCEPTIONS:     AVX512-E6NF
+EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
 PATTERN:    EVV 0x35 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0  NOEVSR  ZEROING=0  ESIZE_32_BITS() NELEM_HALFMEM()
@@ -59306,7 +61277,7 @@ CPL:         3
 CATEGORY:    DATAXFER
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
-EXCEPTIONS:     AVX512-E6NF
+EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
 PATTERN:    EVV 0x35 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W0  NOEVSR  ZEROING=0  ESIZE_32_BITS() NELEM_HALFMEM()
@@ -59338,7 +61309,7 @@ CPL:         3
 CATEGORY:    DATAXFER
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
-EXCEPTIONS:     AVX512-E6NF
+EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
 PATTERN:    EVV 0x34 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0  NOEVSR  ZEROING=0  ESIZE_16_BITS() NELEM_QUARTERMEM()
@@ -59370,7 +61341,7 @@ CPL:         3
 CATEGORY:    DATAXFER
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
-EXCEPTIONS:     AVX512-E6NF
+EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
 PATTERN:    EVV 0x34 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W0  NOEVSR  ZEROING=0  ESIZE_16_BITS() NELEM_QUARTERMEM()
@@ -59402,7 +61373,7 @@ CPL:         3
 CATEGORY:    DATAXFER
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
-EXCEPTIONS:     AVX512-E6NF
+EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
 PATTERN:    EVV 0x21 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0  NOEVSR  ZEROING=0  ESIZE_8_BITS() NELEM_QUARTERMEM()
@@ -59434,7 +61405,7 @@ CPL:         3
 CATEGORY:    DATAXFER
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
-EXCEPTIONS:     AVX512-E6NF
+EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
 PATTERN:    EVV 0x21 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W0  NOEVSR  ZEROING=0  ESIZE_8_BITS() NELEM_QUARTERMEM()
@@ -59466,7 +61437,7 @@ CPL:         3
 CATEGORY:    DATAXFER
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
-EXCEPTIONS:     AVX512-E6NF
+EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
 PATTERN:    EVV 0x23 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0  NOEVSR  ZEROING=0  ESIZE_16_BITS() NELEM_HALFMEM()
@@ -59498,7 +61469,7 @@ CPL:         3
 CATEGORY:    DATAXFER
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
-EXCEPTIONS:     AVX512-E6NF
+EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
 PATTERN:    EVV 0x23 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W0  NOEVSR  ZEROING=0  ESIZE_16_BITS() NELEM_HALFMEM()
@@ -59530,7 +61501,7 @@ CPL:         3
 CATEGORY:    DATAXFER
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
-EXCEPTIONS:     AVX512-E6NF
+EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM
 PATTERN:    EVV 0x22 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0  NOEVSR  ZEROING=0  ESIZE_8_BITS() NELEM_EIGHTHMEM()
@@ -59562,7 +61533,7 @@ CPL:         3
 CATEGORY:    DATAXFER
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
-EXCEPTIONS:     AVX512-E6NF
+EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM
 PATTERN:    EVV 0x22 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W0  NOEVSR  ZEROING=0  ESIZE_8_BITS() NELEM_EIGHTHMEM()
@@ -59594,7 +61565,7 @@ CPL:         3
 CATEGORY:    DATAXFER
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
-EXCEPTIONS:     AVX512-E6NF
+EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
 PATTERN:    EVV 0x25 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0  NOEVSR  ZEROING=0  ESIZE_32_BITS() NELEM_HALFMEM()
@@ -59626,7 +61597,7 @@ CPL:         3
 CATEGORY:    DATAXFER
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
-EXCEPTIONS:     AVX512-E6NF
+EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
 PATTERN:    EVV 0x25 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W0  NOEVSR  ZEROING=0  ESIZE_32_BITS() NELEM_HALFMEM()
@@ -59658,7 +61629,7 @@ CPL:         3
 CATEGORY:    DATAXFER
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
-EXCEPTIONS:     AVX512-E6NF
+EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
 PATTERN:    EVV 0x24 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0  NOEVSR  ZEROING=0  ESIZE_16_BITS() NELEM_QUARTERMEM()
@@ -59690,7 +61661,7 @@ CPL:         3
 CATEGORY:    DATAXFER
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
-EXCEPTIONS:     AVX512-E6NF
+EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
 PATTERN:    EVV 0x24 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W0  NOEVSR  ZEROING=0  ESIZE_16_BITS() NELEM_QUARTERMEM()
@@ -59722,7 +61693,7 @@ CPL:         3
 CATEGORY:    DATAXFER
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512BW_128
-EXCEPTIONS:     AVX512-E6NF
+EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
 PATTERN:    EVV 0x20 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0  NOEVSR  ZEROING=0  ESIZE_8_BITS() NELEM_HALFMEM()
@@ -59754,7 +61725,7 @@ CPL:         3
 CATEGORY:    DATAXFER
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512BW_256
-EXCEPTIONS:     AVX512-E6NF
+EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
 PATTERN:    EVV 0x20 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W0  NOEVSR  ZEROING=0  ESIZE_8_BITS() NELEM_HALFMEM()
@@ -59786,7 +61757,7 @@ CPL:         3
 CATEGORY:    DATAXFER
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512BW_512
-EXCEPTIONS:     AVX512-E6NF
+EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
 PATTERN:    EVV 0x20 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ZEROING=0  ESIZE_8_BITS() NELEM_HALFMEM()
@@ -60208,7 +62179,7 @@ CPL:         3
 CATEGORY:    DATAXFER
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
-EXCEPTIONS:     AVX512-E6NF
+EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
 PATTERN:    EVV 0x11 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0  NOEVSR  ZEROING=0  ESIZE_8_BITS() NELEM_QUARTERMEM()
@@ -60240,7 +62211,7 @@ CPL:         3
 CATEGORY:    DATAXFER
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
-EXCEPTIONS:     AVX512-E6NF
+EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
 PATTERN:    EVV 0x11 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W0  NOEVSR  ZEROING=0  ESIZE_8_BITS() NELEM_QUARTERMEM()
@@ -60272,7 +62243,7 @@ CPL:         3
 CATEGORY:    DATAXFER
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
-EXCEPTIONS:     AVX512-E6NF
+EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
 PATTERN:    EVV 0x13 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0  NOEVSR  ZEROING=0  ESIZE_16_BITS() NELEM_HALFMEM()
@@ -60304,7 +62275,7 @@ CPL:         3
 CATEGORY:    DATAXFER
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
-EXCEPTIONS:     AVX512-E6NF
+EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
 PATTERN:    EVV 0x13 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W0  NOEVSR  ZEROING=0  ESIZE_16_BITS() NELEM_HALFMEM()
@@ -60336,7 +62307,7 @@ CPL:         3
 CATEGORY:    DATAXFER
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
-EXCEPTIONS:     AVX512-E6NF
+EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM
 PATTERN:    EVV 0x12 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0  NOEVSR  ZEROING=0  ESIZE_8_BITS() NELEM_EIGHTHMEM()
@@ -60368,7 +62339,7 @@ CPL:         3
 CATEGORY:    DATAXFER
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
-EXCEPTIONS:     AVX512-E6NF
+EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM
 PATTERN:    EVV 0x12 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W0  NOEVSR  ZEROING=0  ESIZE_8_BITS() NELEM_EIGHTHMEM()
@@ -60400,7 +62371,7 @@ CPL:         3
 CATEGORY:    DATAXFER
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
-EXCEPTIONS:     AVX512-E6NF
+EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
 PATTERN:    EVV 0x15 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0  NOEVSR  ZEROING=0  ESIZE_32_BITS() NELEM_HALFMEM()
@@ -60432,7 +62403,7 @@ CPL:         3
 CATEGORY:    DATAXFER
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
-EXCEPTIONS:     AVX512-E6NF
+EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
 PATTERN:    EVV 0x15 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W0  NOEVSR  ZEROING=0  ESIZE_32_BITS() NELEM_HALFMEM()
@@ -60464,7 +62435,7 @@ CPL:         3
 CATEGORY:    DATAXFER
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
-EXCEPTIONS:     AVX512-E6NF
+EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
 PATTERN:    EVV 0x14 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0  NOEVSR  ZEROING=0  ESIZE_16_BITS() NELEM_QUARTERMEM()
@@ -60496,7 +62467,7 @@ CPL:         3
 CATEGORY:    DATAXFER
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
-EXCEPTIONS:     AVX512-E6NF
+EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
 PATTERN:    EVV 0x14 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W0  NOEVSR  ZEROING=0  ESIZE_16_BITS() NELEM_QUARTERMEM()
@@ -60528,7 +62499,7 @@ CPL:         3
 CATEGORY:    DATAXFER
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512BW_128
-EXCEPTIONS:     AVX512-E6NF
+EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
 PATTERN:    EVV 0x10 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0  NOEVSR  ZEROING=0  ESIZE_8_BITS() NELEM_HALFMEM()
@@ -60560,7 +62531,7 @@ CPL:         3
 CATEGORY:    DATAXFER
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512BW_256
-EXCEPTIONS:     AVX512-E6NF
+EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
 PATTERN:    EVV 0x10 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W0  NOEVSR  ZEROING=0  ESIZE_8_BITS() NELEM_HALFMEM()
@@ -60592,7 +62563,7 @@ CPL:         3
 CATEGORY:    DATAXFER
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512BW_512
-EXCEPTIONS:     AVX512-E6NF
+EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
 PATTERN:    EVV 0x10 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ZEROING=0  ESIZE_8_BITS() NELEM_HALFMEM()
@@ -60669,7 +62640,7 @@ CPL:         3
 CATEGORY:    DATAXFER
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512BW_128
-EXCEPTIONS:     AVX512-E6NF
+EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
 PATTERN:    EVV 0x30 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0  NOEVSR  ZEROING=0  ESIZE_8_BITS() NELEM_HALFMEM()
@@ -60701,7 +62672,7 @@ CPL:         3
 CATEGORY:    DATAXFER
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512BW_256
-EXCEPTIONS:     AVX512-E6NF
+EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
 PATTERN:    EVV 0x30 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W0  NOEVSR  ZEROING=0  ESIZE_8_BITS() NELEM_HALFMEM()
@@ -60733,7 +62704,7 @@ CPL:         3
 CATEGORY:    DATAXFER
 EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512BW_512
-EXCEPTIONS:     AVX512-E6NF
+EXCEPTIONS:     AVX512-E6
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
 PATTERN:    EVV 0x30 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ZEROING=0  ESIZE_8_BITS() NELEM_HALFMEM()
@@ -61141,9 +63112,10 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
+COMMENT:     Strange instruction that uses 32b of each 64b input element
 ATTRIBUTES:  MASKOP_EVEX
 PATTERN:    EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1
-OPERANDS:    REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 REG3=XMM_B3():r:dq:i32
+OPERANDS:    REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i64 REG3=XMM_B3():r:dq:i64
 IFORM:       VPMULDQ_XMMi64_MASKmskw_XMMi32_XMMi32_AVX512
 }
 
@@ -61155,9 +63127,10 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+COMMENT:     Strange instruction that uses 32b of each 64b input element
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP DISP8_FULL BROADCAST_ENABLED MASKOP_EVEX
 PATTERN:    EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1    ESIZE_64_BITS() NELEM_FULL()
-OPERANDS:    REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 MEM0:r:vv:i32:TXT=BCASTSTR
+OPERANDS:    REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i64 MEM0:r:vv:i64:TXT=BCASTSTR
 IFORM:       VPMULDQ_XMMi64_MASKmskw_XMMi32_MEMi32_AVX512
 }
 
@@ -61171,9 +63144,10 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
+COMMENT:     Strange instruction that uses 32b of each 64b input element
 ATTRIBUTES:  MASKOP_EVEX
 PATTERN:    EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1
-OPERANDS:    REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 REG3=YMM_B3():r:qq:i32
+OPERANDS:    REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i64 REG3=YMM_B3():r:qq:i64
 IFORM:       VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512
 }
 
@@ -61185,9 +63159,10 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+COMMENT:     Strange instruction that uses 32b of each 64b input element
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP DISP8_FULL BROADCAST_ENABLED MASKOP_EVEX
 PATTERN:    EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1    ESIZE_64_BITS() NELEM_FULL()
-OPERANDS:    REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 MEM0:r:vv:i32:TXT=BCASTSTR
+OPERANDS:    REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i64 MEM0:r:vv:i64:TXT=BCASTSTR
 IFORM:       VPMULDQ_YMMi64_MASKmskw_YMMi32_MEMi32_AVX512
 }
 
@@ -61711,9 +63686,10 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
+COMMENT:     Strange instruction that uses 32b of each 64b input element
 ATTRIBUTES:  MASKOP_EVEX
 PATTERN:    EVV 0xF4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1
-OPERANDS:    REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
+OPERANDS:    REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
 IFORM:       VPMULUDQ_XMMu64_MASKmskw_XMMu32_XMMu32_AVX512
 }
 
@@ -61725,9 +63701,10 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+COMMENT:     Strange instruction that uses 32b of each 64b input element
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP DISP8_FULL BROADCAST_ENABLED MASKOP_EVEX
 PATTERN:    EVV 0xF4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1    ESIZE_64_BITS() NELEM_FULL()
-OPERANDS:    REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
+OPERANDS:    REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
 IFORM:       VPMULUDQ_XMMu64_MASKmskw_XMMu32_MEMu32_AVX512
 }
 
@@ -61741,9 +63718,10 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
+COMMENT:     Strange instruction that uses 32b of each 64b input element
 ATTRIBUTES:  MASKOP_EVEX
 PATTERN:    EVV 0xF4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1
-OPERANDS:    REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
+OPERANDS:    REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
 IFORM:       VPMULUDQ_YMMu64_MASKmskw_YMMu32_YMMu32_AVX512
 }
 
@@ -61755,9 +63733,10 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+COMMENT:     Strange instruction that uses 32b of each 64b input element
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP DISP8_FULL BROADCAST_ENABLED MASKOP_EVEX
 PATTERN:    EVV 0xF4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1    ESIZE_64_BITS() NELEM_FULL()
-OPERANDS:    REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
+OPERANDS:    REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
 IFORM:       VPMULUDQ_YMMu64_MASKmskw_YMMu32_MEMu32_AVX512
 }
 
@@ -62458,9 +64437,9 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E12
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT
-PATTERN:    EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL128  W0 RM=4 UISA_VMODRM_XMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
-OPERANDS:    MEM0:w:dq:u32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:u32
+ATTRIBUTES:  DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER
+PATTERN:    EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0   VL128  W0 UISA_VMODRM_XMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
+OPERANDS:    MEM0:w:d:u32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:u32
 IFORM:       VPSCATTERDD_MEMu32_MASKmskw_XMMu32_AVX512_VL128
 }
 
@@ -62474,9 +64453,9 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E12
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT
-PATTERN:    EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL256  W0 RM=4 UISA_VMODRM_YMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
-OPERANDS:    MEM0:w:qq:u32 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:u32
+ATTRIBUTES:  DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER
+PATTERN:    EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0   VL256  W0 UISA_VMODRM_YMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
+OPERANDS:    MEM0:w:d:u32 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:u32
 IFORM:       VPSCATTERDD_MEMu32_MASKmskw_YMMu32_AVX512_VL256
 }
 
@@ -62490,9 +64469,9 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E12
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT
-PATTERN:    EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL128  W1 RM=4 UISA_VMODRM_XMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
-OPERANDS:    MEM0:w:dq:u64 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:u64
+ATTRIBUTES:  DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER
+PATTERN:    EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0   VL128  W1 UISA_VMODRM_XMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
+OPERANDS:    MEM0:w:q:u64 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:u64
 IFORM:       VPSCATTERDQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128
 }
 
@@ -62506,9 +64485,9 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E12
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT
-PATTERN:    EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL256  W1 RM=4 UISA_VMODRM_XMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
-OPERANDS:    MEM0:w:qq:u64 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:u64
+ATTRIBUTES:  DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER
+PATTERN:    EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0   VL256  W1 UISA_VMODRM_XMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
+OPERANDS:    MEM0:w:q:u64 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:u64
 IFORM:       VPSCATTERDQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256
 }
 
@@ -62522,9 +64501,9 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E12
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT
-PATTERN:    EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL128  W0 RM=4 UISA_VMODRM_XMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
-OPERANDS:    MEM0:w:q:u32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:u32
+ATTRIBUTES:  QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER
+PATTERN:    EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0   VL128  W0 UISA_VMODRM_XMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
+OPERANDS:    MEM0:w:d:u32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:u32
 IFORM:       VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128
 }
 
@@ -62538,9 +64517,9 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E12
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT
-PATTERN:    EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL256  W0 RM=4 UISA_VMODRM_YMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
-OPERANDS:    MEM0:w:dq:u32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:u32
+ATTRIBUTES:  QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER
+PATTERN:    EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0   VL256  W0 UISA_VMODRM_YMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
+OPERANDS:    MEM0:w:d:u32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:u32
 IFORM:       VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL256
 }
 
@@ -62554,9 +64533,9 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E12
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT
-PATTERN:    EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL128  W1 RM=4 UISA_VMODRM_XMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
-OPERANDS:    MEM0:w:dq:u64 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:u64
+ATTRIBUTES:  QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER
+PATTERN:    EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0   VL128  W1 UISA_VMODRM_XMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
+OPERANDS:    MEM0:w:q:u64 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:u64
 IFORM:       VPSCATTERQQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128
 }
 
@@ -62570,9 +64549,9 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E12
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT
-PATTERN:    EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL256  W1 RM=4 UISA_VMODRM_YMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
-OPERANDS:    MEM0:w:qq:u64 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:u64
+ATTRIBUTES:  QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER
+PATTERN:    EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0   VL256  W1 UISA_VMODRM_YMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
+OPERANDS:    MEM0:w:q:u64 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:u64
 IFORM:       VPSCATTERQQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256
 }
 
@@ -67080,7 +69059,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1   UIMM8()
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
 IFORM:       VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
@@ -67094,7 +69073,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1   UIMM8()  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
 IFORM:       VRANGEPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512
@@ -67110,7 +69089,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1   UIMM8()
 OPERANDS:    REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 IMM0:r:b
 IFORM:       VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512
@@ -67124,7 +69103,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1   UIMM8()  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
 IFORM:       VRANGEPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512
@@ -67140,7 +69119,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   UIMM8()
 OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b
 IFORM:       VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512
@@ -67154,7 +69133,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W1   UIMM8()
 OPERANDS:    REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b
 IFORM:       VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512
@@ -67168,7 +69147,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1   UIMM8()  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
 IFORM:       VRANGEPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512
@@ -67184,7 +69163,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0   UIMM8()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
 IFORM:       VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
@@ -67198,7 +69177,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0   UIMM8()  ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
 IFORM:       VRANGEPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512
@@ -67214,7 +69193,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0   UIMM8()
 OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 IMM0:r:b
 IFORM:       VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512
@@ -67228,7 +69207,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0   UIMM8()  ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
 IFORM:       VRANGEPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512
@@ -67244,7 +69223,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   UIMM8()
 OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b
 IFORM:       VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512
@@ -67258,7 +69237,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W0   UIMM8()
 OPERANDS:    REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b
 IFORM:       VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512
@@ -67272,7 +69251,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0   UIMM8()  ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
 IFORM:       VRANGEPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512
@@ -67288,7 +69267,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x51 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1   UIMM8()
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
 IFORM:       VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
@@ -67302,7 +69281,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x51 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W1   UIMM8()
 OPERANDS:    REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
 IFORM:       VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
@@ -67316,7 +69295,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0x51 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1   UIMM8()  ESIZE_64_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b
 IFORM:       VRANGESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512
@@ -67332,7 +69311,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x51 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0   UIMM8()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
 IFORM:       VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
@@ -67346,7 +69325,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x51 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W0   UIMM8()
 OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
 IFORM:       VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
@@ -67360,7 +69339,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0x51 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0   UIMM8()  ESIZE_32_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b
 IFORM:       VRANGESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512
@@ -67376,7 +69355,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1  NOEVSR
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
 IFORM:       VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512
@@ -67390,7 +69369,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VRCP14PD_XMMf64_MASKmskw_MEMf64_AVX512
@@ -67406,7 +69385,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1  NOEVSR
 OPERANDS:    REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
 IFORM:       VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512
@@ -67420,7 +69399,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VRCP14PD_YMMf64_MASKmskw_MEMf64_AVX512
@@ -67436,7 +69415,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0  NOEVSR
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
 IFORM:       VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512
@@ -67450,7 +69429,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VRCP14PS_XMMf32_MASKmskw_MEMf32_AVX512
@@ -67466,7 +69445,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0  NOEVSR
 OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
 IFORM:       VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512
@@ -67480,7 +69459,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VRCP14PS_YMMf32_MASKmskw_MEMf32_AVX512
@@ -67496,7 +69475,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1  NOEVSR UIMM8()
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 IMM0:r:b
 IFORM:       VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512
@@ -67510,7 +69489,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1  NOEVSR UIMM8()  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
 IFORM:       VREDUCEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512
@@ -67526,7 +69505,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1  NOEVSR UIMM8()
 OPERANDS:    REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 IMM0:r:b
 IFORM:       VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512
@@ -67540,7 +69519,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1  NOEVSR UIMM8()  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
 IFORM:       VREDUCEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512
@@ -67556,7 +69535,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR UIMM8()
 OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b
 IFORM:       VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512
@@ -67570,7 +69549,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W1  NOEVSR UIMM8()
 OPERANDS:    REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b
 IFORM:       VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512
@@ -67584,7 +69563,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1  NOEVSR UIMM8()  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
 IFORM:       VREDUCEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512
@@ -67600,7 +69579,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0  NOEVSR UIMM8()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 IMM0:r:b
 IFORM:       VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512
@@ -67614,7 +69593,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0  NOEVSR UIMM8()  ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
 IFORM:       VREDUCEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512
@@ -67630,7 +69609,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0  NOEVSR UIMM8()
 OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 IMM0:r:b
 IFORM:       VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512
@@ -67644,7 +69623,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0  NOEVSR UIMM8()  ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
 IFORM:       VREDUCEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512
@@ -67660,7 +69639,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR UIMM8()
 OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b
 IFORM:       VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512
@@ -67674,7 +69653,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W0  NOEVSR UIMM8()
 OPERANDS:    REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b
 IFORM:       VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512
@@ -67688,7 +69667,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR UIMM8()  ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
 IFORM:       VREDUCEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512
@@ -67704,7 +69683,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x57 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1   UIMM8()
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
 IFORM:       VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
@@ -67718,7 +69697,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x57 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W1   UIMM8()
 OPERANDS:    REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
 IFORM:       VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
@@ -67732,7 +69711,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0x57 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1   UIMM8()  ESIZE_64_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b
 IFORM:       VREDUCESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512
@@ -67748,7 +69727,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x57 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0   UIMM8()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
 IFORM:       VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
@@ -67762,7 +69741,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR
 PATTERN:    EVV 0x57 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W0   UIMM8()
 OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
 IFORM:       VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
@@ -67776,7 +69755,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512DQ_SCALAR
 EXCEPTIONS:     AVX512-E3
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
 PATTERN:    EVV 0x57 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0   UIMM8()  ESIZE_32_BITS() NELEM_SCALAR()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b
 IFORM:       VREDUCESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512
@@ -67792,7 +69771,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x09 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1  NOEVSR UIMM8()
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 IMM0:r:b
 IFORM:       VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512
@@ -67806,7 +69785,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x09 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1  NOEVSR UIMM8()  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
 IFORM:       VRNDSCALEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512
@@ -67822,7 +69801,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x09 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1  NOEVSR UIMM8()
 OPERANDS:    REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 IMM0:r:b
 IFORM:       VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512
@@ -67836,7 +69815,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x09 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1  NOEVSR UIMM8()  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
 IFORM:       VRNDSCALEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512
@@ -67852,7 +69831,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x08 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0  NOEVSR UIMM8()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 IMM0:r:b
 IFORM:       VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512
@@ -67866,7 +69845,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x08 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0  NOEVSR UIMM8()  ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
 IFORM:       VRNDSCALEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512
@@ -67882,7 +69861,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x08 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0  NOEVSR UIMM8()
 OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 IMM0:r:b
 IFORM:       VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512
@@ -67896,7 +69875,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x08 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0  NOEVSR UIMM8()  ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
 IFORM:       VRNDSCALEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512
@@ -67912,7 +69891,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1  NOEVSR
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
 IFORM:       VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512
@@ -67926,7 +69905,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VRSQRT14PD_XMMf64_MASKmskw_MEMf64_AVX512
@@ -67942,7 +69921,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1  NOEVSR
 OPERANDS:    REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
 IFORM:       VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512
@@ -67956,7 +69935,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VRSQRT14PD_YMMf64_MASKmskw_MEMf64_AVX512
@@ -67972,7 +69951,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0  NOEVSR
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
 IFORM:       VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512
@@ -67986,7 +69965,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VRSQRT14PS_XMMf32_MASKmskw_MEMf32_AVX512
@@ -68002,7 +69981,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0  NOEVSR
 OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
 IFORM:       VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512
@@ -68016,7 +69995,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512
@@ -68032,7 +70011,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -68046,7 +70025,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VSCALEFPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
@@ -68062,7 +70041,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1
 OPERANDS:    REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
 IFORM:       VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
@@ -68076,7 +70055,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VSCALEFPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
@@ -68092,7 +70071,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -68106,7 +70085,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VSCALEFPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
@@ -68122,7 +70101,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0
 OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
 IFORM:       VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
@@ -68136,7 +70115,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VSCALEFPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
@@ -68152,9 +70131,9 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E12
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT
-PATTERN:    EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL128  W1 RM=4 UISA_VMODRM_XMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
-OPERANDS:    MEM0:w:dq:f64 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:f64
+ATTRIBUTES:  DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER
+PATTERN:    EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0   VL128  W1 UISA_VMODRM_XMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
+OPERANDS:    MEM0:w:q:f64 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:f64
 IFORM:       VSCATTERDPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128
 }
 
@@ -68168,9 +70147,9 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E12
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT
-PATTERN:    EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL256  W1 RM=4 UISA_VMODRM_XMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
-OPERANDS:    MEM0:w:qq:f64 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:f64
+ATTRIBUTES:  DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER
+PATTERN:    EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0   VL256  W1 UISA_VMODRM_XMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
+OPERANDS:    MEM0:w:q:f64 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:f64
 IFORM:       VSCATTERDPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256
 }
 
@@ -68184,9 +70163,9 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E12
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT
-PATTERN:    EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL128  W0 RM=4 UISA_VMODRM_XMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
-OPERANDS:    MEM0:w:dq:f32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:f32
+ATTRIBUTES:  DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER
+PATTERN:    EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0   VL128  W0 UISA_VMODRM_XMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
+OPERANDS:    MEM0:w:d:f32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:f32
 IFORM:       VSCATTERDPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128
 }
 
@@ -68200,9 +70179,9 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E12
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT
-PATTERN:    EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL256  W0 RM=4 UISA_VMODRM_YMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
-OPERANDS:    MEM0:w:qq:f32 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:f32
+ATTRIBUTES:  DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER
+PATTERN:    EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0   VL256  W0 UISA_VMODRM_YMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
+OPERANDS:    MEM0:w:d:f32 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:f32
 IFORM:       VSCATTERDPS_MEMf32_MASKmskw_YMMf32_AVX512_VL256
 }
 
@@ -68216,9 +70195,9 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E12
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT
-PATTERN:    EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL128  W1 RM=4 UISA_VMODRM_XMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
-OPERANDS:    MEM0:w:dq:f64 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:f64
+ATTRIBUTES:  QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER
+PATTERN:    EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0   VL128  W1 UISA_VMODRM_XMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
+OPERANDS:    MEM0:w:q:f64 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:f64
 IFORM:       VSCATTERQPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128
 }
 
@@ -68232,9 +70211,9 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E12
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT
-PATTERN:    EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL256  W1 RM=4 UISA_VMODRM_YMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
-OPERANDS:    MEM0:w:qq:f64 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:f64
+ATTRIBUTES:  QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER
+PATTERN:    EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0   VL256  W1 UISA_VMODRM_YMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
+OPERANDS:    MEM0:w:q:f64 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:f64
 IFORM:       VSCATTERQPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256
 }
 
@@ -68248,9 +70227,9 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E12
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT
-PATTERN:    EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL128  W0 RM=4 UISA_VMODRM_XMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
-OPERANDS:    MEM0:w:q:f32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:f32
+ATTRIBUTES:  QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER
+PATTERN:    EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0   VL128  W0 UISA_VMODRM_XMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
+OPERANDS:    MEM0:w:d:f32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:f32
 IFORM:       VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128
 }
 
@@ -68264,9 +70243,9 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E12
 REAL_OPCODE: Y
-ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT
-PATTERN:    EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL256  W0 RM=4 UISA_VMODRM_YMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
-OPERANDS:    MEM0:w:dq:f32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:f32
+ATTRIBUTES:  QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER
+PATTERN:    EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0   VL256  W0 UISA_VMODRM_YMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
+OPERANDS:    MEM0:w:d:f32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:f32
 IFORM:       VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL256
 }
 
@@ -68520,7 +70499,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x51 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1  NOEVSR
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
 IFORM:       VSQRTPD_XMMf64_MASKmskw_XMMf64_AVX512
@@ -68534,7 +70513,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x51 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VSQRTPD_XMMf64_MASKmskw_MEMf64_AVX512
@@ -68550,7 +70529,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x51 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1  NOEVSR
 OPERANDS:    REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
 IFORM:       VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512
@@ -68564,7 +70543,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x51 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VSQRTPD_YMMf64_MASKmskw_MEMf64_AVX512
@@ -68580,7 +70559,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x51 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0  NOEVSR
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
 IFORM:       VSQRTPS_XMMf32_MASKmskw_XMMf32_AVX512
@@ -68594,7 +70573,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x51 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VSQRTPS_XMMf32_MASKmskw_MEMf32_AVX512
@@ -68610,7 +70589,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x51 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0  NOEVSR
 OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
 IFORM:       VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512
@@ -68624,7 +70603,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x51 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VSQRTPS_YMMf32_MASKmskw_MEMf32_AVX512
@@ -68640,7 +70619,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
 IFORM:       VSUBPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
@@ -68654,7 +70633,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x5C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VSUBPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
@@ -68670,7 +70649,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1
 OPERANDS:    REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
 IFORM:       VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
@@ -68684,7 +70663,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x5C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1    ESIZE_64_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
 IFORM:       VSUBPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
@@ -68700,7 +70679,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5C VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
 IFORM:       VSUBPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
@@ -68714,7 +70693,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_128
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x5C VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VSUBPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
@@ -68730,7 +70709,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MASKOP_EVEX
+ATTRIBUTES:  MASKOP_EVEX MXCSR
 PATTERN:    EVV 0x5C VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0
 OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
 IFORM:       VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
@@ -68744,7 +70723,7 @@ EXTENSION:   AVX512EVEX
 ISA_SET:     AVX512F_256
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
-ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
 PATTERN:    EVV 0x5C VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_32_BITS() NELEM_FULL()
 OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
 IFORM:       VSUBPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
@@ -69002,8 +70981,8 @@ EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX
 PATTERN:    EVV 0x57 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1
-OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
-IFORM:       VXORPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
+OPERANDS:    REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
+IFORM:       VXORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
 }
 
 {
@@ -69016,8 +70995,8 @@ EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
 PATTERN:    EVV 0x57 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1    ESIZE_64_BITS() NELEM_FULL()
-OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
-IFORM:       VXORPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
+OPERANDS:    REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
+IFORM:       VXORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
 }
 
 
@@ -69032,8 +71011,8 @@ EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX
 PATTERN:    EVV 0x57 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1
-OPERANDS:    REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
-IFORM:       VXORPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
+OPERANDS:    REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
+IFORM:       VXORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
 }
 
 {
@@ -69046,8 +71025,8 @@ EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
 PATTERN:    EVV 0x57 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1    ESIZE_64_BITS() NELEM_FULL()
-OPERANDS:    REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
-IFORM:       VXORPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
+OPERANDS:    REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
+IFORM:       VXORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
 }
 
 
@@ -69062,8 +71041,8 @@ EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX
 PATTERN:    EVV 0x57 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1
-OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
-IFORM:       VXORPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
+OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
+IFORM:       VXORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
 }
 
 {
@@ -69076,8 +71055,8 @@ EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
 PATTERN:    EVV 0x57 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
-OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
-IFORM:       VXORPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
+OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
+IFORM:       VXORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
 }
 
 
@@ -69092,8 +71071,8 @@ EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX
 PATTERN:    EVV 0x57 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0
-OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
-IFORM:       VXORPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
+OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
+IFORM:       VXORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
 }
 
 {
@@ -69106,8 +71085,8 @@ EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
 PATTERN:    EVV 0x57 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_32_BITS() NELEM_FULL()
-OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
-IFORM:       VXORPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
+OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
+IFORM:       VXORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
 }
 
 
@@ -69122,8 +71101,8 @@ EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX
 PATTERN:    EVV 0x57 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0
-OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
-IFORM:       VXORPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
+OPERANDS:    REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
+IFORM:       VXORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
 }
 
 {
@@ -69136,8 +71115,8 @@ EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
 PATTERN:    EVV 0x57 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_32_BITS() NELEM_FULL()
-OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
-IFORM:       VXORPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
+OPERANDS:    REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
+IFORM:       VXORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
 }
 
 
@@ -69152,8 +71131,8 @@ EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX
 PATTERN:    EVV 0x57 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0
-OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
-IFORM:       VXORPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
+OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
+IFORM:       VXORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
 }
 
 {
@@ -69166,8 +71145,8 @@ EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
 PATTERN:    EVV 0x57 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
-OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
-IFORM:       VXORPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
+OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
+IFORM:       VXORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
 }
 
 
@@ -69466,7 +71445,12 @@ ISA_SET:     AVX512BW_KOP
 EXCEPTIONS:     AVX512-K20
 REAL_OPCODE: Y
 ATTRIBUTES:  KMASK
-PATTERN:    VV1 0x92 VF2 V0F MOD[0b11] MOD=3  REG[rrr] RM[nnn]  VL=0  W0  NOVSR
+COMMENT:     KMOVQ aliases to KMOVD in 32b mode due to W bit being ignored.
+PATTERN:    VV1 0x92 VF2 V0F MOD[0b11] MOD=3  REG[rrr] RM[nnn]  VL=0  W0 mode64  NOVSR
+OPERANDS:    REG0=MASK_R():w:mskw REG1=GPR32_B():r:d:u32
+IFORM:       KMOVD_MASKmskw_GPR32u32_AVX512
+
+PATTERN:    VV1 0x92 VF2 V0F MOD[0b11] MOD=3  REG[rrr] RM[nnn]  VL=0  not64 NOVSR
 OPERANDS:    REG0=MASK_R():w:mskw REG1=GPR32_B():r:d:u32
 IFORM:       KMOVD_MASKmskw_GPR32u32_AVX512
 }
@@ -69482,7 +71466,12 @@ ISA_SET:     AVX512BW_KOP
 EXCEPTIONS:     AVX512-K20
 REAL_OPCODE: Y
 ATTRIBUTES:  KMASK
-PATTERN:    VV1 0x93 VF2 V0F MOD[0b11] MOD=3  REG[rrr] RM[nnn]  VL=0  W0  NOVSR
+COMMENT:     KMOVQ aliases to KMOVD in 32b mode due to W bit being ignored.
+PATTERN:    VV1 0x93 VF2 V0F MOD[0b11] MOD=3  REG[rrr] RM[nnn]  VL=0  W0  mode64 NOVSR
+OPERANDS:    REG0=GPR32_R():w:d:u32 REG1=MASK_B():r:mskw
+IFORM:       KMOVD_GPR32u32_MASKmskw_AVX512
+
+PATTERN:    VV1 0x93 VF2 V0F MOD[0b11] MOD=3  REG[rrr] RM[nnn]  VL=0  not64  NOVSR
 OPERANDS:    REG0=GPR32_R():w:d:u32 REG1=MASK_B():r:mskw
 IFORM:       KMOVD_GPR32u32_MASKmskw_AVX512
 }
@@ -70011,7 +72000,7 @@ IFORM:       KXORQ_MASKmskw_MASKmskw_MASKmskw_AVX512
 
 #BEGIN_LEGAL
 #
-#Copyright (c) 2016 Intel Corporation
+#Copyright (c) 2018 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -70042,7 +72031,7 @@ ICLASS:      VPMADD52HUQ
 CPL:         3
 CATEGORY:    IFMA
 EXTENSION:   AVX512EVEX
-ISA_SET:     AVX512IFMA_128
+ISA_SET:     AVX512_IFMA_128
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX
@@ -70056,7 +72045,7 @@ ICLASS:      VPMADD52HUQ
 CPL:         3
 CATEGORY:    IFMA
 EXTENSION:   AVX512EVEX
-ISA_SET:     AVX512IFMA_128
+ISA_SET:     AVX512_IFMA_128
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
@@ -70072,7 +72061,7 @@ ICLASS:      VPMADD52HUQ
 CPL:         3
 CATEGORY:    IFMA
 EXTENSION:   AVX512EVEX
-ISA_SET:     AVX512IFMA_256
+ISA_SET:     AVX512_IFMA_256
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX
@@ -70086,7 +72075,7 @@ ICLASS:      VPMADD52HUQ
 CPL:         3
 CATEGORY:    IFMA
 EXTENSION:   AVX512EVEX
-ISA_SET:     AVX512IFMA_256
+ISA_SET:     AVX512_IFMA_256
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
@@ -70102,7 +72091,7 @@ ICLASS:      VPMADD52HUQ
 CPL:         3
 CATEGORY:    IFMA
 EXTENSION:   AVX512EVEX
-ISA_SET:     AVX512IFMA_512
+ISA_SET:     AVX512_IFMA_512
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX
@@ -70116,7 +72105,7 @@ ICLASS:      VPMADD52HUQ
 CPL:         3
 CATEGORY:    IFMA
 EXTENSION:   AVX512EVEX
-ISA_SET:     AVX512IFMA_512
+ISA_SET:     AVX512_IFMA_512
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
@@ -70132,7 +72121,7 @@ ICLASS:      VPMADD52LUQ
 CPL:         3
 CATEGORY:    IFMA
 EXTENSION:   AVX512EVEX
-ISA_SET:     AVX512IFMA_128
+ISA_SET:     AVX512_IFMA_128
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX
@@ -70146,7 +72135,7 @@ ICLASS:      VPMADD52LUQ
 CPL:         3
 CATEGORY:    IFMA
 EXTENSION:   AVX512EVEX
-ISA_SET:     AVX512IFMA_128
+ISA_SET:     AVX512_IFMA_128
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
@@ -70162,7 +72151,7 @@ ICLASS:      VPMADD52LUQ
 CPL:         3
 CATEGORY:    IFMA
 EXTENSION:   AVX512EVEX
-ISA_SET:     AVX512IFMA_256
+ISA_SET:     AVX512_IFMA_256
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX
@@ -70176,7 +72165,7 @@ ICLASS:      VPMADD52LUQ
 CPL:         3
 CATEGORY:    IFMA
 EXTENSION:   AVX512EVEX
-ISA_SET:     AVX512IFMA_256
+ISA_SET:     AVX512_IFMA_256
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
@@ -70192,7 +72181,7 @@ ICLASS:      VPMADD52LUQ
 CPL:         3
 CATEGORY:    IFMA
 EXTENSION:   AVX512EVEX
-ISA_SET:     AVX512IFMA_512
+ISA_SET:     AVX512_IFMA_512
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX
@@ -70206,7 +72195,7 @@ ICLASS:      VPMADD52LUQ
 CPL:         3
 CATEGORY:    IFMA
 EXTENSION:   AVX512EVEX
-ISA_SET:     AVX512IFMA_512
+ISA_SET:     AVX512_IFMA_512
 EXCEPTIONS:     AVX512-E4
 REAL_OPCODE: Y
 ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
@@ -70222,7 +72211,7 @@ IFORM:       VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
 
 #BEGIN_LEGAL
 #
-#Copyright (c) 2016 Intel Corporation
+#Copyright (c) 2018 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -70251,9 +72240,9 @@ EVEX_INSTRUCTIONS()::
 {
 ICLASS:      VPERMB
 CPL:         3
-CATEGORY:    AVX512VBMI
+CATEGORY:    AVX512_VBMI
 EXTENSION:   AVX512EVEX
-ISA_SET:     AVX512VBMI_128
+ISA_SET:     AVX512_VBMI_128
 EXCEPTIONS:     AVX512-E4NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX
@@ -70265,9 +72254,9 @@ IFORM:       VPERMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512
 {
 ICLASS:      VPERMB
 CPL:         3
-CATEGORY:    AVX512VBMI
+CATEGORY:    AVX512_VBMI
 EXTENSION:   AVX512EVEX
-ISA_SET:     AVX512VBMI_128
+ISA_SET:     AVX512_VBMI_128
 EXCEPTIONS:     AVX512-E4NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX DISP8_FULLMEM
@@ -70281,9 +72270,9 @@ IFORM:       VPERMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512
 {
 ICLASS:      VPERMB
 CPL:         3
-CATEGORY:    AVX512VBMI
+CATEGORY:    AVX512_VBMI
 EXTENSION:   AVX512EVEX
-ISA_SET:     AVX512VBMI_256
+ISA_SET:     AVX512_VBMI_256
 EXCEPTIONS:     AVX512-E4NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX
@@ -70295,9 +72284,9 @@ IFORM:       VPERMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512
 {
 ICLASS:      VPERMB
 CPL:         3
-CATEGORY:    AVX512VBMI
+CATEGORY:    AVX512_VBMI
 EXTENSION:   AVX512EVEX
-ISA_SET:     AVX512VBMI_256
+ISA_SET:     AVX512_VBMI_256
 EXCEPTIONS:     AVX512-E4NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX DISP8_FULLMEM
@@ -70311,9 +72300,9 @@ IFORM:       VPERMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512
 {
 ICLASS:      VPERMB
 CPL:         3
-CATEGORY:    AVX512VBMI
+CATEGORY:    AVX512_VBMI
 EXTENSION:   AVX512EVEX
-ISA_SET:     AVX512VBMI_512
+ISA_SET:     AVX512_VBMI_512
 EXCEPTIONS:     AVX512-E4NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX
@@ -70325,9 +72314,9 @@ IFORM:       VPERMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512
 {
 ICLASS:      VPERMB
 CPL:         3
-CATEGORY:    AVX512VBMI
+CATEGORY:    AVX512_VBMI
 EXTENSION:   AVX512EVEX
-ISA_SET:     AVX512VBMI_512
+ISA_SET:     AVX512_VBMI_512
 EXCEPTIONS:     AVX512-E4NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX DISP8_FULLMEM
@@ -70341,9 +72330,9 @@ IFORM:       VPERMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512
 {
 ICLASS:      VPERMI2B
 CPL:         3
-CATEGORY:    AVX512VBMI
+CATEGORY:    AVX512_VBMI
 EXTENSION:   AVX512EVEX
-ISA_SET:     AVX512VBMI_128
+ISA_SET:     AVX512_VBMI_128
 EXCEPTIONS:     AVX512-E4NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX
@@ -70355,9 +72344,9 @@ IFORM:       VPERMI2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512
 {
 ICLASS:      VPERMI2B
 CPL:         3
-CATEGORY:    AVX512VBMI
+CATEGORY:    AVX512_VBMI
 EXTENSION:   AVX512EVEX
-ISA_SET:     AVX512VBMI_128
+ISA_SET:     AVX512_VBMI_128
 EXCEPTIONS:     AVX512-E4NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX DISP8_FULLMEM
@@ -70371,9 +72360,9 @@ IFORM:       VPERMI2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512
 {
 ICLASS:      VPERMI2B
 CPL:         3
-CATEGORY:    AVX512VBMI
+CATEGORY:    AVX512_VBMI
 EXTENSION:   AVX512EVEX
-ISA_SET:     AVX512VBMI_256
+ISA_SET:     AVX512_VBMI_256
 EXCEPTIONS:     AVX512-E4NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX
@@ -70385,9 +72374,9 @@ IFORM:       VPERMI2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512
 {
 ICLASS:      VPERMI2B
 CPL:         3
-CATEGORY:    AVX512VBMI
+CATEGORY:    AVX512_VBMI
 EXTENSION:   AVX512EVEX
-ISA_SET:     AVX512VBMI_256
+ISA_SET:     AVX512_VBMI_256
 EXCEPTIONS:     AVX512-E4NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX DISP8_FULLMEM
@@ -70401,9 +72390,9 @@ IFORM:       VPERMI2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512
 {
 ICLASS:      VPERMI2B
 CPL:         3
-CATEGORY:    AVX512VBMI
+CATEGORY:    AVX512_VBMI
 EXTENSION:   AVX512EVEX
-ISA_SET:     AVX512VBMI_512
+ISA_SET:     AVX512_VBMI_512
 EXCEPTIONS:     AVX512-E4NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX
@@ -70415,9 +72404,9 @@ IFORM:       VPERMI2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512
 {
 ICLASS:      VPERMI2B
 CPL:         3
-CATEGORY:    AVX512VBMI
+CATEGORY:    AVX512_VBMI
 EXTENSION:   AVX512EVEX
-ISA_SET:     AVX512VBMI_512
+ISA_SET:     AVX512_VBMI_512
 EXCEPTIONS:     AVX512-E4NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX DISP8_FULLMEM
@@ -70431,9 +72420,9 @@ IFORM:       VPERMI2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512
 {
 ICLASS:      VPERMT2B
 CPL:         3
-CATEGORY:    AVX512VBMI
+CATEGORY:    AVX512_VBMI
 EXTENSION:   AVX512EVEX
-ISA_SET:     AVX512VBMI_128
+ISA_SET:     AVX512_VBMI_128
 EXCEPTIONS:     AVX512-E4NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX
@@ -70445,9 +72434,9 @@ IFORM:       VPERMT2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512
 {
 ICLASS:      VPERMT2B
 CPL:         3
-CATEGORY:    AVX512VBMI
+CATEGORY:    AVX512_VBMI
 EXTENSION:   AVX512EVEX
-ISA_SET:     AVX512VBMI_128
+ISA_SET:     AVX512_VBMI_128
 EXCEPTIONS:     AVX512-E4NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX DISP8_FULLMEM
@@ -70461,9 +72450,9 @@ IFORM:       VPERMT2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512
 {
 ICLASS:      VPERMT2B
 CPL:         3
-CATEGORY:    AVX512VBMI
+CATEGORY:    AVX512_VBMI
 EXTENSION:   AVX512EVEX
-ISA_SET:     AVX512VBMI_256
+ISA_SET:     AVX512_VBMI_256
 EXCEPTIONS:     AVX512-E4NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX
@@ -70475,9 +72464,9 @@ IFORM:       VPERMT2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512
 {
 ICLASS:      VPERMT2B
 CPL:         3
-CATEGORY:    AVX512VBMI
+CATEGORY:    AVX512_VBMI
 EXTENSION:   AVX512EVEX
-ISA_SET:     AVX512VBMI_256
+ISA_SET:     AVX512_VBMI_256
 EXCEPTIONS:     AVX512-E4NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX DISP8_FULLMEM
@@ -70491,9 +72480,9 @@ IFORM:       VPERMT2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512
 {
 ICLASS:      VPERMT2B
 CPL:         3
-CATEGORY:    AVX512VBMI
+CATEGORY:    AVX512_VBMI
 EXTENSION:   AVX512EVEX
-ISA_SET:     AVX512VBMI_512
+ISA_SET:     AVX512_VBMI_512
 EXCEPTIONS:     AVX512-E4NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX
@@ -70505,9 +72494,9 @@ IFORM:       VPERMT2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512
 {
 ICLASS:      VPERMT2B
 CPL:         3
-CATEGORY:    AVX512VBMI
+CATEGORY:    AVX512_VBMI
 EXTENSION:   AVX512EVEX
-ISA_SET:     AVX512VBMI_512
+ISA_SET:     AVX512_VBMI_512
 EXCEPTIONS:     AVX512-E4NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX DISP8_FULLMEM
@@ -70521,9 +72510,9 @@ IFORM:       VPERMT2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512
 {
 ICLASS:      VPMULTISHIFTQB
 CPL:         3
-CATEGORY:    AVX512VBMI
+CATEGORY:    AVX512_VBMI
 EXTENSION:   AVX512EVEX
-ISA_SET:     AVX512VBMI_128
+ISA_SET:     AVX512_VBMI_128
 EXCEPTIONS:     AVX512-E4NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX
@@ -70535,9 +72524,9 @@ IFORM:       VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_XMMu64_AVX512
 {
 ICLASS:      VPMULTISHIFTQB
 CPL:         3
-CATEGORY:    AVX512VBMI
+CATEGORY:    AVX512_VBMI
 EXTENSION:   AVX512EVEX
-ISA_SET:     AVX512VBMI_128
+ISA_SET:     AVX512_VBMI_128
 EXCEPTIONS:     AVX512-E4NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
@@ -70551,9 +72540,9 @@ IFORM:       VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_MEMu64_AVX512
 {
 ICLASS:      VPMULTISHIFTQB
 CPL:         3
-CATEGORY:    AVX512VBMI
+CATEGORY:    AVX512_VBMI
 EXTENSION:   AVX512EVEX
-ISA_SET:     AVX512VBMI_256
+ISA_SET:     AVX512_VBMI_256
 EXCEPTIONS:     AVX512-E4NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX
@@ -70565,9 +72554,9 @@ IFORM:       VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_YMMu64_AVX512
 {
 ICLASS:      VPMULTISHIFTQB
 CPL:         3
-CATEGORY:    AVX512VBMI
+CATEGORY:    AVX512_VBMI
 EXTENSION:   AVX512EVEX
-ISA_SET:     AVX512VBMI_256
+ISA_SET:     AVX512_VBMI_256
 EXCEPTIONS:     AVX512-E4NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
@@ -70581,9 +72570,9 @@ IFORM:       VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_MEMu64_AVX512
 {
 ICLASS:      VPMULTISHIFTQB
 CPL:         3
-CATEGORY:    AVX512VBMI
+CATEGORY:    AVX512_VBMI
 EXTENSION:   AVX512EVEX
-ISA_SET:     AVX512VBMI_512
+ISA_SET:     AVX512_VBMI_512
 EXCEPTIONS:     AVX512-E4NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX
@@ -70595,9 +72584,9 @@ IFORM:       VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_AVX512
 {
 ICLASS:      VPMULTISHIFTQB
 CPL:         3
-CATEGORY:    AVX512VBMI
+CATEGORY:    AVX512_VBMI
 EXTENSION:   AVX512EVEX
-ISA_SET:     AVX512VBMI_512
+ISA_SET:     AVX512_VBMI_512
 EXCEPTIONS:     AVX512-E4NF
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
@@ -70607,3 +72596,3298 @@ IFORM:       VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_AVX512
 }
 
 
+
+
+###FILE: ../xed/datafiles/wbnoinvd/wbnoinvd-isa.xed.txt
+
+#BEGIN_LEGAL
+#
+#Copyright (c) 2018 Intel Corporation
+#
+#  Licensed under the Apache License, Version 2.0 (the "License");
+#  you may not use this file except in compliance with the License.
+#  You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+#  Unless required by applicable law or agreed to in writing, software
+#  distributed under the License is distributed on an "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#  See the License for the specific language governing permissions and
+#  limitations under the License.
+#
+#END_LEGAL
+
+INSTRUCTIONS()::
+{
+ICLASS    : WBINVD
+CPL       : 0
+CATEGORY  : SYSTEM
+EXTENSION : BASE
+ISA_SET   : I486REAL
+ATTRIBUTES : RING0 NOTSX
+PATTERN   : 0x0F 0x09 WBNOINVD=0
+OPERANDS  :
+PATTERN   : 0x0F 0x09 WBNOINVD=1 REP!=3
+OPERANDS  :
+VERSION   : 2
+}
+
+{
+ICLASS    : WBNOINVD
+CPL       : 0
+CATEGORY  : SYSTEM
+EXTENSION : WBNOINVD
+ISA_SET   : WBNOINVD
+ATTRIBUTES : RING0 NOTSX
+PATTERN   : 0x0F 0x09 WBNOINVD=1 f3_refining_prefix
+OPERANDS  :
+}
+
+
+###FILE: ../xed/datafiles/pconfig/pconfig-isa.xed.txt
+
+#BEGIN_LEGAL
+#
+#Copyright (c) 2018 Intel Corporation
+#
+#  Licensed under the Apache License, Version 2.0 (the "License");
+#  you may not use this file except in compliance with the License.
+#  You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+#  Unless required by applicable law or agreed to in writing, software
+#  distributed under the License is distributed on an "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#  See the License for the specific language governing permissions and
+#  limitations under the License.
+#
+#END_LEGAL
+#
+#
+#
+#    ***** GENERATED FILE -- DO NOT EDIT! *****
+#    ***** GENERATED FILE -- DO NOT EDIT! *****
+#    ***** GENERATED FILE -- DO NOT EDIT! *****
+#
+#
+#
+INSTRUCTIONS()::
+# EMITTING PCONFIG (PCONFIG-N/A-1)
+{
+ICLASS:      PCONFIG
+CPL:         0
+CATEGORY:    PCONFIG
+EXTENSION:   PCONFIG
+ISA_SET:     PCONFIG
+REAL_OPCODE: Y
+FLAGS:       MUST [  zf-mod  cf-0 pf-0 of-0 sf-0 af-0  ]
+PATTERN:     0x0F 0x01 MOD[0b11] MOD=3  REG[0b000] RM[0b101]  no_refining_prefix
+OPERANDS:    REG0=XED_REG_EAX:rw:SUPP:d:u32 REG1=XED_REG_EBX:crw:SUPP:d:u32 REG2=XED_REG_ECX:crw:SUPP:d:u32 REG3=XED_REG_EDX:crw:SUPP:d:u32
+IFORM:       PCONFIG
+}
+
+
+
+
+###FILE: ../xed/datafiles/bitalg/bitalg-isa.xed.txt
+
+#BEGIN_LEGAL
+#
+#Copyright (c) 2018 Intel Corporation
+#
+#  Licensed under the Apache License, Version 2.0 (the "License");
+#  you may not use this file except in compliance with the License.
+#  You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+#  Unless required by applicable law or agreed to in writing, software
+#  distributed under the License is distributed on an "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#  See the License for the specific language governing permissions and
+#  limitations under the License.
+#
+#END_LEGAL
+#
+#
+#
+#    ***** GENERATED FILE -- DO NOT EDIT! *****
+#    ***** GENERATED FILE -- DO NOT EDIT! *****
+#    ***** GENERATED FILE -- DO NOT EDIT! *****
+#
+#
+#
+EVEX_INSTRUCTIONS()::
+# EMITTING VPOPCNTB (VPOPCNTB-128-1)
+{
+ICLASS:      VPOPCNTB
+CPL:         3
+CATEGORY:    AVX512
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_BITALG_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:     EVV 0x54 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0  NOEVSR
+OPERANDS:    REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u8
+IFORM:       VPOPCNTB_XMMu8_MASKmskw_XMMu8_AVX512
+}
+
+{
+ICLASS:      VPOPCNTB
+CPL:         3
+CATEGORY:    AVX512
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_BITALG_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
+PATTERN:     EVV 0x54 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0  NOEVSR  ESIZE_8_BITS() NELEM_FULLMEM()
+OPERANDS:    REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u8
+IFORM:       VPOPCNTB_XMMu8_MASKmskw_MEMu8_AVX512
+}
+
+
+# EMITTING VPOPCNTB (VPOPCNTB-256-1)
+{
+ICLASS:      VPOPCNTB
+CPL:         3
+CATEGORY:    AVX512
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_BITALG_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:     EVV 0x54 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0  NOEVSR
+OPERANDS:    REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u8
+IFORM:       VPOPCNTB_YMMu8_MASKmskw_YMMu8_AVX512
+}
+
+{
+ICLASS:      VPOPCNTB
+CPL:         3
+CATEGORY:    AVX512
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_BITALG_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
+PATTERN:     EVV 0x54 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W0  NOEVSR  ESIZE_8_BITS() NELEM_FULLMEM()
+OPERANDS:    REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u8
+IFORM:       VPOPCNTB_YMMu8_MASKmskw_MEMu8_AVX512
+}
+
+
+# EMITTING VPOPCNTB (VPOPCNTB-512-1)
+{
+ICLASS:      VPOPCNTB
+CPL:         3
+CATEGORY:    AVX512_BITALG
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_BITALG_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:     EVV 0x54 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR
+OPERANDS:    REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu8
+IFORM:       VPOPCNTB_ZMMu8_MASKmskw_ZMMu8_AVX512
+}
+
+{
+ICLASS:      VPOPCNTB
+CPL:         3
+CATEGORY:    AVX512_BITALG
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_BITALG_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
+PATTERN:     EVV 0x54 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ESIZE_8_BITS() NELEM_FULLMEM()
+OPERANDS:    REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u8
+IFORM:       VPOPCNTB_ZMMu8_MASKmskw_MEMu8_AVX512
+}
+
+
+# EMITTING VPOPCNTW (VPOPCNTW-128-1)
+{
+ICLASS:      VPOPCNTW
+CPL:         3
+CATEGORY:    AVX512
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_BITALG_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:     EVV 0x54 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1  NOEVSR
+OPERANDS:    REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16
+IFORM:       VPOPCNTW_XMMu16_MASKmskw_XMMu16_AVX512
+}
+
+{
+ICLASS:      VPOPCNTW
+CPL:         3
+CATEGORY:    AVX512
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_BITALG_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
+PATTERN:     EVV 0x54 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W1  NOEVSR  ESIZE_16_BITS() NELEM_FULLMEM()
+OPERANDS:    REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16
+IFORM:       VPOPCNTW_XMMu16_MASKmskw_MEMu16_AVX512
+}
+
+
+# EMITTING VPOPCNTW (VPOPCNTW-256-1)
+{
+ICLASS:      VPOPCNTW
+CPL:         3
+CATEGORY:    AVX512
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_BITALG_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:     EVV 0x54 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1  NOEVSR
+OPERANDS:    REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16
+IFORM:       VPOPCNTW_YMMu16_MASKmskw_YMMu16_AVX512
+}
+
+{
+ICLASS:      VPOPCNTW
+CPL:         3
+CATEGORY:    AVX512
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_BITALG_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
+PATTERN:     EVV 0x54 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W1  NOEVSR  ESIZE_16_BITS() NELEM_FULLMEM()
+OPERANDS:    REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16
+IFORM:       VPOPCNTW_YMMu16_MASKmskw_MEMu16_AVX512
+}
+
+
+# EMITTING VPOPCNTW (VPOPCNTW-512-1)
+{
+ICLASS:      VPOPCNTW
+CPL:         3
+CATEGORY:    AVX512_BITALG
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_BITALG_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:     EVV 0x54 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR
+OPERANDS:    REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16
+IFORM:       VPOPCNTW_ZMMu16_MASKmskw_ZMMu16_AVX512
+}
+
+{
+ICLASS:      VPOPCNTW
+CPL:         3
+CATEGORY:    AVX512_BITALG
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_BITALG_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
+PATTERN:     EVV 0x54 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W1  NOEVSR  ESIZE_16_BITS() NELEM_FULLMEM()
+OPERANDS:    REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16
+IFORM:       VPOPCNTW_ZMMu16_MASKmskw_MEMu16_AVX512
+}
+
+
+# EMITTING VPSHUFBITQMB (VPSHUFBITQMB-128-1)
+{
+ICLASS:      VPSHUFBITQMB
+CPL:         3
+CATEGORY:    AVX512
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_BITALG_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:     EVV 0x8F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0    ZEROING=0
+OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u8
+IFORM:       VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_XMMu8_AVX512
+}
+
+{
+ICLASS:      VPSHUFBITQMB
+CPL:         3
+CATEGORY:    AVX512
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_BITALG_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
+PATTERN:     EVV 0x8F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0    ZEROING=0  ESIZE_8_BITS() NELEM_FULLMEM()
+OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 MEM0:r:dq:u8
+IFORM:       VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_MEMu8_AVX512
+}
+
+
+# EMITTING VPSHUFBITQMB (VPSHUFBITQMB-256-1)
+{
+ICLASS:      VPSHUFBITQMB
+CPL:         3
+CATEGORY:    AVX512
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_BITALG_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:     EVV 0x8F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0    ZEROING=0
+OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u8
+IFORM:       VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_YMMu8_AVX512
+}
+
+{
+ICLASS:      VPSHUFBITQMB
+CPL:         3
+CATEGORY:    AVX512
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_BITALG_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
+PATTERN:     EVV 0x8F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W0    ZEROING=0  ESIZE_8_BITS() NELEM_FULLMEM()
+OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 MEM0:r:qq:u8
+IFORM:       VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_MEMu8_AVX512
+}
+
+
+# EMITTING VPSHUFBITQMB (VPSHUFBITQMB-512-1)
+{
+ICLASS:      VPSHUFBITQMB
+CPL:         3
+CATEGORY:    AVX512_BITALG
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_BITALG_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:     EVV 0x8F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0    ZEROING=0
+OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu8
+IFORM:       VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_ZMMu8_AVX512
+}
+
+{
+ICLASS:      VPSHUFBITQMB
+CPL:         3
+CATEGORY:    AVX512_BITALG
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_BITALG_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
+PATTERN:     EVV 0x8F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0    ZEROING=0  ESIZE_8_BITS() NELEM_FULLMEM()
+OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 MEM0:r:zd:u8
+IFORM:       VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_MEMu8_AVX512
+}
+
+
+
+
+###FILE: ../xed/datafiles/vbmi2/vbmi2-isa.xed.txt
+
+#BEGIN_LEGAL
+#
+#Copyright (c) 2018 Intel Corporation
+#
+#  Licensed under the Apache License, Version 2.0 (the "License");
+#  you may not use this file except in compliance with the License.
+#  You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+#  Unless required by applicable law or agreed to in writing, software
+#  distributed under the License is distributed on an "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#  See the License for the specific language governing permissions and
+#  limitations under the License.
+#
+#END_LEGAL
+#
+#
+#
+#    ***** GENERATED FILE -- DO NOT EDIT! *****
+#    ***** GENERATED FILE -- DO NOT EDIT! *****
+#    ***** GENERATED FILE -- DO NOT EDIT! *****
+#
+#
+#
+EVEX_INSTRUCTIONS()::
+# EMITTING VPCOMPRESSB (VPCOMPRESSB-128-1)
+{
+ICLASS:      VPCOMPRESSB
+CPL:         3
+CATEGORY:    COMPRESS
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
+PATTERN:    EVV 0x63 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0  NOEVSR  ZEROING=0  ESIZE_8_BITS() NELEM_GSCAT()
+OPERANDS:    MEM0:w:dq:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u8
+IFORM:       VPCOMPRESSB_MEMu8_MASKmskw_XMMu8_AVX512
+}
+
+
+# EMITTING VPCOMPRESSB (VPCOMPRESSB-128-2)
+{
+ICLASS:      VPCOMPRESSB
+CPL:         3
+CATEGORY:    COMPRESS
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0  NOEVSR
+OPERANDS:    REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u8
+IFORM:       VPCOMPRESSB_XMMu8_MASKmskw_XMMu8_AVX512
+}
+
+
+# EMITTING VPCOMPRESSB (VPCOMPRESSB-256-1)
+{
+ICLASS:      VPCOMPRESSB
+CPL:         3
+CATEGORY:    COMPRESS
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
+PATTERN:    EVV 0x63 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W0  NOEVSR  ZEROING=0  ESIZE_8_BITS() NELEM_GSCAT()
+OPERANDS:    MEM0:w:qq:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u8
+IFORM:       VPCOMPRESSB_MEMu8_MASKmskw_YMMu8_AVX512
+}
+
+
+# EMITTING VPCOMPRESSB (VPCOMPRESSB-256-2)
+{
+ICLASS:      VPCOMPRESSB
+CPL:         3
+CATEGORY:    COMPRESS
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0  NOEVSR
+OPERANDS:    REG0=YMM_B3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u8
+IFORM:       VPCOMPRESSB_YMMu8_MASKmskw_YMMu8_AVX512
+}
+
+
+# EMITTING VPCOMPRESSB (VPCOMPRESSB-512-1)
+{
+ICLASS:      VPCOMPRESSB
+CPL:         3
+CATEGORY:    COMPRESS
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
+PATTERN:    EVV 0x63 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ZEROING=0  ESIZE_8_BITS() NELEM_GSCAT()
+OPERANDS:    MEM0:w:zd:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu8
+IFORM:       VPCOMPRESSB_MEMu8_MASKmskw_ZMMu8_AVX512
+}
+
+
+# EMITTING VPCOMPRESSB (VPCOMPRESSB-512-2)
+{
+ICLASS:      VPCOMPRESSB
+CPL:         3
+CATEGORY:    COMPRESS
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR
+OPERANDS:    REG0=ZMM_B3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu8
+IFORM:       VPCOMPRESSB_ZMMu8_MASKmskw_ZMMu8_AVX512
+}
+
+
+# EMITTING VPCOMPRESSW (VPCOMPRESSW-128-1)
+{
+ICLASS:      VPCOMPRESSW
+CPL:         3
+CATEGORY:    COMPRESS
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
+PATTERN:    EVV 0x63 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W1  NOEVSR  ZEROING=0  ESIZE_16_BITS() NELEM_GSCAT()
+OPERANDS:    MEM0:w:dq:u16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u16
+IFORM:       VPCOMPRESSW_MEMu16_MASKmskw_XMMu16_AVX512
+}
+
+
+# EMITTING VPCOMPRESSW (VPCOMPRESSW-128-2)
+{
+ICLASS:      VPCOMPRESSW
+CPL:         3
+CATEGORY:    COMPRESS
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1  NOEVSR
+OPERANDS:    REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u16
+IFORM:       VPCOMPRESSW_XMMu16_MASKmskw_XMMu16_AVX512
+}
+
+
+# EMITTING VPCOMPRESSW (VPCOMPRESSW-256-1)
+{
+ICLASS:      VPCOMPRESSW
+CPL:         3
+CATEGORY:    COMPRESS
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
+PATTERN:    EVV 0x63 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W1  NOEVSR  ZEROING=0  ESIZE_16_BITS() NELEM_GSCAT()
+OPERANDS:    MEM0:w:qq:u16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u16
+IFORM:       VPCOMPRESSW_MEMu16_MASKmskw_YMMu16_AVX512
+}
+
+
+# EMITTING VPCOMPRESSW (VPCOMPRESSW-256-2)
+{
+ICLASS:      VPCOMPRESSW
+CPL:         3
+CATEGORY:    COMPRESS
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1  NOEVSR
+OPERANDS:    REG0=YMM_B3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u16
+IFORM:       VPCOMPRESSW_YMMu16_MASKmskw_YMMu16_AVX512
+}
+
+
+# EMITTING VPCOMPRESSW (VPCOMPRESSW-512-1)
+{
+ICLASS:      VPCOMPRESSW
+CPL:         3
+CATEGORY:    COMPRESS
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
+PATTERN:    EVV 0x63 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W1  NOEVSR  ZEROING=0  ESIZE_16_BITS() NELEM_GSCAT()
+OPERANDS:    MEM0:w:zd:u16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu16
+IFORM:       VPCOMPRESSW_MEMu16_MASKmskw_ZMMu16_AVX512
+}
+
+
+# EMITTING VPCOMPRESSW (VPCOMPRESSW-512-2)
+{
+ICLASS:      VPCOMPRESSW
+CPL:         3
+CATEGORY:    COMPRESS
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR
+OPERANDS:    REG0=ZMM_B3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu16
+IFORM:       VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512
+}
+
+
+# EMITTING VPEXPANDB (VPEXPANDB-128-1)
+{
+ICLASS:      VPEXPANDB
+CPL:         3
+CATEGORY:    EXPAND
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
+PATTERN:    EVV 0x62 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0  NOEVSR  ESIZE_8_BITS() NELEM_GSCAT()
+OPERANDS:    REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u8
+IFORM:       VPEXPANDB_XMMu8_MASKmskw_MEMu8_AVX512
+}
+
+
+# EMITTING VPEXPANDB (VPEXPANDB-128-2)
+{
+ICLASS:      VPEXPANDB
+CPL:         3
+CATEGORY:    EXPAND
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x62 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0  NOEVSR
+OPERANDS:    REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u8
+IFORM:       VPEXPANDB_XMMu8_MASKmskw_XMMu8_AVX512
+}
+
+
+# EMITTING VPEXPANDB (VPEXPANDB-256-1)
+{
+ICLASS:      VPEXPANDB
+CPL:         3
+CATEGORY:    EXPAND
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
+PATTERN:    EVV 0x62 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W0  NOEVSR  ESIZE_8_BITS() NELEM_GSCAT()
+OPERANDS:    REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u8
+IFORM:       VPEXPANDB_YMMu8_MASKmskw_MEMu8_AVX512
+}
+
+
+# EMITTING VPEXPANDB (VPEXPANDB-256-2)
+{
+ICLASS:      VPEXPANDB
+CPL:         3
+CATEGORY:    EXPAND
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x62 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0  NOEVSR
+OPERANDS:    REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u8
+IFORM:       VPEXPANDB_YMMu8_MASKmskw_YMMu8_AVX512
+}
+
+
+# EMITTING VPEXPANDB (VPEXPANDB-512-1)
+{
+ICLASS:      VPEXPANDB
+CPL:         3
+CATEGORY:    EXPAND
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
+PATTERN:    EVV 0x62 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ESIZE_8_BITS() NELEM_GSCAT()
+OPERANDS:    REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u8
+IFORM:       VPEXPANDB_ZMMu8_MASKmskw_MEMu8_AVX512
+}
+
+
+# EMITTING VPEXPANDB (VPEXPANDB-512-2)
+{
+ICLASS:      VPEXPANDB
+CPL:         3
+CATEGORY:    EXPAND
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x62 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR
+OPERANDS:    REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu8
+IFORM:       VPEXPANDB_ZMMu8_MASKmskw_ZMMu8_AVX512
+}
+
+
+# EMITTING VPEXPANDW (VPEXPANDW-128-1)
+{
+ICLASS:      VPEXPANDW
+CPL:         3
+CATEGORY:    EXPAND
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
+PATTERN:    EVV 0x62 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W1  NOEVSR  ESIZE_16_BITS() NELEM_GSCAT()
+OPERANDS:    REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16
+IFORM:       VPEXPANDW_XMMu16_MASKmskw_MEMu16_AVX512
+}
+
+
+# EMITTING VPEXPANDW (VPEXPANDW-128-2)
+{
+ICLASS:      VPEXPANDW
+CPL:         3
+CATEGORY:    EXPAND
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x62 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1  NOEVSR
+OPERANDS:    REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16
+IFORM:       VPEXPANDW_XMMu16_MASKmskw_XMMu16_AVX512
+}
+
+
+# EMITTING VPEXPANDW (VPEXPANDW-256-1)
+{
+ICLASS:      VPEXPANDW
+CPL:         3
+CATEGORY:    EXPAND
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
+PATTERN:    EVV 0x62 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W1  NOEVSR  ESIZE_16_BITS() NELEM_GSCAT()
+OPERANDS:    REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16
+IFORM:       VPEXPANDW_YMMu16_MASKmskw_MEMu16_AVX512
+}
+
+
+# EMITTING VPEXPANDW (VPEXPANDW-256-2)
+{
+ICLASS:      VPEXPANDW
+CPL:         3
+CATEGORY:    EXPAND
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x62 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1  NOEVSR
+OPERANDS:    REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16
+IFORM:       VPEXPANDW_YMMu16_MASKmskw_YMMu16_AVX512
+}
+
+
+# EMITTING VPEXPANDW (VPEXPANDW-512-1)
+{
+ICLASS:      VPEXPANDW
+CPL:         3
+CATEGORY:    EXPAND
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
+PATTERN:    EVV 0x62 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W1  NOEVSR  ESIZE_16_BITS() NELEM_GSCAT()
+OPERANDS:    REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16
+IFORM:       VPEXPANDW_ZMMu16_MASKmskw_MEMu16_AVX512
+}
+
+
+# EMITTING VPEXPANDW (VPEXPANDW-512-2)
+{
+ICLASS:      VPEXPANDW
+CPL:         3
+CATEGORY:    EXPAND
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x62 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR
+OPERANDS:    REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16
+IFORM:       VPEXPANDW_ZMMu16_MASKmskw_ZMMu16_AVX512
+}
+
+
+# EMITTING VPSHLDD (VPSHLDD-128-1)
+{
+ICLASS:      VPSHLDD
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x71 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0   UIMM8()
+OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 IMM0:r:b
+IFORM:       VPSHLDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512
+}
+
+{
+ICLASS:      VPSHLDD
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+PATTERN:    EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0   UIMM8()  ESIZE_32_BITS() NELEM_FULL()
+OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
+IFORM:       VPSHLDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512
+}
+
+
+# EMITTING VPSHLDD (VPSHLDD-256-1)
+{
+ICLASS:      VPSHLDD
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x71 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0   UIMM8()
+OPERANDS:    REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 IMM0:r:b
+IFORM:       VPSHLDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512
+}
+
+{
+ICLASS:      VPSHLDD
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+PATTERN:    EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0   UIMM8()  ESIZE_32_BITS() NELEM_FULL()
+OPERANDS:    REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
+IFORM:       VPSHLDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512
+}
+
+
+# EMITTING VPSHLDD (VPSHLDD-512-1)
+{
+ICLASS:      VPSHLDD
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x71 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   UIMM8()
+OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 IMM0:r:b
+IFORM:       VPSHLDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512
+}
+
+{
+ICLASS:      VPSHLDD
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+PATTERN:    EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0   UIMM8()  ESIZE_32_BITS() NELEM_FULL()
+OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
+IFORM:       VPSHLDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512
+}
+
+
+# EMITTING VPSHLDQ (VPSHLDQ-128-1)
+{
+ICLASS:      VPSHLDQ
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x71 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1   UIMM8()
+OPERANDS:    REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 IMM0:r:b
+IFORM:       VPSHLDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512
+}
+
+{
+ICLASS:      VPSHLDQ
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+PATTERN:    EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1   UIMM8()  ESIZE_64_BITS() NELEM_FULL()
+OPERANDS:    REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
+IFORM:       VPSHLDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512
+}
+
+
+# EMITTING VPSHLDQ (VPSHLDQ-256-1)
+{
+ICLASS:      VPSHLDQ
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x71 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1   UIMM8()
+OPERANDS:    REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 IMM0:r:b
+IFORM:       VPSHLDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512
+}
+
+{
+ICLASS:      VPSHLDQ
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+PATTERN:    EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1   UIMM8()  ESIZE_64_BITS() NELEM_FULL()
+OPERANDS:    REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
+IFORM:       VPSHLDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512
+}
+
+
+# EMITTING VPSHLDQ (VPSHLDQ-512-1)
+{
+ICLASS:      VPSHLDQ
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x71 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   UIMM8()
+OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 IMM0:r:b
+IFORM:       VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512
+}
+
+{
+ICLASS:      VPSHLDQ
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+PATTERN:    EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1   UIMM8()  ESIZE_64_BITS() NELEM_FULL()
+OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
+IFORM:       VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512
+}
+
+
+# EMITTING VPSHLDVD (VPSHLDVD-128-1)
+{
+ICLASS:      VPSHLDVD
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x71 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0
+OPERANDS:    REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
+IFORM:       VPSHLDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
+}
+
+{
+ICLASS:      VPSHLDVD
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+PATTERN:    EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_32_BITS() NELEM_FULL()
+OPERANDS:    REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
+IFORM:       VPSHLDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
+}
+
+
+# EMITTING VPSHLDVD (VPSHLDVD-256-1)
+{
+ICLASS:      VPSHLDVD
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x71 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0
+OPERANDS:    REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
+IFORM:       VPSHLDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
+}
+
+{
+ICLASS:      VPSHLDVD
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+PATTERN:    EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_32_BITS() NELEM_FULL()
+OPERANDS:    REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
+IFORM:       VPSHLDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
+}
+
+
+# EMITTING VPSHLDVD (VPSHLDVD-512-1)
+{
+ICLASS:      VPSHLDVD
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x71 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0
+OPERANDS:    REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
+IFORM:       VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
+}
+
+{
+ICLASS:      VPSHLDVD
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+PATTERN:    EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
+OPERANDS:    REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
+IFORM:       VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
+}
+
+
+# EMITTING VPSHLDVQ (VPSHLDVQ-128-1)
+{
+ICLASS:      VPSHLDVQ
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x71 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1
+OPERANDS:    REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
+IFORM:       VPSHLDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
+}
+
+{
+ICLASS:      VPSHLDVQ
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+PATTERN:    EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1    ESIZE_64_BITS() NELEM_FULL()
+OPERANDS:    REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
+IFORM:       VPSHLDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
+}
+
+
+# EMITTING VPSHLDVQ (VPSHLDVQ-256-1)
+{
+ICLASS:      VPSHLDVQ
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x71 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1
+OPERANDS:    REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
+IFORM:       VPSHLDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
+}
+
+{
+ICLASS:      VPSHLDVQ
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+PATTERN:    EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1    ESIZE_64_BITS() NELEM_FULL()
+OPERANDS:    REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
+IFORM:       VPSHLDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
+}
+
+
+# EMITTING VPSHLDVQ (VPSHLDVQ-512-1)
+{
+ICLASS:      VPSHLDVQ
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x71 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1
+OPERANDS:    REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
+IFORM:       VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
+}
+
+{
+ICLASS:      VPSHLDVQ
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+PATTERN:    EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
+OPERANDS:    REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
+IFORM:       VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
+}
+
+
+# EMITTING VPSHLDVW (VPSHLDVW-128-1)
+{
+ICLASS:      VPSHLDVW
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x70 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1
+OPERANDS:    REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
+IFORM:       VPSHLDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
+}
+
+{
+ICLASS:      VPSHLDVW
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
+PATTERN:    EVV 0x70 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W1    ESIZE_16_BITS() NELEM_FULLMEM()
+OPERANDS:    REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
+IFORM:       VPSHLDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
+}
+
+
+# EMITTING VPSHLDVW (VPSHLDVW-256-1)
+{
+ICLASS:      VPSHLDVW
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x70 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1
+OPERANDS:    REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
+IFORM:       VPSHLDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
+}
+
+{
+ICLASS:      VPSHLDVW
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
+PATTERN:    EVV 0x70 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W1    ESIZE_16_BITS() NELEM_FULLMEM()
+OPERANDS:    REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
+IFORM:       VPSHLDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
+}
+
+
+# EMITTING VPSHLDVW (VPSHLDVW-512-1)
+{
+ICLASS:      VPSHLDVW
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x70 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1
+OPERANDS:    REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
+IFORM:       VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
+}
+
+{
+ICLASS:      VPSHLDVW
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
+PATTERN:    EVV 0x70 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W1    ESIZE_16_BITS() NELEM_FULLMEM()
+OPERANDS:    REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
+IFORM:       VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
+}
+
+
+# EMITTING VPSHLDW (VPSHLDW-128-1)
+{
+ICLASS:      VPSHLDW
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x70 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1   UIMM8()
+OPERANDS:    REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 IMM0:r:b
+IFORM:       VPSHLDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512
+}
+
+{
+ICLASS:      VPSHLDW
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
+PATTERN:    EVV 0x70 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W1   UIMM8()  ESIZE_16_BITS() NELEM_FULLMEM()
+OPERANDS:    REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 IMM0:r:b
+IFORM:       VPSHLDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512
+}
+
+
+# EMITTING VPSHLDW (VPSHLDW-256-1)
+{
+ICLASS:      VPSHLDW
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x70 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1   UIMM8()
+OPERANDS:    REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 IMM0:r:b
+IFORM:       VPSHLDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512
+}
+
+{
+ICLASS:      VPSHLDW
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
+PATTERN:    EVV 0x70 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W1   UIMM8()  ESIZE_16_BITS() NELEM_FULLMEM()
+OPERANDS:    REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 IMM0:r:b
+IFORM:       VPSHLDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512
+}
+
+
+# EMITTING VPSHLDW (VPSHLDW-512-1)
+{
+ICLASS:      VPSHLDW
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x70 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   UIMM8()
+OPERANDS:    REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 IMM0:r:b
+IFORM:       VPSHLDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512
+}
+
+{
+ICLASS:      VPSHLDW
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
+PATTERN:    EVV 0x70 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W1   UIMM8()  ESIZE_16_BITS() NELEM_FULLMEM()
+OPERANDS:    REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 IMM0:r:b
+IFORM:       VPSHLDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512
+}
+
+
+# EMITTING VPSHRDD (VPSHRDD-128-1)
+{
+ICLASS:      VPSHRDD
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x73 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0   UIMM8()
+OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 IMM0:r:b
+IFORM:       VPSHRDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512
+}
+
+{
+ICLASS:      VPSHRDD
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+PATTERN:    EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0   UIMM8()  ESIZE_32_BITS() NELEM_FULL()
+OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
+IFORM:       VPSHRDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512
+}
+
+
+# EMITTING VPSHRDD (VPSHRDD-256-1)
+{
+ICLASS:      VPSHRDD
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x73 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0   UIMM8()
+OPERANDS:    REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 IMM0:r:b
+IFORM:       VPSHRDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512
+}
+
+{
+ICLASS:      VPSHRDD
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+PATTERN:    EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0   UIMM8()  ESIZE_32_BITS() NELEM_FULL()
+OPERANDS:    REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
+IFORM:       VPSHRDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512
+}
+
+
+# EMITTING VPSHRDD (VPSHRDD-512-1)
+{
+ICLASS:      VPSHRDD
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x73 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   UIMM8()
+OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 IMM0:r:b
+IFORM:       VPSHRDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512
+}
+
+{
+ICLASS:      VPSHRDD
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+PATTERN:    EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0   UIMM8()  ESIZE_32_BITS() NELEM_FULL()
+OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
+IFORM:       VPSHRDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512
+}
+
+
+# EMITTING VPSHRDQ (VPSHRDQ-128-1)
+{
+ICLASS:      VPSHRDQ
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x73 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1   UIMM8()
+OPERANDS:    REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 IMM0:r:b
+IFORM:       VPSHRDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512
+}
+
+{
+ICLASS:      VPSHRDQ
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+PATTERN:    EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1   UIMM8()  ESIZE_64_BITS() NELEM_FULL()
+OPERANDS:    REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
+IFORM:       VPSHRDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512
+}
+
+
+# EMITTING VPSHRDQ (VPSHRDQ-256-1)
+{
+ICLASS:      VPSHRDQ
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x73 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1   UIMM8()
+OPERANDS:    REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 IMM0:r:b
+IFORM:       VPSHRDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512
+}
+
+{
+ICLASS:      VPSHRDQ
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+PATTERN:    EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1   UIMM8()  ESIZE_64_BITS() NELEM_FULL()
+OPERANDS:    REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
+IFORM:       VPSHRDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512
+}
+
+
+# EMITTING VPSHRDQ (VPSHRDQ-512-1)
+{
+ICLASS:      VPSHRDQ
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x73 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   UIMM8()
+OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 IMM0:r:b
+IFORM:       VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512
+}
+
+{
+ICLASS:      VPSHRDQ
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+PATTERN:    EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1   UIMM8()  ESIZE_64_BITS() NELEM_FULL()
+OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
+IFORM:       VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512
+}
+
+
+# EMITTING VPSHRDVD (VPSHRDVD-128-1)
+{
+ICLASS:      VPSHRDVD
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x73 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0
+OPERANDS:    REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
+IFORM:       VPSHRDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
+}
+
+{
+ICLASS:      VPSHRDVD
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+PATTERN:    EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_32_BITS() NELEM_FULL()
+OPERANDS:    REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
+IFORM:       VPSHRDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
+}
+
+
+# EMITTING VPSHRDVD (VPSHRDVD-256-1)
+{
+ICLASS:      VPSHRDVD
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x73 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0
+OPERANDS:    REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
+IFORM:       VPSHRDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
+}
+
+{
+ICLASS:      VPSHRDVD
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+PATTERN:    EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_32_BITS() NELEM_FULL()
+OPERANDS:    REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
+IFORM:       VPSHRDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
+}
+
+
+# EMITTING VPSHRDVD (VPSHRDVD-512-1)
+{
+ICLASS:      VPSHRDVD
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x73 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0
+OPERANDS:    REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
+IFORM:       VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
+}
+
+{
+ICLASS:      VPSHRDVD
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+PATTERN:    EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
+OPERANDS:    REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
+IFORM:       VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
+}
+
+
+# EMITTING VPSHRDVQ (VPSHRDVQ-128-1)
+{
+ICLASS:      VPSHRDVQ
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x73 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1
+OPERANDS:    REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
+IFORM:       VPSHRDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
+}
+
+{
+ICLASS:      VPSHRDVQ
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+PATTERN:    EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1    ESIZE_64_BITS() NELEM_FULL()
+OPERANDS:    REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
+IFORM:       VPSHRDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
+}
+
+
+# EMITTING VPSHRDVQ (VPSHRDVQ-256-1)
+{
+ICLASS:      VPSHRDVQ
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x73 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1
+OPERANDS:    REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
+IFORM:       VPSHRDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
+}
+
+{
+ICLASS:      VPSHRDVQ
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+PATTERN:    EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1    ESIZE_64_BITS() NELEM_FULL()
+OPERANDS:    REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
+IFORM:       VPSHRDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
+}
+
+
+# EMITTING VPSHRDVQ (VPSHRDVQ-512-1)
+{
+ICLASS:      VPSHRDVQ
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x73 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1
+OPERANDS:    REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
+IFORM:       VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
+}
+
+{
+ICLASS:      VPSHRDVQ
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+PATTERN:    EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
+OPERANDS:    REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
+IFORM:       VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
+}
+
+
+# EMITTING VPSHRDVW (VPSHRDVW-128-1)
+{
+ICLASS:      VPSHRDVW
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x72 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1
+OPERANDS:    REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
+IFORM:       VPSHRDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
+}
+
+{
+ICLASS:      VPSHRDVW
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
+PATTERN:    EVV 0x72 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W1    ESIZE_16_BITS() NELEM_FULLMEM()
+OPERANDS:    REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
+IFORM:       VPSHRDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
+}
+
+
+# EMITTING VPSHRDVW (VPSHRDVW-256-1)
+{
+ICLASS:      VPSHRDVW
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x72 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1
+OPERANDS:    REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
+IFORM:       VPSHRDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
+}
+
+{
+ICLASS:      VPSHRDVW
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
+PATTERN:    EVV 0x72 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W1    ESIZE_16_BITS() NELEM_FULLMEM()
+OPERANDS:    REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
+IFORM:       VPSHRDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
+}
+
+
+# EMITTING VPSHRDVW (VPSHRDVW-512-1)
+{
+ICLASS:      VPSHRDVW
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x72 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1
+OPERANDS:    REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
+IFORM:       VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
+}
+
+{
+ICLASS:      VPSHRDVW
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
+PATTERN:    EVV 0x72 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W1    ESIZE_16_BITS() NELEM_FULLMEM()
+OPERANDS:    REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
+IFORM:       VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
+}
+
+
+# EMITTING VPSHRDW (VPSHRDW-128-1)
+{
+ICLASS:      VPSHRDW
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x72 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1   UIMM8()
+OPERANDS:    REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 IMM0:r:b
+IFORM:       VPSHRDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512
+}
+
+{
+ICLASS:      VPSHRDW
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
+PATTERN:    EVV 0x72 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W1   UIMM8()  ESIZE_16_BITS() NELEM_FULLMEM()
+OPERANDS:    REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 IMM0:r:b
+IFORM:       VPSHRDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512
+}
+
+
+# EMITTING VPSHRDW (VPSHRDW-256-1)
+{
+ICLASS:      VPSHRDW
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x72 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1   UIMM8()
+OPERANDS:    REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 IMM0:r:b
+IFORM:       VPSHRDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512
+}
+
+{
+ICLASS:      VPSHRDW
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
+PATTERN:    EVV 0x72 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W1   UIMM8()  ESIZE_16_BITS() NELEM_FULLMEM()
+OPERANDS:    REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 IMM0:r:b
+IFORM:       VPSHRDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512
+}
+
+
+# EMITTING VPSHRDW (VPSHRDW-512-1)
+{
+ICLASS:      VPSHRDW
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x72 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   UIMM8()
+OPERANDS:    REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 IMM0:r:b
+IFORM:       VPSHRDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512
+}
+
+{
+ICLASS:      VPSHRDW
+CPL:         3
+CATEGORY:    VBMI2
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VBMI2_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
+PATTERN:    EVV 0x72 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W1   UIMM8()  ESIZE_16_BITS() NELEM_FULLMEM()
+OPERANDS:    REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 IMM0:r:b
+IFORM:       VPSHRDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512
+}
+
+
+
+
+###FILE: ../xed/datafiles/gfni-vaes-vpcl/gfni-sse-isa.xed.txt
+
+#BEGIN_LEGAL
+#
+#Copyright (c) 2018 Intel Corporation
+#
+#  Licensed under the Apache License, Version 2.0 (the "License");
+#  you may not use this file except in compliance with the License.
+#  You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+#  Unless required by applicable law or agreed to in writing, software
+#  distributed under the License is distributed on an "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#  See the License for the specific language governing permissions and
+#  limitations under the License.
+#
+#END_LEGAL
+#
+#
+#
+#    ***** GENERATED FILE -- DO NOT EDIT! *****
+#    ***** GENERATED FILE -- DO NOT EDIT! *****
+#    ***** GENERATED FILE -- DO NOT EDIT! *****
+#
+#
+#
+INSTRUCTIONS()::
+# EMITTING GF2P8AFFINEINVQB (GF2P8AFFINEINVQB-N/A-1)
+{
+ICLASS:      GF2P8AFFINEINVQB
+CPL:         3
+CATEGORY:    GFNI
+EXTENSION:   GFNI
+ISA_SET:     GFNI
+EXCEPTIONS:     SSE_TYPE_4
+REAL_OPCODE: Y
+PATTERN:     0x0F 0x3A 0xCF MOD[0b11] MOD=3  REG[rrr] RM[nnn]  osz_refining_prefix     UIMM8()
+OPERANDS:    REG0=XMM_R():rw:dq:u8 REG1=XMM_B():r:dq:u64 IMM0:r:b
+IFORM:       GF2P8AFFINEINVQB_XMMu8_XMMu64_IMM8
+}
+
+{
+ICLASS:      GF2P8AFFINEINVQB
+CPL:         3
+CATEGORY:    GFNI
+EXTENSION:   GFNI
+ISA_SET:     GFNI
+EXCEPTIONS:     SSE_TYPE_4
+REAL_OPCODE: Y
+ATTRIBUTES:  REQUIRES_ALIGNMENT
+PATTERN:     0x0F 0x3A 0xCF MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  osz_refining_prefix     UIMM8()
+OPERANDS:    REG0=XMM_R():rw:dq:u8 MEM0:r:dq:u64 IMM0:r:b
+IFORM:       GF2P8AFFINEINVQB_XMMu8_MEMu64_IMM8
+}
+
+
+# EMITTING GF2P8AFFINEQB (GF2P8AFFINEQB-N/A-1)
+{
+ICLASS:      GF2P8AFFINEQB
+CPL:         3
+CATEGORY:    GFNI
+EXTENSION:   GFNI
+ISA_SET:     GFNI
+EXCEPTIONS:     SSE_TYPE_4
+REAL_OPCODE: Y
+PATTERN:     0x0F 0x3A 0xCE MOD[0b11] MOD=3  REG[rrr] RM[nnn]  osz_refining_prefix     UIMM8()
+OPERANDS:    REG0=XMM_R():rw:dq:u8 REG1=XMM_B():r:dq:u64 IMM0:r:b
+IFORM:       GF2P8AFFINEQB_XMMu8_XMMu64_IMM8
+}
+
+{
+ICLASS:      GF2P8AFFINEQB
+CPL:         3
+CATEGORY:    GFNI
+EXTENSION:   GFNI
+ISA_SET:     GFNI
+EXCEPTIONS:     SSE_TYPE_4
+REAL_OPCODE: Y
+ATTRIBUTES:  REQUIRES_ALIGNMENT
+PATTERN:     0x0F 0x3A 0xCE MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  osz_refining_prefix     UIMM8()
+OPERANDS:    REG0=XMM_R():rw:dq:u8 MEM0:r:dq:u64 IMM0:r:b
+IFORM:       GF2P8AFFINEQB_XMMu8_MEMu64_IMM8
+}
+
+
+# EMITTING GF2P8MULB (GF2P8MULB-N/A-1)
+{
+ICLASS:      GF2P8MULB
+CPL:         3
+CATEGORY:    GFNI
+EXTENSION:   GFNI
+ISA_SET:     GFNI
+EXCEPTIONS:     SSE_TYPE_4
+REAL_OPCODE: Y
+PATTERN:     0x0F 0x38 0xCF MOD[0b11] MOD=3  REG[rrr] RM[nnn]  osz_refining_prefix
+OPERANDS:    REG0=XMM_R():rw:dq:u8 REG1=XMM_B():r:dq:u8
+IFORM:       GF2P8MULB_XMMu8_XMMu8
+}
+
+{
+ICLASS:      GF2P8MULB
+CPL:         3
+CATEGORY:    GFNI
+EXTENSION:   GFNI
+ISA_SET:     GFNI
+EXCEPTIONS:     SSE_TYPE_4
+REAL_OPCODE: Y
+ATTRIBUTES:  REQUIRES_ALIGNMENT
+PATTERN:     0x0F 0x38 0xCF MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  osz_refining_prefix
+OPERANDS:    REG0=XMM_R():rw:dq:u8 MEM0:r:dq:u8
+IFORM:       GF2P8MULB_XMMu8_MEMu8
+}
+
+
+
+
+###FILE: ../xed/datafiles/gfni-vaes-vpcl/gfni-evex-isa.xed.txt
+
+#BEGIN_LEGAL
+#
+#Copyright (c) 2018 Intel Corporation
+#
+#  Licensed under the Apache License, Version 2.0 (the "License");
+#  you may not use this file except in compliance with the License.
+#  You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+#  Unless required by applicable law or agreed to in writing, software
+#  distributed under the License is distributed on an "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#  See the License for the specific language governing permissions and
+#  limitations under the License.
+#
+#END_LEGAL
+#
+#
+#
+#    ***** GENERATED FILE -- DO NOT EDIT! *****
+#    ***** GENERATED FILE -- DO NOT EDIT! *****
+#    ***** GENERATED FILE -- DO NOT EDIT! *****
+#
+#
+#
+EVEX_INSTRUCTIONS()::
+# EMITTING VGF2P8AFFINEINVQB (VGF2P8AFFINEINVQB-128-1)
+{
+ICLASS:      VGF2P8AFFINEINVQB
+CPL:         3
+CATEGORY:    GFNI
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_GFNI_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0xCF V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1   UIMM8()
+OPERANDS:    REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u64 IMM0:r:b
+IFORM:       VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512
+}
+
+{
+ICLASS:      VGF2P8AFFINEINVQB
+CPL:         3
+CATEGORY:    GFNI
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_GFNI_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+PATTERN:    EVV 0xCF V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1   UIMM8()  ESIZE_64_BITS() NELEM_FULL()
+OPERANDS:    REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
+IFORM:       VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512
+}
+
+
+# EMITTING VGF2P8AFFINEINVQB (VGF2P8AFFINEINVQB-256-1)
+{
+ICLASS:      VGF2P8AFFINEINVQB
+CPL:         3
+CATEGORY:    GFNI
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_GFNI_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0xCF V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1   UIMM8()
+OPERANDS:    REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u64 IMM0:r:b
+IFORM:       VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512
+}
+
+{
+ICLASS:      VGF2P8AFFINEINVQB
+CPL:         3
+CATEGORY:    GFNI
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_GFNI_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+PATTERN:    EVV 0xCF V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1   UIMM8()  ESIZE_64_BITS() NELEM_FULL()
+OPERANDS:    REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
+IFORM:       VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512
+}
+
+
+# EMITTING VGF2P8AFFINEINVQB (VGF2P8AFFINEINVQB-512-1)
+{
+ICLASS:      VGF2P8AFFINEINVQB
+CPL:         3
+CATEGORY:    GFNI
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_GFNI_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0xCF V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   UIMM8()
+OPERANDS:    REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu64 IMM0:r:b
+IFORM:       VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512
+}
+
+{
+ICLASS:      VGF2P8AFFINEINVQB
+CPL:         3
+CATEGORY:    GFNI
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_GFNI_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+PATTERN:    EVV 0xCF V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1   UIMM8()  ESIZE_64_BITS() NELEM_FULL()
+OPERANDS:    REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
+IFORM:       VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512
+}
+
+
+# EMITTING VGF2P8AFFINEQB (VGF2P8AFFINEQB-128-1)
+{
+ICLASS:      VGF2P8AFFINEQB
+CPL:         3
+CATEGORY:    GFNI
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_GFNI_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0xCE V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1   UIMM8()
+OPERANDS:    REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u64 IMM0:r:b
+IFORM:       VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512
+}
+
+{
+ICLASS:      VGF2P8AFFINEQB
+CPL:         3
+CATEGORY:    GFNI
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_GFNI_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+PATTERN:    EVV 0xCE V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1   UIMM8()  ESIZE_64_BITS() NELEM_FULL()
+OPERANDS:    REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
+IFORM:       VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512
+}
+
+
+# EMITTING VGF2P8AFFINEQB (VGF2P8AFFINEQB-256-1)
+{
+ICLASS:      VGF2P8AFFINEQB
+CPL:         3
+CATEGORY:    GFNI
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_GFNI_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0xCE V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1   UIMM8()
+OPERANDS:    REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u64 IMM0:r:b
+IFORM:       VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512
+}
+
+{
+ICLASS:      VGF2P8AFFINEQB
+CPL:         3
+CATEGORY:    GFNI
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_GFNI_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+PATTERN:    EVV 0xCE V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1   UIMM8()  ESIZE_64_BITS() NELEM_FULL()
+OPERANDS:    REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
+IFORM:       VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512
+}
+
+
+# EMITTING VGF2P8AFFINEQB (VGF2P8AFFINEQB-512-1)
+{
+ICLASS:      VGF2P8AFFINEQB
+CPL:         3
+CATEGORY:    GFNI
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_GFNI_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0xCE V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   UIMM8()
+OPERANDS:    REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu64 IMM0:r:b
+IFORM:       VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512
+}
+
+{
+ICLASS:      VGF2P8AFFINEQB
+CPL:         3
+CATEGORY:    GFNI
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_GFNI_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+PATTERN:    EVV 0xCE V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1   UIMM8()  ESIZE_64_BITS() NELEM_FULL()
+OPERANDS:    REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
+IFORM:       VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512
+}
+
+
+# EMITTING VGF2P8MULB (VGF2P8MULB-128-1)
+{
+ICLASS:      VGF2P8MULB
+CPL:         3
+CATEGORY:    GFNI
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_GFNI_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0xCF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0
+OPERANDS:    REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8
+IFORM:       VGF2P8MULB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512
+}
+
+{
+ICLASS:      VGF2P8MULB
+CPL:         3
+CATEGORY:    GFNI
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_GFNI_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
+PATTERN:    EVV 0xCF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0    ESIZE_8_BITS() NELEM_FULLMEM()
+OPERANDS:    REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8
+IFORM:       VGF2P8MULB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512
+}
+
+
+# EMITTING VGF2P8MULB (VGF2P8MULB-256-1)
+{
+ICLASS:      VGF2P8MULB
+CPL:         3
+CATEGORY:    GFNI
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_GFNI_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0xCF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0
+OPERANDS:    REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8
+IFORM:       VGF2P8MULB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512
+}
+
+{
+ICLASS:      VGF2P8MULB
+CPL:         3
+CATEGORY:    GFNI
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_GFNI_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
+PATTERN:    EVV 0xCF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W0    ESIZE_8_BITS() NELEM_FULLMEM()
+OPERANDS:    REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8
+IFORM:       VGF2P8MULB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512
+}
+
+
+# EMITTING VGF2P8MULB (VGF2P8MULB-512-1)
+{
+ICLASS:      VGF2P8MULB
+CPL:         3
+CATEGORY:    GFNI
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_GFNI_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0xCF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0
+OPERANDS:    REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8
+IFORM:       VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512
+}
+
+{
+ICLASS:      VGF2P8MULB
+CPL:         3
+CATEGORY:    GFNI
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_GFNI_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
+PATTERN:    EVV 0xCF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0    ESIZE_8_BITS() NELEM_FULLMEM()
+OPERANDS:    REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8
+IFORM:       VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512
+}
+
+
+
+
+###FILE: ../xed/datafiles/gfni-vaes-vpcl/gfni-vex-isa.xed.txt
+
+#BEGIN_LEGAL
+#
+#Copyright (c) 2018 Intel Corporation
+#
+#  Licensed under the Apache License, Version 2.0 (the "License");
+#  you may not use this file except in compliance with the License.
+#  You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+#  Unless required by applicable law or agreed to in writing, software
+#  distributed under the License is distributed on an "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#  See the License for the specific language governing permissions and
+#  limitations under the License.
+#
+#END_LEGAL
+#
+#
+#
+#    ***** GENERATED FILE -- DO NOT EDIT! *****
+#    ***** GENERATED FILE -- DO NOT EDIT! *****
+#    ***** GENERATED FILE -- DO NOT EDIT! *****
+#
+#
+#
+AVX_INSTRUCTIONS()::
+# EMITTING VGF2P8AFFINEINVQB (VGF2P8AFFINEINVQB-128-2)
+{
+ICLASS:      VGF2P8AFFINEINVQB
+CPL:         3
+CATEGORY:    GFNI
+EXTENSION:   GFNI
+ISA_SET:     AVX_GFNI
+EXCEPTIONS:     avx-type-4
+REAL_OPCODE: Y
+PATTERN:    VV1 0xCF V66 V0F3A MOD[0b11] MOD=3  REG[rrr] RM[nnn]  VL128  W1   UIMM8()
+OPERANDS:    REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u64 IMM0:r:b
+IFORM:       VGF2P8AFFINEINVQB_XMMu8_XMMu8_XMMu64_IMM8
+}
+
+{
+ICLASS:      VGF2P8AFFINEINVQB
+CPL:         3
+CATEGORY:    GFNI
+EXTENSION:   GFNI
+ISA_SET:     AVX_GFNI
+EXCEPTIONS:     avx-type-4
+REAL_OPCODE: Y
+PATTERN:    VV1 0xCF V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1   UIMM8()
+OPERANDS:    REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u64 IMM0:r:b
+IFORM:       VGF2P8AFFINEINVQB_XMMu8_XMMu8_MEMu64_IMM8
+}
+
+
+# EMITTING VGF2P8AFFINEINVQB (VGF2P8AFFINEINVQB-256-2)
+{
+ICLASS:      VGF2P8AFFINEINVQB
+CPL:         3
+CATEGORY:    GFNI
+EXTENSION:   GFNI
+ISA_SET:     AVX_GFNI
+EXCEPTIONS:     avx-type-4
+REAL_OPCODE: Y
+PATTERN:    VV1 0xCF V66 V0F3A MOD[0b11] MOD=3  REG[rrr] RM[nnn]  VL256  W1   UIMM8()
+OPERANDS:    REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u64 IMM0:r:b
+IFORM:       VGF2P8AFFINEINVQB_YMMu8_YMMu8_YMMu64_IMM8
+}
+
+{
+ICLASS:      VGF2P8AFFINEINVQB
+CPL:         3
+CATEGORY:    GFNI
+EXTENSION:   GFNI
+ISA_SET:     AVX_GFNI
+EXCEPTIONS:     avx-type-4
+REAL_OPCODE: Y
+PATTERN:    VV1 0xCF V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1   UIMM8()
+OPERANDS:    REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u64 IMM0:r:b
+IFORM:       VGF2P8AFFINEINVQB_YMMu8_YMMu8_MEMu64_IMM8
+}
+
+
+# EMITTING VGF2P8AFFINEQB (VGF2P8AFFINEQB-128-2)
+{
+ICLASS:      VGF2P8AFFINEQB
+CPL:         3
+CATEGORY:    GFNI
+EXTENSION:   GFNI
+ISA_SET:     AVX_GFNI
+EXCEPTIONS:     avx-type-4
+REAL_OPCODE: Y
+PATTERN:    VV1 0xCE V66 V0F3A MOD[0b11] MOD=3  REG[rrr] RM[nnn]  VL128  W1   UIMM8()
+OPERANDS:    REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u64 IMM0:r:b
+IFORM:       VGF2P8AFFINEQB_XMMu8_XMMu8_XMMu64_IMM8
+}
+
+{
+ICLASS:      VGF2P8AFFINEQB
+CPL:         3
+CATEGORY:    GFNI
+EXTENSION:   GFNI
+ISA_SET:     AVX_GFNI
+EXCEPTIONS:     avx-type-4
+REAL_OPCODE: Y
+PATTERN:    VV1 0xCE V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1   UIMM8()
+OPERANDS:    REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u64 IMM0:r:b
+IFORM:       VGF2P8AFFINEQB_XMMu8_XMMu8_MEMu64_IMM8
+}
+
+
+# EMITTING VGF2P8AFFINEQB (VGF2P8AFFINEQB-256-2)
+{
+ICLASS:      VGF2P8AFFINEQB
+CPL:         3
+CATEGORY:    GFNI
+EXTENSION:   GFNI
+ISA_SET:     AVX_GFNI
+EXCEPTIONS:     avx-type-4
+REAL_OPCODE: Y
+PATTERN:    VV1 0xCE V66 V0F3A MOD[0b11] MOD=3  REG[rrr] RM[nnn]  VL256  W1   UIMM8()
+OPERANDS:    REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u64 IMM0:r:b
+IFORM:       VGF2P8AFFINEQB_YMMu8_YMMu8_YMMu64_IMM8
+}
+
+{
+ICLASS:      VGF2P8AFFINEQB
+CPL:         3
+CATEGORY:    GFNI
+EXTENSION:   GFNI
+ISA_SET:     AVX_GFNI
+EXCEPTIONS:     avx-type-4
+REAL_OPCODE: Y
+PATTERN:    VV1 0xCE V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1   UIMM8()
+OPERANDS:    REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u64 IMM0:r:b
+IFORM:       VGF2P8AFFINEQB_YMMu8_YMMu8_MEMu64_IMM8
+}
+
+
+# EMITTING VGF2P8MULB (VGF2P8MULB-128-2)
+{
+ICLASS:      VGF2P8MULB
+CPL:         3
+CATEGORY:    GFNI
+EXTENSION:   GFNI
+ISA_SET:     AVX_GFNI
+EXCEPTIONS:     avx-type-4
+REAL_OPCODE: Y
+PATTERN:    VV1 0xCF V66 V0F38 MOD[0b11] MOD=3  REG[rrr] RM[nnn]  VL128  W0
+OPERANDS:    REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8
+IFORM:       VGF2P8MULB_XMMu8_XMMu8_XMMu8
+}
+
+{
+ICLASS:      VGF2P8MULB
+CPL:         3
+CATEGORY:    GFNI
+EXTENSION:   GFNI
+ISA_SET:     AVX_GFNI
+EXCEPTIONS:     avx-type-4
+REAL_OPCODE: Y
+PATTERN:    VV1 0xCF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0
+OPERANDS:    REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8
+IFORM:       VGF2P8MULB_XMMu8_XMMu8_MEMu8
+}
+
+
+# EMITTING VGF2P8MULB (VGF2P8MULB-256-2)
+{
+ICLASS:      VGF2P8MULB
+CPL:         3
+CATEGORY:    GFNI
+EXTENSION:   GFNI
+ISA_SET:     AVX_GFNI
+EXCEPTIONS:     avx-type-4
+REAL_OPCODE: Y
+PATTERN:    VV1 0xCF V66 V0F38 MOD[0b11] MOD=3  REG[rrr] RM[nnn]  VL256  W0
+OPERANDS:    REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8
+IFORM:       VGF2P8MULB_YMMu8_YMMu8_YMMu8
+}
+
+{
+ICLASS:      VGF2P8MULB
+CPL:         3
+CATEGORY:    GFNI
+EXTENSION:   GFNI
+ISA_SET:     AVX_GFNI
+EXCEPTIONS:     avx-type-4
+REAL_OPCODE: Y
+PATTERN:    VV1 0xCF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0
+OPERANDS:    REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8
+IFORM:       VGF2P8MULB_YMMu8_YMMu8_MEMu8
+}
+
+
+
+
+###FILE: ../xed/datafiles/gfni-vaes-vpcl/vaes-evex-isa.xed.txt
+
+#BEGIN_LEGAL
+#
+#Copyright (c) 2018 Intel Corporation
+#
+#  Licensed under the Apache License, Version 2.0 (the "License");
+#  you may not use this file except in compliance with the License.
+#  You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+#  Unless required by applicable law or agreed to in writing, software
+#  distributed under the License is distributed on an "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#  See the License for the specific language governing permissions and
+#  limitations under the License.
+#
+#END_LEGAL
+#
+#
+#
+#    ***** GENERATED FILE -- DO NOT EDIT! *****
+#    ***** GENERATED FILE -- DO NOT EDIT! *****
+#    ***** GENERATED FILE -- DO NOT EDIT! *****
+#
+#
+#
+EVEX_INSTRUCTIONS()::
+# EMITTING VAESDEC (VAESDEC-128-1)
+{
+ICLASS:      VAESDEC
+CPL:         3
+CATEGORY:    VAES
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VAES_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+PATTERN:    EVV 0xDE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128      ZEROING=0 MASK=0
+OPERANDS:    REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 REG2=XMM_B3():r:dq:u128
+IFORM:       VAESDEC_XMMu128_XMMu128_XMMu128_AVX512
+}
+
+{
+ICLASS:      VAESDEC
+CPL:         3
+CATEGORY:    VAES
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VAES_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  DISP8_FULLMEM
+PATTERN:    EVV 0xDE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128      ZEROING=0 MASK=0  ESIZE_128_BITS() NELEM_FULLMEM()
+OPERANDS:    REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 MEM0:r:dq:u128
+IFORM:       VAESDEC_XMMu128_XMMu128_MEMu128_AVX512
+}
+
+
+# EMITTING VAESDEC (VAESDEC-256-1)
+{
+ICLASS:      VAESDEC
+CPL:         3
+CATEGORY:    VAES
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VAES_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+PATTERN:    EVV 0xDE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256      ZEROING=0 MASK=0
+OPERANDS:    REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 REG2=YMM_B3():r:qq:u128
+IFORM:       VAESDEC_YMMu128_YMMu128_YMMu128_AVX512
+}
+
+{
+ICLASS:      VAESDEC
+CPL:         3
+CATEGORY:    VAES
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VAES_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  DISP8_FULLMEM
+PATTERN:    EVV 0xDE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256      ZEROING=0 MASK=0  ESIZE_128_BITS() NELEM_FULLMEM()
+OPERANDS:    REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 MEM0:r:qq:u128
+IFORM:       VAESDEC_YMMu128_YMMu128_MEMu128_AVX512
+}
+
+
+# EMITTING VAESDEC (VAESDEC-512-1)
+{
+ICLASS:      VAESDEC
+CPL:         3
+CATEGORY:    VAES
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VAES_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+PATTERN:    EVV 0xDE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512      ZEROING=0 MASK=0
+OPERANDS:    REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 REG2=ZMM_B3():r:zu128
+IFORM:       VAESDEC_ZMMu128_ZMMu128_ZMMu128_AVX512
+}
+
+{
+ICLASS:      VAESDEC
+CPL:         3
+CATEGORY:    VAES
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VAES_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  DISP8_FULLMEM
+PATTERN:    EVV 0xDE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512      ZEROING=0 MASK=0  ESIZE_128_BITS() NELEM_FULLMEM()
+OPERANDS:    REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 MEM0:r:zd:u128
+IFORM:       VAESDEC_ZMMu128_ZMMu128_MEMu128_AVX512
+}
+
+
+# EMITTING VAESDECLAST (VAESDECLAST-128-1)
+{
+ICLASS:      VAESDECLAST
+CPL:         3
+CATEGORY:    VAES
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VAES_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+PATTERN:    EVV 0xDF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128      ZEROING=0 MASK=0
+OPERANDS:    REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 REG2=XMM_B3():r:dq:u128
+IFORM:       VAESDECLAST_XMMu128_XMMu128_XMMu128_AVX512
+}
+
+{
+ICLASS:      VAESDECLAST
+CPL:         3
+CATEGORY:    VAES
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VAES_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  DISP8_FULLMEM
+PATTERN:    EVV 0xDF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128      ZEROING=0 MASK=0  ESIZE_128_BITS() NELEM_FULLMEM()
+OPERANDS:    REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 MEM0:r:dq:u128
+IFORM:       VAESDECLAST_XMMu128_XMMu128_MEMu128_AVX512
+}
+
+
+# EMITTING VAESDECLAST (VAESDECLAST-256-1)
+{
+ICLASS:      VAESDECLAST
+CPL:         3
+CATEGORY:    VAES
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VAES_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+PATTERN:    EVV 0xDF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256      ZEROING=0 MASK=0
+OPERANDS:    REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 REG2=YMM_B3():r:qq:u128
+IFORM:       VAESDECLAST_YMMu128_YMMu128_YMMu128_AVX512
+}
+
+{
+ICLASS:      VAESDECLAST
+CPL:         3
+CATEGORY:    VAES
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VAES_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  DISP8_FULLMEM
+PATTERN:    EVV 0xDF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256      ZEROING=0 MASK=0  ESIZE_128_BITS() NELEM_FULLMEM()
+OPERANDS:    REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 MEM0:r:qq:u128
+IFORM:       VAESDECLAST_YMMu128_YMMu128_MEMu128_AVX512
+}
+
+
+# EMITTING VAESDECLAST (VAESDECLAST-512-1)
+{
+ICLASS:      VAESDECLAST
+CPL:         3
+CATEGORY:    VAES
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VAES_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+PATTERN:    EVV 0xDF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512      ZEROING=0 MASK=0
+OPERANDS:    REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 REG2=ZMM_B3():r:zu128
+IFORM:       VAESDECLAST_ZMMu128_ZMMu128_ZMMu128_AVX512
+}
+
+{
+ICLASS:      VAESDECLAST
+CPL:         3
+CATEGORY:    VAES
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VAES_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  DISP8_FULLMEM
+PATTERN:    EVV 0xDF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512      ZEROING=0 MASK=0  ESIZE_128_BITS() NELEM_FULLMEM()
+OPERANDS:    REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 MEM0:r:zd:u128
+IFORM:       VAESDECLAST_ZMMu128_ZMMu128_MEMu128_AVX512
+}
+
+
+# EMITTING VAESENC (VAESENC-128-1)
+{
+ICLASS:      VAESENC
+CPL:         3
+CATEGORY:    VAES
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VAES_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+PATTERN:    EVV 0xDC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128      ZEROING=0 MASK=0
+OPERANDS:    REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 REG2=XMM_B3():r:dq:u128
+IFORM:       VAESENC_XMMu128_XMMu128_XMMu128_AVX512
+}
+
+{
+ICLASS:      VAESENC
+CPL:         3
+CATEGORY:    VAES
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VAES_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  DISP8_FULLMEM
+PATTERN:    EVV 0xDC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128      ZEROING=0 MASK=0  ESIZE_128_BITS() NELEM_FULLMEM()
+OPERANDS:    REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 MEM0:r:dq:u128
+IFORM:       VAESENC_XMMu128_XMMu128_MEMu128_AVX512
+}
+
+
+# EMITTING VAESENC (VAESENC-256-1)
+{
+ICLASS:      VAESENC
+CPL:         3
+CATEGORY:    VAES
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VAES_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+PATTERN:    EVV 0xDC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256      ZEROING=0 MASK=0
+OPERANDS:    REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 REG2=YMM_B3():r:qq:u128
+IFORM:       VAESENC_YMMu128_YMMu128_YMMu128_AVX512
+}
+
+{
+ICLASS:      VAESENC
+CPL:         3
+CATEGORY:    VAES
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VAES_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  DISP8_FULLMEM
+PATTERN:    EVV 0xDC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256      ZEROING=0 MASK=0  ESIZE_128_BITS() NELEM_FULLMEM()
+OPERANDS:    REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 MEM0:r:qq:u128
+IFORM:       VAESENC_YMMu128_YMMu128_MEMu128_AVX512
+}
+
+
+# EMITTING VAESENC (VAESENC-512-1)
+{
+ICLASS:      VAESENC
+CPL:         3
+CATEGORY:    VAES
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VAES_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+PATTERN:    EVV 0xDC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512      ZEROING=0 MASK=0
+OPERANDS:    REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 REG2=ZMM_B3():r:zu128
+IFORM:       VAESENC_ZMMu128_ZMMu128_ZMMu128_AVX512
+}
+
+{
+ICLASS:      VAESENC
+CPL:         3
+CATEGORY:    VAES
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VAES_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  DISP8_FULLMEM
+PATTERN:    EVV 0xDC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512      ZEROING=0 MASK=0  ESIZE_128_BITS() NELEM_FULLMEM()
+OPERANDS:    REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 MEM0:r:zd:u128
+IFORM:       VAESENC_ZMMu128_ZMMu128_MEMu128_AVX512
+}
+
+
+# EMITTING VAESENCLAST (VAESENCLAST-128-1)
+{
+ICLASS:      VAESENCLAST
+CPL:         3
+CATEGORY:    VAES
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VAES_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+PATTERN:    EVV 0xDD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128      ZEROING=0 MASK=0
+OPERANDS:    REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 REG2=XMM_B3():r:dq:u128
+IFORM:       VAESENCLAST_XMMu128_XMMu128_XMMu128_AVX512
+}
+
+{
+ICLASS:      VAESENCLAST
+CPL:         3
+CATEGORY:    VAES
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VAES_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  DISP8_FULLMEM
+PATTERN:    EVV 0xDD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128      ZEROING=0 MASK=0  ESIZE_128_BITS() NELEM_FULLMEM()
+OPERANDS:    REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 MEM0:r:dq:u128
+IFORM:       VAESENCLAST_XMMu128_XMMu128_MEMu128_AVX512
+}
+
+
+# EMITTING VAESENCLAST (VAESENCLAST-256-1)
+{
+ICLASS:      VAESENCLAST
+CPL:         3
+CATEGORY:    VAES
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VAES_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+PATTERN:    EVV 0xDD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256      ZEROING=0 MASK=0
+OPERANDS:    REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 REG2=YMM_B3():r:qq:u128
+IFORM:       VAESENCLAST_YMMu128_YMMu128_YMMu128_AVX512
+}
+
+{
+ICLASS:      VAESENCLAST
+CPL:         3
+CATEGORY:    VAES
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VAES_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  DISP8_FULLMEM
+PATTERN:    EVV 0xDD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256      ZEROING=0 MASK=0  ESIZE_128_BITS() NELEM_FULLMEM()
+OPERANDS:    REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 MEM0:r:qq:u128
+IFORM:       VAESENCLAST_YMMu128_YMMu128_MEMu128_AVX512
+}
+
+
+# EMITTING VAESENCLAST (VAESENCLAST-512-1)
+{
+ICLASS:      VAESENCLAST
+CPL:         3
+CATEGORY:    VAES
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VAES_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+PATTERN:    EVV 0xDD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512      ZEROING=0 MASK=0
+OPERANDS:    REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 REG2=ZMM_B3():r:zu128
+IFORM:       VAESENCLAST_ZMMu128_ZMMu128_ZMMu128_AVX512
+}
+
+{
+ICLASS:      VAESENCLAST
+CPL:         3
+CATEGORY:    VAES
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VAES_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  DISP8_FULLMEM
+PATTERN:    EVV 0xDD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512      ZEROING=0 MASK=0  ESIZE_128_BITS() NELEM_FULLMEM()
+OPERANDS:    REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 MEM0:r:zd:u128
+IFORM:       VAESENCLAST_ZMMu128_ZMMu128_MEMu128_AVX512
+}
+
+
+# EMITTING VPCLMULQDQ (VPCLMULQDQ-128-1)
+{
+ICLASS:      VPCLMULQDQ
+CPL:         3
+CATEGORY:    VPCLMULQDQ
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VPCLMULQDQ_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+PATTERN:    EVV 0x44 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128      ZEROING=0 MASK=0 UIMM8()
+OPERANDS:    REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u64 REG2=XMM_B3():r:dq:u64 IMM0:r:b
+IFORM:       VPCLMULQDQ_XMMu128_XMMu64_XMMu64_IMM8_AVX512
+}
+
+{
+ICLASS:      VPCLMULQDQ
+CPL:         3
+CATEGORY:    VPCLMULQDQ
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VPCLMULQDQ_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  DISP8_FULLMEM
+PATTERN:    EVV 0x44 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128      ZEROING=0 MASK=0 UIMM8()  ESIZE_64_BITS() NELEM_FULLMEM()
+OPERANDS:    REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u64 MEM0:r:dq:u64 IMM0:r:b
+IFORM:       VPCLMULQDQ_XMMu128_XMMu64_MEMu64_IMM8_AVX512
+}
+
+
+# EMITTING VPCLMULQDQ (VPCLMULQDQ-256-1)
+{
+ICLASS:      VPCLMULQDQ
+CPL:         3
+CATEGORY:    VPCLMULQDQ
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VPCLMULQDQ_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+PATTERN:    EVV 0x44 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256      ZEROING=0 MASK=0 UIMM8()
+OPERANDS:    REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u64 REG2=YMM_B3():r:qq:u64 IMM0:r:b
+IFORM:       VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_AVX512
+}
+
+{
+ICLASS:      VPCLMULQDQ
+CPL:         3
+CATEGORY:    VPCLMULQDQ
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VPCLMULQDQ_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  DISP8_FULLMEM
+PATTERN:    EVV 0x44 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256      ZEROING=0 MASK=0 UIMM8()  ESIZE_64_BITS() NELEM_FULLMEM()
+OPERANDS:    REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u64 MEM0:r:qq:u64 IMM0:r:b
+IFORM:       VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8_AVX512
+}
+
+
+# EMITTING VPCLMULQDQ (VPCLMULQDQ-512-1)
+{
+ICLASS:      VPCLMULQDQ
+CPL:         3
+CATEGORY:    VPCLMULQDQ
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VPCLMULQDQ_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+PATTERN:    EVV 0x44 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512      ZEROING=0 MASK=0 UIMM8()
+OPERANDS:    REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu64 REG2=ZMM_B3():r:zu64 IMM0:r:b
+IFORM:       VPCLMULQDQ_ZMMu128_ZMMu64_ZMMu64_IMM8_AVX512
+}
+
+{
+ICLASS:      VPCLMULQDQ
+CPL:         3
+CATEGORY:    VPCLMULQDQ
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VPCLMULQDQ_512
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  DISP8_FULLMEM
+PATTERN:    EVV 0x44 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512      ZEROING=0 MASK=0 UIMM8()  ESIZE_64_BITS() NELEM_FULLMEM()
+OPERANDS:    REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu64 MEM0:r:zd:u64 IMM0:r:b
+IFORM:       VPCLMULQDQ_ZMMu128_ZMMu64_MEMu64_IMM8_AVX512
+}
+
+
+
+
+###FILE: ../xed/datafiles/gfni-vaes-vpcl/vaes-vex-isa.xed.txt
+
+#BEGIN_LEGAL
+#
+#Copyright (c) 2018 Intel Corporation
+#
+#  Licensed under the Apache License, Version 2.0 (the "License");
+#  you may not use this file except in compliance with the License.
+#  You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+#  Unless required by applicable law or agreed to in writing, software
+#  distributed under the License is distributed on an "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#  See the License for the specific language governing permissions and
+#  limitations under the License.
+#
+#END_LEGAL
+#
+#
+#
+#    ***** GENERATED FILE -- DO NOT EDIT! *****
+#    ***** GENERATED FILE -- DO NOT EDIT! *****
+#    ***** GENERATED FILE -- DO NOT EDIT! *****
+#
+#
+#
+AVX_INSTRUCTIONS()::
+# EMITTING VAESDEC (VAESDEC-256-2)
+{
+ICLASS:      VAESDEC
+CPL:         3
+CATEGORY:    VAES
+EXTENSION:   VAES
+ISA_SET:     VAES
+EXCEPTIONS:     avx-type-4
+REAL_OPCODE: Y
+PATTERN:    VV1 0xDE V66 V0F38 MOD[0b11] MOD=3  REG[rrr] RM[nnn]  VL256
+OPERANDS:    REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 REG2=YMM_B():r:qq:u128
+IFORM:       VAESDEC_YMMu128_YMMu128_YMMu128
+}
+
+{
+ICLASS:      VAESDEC
+CPL:         3
+CATEGORY:    VAES
+EXTENSION:   VAES
+ISA_SET:     VAES
+EXCEPTIONS:     avx-type-4
+REAL_OPCODE: Y
+PATTERN:    VV1 0xDE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256
+OPERANDS:    REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 MEM0:r:qq:u128
+IFORM:       VAESDEC_YMMu128_YMMu128_MEMu128
+}
+
+
+# EMITTING VAESDECLAST (VAESDECLAST-256-2)
+{
+ICLASS:      VAESDECLAST
+CPL:         3
+CATEGORY:    VAES
+EXTENSION:   VAES
+ISA_SET:     VAES
+EXCEPTIONS:     avx-type-4
+REAL_OPCODE: Y
+PATTERN:    VV1 0xDF V66 V0F38 MOD[0b11] MOD=3  REG[rrr] RM[nnn]  VL256
+OPERANDS:    REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 REG2=YMM_B():r:qq:u128
+IFORM:       VAESDECLAST_YMMu128_YMMu128_YMMu128
+}
+
+{
+ICLASS:      VAESDECLAST
+CPL:         3
+CATEGORY:    VAES
+EXTENSION:   VAES
+ISA_SET:     VAES
+EXCEPTIONS:     avx-type-4
+REAL_OPCODE: Y
+PATTERN:    VV1 0xDF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256
+OPERANDS:    REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 MEM0:r:qq:u128
+IFORM:       VAESDECLAST_YMMu128_YMMu128_MEMu128
+}
+
+
+# EMITTING VAESENC (VAESENC-256-2)
+{
+ICLASS:      VAESENC
+CPL:         3
+CATEGORY:    VAES
+EXTENSION:   VAES
+ISA_SET:     VAES
+EXCEPTIONS:     avx-type-4
+REAL_OPCODE: Y
+PATTERN:    VV1 0xDC V66 V0F38 MOD[0b11] MOD=3  REG[rrr] RM[nnn]  VL256
+OPERANDS:    REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 REG2=YMM_B():r:qq:u128
+IFORM:       VAESENC_YMMu128_YMMu128_YMMu128
+}
+
+{
+ICLASS:      VAESENC
+CPL:         3
+CATEGORY:    VAES
+EXTENSION:   VAES
+ISA_SET:     VAES
+EXCEPTIONS:     avx-type-4
+REAL_OPCODE: Y
+PATTERN:    VV1 0xDC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256
+OPERANDS:    REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 MEM0:r:qq:u128
+IFORM:       VAESENC_YMMu128_YMMu128_MEMu128
+}
+
+
+# EMITTING VAESENCLAST (VAESENCLAST-256-2)
+{
+ICLASS:      VAESENCLAST
+CPL:         3
+CATEGORY:    VAES
+EXTENSION:   VAES
+ISA_SET:     VAES
+EXCEPTIONS:     avx-type-4
+REAL_OPCODE: Y
+PATTERN:    VV1 0xDD V66 V0F38 MOD[0b11] MOD=3  REG[rrr] RM[nnn]  VL256
+OPERANDS:    REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 REG2=YMM_B():r:qq:u128
+IFORM:       VAESENCLAST_YMMu128_YMMu128_YMMu128
+}
+
+{
+ICLASS:      VAESENCLAST
+CPL:         3
+CATEGORY:    VAES
+EXTENSION:   VAES
+ISA_SET:     VAES
+EXCEPTIONS:     avx-type-4
+REAL_OPCODE: Y
+PATTERN:    VV1 0xDD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256
+OPERANDS:    REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 MEM0:r:qq:u128
+IFORM:       VAESENCLAST_YMMu128_YMMu128_MEMu128
+}
+
+
+# EMITTING VPCLMULQDQ (VPCLMULQDQ-256-2)
+{
+ICLASS:      VPCLMULQDQ
+CPL:         3
+CATEGORY:    VPCLMULQDQ
+EXTENSION:   VPCLMULQDQ
+ISA_SET:     VPCLMULQDQ
+EXCEPTIONS:     avx-type-4
+REAL_OPCODE: Y
+PATTERN:    VV1 0x44 V66 V0F3A MOD[0b11] MOD=3  REG[rrr] RM[nnn]  VL256     UIMM8()
+OPERANDS:    REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 IMM0:r:b
+IFORM:       VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8
+}
+
+{
+ICLASS:      VPCLMULQDQ
+CPL:         3
+CATEGORY:    VPCLMULQDQ
+EXTENSION:   VPCLMULQDQ
+ISA_SET:     VPCLMULQDQ
+EXCEPTIONS:     avx-type-4
+REAL_OPCODE: Y
+PATTERN:    VV1 0x44 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256     UIMM8()
+OPERANDS:    REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 IMM0:r:b
+IFORM:       VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8
+}
+
+
+
+
+###FILE: ../xed/datafiles/vpopcntdq-vl/vpopcntdq-vl-isa.xed.txt
+
+#BEGIN_LEGAL
+#
+#Copyright (c) 2018 Intel Corporation
+#
+#  Licensed under the Apache License, Version 2.0 (the "License");
+#  you may not use this file except in compliance with the License.
+#  You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+#  Unless required by applicable law or agreed to in writing, software
+#  distributed under the License is distributed on an "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#  See the License for the specific language governing permissions and
+#  limitations under the License.
+#
+#END_LEGAL
+#
+#
+#
+#    ***** GENERATED FILE -- DO NOT EDIT! *****
+#    ***** GENERATED FILE -- DO NOT EDIT! *****
+#    ***** GENERATED FILE -- DO NOT EDIT! *****
+#
+#
+#
+EVEX_INSTRUCTIONS()::
+# EMITTING VPOPCNTD (VPOPCNTD-128-1)
+{
+ICLASS:      VPOPCNTD
+CPL:         3
+CATEGORY:    AVX512
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VPOPCNTDQ_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x55 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0  NOEVSR
+OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32
+IFORM:       VPOPCNTD_XMMu32_MASKmskw_XMMu32_AVX512
+}
+
+{
+ICLASS:      VPOPCNTD
+CPL:         3
+CATEGORY:    AVX512
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VPOPCNTDQ_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+PATTERN:    EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL()
+OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR
+IFORM:       VPOPCNTD_XMMu32_MASKmskw_MEMu32_AVX512
+}
+
+
+# EMITTING VPOPCNTD (VPOPCNTD-256-1)
+{
+ICLASS:      VPOPCNTD
+CPL:         3
+CATEGORY:    AVX512
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VPOPCNTDQ_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x55 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0  NOEVSR
+OPERANDS:    REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32
+IFORM:       VPOPCNTD_YMMu32_MASKmskw_YMMu32_AVX512
+}
+
+{
+ICLASS:      VPOPCNTD
+CPL:         3
+CATEGORY:    AVX512
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VPOPCNTDQ_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+PATTERN:    EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL()
+OPERANDS:    REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR
+IFORM:       VPOPCNTD_YMMu32_MASKmskw_MEMu32_AVX512
+}
+
+
+# EMITTING VPOPCNTQ (VPOPCNTQ-128-1)
+{
+ICLASS:      VPOPCNTQ
+CPL:         3
+CATEGORY:    AVX512
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VPOPCNTDQ_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x55 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1  NOEVSR
+OPERANDS:    REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64
+IFORM:       VPOPCNTQ_XMMu64_MASKmskw_XMMu64_AVX512
+}
+
+{
+ICLASS:      VPOPCNTQ
+CPL:         3
+CATEGORY:    AVX512
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VPOPCNTDQ_128
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+PATTERN:    EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
+OPERANDS:    REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
+IFORM:       VPOPCNTQ_XMMu64_MASKmskw_MEMu64_AVX512
+}
+
+
+# EMITTING VPOPCNTQ (VPOPCNTQ-256-1)
+{
+ICLASS:      VPOPCNTQ
+CPL:         3
+CATEGORY:    AVX512
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VPOPCNTDQ_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MASKOP_EVEX
+PATTERN:    EVV 0x55 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1  NOEVSR
+OPERANDS:    REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64
+IFORM:       VPOPCNTQ_YMMu64_MASKmskw_YMMu64_AVX512
+}
+
+{
+ICLASS:      VPOPCNTQ
+CPL:         3
+CATEGORY:    AVX512
+EXTENSION:   AVX512EVEX
+ISA_SET:     AVX512_VPOPCNTDQ_256
+EXCEPTIONS:     AVX512-E4
+REAL_OPCODE: Y
+ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
+PATTERN:    EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
+OPERANDS:    REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
+IFORM:       VPOPCNTQ_YMMu64_MASKmskw_MEMu64_AVX512
+}
+
+
diff --git a/pkg/ifuzz/gen/gen.go b/pkg/ifuzz/gen/gen.go
index 80caf1bb5..86c04617d 100644
--- a/pkg/ifuzz/gen/gen.go
+++ b/pkg/ifuzz/gen/gen.go
@@ -362,6 +362,9 @@ func parsePattern(insn *ifuzz.Insn, vals []string) error {
 			insn.No66Prefix = true
 		case v == "no66_prefix", v == "eosz32", v == "eosz64":
 			insn.No66Prefix = true
+		case v == "eosz16", v == "eosznot64", v == "REP!=3":
+			// TODO(dvyukov): this may have some effect on REP/66 prefixes,
+			// but this wasn't checked. These are just added here to unbreak build.
 		case v == "f2_refining_prefix", v == "refining_f2", v == "repne", v == "REP=2":
 			insn.Prefix = append(insn.Prefix, 0xF2)
 			insn.NoRepPrefix = true
@@ -416,6 +419,7 @@ func parsePattern(insn *ifuzz.Insn, vals []string) error {
 			v == "ESIZE_16_BITS()",
 			v == "ESIZE_32_BITS()",
 			v == "ESIZE_64_BITS()",
+			v == "ESIZE_128_BITS()",
 			v == "NELEM_GPR_WRITER_STORE()",
 			v == "NELEM_GPR_WRITER_STORE_BYTE()",
 			v == "NELEM_GPR_WRITER_STORE_WORD()",
@@ -452,6 +456,13 @@ func parsePattern(insn *ifuzz.Insn, vals []string) error {
 			v == "SAE()",
 			v == "VL512", // VL=2
 			v == "not_refining_f3",
+			v == "EVEXRR_ONE",
+			v == "CET=0",
+			v == "CET=1",
+			v == "WBNOINVD=0",
+			v == "WBNOINVD=1",
+			v == "CLDEMOTE=0",
+			v == "CLDEMOTE=1",
 			strings.HasPrefix(v, "MODEP5="):
 		default:
 			return errSkip(fmt.Sprintf("unknown pattern %v", v))
diff --git a/pkg/ifuzz/generated/insns.go b/pkg/ifuzz/generated/insns.go
index f72d1c349..f63233a9a 100644
--- a/pkg/ifuzz/generated/insns.go
+++ b/pkg/ifuzz/generated/insns.go
@@ -284,9 +284,9 @@ var insns = []*Insn{
 	{Name: "INC", Extension: "BASE", Mode: 15, Opcode: []uint8{255}, Modrm: true, Mod: -1, Rm: -1, VexP: -1},
 	{Name: "DEC_LOCK", Extension: "BASE", Mode: 15, Opcode: []uint8{255}, Prefix: []uint8{240}, Modrm: true, Mod: -3, Reg: 1, Rm: -1, VexP: -1},
 	{Name: "DEC", Extension: "BASE", Mode: 15, Opcode: []uint8{255}, Modrm: true, Mod: -1, Reg: 1, Rm: -1, VexP: -1},
+	{Name: "CALL_NEAR", Extension: "BASE", Mode: 15, Opcode: []uint8{255}, Modrm: true, Mod: -1, Reg: 2, Rm: -1, VexP: -1},
 	{Name: "CALL_NEAR", Extension: "BASE", Mode: 14, Opcode: []uint8{232}, Mod: -100, Reg: -100, Rm: -100, Imm: -1, VexP: -1},
 	{Name: "CALL_NEAR", Extension: "BASE", Mode: 1, Opcode: []uint8{232}, Mod: -100, Reg: -100, Rm: -100, Imm: 4, VexP: -1},
-	{Name: "CALL_NEAR", Extension: "BASE", Mode: 15, Opcode: []uint8{255}, Modrm: true, Mod: -1, Reg: 2, Rm: -1, VexP: -1},
 	{Name: "JMP", Extension: "BASE", Mode: 15, Opcode: []uint8{255}, Modrm: true, Mod: -1, Reg: 4, Rm: -1, VexP: -1},
 	{Name: "JMP_FAR", Extension: "BASE", Mode: 15, Opcode: []uint8{255}, Modrm: true, Mod: -3, Reg: 5, Rm: -1, VexP: -1},
 	{Name: "PUSH", Extension: "BASE", Mode: 15, Opcode: []uint8{255}, Modrm: true, Mod: -1, Reg: 6, Rm: -1, VexP: -1},
@@ -307,10 +307,10 @@ var insns = []*Insn{
 	{Name: "BTR", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 186}, Modrm: true, Mod: -1, Reg: 6, Rm: -1, Imm: 1, VexP: -1},
 	{Name: "BTC_LOCK", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 186}, Prefix: []uint8{240}, Modrm: true, Mod: -3, Reg: 7, Rm: -1, Imm: 1, VexP: -1},
 	{Name: "BTC", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 186}, Modrm: true, Mod: -1, Reg: 7, Rm: -1, Imm: 1, VexP: -1},
-	{Name: "VMCLEAR", Extension: "VTX", Mode: 15, Opcode: []uint8{15, 199}, Prefix: []uint8{102}, Modrm: true, Mod: -3, Reg: 6, Rm: -1, NoRepPrefix: true, VexP: -1},
-	{Name: "VMPTRLD", Extension: "VTX", Mode: 15, Opcode: []uint8{15, 199}, Modrm: true, Mod: -3, Reg: 6, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1},
-	{Name: "VMPTRST", Extension: "VTX", Mode: 15, Opcode: []uint8{15, 199}, Modrm: true, Mod: -3, Reg: 7, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1},
-	{Name: "VMXON", Extension: "VTX", Mode: 15, Opcode: []uint8{15, 199}, Prefix: []uint8{243}, Modrm: true, Mod: -3, Reg: 6, Rm: -1, NoRepPrefix: true, VexP: -1},
+	{Name: "VMCLEAR", Extension: "VTX", Mode: 15, Priv: true, Opcode: []uint8{15, 199}, Prefix: []uint8{102}, Modrm: true, Mod: -3, Reg: 6, Rm: -1, NoRepPrefix: true, VexP: -1},
+	{Name: "VMPTRLD", Extension: "VTX", Mode: 15, Priv: true, Opcode: []uint8{15, 199}, Modrm: true, Mod: -3, Reg: 6, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1},
+	{Name: "VMPTRST", Extension: "VTX", Mode: 15, Priv: true, Opcode: []uint8{15, 199}, Modrm: true, Mod: -3, Reg: 7, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1},
+	{Name: "VMXON", Extension: "VTX", Mode: 15, Priv: true, Opcode: []uint8{15, 199}, Prefix: []uint8{243}, Modrm: true, Mod: -3, Reg: 6, Rm: -1, NoRepPrefix: true, VexP: -1},
 	{Name: "CMPXCHG8B_LOCK", Extension: "BASE", Mode: 14, Opcode: []uint8{15, 199}, Prefix: []uint8{240}, Modrm: true, Mod: -3, Reg: 1, Rm: -1, VexP: -1},
 	{Name: "CMPXCHG8B_LOCK", Extension: "BASE", Mode: 1, Opcode: []uint8{15, 199}, Prefix: []uint8{240}, Modrm: true, Mod: -3, Reg: 1, Rm: -1, Rexw: -1, VexP: -1},
 	{Name: "CMPXCHG8B", Extension: "BASE", Mode: 14, Opcode: []uint8{15, 199}, Modrm: true, Mod: -3, Reg: 1, Rm: -1, VexP: -1},
@@ -362,16 +362,17 @@ var insns = []*Insn{
 	{Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 29}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1},
 	{Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 30}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1},
 	{Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 31}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1},
-	{Name: "VMCALL", Extension: "VTX", Mode: 15, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Rm: 1, VexP: -1},
-	{Name: "VMLAUNCH", Extension: "VTX", Mode: 15, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Rm: 2, VexP: -1},
-	{Name: "VMRESUME", Extension: "VTX", Mode: 15, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Rm: 3, VexP: -1},
-	{Name: "VMXOFF", Extension: "VTX", Mode: 15, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Rm: 4, VexP: -1},
+	{Name: "VMCALL", Extension: "VTX", Mode: 15, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Rm: 1, NoRepPrefix: true, No66Prefix: true, VexP: -1},
+	{Name: "VMLAUNCH", Extension: "VTX", Mode: 15, Priv: true, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Rm: 2, NoRepPrefix: true, No66Prefix: true, VexP: -1},
+	{Name: "VMRESUME", Extension: "VTX", Mode: 15, Priv: true, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Rm: 3, NoRepPrefix: true, No66Prefix: true, VexP: -1},
+	{Name: "VMXOFF", Extension: "VTX", Mode: 15, Priv: true, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Rm: 4, NoRepPrefix: true, No66Prefix: true, VexP: -1},
 	{Name: "SGDT", Extension: "BASE", Mode: 1, Opcode: []uint8{15, 1}, Modrm: true, Mod: -3, Rm: -1, VexP: -1},
 	{Name: "SGDT", Extension: "BASE", Mode: 14, Opcode: []uint8{15, 1}, Modrm: true, Mod: -3, Rm: -1, VexP: -1},
 	{Name: "LIDT", Extension: "BASE", Mode: 1, Priv: true, Opcode: []uint8{15, 1}, Modrm: true, Mod: -3, Reg: 3, Rm: -1, VexP: -1},
 	{Name: "LIDT", Extension: "BASE", Mode: 14, Priv: true, Opcode: []uint8{15, 1}, Modrm: true, Mod: -3, Reg: 3, Rm: -1, VexP: -1},
-	{Name: "MONITOR", Extension: "SSE3", Mode: 15, Priv: true, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Reg: 1, VexP: -1},
-	{Name: "MWAIT", Extension: "SSE3", Mode: 15, Priv: true, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Reg: 1, Rm: 1, VexP: -1},
+	{Name: "MONITOR", Extension: "MONITOR", Mode: 14, Priv: true, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Reg: 1, NoRepPrefix: true, No66Prefix: true, VexP: -1},
+	{Name: "MONITOR", Extension: "MONITOR", Mode: 1, Priv: true, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Reg: 1, NoRepPrefix: true, No66Prefix: true, VexP: -1},
+	{Name: "MWAIT", Extension: "MONITOR", Mode: 15, Priv: true, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Reg: 1, Rm: 1, NoRepPrefix: true, No66Prefix: true, VexP: -1},
 	{Name: "SIDT", Extension: "BASE", Mode: 14, Opcode: []uint8{15, 1}, Modrm: true, Mod: -3, Reg: 1, Rm: -1, VexP: -1},
 	{Name: "SIDT", Extension: "BASE", Mode: 1, Opcode: []uint8{15, 1}, Modrm: true, Mod: -3, Reg: 1, Rm: -1, VexP: -1},
 	{Name: "INVLPG", Extension: "BASE", Mode: 15, Priv: true, Opcode: []uint8{15, 1}, Modrm: true, Mod: -3, Reg: 7, Rm: -1, VexP: -1},
@@ -466,8 +467,8 @@ var insns = []*Insn{
 	{Name: "PUSHAD", Extension: "BASE", Mode: 14, Opcode: []uint8{96}, Mod: -100, Reg: -100, Rm: -100, VexP: -1},
 	{Name: "POPA", Extension: "BASE", Mode: 14, Opcode: []uint8{97}, Mod: -100, Reg: -100, Rm: -100, VexP: -1},
 	{Name: "POPAD", Extension: "BASE", Mode: 14, Opcode: []uint8{97}, Mod: -100, Reg: -100, Rm: -100, VexP: -1},
-	{Name: "BOUND", Extension: "BASE", Mode: 12, Opcode: []uint8{98}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, VexP: -1},
-	{Name: "BOUND", Extension: "BASE", Mode: 2, Opcode: []uint8{98}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, VexP: -1},
+	{Name: "BOUND", Extension: "BASE", Mode: 14, Opcode: []uint8{98}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, VexP: -1},
+	{Name: "BOUND", Extension: "BASE", Mode: 14, Opcode: []uint8{98}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, No66Prefix: true, VexP: -1},
 	{Name: "ARPL", Extension: "BASE", Mode: 14, Opcode: []uint8{99}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1},
 	{Name: "MOVSXD", Extension: "LONGMODE", Mode: 1, Opcode: []uint8{99}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1},
 	{Name: "PUSH", Extension: "BASE", Mode: 15, Opcode: []uint8{104}, Mod: -100, Reg: -100, Rm: -100, Imm: -1, VexP: -1},
@@ -536,7 +537,7 @@ var insns = []*Insn{
 	{Name: "MOV", Extension: "BASE", Mode: 15, Opcode: []uint8{139}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1},
 	{Name: "MOV", Extension: "BASE", Mode: 15, Opcode: []uint8{140}, Modrm: true, Mod: -1, Reg: -6, Rm: -1, VexP: -1},
 	{Name: "LEA", Extension: "BASE", Mode: 15, Opcode: []uint8{141}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, VexP: -1},
-	{Name: "MOV", Extension: "BASE", Mode: 15, Opcode: []uint8{142}, Modrm: true, Mod: -1, Reg: -6, Rm: -1, VexP: -1},
+	{Name: "MOV", Extension: "BASE", Mode: 15, Opcode: []uint8{142}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1},
 	{Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{144}, Mod: -100, Reg: -100, Srm: true, VexP: -1},
 	{Name: "PAUSE", Extension: "PAUSE", Mode: 15, Opcode: []uint8{144}, Prefix: []uint8{243}, Mod: -100, Reg: -100, Srm: true, NoRepPrefix: true, VexP: -1},
 	{Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{144}, Prefix: []uint8{243}, Mod: -100, Reg: -100, Srm: true, NoRepPrefix: true, VexP: -1},
@@ -654,7 +655,8 @@ var insns = []*Insn{
 	{Name: "LOOPE", Extension: "BASE", Mode: 15, Opcode: []uint8{224}, Prefix: []uint8{243}, Mod: -100, Reg: -100, Rm: -100, Imm: 1, NoRepPrefix: true, VexP: -1},
 	{Name: "LOOP", Extension: "BASE", Mode: 15, Opcode: []uint8{226}, Mod: -100, Reg: -100, Rm: -100, Imm: 1, VexP: -1},
 	{Name: "JCXZ", Extension: "BASE", Mode: 15, Opcode: []uint8{227}, Mod: -100, Reg: -100, Rm: -100, Imm: 1, VexP: -1},
-	{Name: "JECXZ", Extension: "BASE", Mode: 15, Opcode: []uint8{227}, Mod: -100, Reg: -100, Rm: -100, Imm: 1, VexP: -1},
+	{Name: "JECXZ", Extension: "BASE", Mode: 14, Opcode: []uint8{227}, Mod: -100, Reg: -100, Rm: -100, Imm: 1, VexP: -1},
+	{Name: "JECXZ", Extension: "BASE", Mode: 1, Opcode: []uint8{227}, Mod: -100, Reg: -100, Rm: -100, Imm: 1, VexP: -1},
 	{Name: "JRCXZ", Extension: "BASE", Mode: 15, Opcode: []uint8{227}, Mod: -100, Reg: -100, Rm: -100, Imm: 1, VexP: -1},
 	{Name: "IN", Extension: "BASE", Mode: 15, Opcode: []uint8{228}, Mod: -100, Reg: -100, Rm: -100, Imm: 1, VexP: -1},
 	{Name: "IN", Extension: "BASE", Mode: 15, Opcode: []uint8{229}, Mod: -100, Reg: -100, Rm: -100, Imm: 1, VexP: -1},
@@ -663,7 +665,8 @@ var insns = []*Insn{
 	{Name: "JMP", Extension: "BASE", Mode: 14, Opcode: []uint8{233}, Mod: -100, Reg: -100, Rm: -100, Imm: -1, VexP: -1},
 	{Name: "JMP", Extension: "BASE", Mode: 1, Opcode: []uint8{233}, Mod: -100, Reg: -100, Rm: -100, Imm: 4, VexP: -1},
 	{Name: "JMP_FAR", Extension: "BASE", Mode: 14, Opcode: []uint8{234}, Mod: -100, Reg: -100, Rm: -100, Imm: -1, Imm2: 2, VexP: -1},
-	{Name: "JMP", Extension: "BASE", Mode: 15, Opcode: []uint8{235}, Mod: -100, Reg: -100, Rm: -100, Imm: 1, VexP: -1},
+	{Name: "JMP", Extension: "BASE", Mode: 14, Opcode: []uint8{235}, Mod: -100, Reg: -100, Rm: -100, Imm: 1, VexP: -1},
+	{Name: "JMP", Extension: "BASE", Mode: 1, Opcode: []uint8{235}, Mod: -100, Reg: -100, Rm: -100, Imm: 1, VexP: -1},
 	{Name: "IN", Extension: "BASE", Mode: 15, Opcode: []uint8{236}, Mod: -100, Reg: -100, Rm: -100, VexP: -1},
 	{Name: "IN", Extension: "BASE", Mode: 15, Opcode: []uint8{237}, Mod: -100, Reg: -100, Rm: -100, VexP: -1},
 	{Name: "OUT", Extension: "BASE", Mode: 15, Opcode: []uint8{238}, Mod: -100, Reg: -100, Rm: -100, VexP: -1},
@@ -682,6 +685,7 @@ var insns = []*Insn{
 	{Name: "SYSCALL", Extension: "LONGMODE", Mode: 1, Opcode: []uint8{15, 5}, Mod: -100, Reg: -100, Rm: -100, VexP: -1},
 	{Name: "CLTS", Extension: "BASE", Mode: 15, Priv: true, Opcode: []uint8{15, 6}, Mod: -100, Reg: -100, Rm: -100, VexP: -1},
 	{Name: "SYSRET", Extension: "LONGMODE", Mode: 1, Priv: true, Opcode: []uint8{15, 7}, Mod: -100, Reg: -100, Rm: -100, No66Prefix: true, VexP: -1},
+	{Name: "SYSRET", Extension: "LONGMODE", Mode: 1, Priv: true, Opcode: []uint8{15, 7}, Mod: -100, Reg: -100, Rm: -100, VexP: -1},
 	{Name: "MOVUPS", Extension: "SSE", Mode: 15, Opcode: []uint8{15, 16}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1},
 	{Name: "MOVUPS", Extension: "SSE", Mode: 15, Opcode: []uint8{15, 17}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1},
 	{Name: "MOVLPS", Extension: "SSE", Mode: 15, Opcode: []uint8{15, 19}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1},
@@ -715,8 +719,10 @@ var insns = []*Insn{
 	{Name: "RDTSC", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 49}, Mod: -100, Reg: -100, Rm: -100, VexP: -1},
 	{Name: "RDMSR", Extension: "BASE", Mode: 15, Priv: true, Opcode: []uint8{15, 50}, Mod: -100, Reg: -100, Rm: -100, VexP: -1},
 	{Name: "RDPMC", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 51}, Mod: -100, Reg: -100, Rm: -100, VexP: -1},
-	{Name: "SYSENTER", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 52}, Mod: -100, Reg: -100, Rm: -100, VexP: -1},
-	{Name: "SYSEXIT", Extension: "BASE", Mode: 15, Priv: true, Opcode: []uint8{15, 53}, Mod: -100, Reg: -100, Rm: -100, VexP: -1},
+	{Name: "SYSENTER", Extension: "BASE", Mode: 14, Opcode: []uint8{15, 52}, Mod: -100, Reg: -100, Rm: -100, VexP: -1},
+	{Name: "SYSENTER", Extension: "BASE", Mode: 1, Opcode: []uint8{15, 52}, Mod: -100, Reg: -100, Rm: -100, VexP: -1},
+	{Name: "SYSEXIT", Extension: "BASE", Mode: 14, Priv: true, Opcode: []uint8{15, 53}, Mod: -100, Reg: -100, Rm: -100, VexP: -1},
+	{Name: "SYSEXIT", Extension: "BASE", Mode: 1, Priv: true, Opcode: []uint8{15, 53}, Mod: -100, Reg: -100, Rm: -100, VexP: -1},
 	{Name: "CMOVO", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 64}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1},
 	{Name: "CMOVNO", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 65}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1},
 	{Name: "CMOVB", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 66}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1},
@@ -874,6 +880,8 @@ var insns = []*Insn{
 	{Name: "LDDQU", Extension: "SSE3", Mode: 15, Opcode: []uint8{15, 240}, Prefix: []uint8{242}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1},
 	{Name: "INVD", Extension: "BASE", Mode: 15, Priv: true, Opcode: []uint8{15, 8}, Mod: -100, Reg: -100, Rm: -100, VexP: -1},
 	{Name: "WBINVD", Extension: "BASE", Mode: 15, Priv: true, Opcode: []uint8{15, 9}, Mod: -100, Reg: -100, Rm: -100, VexP: -1},
+	{Name: "UD0", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 255}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1},
+	{Name: "UD1", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 185}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1},
 	{Name: "UD2", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 11}, Mod: -100, Reg: -100, Rm: -100, VexP: -1},
 	{Name: "MOVAPS", Extension: "SSE", Mode: 15, Opcode: []uint8{15, 40}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1},
 	{Name: "MOVAPS", Extension: "SSE", Mode: 15, Opcode: []uint8{15, 41}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1},
@@ -970,10 +978,10 @@ var insns = []*Insn{
 	{Name: "PUNPCKHQDQ", Extension: "SSE2", Mode: 15, Opcode: []uint8{15, 109}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1},
 	{Name: "MOVDQU", Extension: "SSE2", Mode: 15, Opcode: []uint8{15, 111}, Prefix: []uint8{243}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1},
 	{Name: "MOVDQU", Extension: "SSE2", Mode: 15, Opcode: []uint8{15, 127}, Prefix: []uint8{243}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1},
-	{Name: "VMREAD", Extension: "VTX", Mode: 1, Opcode: []uint8{15, 120}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1},
-	{Name: "VMREAD", Extension: "VTX", Mode: 14, Opcode: []uint8{15, 120}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1},
-	{Name: "VMWRITE", Extension: "VTX", Mode: 1, Opcode: []uint8{15, 121}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1},
-	{Name: "VMWRITE", Extension: "VTX", Mode: 14, Opcode: []uint8{15, 121}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1},
+	{Name: "VMREAD", Extension: "VTX", Mode: 1, Priv: true, Opcode: []uint8{15, 120}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1},
+	{Name: "VMREAD", Extension: "VTX", Mode: 14, Priv: true, Opcode: []uint8{15, 120}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1},
+	{Name: "VMWRITE", Extension: "VTX", Mode: 1, Priv: true, Opcode: []uint8{15, 121}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1},
+	{Name: "VMWRITE", Extension: "VTX", Mode: 14, Priv: true, Opcode: []uint8{15, 121}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1},
 	{Name: "HADDPD", Extension: "SSE3", Mode: 15, Opcode: []uint8{15, 124}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1},
 	{Name: "HSUBPD", Extension: "SSE3", Mode: 15, Opcode: []uint8{15, 125}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1},
 	{Name: "MOVDQA", Extension: "SSE2", Mode: 15, Opcode: []uint8{15, 127}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1},
@@ -1152,12 +1160,9 @@ var insns = []*Insn{
 	{Name: "PMOVZXWD", Extension: "SSE4", Mode: 15, Opcode: []uint8{15, 56, 51}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1},
 	{Name: "PMOVZXWQ", Extension: "SSE4", Mode: 15, Opcode: []uint8{15, 56, 52}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1},
 	{Name: "PMOVZXDQ", Extension: "SSE4", Mode: 15, Opcode: []uint8{15, 56, 53}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1},
-	{Name: "PCMPESTRI", Extension: "SSE4", Mode: 15, Opcode: []uint8{15, 58, 97}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, NoRepPrefix: true, Rexw: -1, VexP: -1},
-	{Name: "PCMPESTRI", Extension: "SSE4", Mode: 15, Opcode: []uint8{15, 58, 97}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, NoRepPrefix: true, Rexw: 1, VexP: -1},
-	{Name: "PCMPISTRI", Extension: "SSE4", Mode: 15, Opcode: []uint8{15, 58, 99}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, NoRepPrefix: true, Rexw: -1, VexP: -1},
-	{Name: "PCMPISTRI", Extension: "SSE4", Mode: 15, Opcode: []uint8{15, 58, 99}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, NoRepPrefix: true, Rexw: 1, VexP: -1},
-	{Name: "PCMPESTRM", Extension: "SSE4", Mode: 15, Opcode: []uint8{15, 58, 96}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, NoRepPrefix: true, Rexw: -1, VexP: -1},
-	{Name: "PCMPESTRM", Extension: "SSE4", Mode: 15, Opcode: []uint8{15, 58, 96}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, NoRepPrefix: true, Rexw: 1, VexP: -1},
+	{Name: "PCMPESTRI", Extension: "SSE4", Mode: 15, Opcode: []uint8{15, 58, 97}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, NoRepPrefix: true, VexP: -1},
+	{Name: "PCMPISTRI", Extension: "SSE4", Mode: 15, Opcode: []uint8{15, 58, 99}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, NoRepPrefix: true, VexP: -1},
+	{Name: "PCMPESTRM", Extension: "SSE4", Mode: 15, Opcode: []uint8{15, 58, 96}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, NoRepPrefix: true, VexP: -1},
 	{Name: "PCMPISTRM", Extension: "SSE4", Mode: 15, Opcode: []uint8{15, 58, 98}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, NoRepPrefix: true, VexP: -1},
 	{Name: "XGETBV", Extension: "XSAVE", Mode: 15, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Reg: 2, NoRepPrefix: true, No66Prefix: true, VexP: -1},
 	{Name: "XSETBV", Extension: "XSAVE", Mode: 15, Priv: true, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Reg: 2, Rm: 1, NoRepPrefix: true, No66Prefix: true, VexP: -1},
@@ -1167,7 +1172,7 @@ var insns = []*Insn{
 	{Name: "XRSTOR64", Extension: "XSAVE", Mode: 15, Opcode: []uint8{15, 174}, Modrm: true, Mod: -3, Reg: 5, Rm: -1, NoRepPrefix: true, No66Prefix: true, Rexw: 1, VexP: -1},
 	{Name: "MOVBE", Extension: "MOVBE", Mode: 15, Opcode: []uint8{15, 56, 240}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1},
 	{Name: "MOVBE", Extension: "MOVBE", Mode: 15, Opcode: []uint8{15, 56, 241}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1},
-	{Name: "GETSEC", Extension: "SMX", Mode: 15, Opcode: []uint8{15, 55}, Mod: -100, Reg: -100, Rm: -100, VexP: -1},
+	{Name: "GETSEC", Extension: "SMX", Mode: 15, Opcode: []uint8{15, 55}, Mod: -100, Reg: -100, Rm: -100, NoRepPrefix: true, No66Prefix: true, VexP: -1},
 	{Name: "AESKEYGENASSIST", Extension: "AES", Mode: 15, Opcode: []uint8{15, 58, 223}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, NoRepPrefix: true, VexP: -1},
 	{Name: "AESENC", Extension: "AES", Mode: 15, Opcode: []uint8{15, 56, 220}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1},
 	{Name: "AESENCLAST", Extension: "AES", Mode: 15, Opcode: []uint8{15, 56, 221}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1},
@@ -1176,9 +1181,9 @@ var insns = []*Insn{
 	{Name: "AESIMC", Extension: "AES", Mode: 15, Opcode: []uint8{15, 56, 219}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1},
 	{Name: "PCLMULQDQ", Extension: "PCLMULQDQ", Mode: 15, Opcode: []uint8{15, 58, 68}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, NoRepPrefix: true, VexP: -1},
 	{Name: "INVEPT", Extension: "VTX", Mode: 1, Priv: true, Opcode: []uint8{15, 56, 128}, Prefix: []uint8{102}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1},
-	{Name: "INVEPT", Extension: "VTX", Mode: 2, Priv: true, Opcode: []uint8{15, 56, 128}, Prefix: []uint8{102}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1},
+	{Name: "INVEPT", Extension: "VTX", Mode: 14, Priv: true, Opcode: []uint8{15, 56, 128}, Prefix: []uint8{102}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1},
 	{Name: "INVVPID", Extension: "VTX", Mode: 1, Priv: true, Opcode: []uint8{15, 56, 129}, Prefix: []uint8{102}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1},
-	{Name: "INVVPID", Extension: "VTX", Mode: 2, Priv: true, Opcode: []uint8{15, 56, 129}, Prefix: []uint8{102}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1},
+	{Name: "INVVPID", Extension: "VTX", Mode: 14, Priv: true, Opcode: []uint8{15, 56, 129}, Prefix: []uint8{102}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1},
 	{Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 13}, Modrm: true, Mod: 3, Reg: -1, Rm: -1, VexP: -1},
 	{Name: "PREFETCH_EXCLUSIVE", Extension: "3DNOW", Mode: 15, Opcode: []uint8{15, 13}, Modrm: true, Mod: -3, Rm: -1, VexP: -1},
 	{Name: "PREFETCHW", Extension: "3DNOW", Mode: 15, Opcode: []uint8{15, 13}, Modrm: true, Mod: -3, Reg: 1, Rm: -1, VexP: -1},
@@ -1191,6 +1196,16 @@ var insns = []*Insn{
 	{Name: "NOP2", Extension: "BASE", Mode: 15, Opcode: []uint8{102, 144}, Mod: -100, Reg: -100, Rm: -100, VexP: -1},
 	{Name: "NOP3", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 31, 0}, Mod: -100, Reg: -100, Rm: -100, VexP: -1},
 	{Name: "NOP4", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 31, 64, 0}, Mod: -100, Reg: -100, Rm: -100, VexP: -1},
+	{Name: "XSTORE", Extension: "VIA_PADLOCK_RNG", Mode: 15, Opcode: []uint8{15, 167}, Modrm: true, Mod: 3, NoRepPrefix: true, VexP: -1},
+	{Name: "REP_XSTORE", Extension: "VIA_PADLOCK_RNG", Mode: 15, Opcode: []uint8{15, 167}, Prefix: []uint8{243}, Modrm: true, Mod: 3, NoRepPrefix: true, VexP: -1},
+	{Name: "REP_XCRYPTECB", Extension: "VIA_PADLOCK_AES", Mode: 15, Opcode: []uint8{15, 167}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 1, NoRepPrefix: true, VexP: -1},
+	{Name: "REP_XCRYPTCBC", Extension: "VIA_PADLOCK_AES", Mode: 15, Opcode: []uint8{15, 167}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 2, NoRepPrefix: true, VexP: -1},
+	{Name: "REP_XCRYPTCTR", Extension: "VIA_PADLOCK_AES", Mode: 15, Opcode: []uint8{15, 167}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 3, NoRepPrefix: true, VexP: -1},
+	{Name: "REP_XCRYPTCFB", Extension: "VIA_PADLOCK_AES", Mode: 15, Opcode: []uint8{15, 167}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 4, NoRepPrefix: true, VexP: -1},
+	{Name: "REP_XCRYPTOFB", Extension: "VIA_PADLOCK_AES", Mode: 15, Opcode: []uint8{15, 167}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 5, NoRepPrefix: true, VexP: -1},
+	{Name: "REP_XSHA1", Extension: "VIA_PADLOCK_SHA", Mode: 15, Opcode: []uint8{15, 166}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 1, NoRepPrefix: true, VexP: -1},
+	{Name: "REP_XSHA256", Extension: "VIA_PADLOCK_SHA", Mode: 15, Opcode: []uint8{15, 166}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 2, NoRepPrefix: true, VexP: -1},
+	{Name: "REP_MONTMUL", Extension: "VIA_PADLOCK_MONTMUL", Mode: 15, Opcode: []uint8{15, 166}, Prefix: []uint8{243}, Modrm: true, Mod: 3, NoRepPrefix: true, VexP: -1},
 	{Name: "FEMMS", Extension: "3DNOW", Mode: 15, Opcode: []uint8{15, 14}, Mod: -100, Reg: -100, Rm: -100, VexP: -1},
 	{Name: "PI2FW", Extension: "3DNOW", Mode: 15, Opcode: []uint8{15, 15}, Suffix: []uint8{12}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1},
 	{Name: "PI2FD", Extension: "3DNOW", Mode: 15, Opcode: []uint8{15, 15}, Suffix: []uint8{13}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1},
@@ -1201,12 +1216,12 @@ var insns = []*Insn{
 	{Name: "PFCMPGE", Extension: "3DNOW", Mode: 15, Opcode: []uint8{15, 15}, Suffix: []uint8{144}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1},
 	{Name: "PFMIN", Extension: "3DNOW", Mode: 15, Opcode: []uint8{15, 15}, Suffix: []uint8{148}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1},
 	{Name: "PFRCP", Extension: "3DNOW", Mode: 15, Opcode: []uint8{15, 15}, Suffix: []uint8{150}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1},
-	{Name: "PFSQRT", Extension: "3DNOW", Mode: 15, Opcode: []uint8{15, 15}, Suffix: []uint8{151}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1},
+	{Name: "PFRSQRT", Extension: "3DNOW", Mode: 15, Opcode: []uint8{15, 15}, Suffix: []uint8{151}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1},
 	{Name: "PFSUB", Extension: "3DNOW", Mode: 15, Opcode: []uint8{15, 15}, Suffix: []uint8{154}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1},
 	{Name: "PFADD", Extension: "3DNOW", Mode: 15, Opcode: []uint8{15, 15}, Suffix: []uint8{158}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1},
 	{Name: "PFCMPGT", Extension: "3DNOW", Mode: 15, Opcode: []uint8{15, 15}, Suffix: []uint8{160}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1},
 	{Name: "PFMAX", Extension: "3DNOW", Mode: 15, Opcode: []uint8{15, 15}, Suffix: []uint8{164}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1},
-	{Name: "PFCPIT1", Extension: "3DNOW", Mode: 15, Opcode: []uint8{15, 15}, Suffix: []uint8{166}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1},
+	{Name: "PFRCPIT1", Extension: "3DNOW", Mode: 15, Opcode: []uint8{15, 15}, Suffix: []uint8{166}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1},
 	{Name: "PFRSQIT1", Extension: "3DNOW", Mode: 15, Opcode: []uint8{15, 15}, Suffix: []uint8{167}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1},
 	{Name: "PFSUBR", Extension: "3DNOW", Mode: 15, Opcode: []uint8{15, 15}, Suffix: []uint8{170}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1},
 	{Name: "PFACC", Extension: "3DNOW", Mode: 15, Opcode: []uint8{15, 15}, Suffix: []uint8{174}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1},
@@ -1234,6 +1249,9 @@ var insns = []*Insn{
 	{Name: "MOVNTSS", Extension: "SSE4a", Mode: 15, Opcode: []uint8{15, 43}, Prefix: []uint8{243}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1},
 	{Name: "LZCNT", Extension: "AMD", Mode: 15, Opcode: []uint8{15, 189}, Prefix: []uint8{243}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1},
 	{Name: "CLZERO", Extension: "CLZERO", Mode: 15, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Reg: 7, Rm: 4, VexP: -1},
+	{Name: "MONITORX", Extension: "MONITORX", Mode: 14, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Reg: 7, Rm: 2, NoRepPrefix: true, No66Prefix: true, VexP: -1},
+	{Name: "MONITORX", Extension: "MONITORX", Mode: 1, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Reg: 7, Rm: 2, NoRepPrefix: true, No66Prefix: true, VexP: -1},
+	{Name: "MWAITX", Extension: "MONITORX", Mode: 15, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Reg: 7, Rm: 3, NoRepPrefix: true, No66Prefix: true, VexP: -1},
 	{Name: "VPMACSSWW", Extension: "XOP", Mode: 3, Opcode: []uint8{133}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: -1, Vex: 143, VexMap: 8, VexL: -1},
 	{Name: "VPMACSSWD", Extension: "XOP", Mode: 3, Opcode: []uint8{134}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: -1, Vex: 143, VexMap: 8, VexL: -1},
 	{Name: "VPMACSSDQL", Extension: "XOP", Mode: 3, Opcode: []uint8{135}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: -1, Vex: 143, VexMap: 8, VexL: -1},
@@ -1309,20 +1327,30 @@ var insns = []*Insn{
 	{Name: "VPSHAQ", Extension: "XOP", Mode: 3, Opcode: []uint8{155}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 143, VexMap: 9, VexL: -1},
 	{Name: "VPHADDDQ", Extension: "XOP", Mode: 3, Opcode: []uint8{203}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 143, VexMap: 9, VexL: -1, VexNoR: true},
 	{Name: "VPHADDUDQ", Extension: "XOP", Mode: 3, Opcode: []uint8{219}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 143, VexMap: 9, VexL: -1, VexNoR: true},
-	{Name: "BEXTR_XOP", Extension: "TBM", Mode: 7, Opcode: []uint8{16}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 4, Rexw: -1, Vex: 143, VexMap: 10, VexL: -1, VexNoR: true},
-	{Name: "BLCFILL", Extension: "TBM", Mode: 7, Opcode: []uint8{1}, Modrm: true, Mod: -1, Reg: 1, Rm: -1, Rexw: -1, Vex: 143, VexMap: 9, VexL: -1},
-	{Name: "BLSFILL", Extension: "TBM", Mode: 7, Opcode: []uint8{1}, Modrm: true, Mod: -1, Reg: 2, Rm: -1, Rexw: -1, Vex: 143, VexMap: 9, VexL: -1},
-	{Name: "BLCS", Extension: "TBM", Mode: 7, Opcode: []uint8{1}, Modrm: true, Mod: -1, Reg: 3, Rm: -1, Rexw: -1, Vex: 143, VexMap: 9, VexL: -1},
-	{Name: "TZMSK", Extension: "TBM", Mode: 7, Opcode: []uint8{1}, Modrm: true, Mod: -1, Reg: 4, Rm: -1, Rexw: -1, Vex: 143, VexMap: 9, VexL: -1},
-	{Name: "BLCIC", Extension: "TBM", Mode: 7, Opcode: []uint8{1}, Modrm: true, Mod: -1, Reg: 5, Rm: -1, Rexw: -1, Vex: 143, VexMap: 9, VexL: -1},
-	{Name: "BLSIC", Extension: "TBM", Mode: 7, Opcode: []uint8{1}, Modrm: true, Mod: -1, Reg: 6, Rm: -1, Rexw: -1, Vex: 143, VexMap: 9, VexL: -1},
-	{Name: "T1MSKC", Extension: "TBM", Mode: 7, Opcode: []uint8{1}, Modrm: true, Mod: -1, Reg: 7, Rm: -1, Rexw: -1, Vex: 143, VexMap: 9, VexL: -1},
-	{Name: "BLCMSK", Extension: "TBM", Mode: 7, Opcode: []uint8{2}, Modrm: true, Mod: -1, Reg: 1, Rm: -1, Rexw: -1, Vex: 143, VexMap: 9, VexL: -1},
-	{Name: "BLCI", Extension: "TBM", Mode: 7, Opcode: []uint8{2}, Modrm: true, Mod: -1, Reg: 6, Rm: -1, Rexw: -1, Vex: 143, VexMap: 9, VexL: -1},
-	{Name: "LLWPCB", Extension: "XOP", Mode: 3, Opcode: []uint8{18}, Modrm: true, Mod: 3, Rm: -1, Rexw: -1, Vex: 143, VexMap: 9, VexL: -1, VexNoR: true},
-	{Name: "SLWPCB", Extension: "XOP", Mode: 3, Opcode: []uint8{18}, Modrm: true, Mod: 3, Reg: 1, Rm: -1, Rexw: -1, Vex: 143, VexMap: 9, VexL: -1, VexNoR: true},
-	{Name: "LWPINS", Extension: "XOP", Mode: 3, Opcode: []uint8{18}, Modrm: true, Mod: -1, Rm: -1, Imm: 4, Rexw: -1, Vex: 143, VexMap: 10, VexL: -1},
-	{Name: "LWPVAL", Extension: "XOP", Mode: 3, Opcode: []uint8{18}, Modrm: true, Mod: -1, Reg: 1, Rm: -1, Imm: 4, Rexw: -1, Vex: 143, VexMap: 10, VexL: -1},
+	{Name: "BEXTR_XOP", Extension: "TBM", Mode: 6, Opcode: []uint8{16}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 4, Vex: 143, VexMap: 10, VexL: -1, VexNoR: true},
+	{Name: "BEXTR_XOP", Extension: "TBM", Mode: 1, Opcode: []uint8{16}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 4, Vex: 143, VexMap: 10, VexL: -1, VexNoR: true},
+	{Name: "BLCFILL", Extension: "TBM", Mode: 6, Opcode: []uint8{1}, Modrm: true, Mod: -1, Reg: 1, Rm: -1, Vex: 143, VexMap: 9, VexL: -1},
+	{Name: "BLCFILL", Extension: "TBM", Mode: 1, Opcode: []uint8{1}, Modrm: true, Mod: -1, Reg: 1, Rm: -1, Vex: 143, VexMap: 9, VexL: -1},
+	{Name: "BLSFILL", Extension: "TBM", Mode: 6, Opcode: []uint8{1}, Modrm: true, Mod: -1, Reg: 2, Rm: -1, Vex: 143, VexMap: 9, VexL: -1},
+	{Name: "BLSFILL", Extension: "TBM", Mode: 1, Opcode: []uint8{1}, Modrm: true, Mod: -1, Reg: 2, Rm: -1, Vex: 143, VexMap: 9, VexL: -1},
+	{Name: "BLCS", Extension: "TBM", Mode: 6, Opcode: []uint8{1}, Modrm: true, Mod: -1, Reg: 3, Rm: -1, Vex: 143, VexMap: 9, VexL: -1},
+	{Name: "BLCS", Extension: "TBM", Mode: 1, Opcode: []uint8{1}, Modrm: true, Mod: -1, Reg: 3, Rm: -1, Vex: 143, VexMap: 9, VexL: -1},
+	{Name: "TZMSK", Extension: "TBM", Mode: 6, Opcode: []uint8{1}, Modrm: true, Mod: -1, Reg: 4, Rm: -1, Vex: 143, VexMap: 9, VexL: -1},
+	{Name: "TZMSK", Extension: "TBM", Mode: 1, Opcode: []uint8{1}, Modrm: true, Mod: -1, Reg: 4, Rm: -1, Vex: 143, VexMap: 9, VexL: -1},
+	{Name: "BLCIC", Extension: "TBM", Mode: 6, Opcode: []uint8{1}, Modrm: true, Mod: -1, Reg: 5, Rm: -1, Vex: 143, VexMap: 9, VexL: -1},
+	{Name: "BLCIC", Extension: "TBM", Mode: 1, Opcode: []uint8{1}, Modrm: true, Mod: -1, Reg: 5, Rm: -1, Vex: 143, VexMap: 9, VexL: -1},
+	{Name: "BLSIC", Extension: "TBM", Mode: 6, Opcode: []uint8{1}, Modrm: true, Mod: -1, Reg: 6, Rm: -1, Vex: 143, VexMap: 9, VexL: -1},
+	{Name: "BLSIC", Extension: "TBM", Mode: 1, Opcode: []uint8{1}, Modrm: true, Mod: -1, Reg: 6, Rm: -1, Vex: 143, VexMap: 9, VexL: -1},
+	{Name: "T1MSKC", Extension: "TBM", Mode: 6, Opcode: []uint8{1}, Modrm: true, Mod: -1, Reg: 7, Rm: -1, Vex: 143, VexMap: 9, VexL: -1},
+	{Name: "T1MSKC", Extension: "TBM", Mode: 1, Opcode: []uint8{1}, Modrm: true, Mod: -1, Reg: 7, Rm: -1, Vex: 143, VexMap: 9, VexL: -1},
+	{Name: "BLCMSK", Extension: "TBM", Mode: 6, Opcode: []uint8{2}, Modrm: true, Mod: -1, Reg: 1, Rm: -1, Vex: 143, VexMap: 9, VexL: -1},
+	{Name: "BLCMSK", Extension: "TBM", Mode: 1, Opcode: []uint8{2}, Modrm: true, Mod: -1, Reg: 1, Rm: -1, Vex: 143, VexMap: 9, VexL: -1},
+	{Name: "BLCI", Extension: "TBM", Mode: 6, Opcode: []uint8{2}, Modrm: true, Mod: -1, Reg: 6, Rm: -1, Vex: 143, VexMap: 9, VexL: -1},
+	{Name: "BLCI", Extension: "TBM", Mode: 1, Opcode: []uint8{2}, Modrm: true, Mod: -1, Reg: 6, Rm: -1, Vex: 143, VexMap: 9, VexL: -1},
+	{Name: "LLWPCB", Extension: "XOP", Mode: 3, Opcode: []uint8{18}, Modrm: true, Mod: 3, Rm: -1, Vex: 143, VexMap: 9, VexL: -1, VexNoR: true},
+	{Name: "SLWPCB", Extension: "XOP", Mode: 3, Opcode: []uint8{18}, Modrm: true, Mod: 3, Reg: 1, Rm: -1, Vex: 143, VexMap: 9, VexL: -1, VexNoR: true},
+	{Name: "LWPINS", Extension: "XOP", Mode: 3, Opcode: []uint8{18}, Modrm: true, Mod: -1, Rm: -1, Imm: 4, Vex: 143, VexMap: 10, VexL: -1},
+	{Name: "LWPVAL", Extension: "XOP", Mode: 3, Opcode: []uint8{18}, Modrm: true, Mod: -1, Reg: 1, Rm: -1, Imm: 4, Vex: 143, VexMap: 10, VexL: -1},
 	{Name: "VFMADDSUBPS", Extension: "FMA4", Mode: 3, Opcode: []uint8{92}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: -1, Vex: 196, VexMap: 3, VexL: -1, VexP: 1},
 	{Name: "VFMADDSUBPS", Extension: "FMA4", Mode: 3, Opcode: []uint8{92}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: 1, Vex: 196, VexMap: 3, VexL: -1, VexP: 1},
 	{Name: "VFMADDSUBPS", Extension: "FMA4", Mode: 3, Opcode: []uint8{92}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: -1, Vex: 196, VexMap: 3, VexL: 1, VexP: 1},
@@ -1395,8 +1423,6 @@ var insns = []*Insn{
 	{Name: "VPERMIL2PD", Extension: "XOP", Mode: 3, Opcode: []uint8{73}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: -1, Vex: 196, VexMap: 3, VexL: 1, VexP: 1},
 	{Name: "VPERMIL2PD", Extension: "XOP", Mode: 3, Opcode: []uint8{73}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: 1, Vex: 196, VexMap: 3, VexL: -1, VexP: 1},
 	{Name: "VPERMIL2PD", Extension: "XOP", Mode: 3, Opcode: []uint8{73}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: 1, Vex: 196, VexMap: 3, VexL: 1, VexP: 1},
-	{Name: "XSAVEOPT", Extension: "XSAVEOPT", Mode: 15, Opcode: []uint8{15, 174}, Modrm: true, Mod: -3, Reg: 6, Rm: -1, NoRepPrefix: true, No66Prefix: true, Rexw: -1, VexP: -1},
-	{Name: "XSAVEOPT64", Extension: "XSAVEOPT", Mode: 15, Opcode: []uint8{15, 174}, Modrm: true, Mod: -3, Reg: 6, Rm: -1, NoRepPrefix: true, No66Prefix: true, Rexw: 1, VexP: -1},
 	{Name: "BNDMK", Extension: "MPX", Mode: 15, Opcode: []uint8{15, 27}, Prefix: []uint8{243}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1},
 	{Name: "BNDCL", Extension: "MPX", Mode: 15, Opcode: []uint8{15, 26}, Prefix: []uint8{243}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1},
 	{Name: "BNDCL", Extension: "MPX", Mode: 1, Opcode: []uint8{15, 26}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1},
@@ -1426,6 +1452,40 @@ var insns = []*Insn{
 	{Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 26}, Modrm: true, Mod: 3, Reg: -1, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1},
 	{Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 27}, Modrm: true, Mod: 3, Reg: -1, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1},
 	{Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 27}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1},
+	{Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 30}, Modrm: true, Mod: 3, Reg: -1, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1},
+	{Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 30}, Prefix: []uint8{242}, Modrm: true, Mod: 3, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1},
+	{Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 30}, Prefix: []uint8{102}, Modrm: true, Mod: 3, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1},
+	{Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 30}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Rm: -1, NoRepPrefix: true, VexP: -1},
+	{Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 30}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 2, Rm: -1, NoRepPrefix: true, VexP: -1},
+	{Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 30}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 3, Rm: -1, NoRepPrefix: true, VexP: -1},
+	{Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 30}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 4, Rm: -1, NoRepPrefix: true, VexP: -1},
+	{Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 30}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 5, Rm: -1, NoRepPrefix: true, VexP: -1},
+	{Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 30}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 6, Rm: -1, NoRepPrefix: true, VexP: -1},
+	{Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 30}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 7, NoRepPrefix: true, VexP: -1},
+	{Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 30}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 7, Rm: 1, NoRepPrefix: true, VexP: -1},
+	{Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 30}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 7, Rm: 4, NoRepPrefix: true, VexP: -1},
+	{Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 30}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 7, Rm: 5, NoRepPrefix: true, VexP: -1},
+	{Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 30}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 7, Rm: 6, NoRepPrefix: true, VexP: -1},
+	{Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 30}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 7, Rm: 7, NoRepPrefix: true, VexP: -1},
+	{Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 30}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 7, Rm: 2, NoRepPrefix: true, VexP: -1},
+	{Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 30}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 7, Rm: 3, NoRepPrefix: true, VexP: -1},
+	{Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 30}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 1, Rm: -1, NoRepPrefix: true, Rexw: -1, VexP: -1},
+	{Name: "NOP", Extension: "BASE", Mode: 1, Opcode: []uint8{15, 30}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 1, Rm: -1, NoRepPrefix: true, Rexw: 1, VexP: -1},
+	{Name: "CLRSSBSY", Extension: "CET", Mode: 15, Opcode: []uint8{15, 174}, Prefix: []uint8{243}, Modrm: true, Mod: -3, Reg: 6, Rm: -1, NoRepPrefix: true, VexP: -1},
+	{Name: "ENDBR32", Extension: "CET", Mode: 15, Opcode: []uint8{15, 30}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 7, Rm: 3, NoRepPrefix: true, VexP: -1},
+	{Name: "ENDBR64", Extension: "CET", Mode: 15, Opcode: []uint8{15, 30}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 7, Rm: 2, NoRepPrefix: true, VexP: -1},
+	{Name: "INCSSPD", Extension: "CET", Mode: 15, Opcode: []uint8{15, 174}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 5, Rm: -1, NoRepPrefix: true, Rexw: -1, VexP: -1},
+	{Name: "INCSSPQ", Extension: "CET", Mode: 1, Opcode: []uint8{15, 174}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 5, Rm: -1, NoRepPrefix: true, Rexw: 1, VexP: -1},
+	{Name: "RDSSPD", Extension: "CET", Mode: 15, Opcode: []uint8{15, 30}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 1, Rm: -1, NoRepPrefix: true, Rexw: -1, VexP: -1},
+	{Name: "RDSSPQ", Extension: "CET", Mode: 1, Opcode: []uint8{15, 30}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 1, Rm: -1, NoRepPrefix: true, Rexw: 1, VexP: -1},
+	{Name: "RSTORSSP", Extension: "CET", Mode: 15, Opcode: []uint8{15, 1}, Prefix: []uint8{243}, Modrm: true, Mod: -3, Reg: 5, Rm: -1, NoRepPrefix: true, VexP: -1},
+	{Name: "SAVEPREVSSP", Extension: "CET", Mode: 15, Opcode: []uint8{15, 1}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 5, Rm: 2, NoRepPrefix: true, VexP: -1},
+	{Name: "SETSSBSY", Extension: "CET", Mode: 15, Opcode: []uint8{15, 1}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 5, NoRepPrefix: true, VexP: -1},
+	{Name: "WRSSD", Extension: "CET", Mode: 15, Opcode: []uint8{15, 56, 246}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, NoRepPrefix: true, No66Prefix: true, Rexw: -1, VexP: -1},
+	{Name: "WRSSQ", Extension: "CET", Mode: 1, Opcode: []uint8{15, 56, 246}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, NoRepPrefix: true, No66Prefix: true, Rexw: 1, VexP: -1},
+	{Name: "WRUSSD", Extension: "CET", Mode: 15, Opcode: []uint8{15, 56, 245}, Prefix: []uint8{102}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, NoRepPrefix: true, Rexw: -1, VexP: -1},
+	{Name: "WRUSSQ", Extension: "CET", Mode: 1, Opcode: []uint8{15, 56, 245}, Prefix: []uint8{102}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, NoRepPrefix: true, Rexw: 1, VexP: -1},
+	{Name: "RDRAND", Extension: "RDRAND", Mode: 15, Opcode: []uint8{15, 199}, Modrm: true, Mod: 3, Reg: 6, Rm: -1, NoRepPrefix: true, VexP: -1},
 	{Name: "SHA1MSG1", Extension: "SHA", Mode: 15, Opcode: []uint8{15, 56, 201}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1},
 	{Name: "SHA1MSG2", Extension: "SHA", Mode: 15, Opcode: []uint8{15, 56, 202}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1},
 	{Name: "SHA1NEXTE", Extension: "SHA", Mode: 15, Opcode: []uint8{15, 56, 200}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1},
@@ -1433,17 +1493,49 @@ var insns = []*Insn{
 	{Name: "SHA256MSG1", Extension: "SHA", Mode: 15, Opcode: []uint8{15, 56, 204}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1},
 	{Name: "SHA256MSG2", Extension: "SHA", Mode: 15, Opcode: []uint8{15, 56, 205}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1},
 	{Name: "SHA256RNDS2", Extension: "SHA", Mode: 15, Opcode: []uint8{15, 56, 203}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1},
-	{Name: "RDRAND", Extension: "RDRAND", Mode: 15, Opcode: []uint8{15, 199}, Modrm: true, Mod: 3, Reg: 6, Rm: -1, NoRepPrefix: true, VexP: -1},
-	{Name: "RDFSBASE", Extension: "RDWRFSGS", Mode: 1, Opcode: []uint8{15, 174}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1},
-	{Name: "RDGSBASE", Extension: "RDWRFSGS", Mode: 1, Opcode: []uint8{15, 174}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 1, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1},
-	{Name: "WRFSBASE", Extension: "RDWRFSGS", Mode: 1, Opcode: []uint8{15, 174}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 2, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1},
-	{Name: "WRGSBASE", Extension: "RDWRFSGS", Mode: 1, Opcode: []uint8{15, 174}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 3, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1},
+	{Name: "XSAVEOPT", Extension: "XSAVEOPT", Mode: 15, Opcode: []uint8{15, 174}, Modrm: true, Mod: -3, Reg: 6, Rm: -1, NoRepPrefix: true, No66Prefix: true, Rexw: -1, VexP: -1},
+	{Name: "XSAVEOPT64", Extension: "XSAVEOPT", Mode: 15, Opcode: []uint8{15, 174}, Modrm: true, Mod: -3, Reg: 6, Rm: -1, NoRepPrefix: true, No66Prefix: true, Rexw: 1, VexP: -1},
 	{Name: "XSAVES", Extension: "XSAVES", Mode: 15, Priv: true, Opcode: []uint8{15, 199}, Modrm: true, Mod: -3, Reg: 5, Rm: -1, NoRepPrefix: true, No66Prefix: true, Rexw: -1, VexP: -1},
 	{Name: "XSAVES64", Extension: "XSAVES", Mode: 15, Priv: true, Opcode: []uint8{15, 199}, Modrm: true, Mod: -3, Reg: 5, Rm: -1, NoRepPrefix: true, No66Prefix: true, Rexw: 1, VexP: -1},
 	{Name: "XRSTORS", Extension: "XSAVES", Mode: 15, Priv: true, Opcode: []uint8{15, 199}, Modrm: true, Mod: -3, Reg: 3, Rm: -1, NoRepPrefix: true, No66Prefix: true, Rexw: -1, VexP: -1},
 	{Name: "XRSTORS64", Extension: "XSAVES", Mode: 15, Priv: true, Opcode: []uint8{15, 199}, Modrm: true, Mod: -3, Reg: 3, Rm: -1, NoRepPrefix: true, No66Prefix: true, Rexw: 1, VexP: -1},
 	{Name: "XSAVEC", Extension: "XSAVEC", Mode: 15, Opcode: []uint8{15, 199}, Modrm: true, Mod: -3, Reg: 4, Rm: -1, NoRepPrefix: true, No66Prefix: true, Rexw: -1, VexP: -1},
 	{Name: "XSAVEC64", Extension: "XSAVEC", Mode: 15, Opcode: []uint8{15, 199}, Modrm: true, Mod: -3, Reg: 4, Rm: -1, NoRepPrefix: true, No66Prefix: true, Rexw: 1, VexP: -1},
+	{Name: "CLFLUSHOPT", Extension: "CLFLUSHOPT", Mode: 15, Opcode: []uint8{15, 174}, Prefix: []uint8{102}, Modrm: true, Mod: -3, Reg: 7, Rm: -1, NoRepPrefix: true, VexP: -1},
+	{Name: "RDSEED", Extension: "RDSEED", Mode: 15, Opcode: []uint8{15, 199}, Modrm: true, Mod: 3, Reg: 7, Rm: -1, NoRepPrefix: true, VexP: -1},
+	{Name: "RDFSBASE", Extension: "RDWRFSGS", Mode: 1, Opcode: []uint8{15, 174}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Rm: -1, NoRepPrefix: true, VexP: -1},
+	{Name: "RDGSBASE", Extension: "RDWRFSGS", Mode: 1, Opcode: []uint8{15, 174}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 1, Rm: -1, NoRepPrefix: true, VexP: -1},
+	{Name: "WRFSBASE", Extension: "RDWRFSGS", Mode: 1, Opcode: []uint8{15, 174}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 2, Rm: -1, NoRepPrefix: true, VexP: -1},
+	{Name: "WRGSBASE", Extension: "RDWRFSGS", Mode: 1, Opcode: []uint8{15, 174}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 3, Rm: -1, NoRepPrefix: true, VexP: -1},
+	{Name: "CLAC", Extension: "SMAP", Mode: 15, Priv: true, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Reg: 1, Rm: 2, NoRepPrefix: true, No66Prefix: true, VexP: -1},
+	{Name: "STAC", Extension: "SMAP", Mode: 15, Priv: true, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Reg: 1, Rm: 3, NoRepPrefix: true, No66Prefix: true, VexP: -1},
+	{Name: "ENCLU", Extension: "SGX", Mode: 15, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Reg: 2, Rm: 7, NoRepPrefix: true, No66Prefix: true, VexP: -1},
+	{Name: "ENCLS", Extension: "SGX", Mode: 15, Priv: true, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Reg: 1, Rm: 7, NoRepPrefix: true, No66Prefix: true, VexP: -1},
+	{Name: "RDPID", Extension: "RDPID", Mode: 14, Opcode: []uint8{15, 199}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 7, Rm: -1, NoRepPrefix: true, VexP: -1},
+	{Name: "RDPID", Extension: "RDPID", Mode: 1, Opcode: []uint8{15, 199}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 7, Rm: -1, NoRepPrefix: true, VexP: -1},
+	{Name: "PTWRITE", Extension: "PT", Mode: 15, Opcode: []uint8{15, 174}, Prefix: []uint8{243}, Modrm: true, Mod: -1, Reg: 4, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1},
+	{Name: "MOVDIR64B", Extension: "MOVDIR", Mode: 14, Opcode: []uint8{15, 56, 248}, Prefix: []uint8{102}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1},
+	{Name: "MOVDIR64B", Extension: "MOVDIR", Mode: 1, Opcode: []uint8{15, 56, 248}, Prefix: []uint8{102}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1},
+	{Name: "MOVDIRI", Extension: "MOVDIR", Mode: 15, Opcode: []uint8{15, 56, 249}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, NoRepPrefix: true, No66Prefix: true, Rexw: -1, VexP: -1},
+	{Name: "MOVDIRI", Extension: "MOVDIR", Mode: 1, Opcode: []uint8{15, 56, 249}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, NoRepPrefix: true, No66Prefix: true, Rexw: 1, VexP: -1},
+	{Name: "TPAUSE", Extension: "WAITPKG", Mode: 15, Opcode: []uint8{15, 174}, Prefix: []uint8{102}, Modrm: true, Mod: 3, Reg: 6, Rm: -1, NoRepPrefix: true, Rexw: -1, VexP: -1},
+	{Name: "TPAUSE", Extension: "WAITPKG", Mode: 1, Opcode: []uint8{15, 174}, Prefix: []uint8{102}, Modrm: true, Mod: 3, Reg: 6, Rm: -1, NoRepPrefix: true, Rexw: 1, VexP: -1},
+	{Name: "UMONITOR", Extension: "WAITPKG", Mode: 15, Opcode: []uint8{15, 174}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 6, Rm: -1, NoRepPrefix: true, VexP: -1},
+	{Name: "UMWAIT", Extension: "WAITPKG", Mode: 15, Opcode: []uint8{15, 174}, Prefix: []uint8{242}, Modrm: true, Mod: 3, Reg: 6, Rm: -1, NoRepPrefix: true, Rexw: -1, VexP: -1},
+	{Name: "UMWAIT", Extension: "WAITPKG", Mode: 1, Opcode: []uint8{15, 174}, Prefix: []uint8{242}, Modrm: true, Mod: 3, Reg: 6, Rm: -1, NoRepPrefix: true, Rexw: 1, VexP: -1},
+	{Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 28}, Prefix: []uint8{242}, Modrm: true, Mod: -3, Rm: -1, NoRepPrefix: true, VexP: -1},
+	{Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 28}, Prefix: []uint8{243}, Modrm: true, Mod: -3, Rm: -1, NoRepPrefix: true, VexP: -1},
+	{Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 28}, Prefix: []uint8{102}, Modrm: true, Mod: -3, Rm: -1, NoRepPrefix: true, VexP: -1},
+	{Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 28}, Modrm: true, Mod: -3, Reg: 1, Rm: -1, VexP: -1},
+	{Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 28}, Modrm: true, Mod: -3, Reg: 2, Rm: -1, VexP: -1},
+	{Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 28}, Modrm: true, Mod: -3, Reg: 3, Rm: -1, VexP: -1},
+	{Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 28}, Modrm: true, Mod: -3, Reg: 4, Rm: -1, VexP: -1},
+	{Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 28}, Modrm: true, Mod: -3, Reg: 5, Rm: -1, VexP: -1},
+	{Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 28}, Modrm: true, Mod: -3, Reg: 6, Rm: -1, VexP: -1},
+	{Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 28}, Modrm: true, Mod: -3, Reg: 7, Rm: -1, VexP: -1},
+	{Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 28}, Modrm: true, Mod: -3, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1},
+	{Name: "CLDEMOTE", Extension: "CLDEMOTE", Mode: 15, Opcode: []uint8{15, 28}, Modrm: true, Mod: -3, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1},
+	{Name: "ENCLV", Extension: "SGX_ENCLV", Mode: 15, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, NoRepPrefix: true, No66Prefix: true, VexP: -1},
 	{Name: "VADDPD", Extension: "AVX", Mode: 3, Opcode: []uint8{88}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 1, VexL: -1, VexP: 1},
 	{Name: "VADDPD", Extension: "AVX", Mode: 3, Opcode: []uint8{88}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 1, VexL: 1, VexP: 1},
 	{Name: "VADDPS", Extension: "AVX", Mode: 3, Opcode: []uint8{88}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 1, VexL: -1},
@@ -1471,7 +1563,7 @@ var insns = []*Insn{
 	{Name: "VCMPPS", Extension: "AVX", Mode: 3, Opcode: []uint8{194}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Vex: 196, VexMap: 1, VexL: -1},
 	{Name: "VCMPPS", Extension: "AVX", Mode: 3, Opcode: []uint8{194}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Vex: 196, VexMap: 1, VexL: 1},
 	{Name: "VCMPSD", Extension: "AVX", Mode: 3, Opcode: []uint8{194}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Vex: 196, VexMap: 1, VexP: 3},
-	{Name: "VCMPSS", Extension: "AVX", Mode: 3, Opcode: []uint8{194}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Vex: 196, VexMap: 1, VexL: -1, VexP: 2},
+	{Name: "VCMPSS", Extension: "AVX", Mode: 3, Opcode: []uint8{194}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Vex: 196, VexMap: 1, VexP: 2},
 	{Name: "VCOMISD", Extension: "AVX", Mode: 3, Opcode: []uint8{47}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 1, VexNoR: true, VexP: 1},
 	{Name: "VCOMISS", Extension: "AVX", Mode: 3, Opcode: []uint8{47}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 1, VexNoR: true},
 	{Name: "VCVTDQ2PD", Extension: "AVX", Mode: 3, Opcode: []uint8{230}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 1, VexL: -1, VexNoR: true, VexP: 2},
@@ -1490,18 +1582,18 @@ var insns = []*Insn{
 	{Name: "VCVTTPS2DQ", Extension: "AVX", Mode: 3, Opcode: []uint8{91}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 1, VexL: 1, VexNoR: true, VexP: 2},
 	{Name: "VCVTPS2PD", Extension: "AVX", Mode: 3, Opcode: []uint8{90}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 1, VexL: -1, VexNoR: true},
 	{Name: "VCVTPS2PD", Extension: "AVX", Mode: 3, Opcode: []uint8{90}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 1, VexL: 1, VexNoR: true},
-	{Name: "VCVTSD2SI", Extension: "AVX", Mode: 2, Opcode: []uint8{45}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 1, VexL: -1, VexNoR: true, VexP: 3},
-	{Name: "VCVTSD2SI", Extension: "AVX", Mode: 1, Opcode: []uint8{45}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 1, VexL: -1, VexNoR: true, VexP: 3},
-	{Name: "VCVTSD2SI", Extension: "AVX", Mode: 1, Opcode: []uint8{45}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 1, VexL: -1, VexNoR: true, VexP: 3},
-	{Name: "VCVTTSD2SI", Extension: "AVX", Mode: 2, Opcode: []uint8{44}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 1, VexL: -1, VexNoR: true, VexP: 3},
-	{Name: "VCVTTSD2SI", Extension: "AVX", Mode: 1, Opcode: []uint8{44}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 1, VexL: -1, VexNoR: true, VexP: 3},
-	{Name: "VCVTTSD2SI", Extension: "AVX", Mode: 1, Opcode: []uint8{44}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 1, VexL: -1, VexNoR: true, VexP: 3},
-	{Name: "VCVTSS2SI", Extension: "AVX", Mode: 2, Opcode: []uint8{45}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 1, VexL: -1, VexNoR: true, VexP: 2},
-	{Name: "VCVTSS2SI", Extension: "AVX", Mode: 1, Opcode: []uint8{45}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 1, VexL: -1, VexNoR: true, VexP: 2},
-	{Name: "VCVTSS2SI", Extension: "AVX", Mode: 1, Opcode: []uint8{45}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 1, VexL: -1, VexNoR: true, VexP: 2},
-	{Name: "VCVTTSS2SI", Extension: "AVX", Mode: 2, Opcode: []uint8{44}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 1, VexL: -1, VexNoR: true, VexP: 2},
-	{Name: "VCVTTSS2SI", Extension: "AVX", Mode: 1, Opcode: []uint8{44}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 1, VexL: -1, VexNoR: true, VexP: 2},
-	{Name: "VCVTTSS2SI", Extension: "AVX", Mode: 1, Opcode: []uint8{44}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 1, VexL: -1, VexNoR: true, VexP: 2},
+	{Name: "VCVTSD2SI", Extension: "AVX", Mode: 2, Opcode: []uint8{45}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 1, VexNoR: true, VexP: 3},
+	{Name: "VCVTSD2SI", Extension: "AVX", Mode: 1, Opcode: []uint8{45}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 1, VexNoR: true, VexP: 3},
+	{Name: "VCVTSD2SI", Extension: "AVX", Mode: 1, Opcode: []uint8{45}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 1, VexNoR: true, VexP: 3},
+	{Name: "VCVTTSD2SI", Extension: "AVX", Mode: 2, Opcode: []uint8{44}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 1, VexNoR: true, VexP: 3},
+	{Name: "VCVTTSD2SI", Extension: "AVX", Mode: 1, Opcode: []uint8{44}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 1, VexNoR: true, VexP: 3},
+	{Name: "VCVTTSD2SI", Extension: "AVX", Mode: 1, Opcode: []uint8{44}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 1, VexNoR: true, VexP: 3},
+	{Name: "VCVTSS2SI", Extension: "AVX", Mode: 2, Opcode: []uint8{45}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 1, VexNoR: true, VexP: 2},
+	{Name: "VCVTSS2SI", Extension: "AVX", Mode: 1, Opcode: []uint8{45}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 1, VexNoR: true, VexP: 2},
+	{Name: "VCVTSS2SI", Extension: "AVX", Mode: 1, Opcode: []uint8{45}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 1, VexNoR: true, VexP: 2},
+	{Name: "VCVTTSS2SI", Extension: "AVX", Mode: 2, Opcode: []uint8{44}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 1, VexNoR: true, VexP: 2},
+	{Name: "VCVTTSS2SI", Extension: "AVX", Mode: 1, Opcode: []uint8{44}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 1, VexNoR: true, VexP: 2},
+	{Name: "VCVTTSS2SI", Extension: "AVX", Mode: 1, Opcode: []uint8{44}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 1, VexNoR: true, VexP: 2},
 	{Name: "VCVTSD2SS", Extension: "AVX", Mode: 3, Opcode: []uint8{90}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 1, VexP: 3},
 	{Name: "VCVTSI2SD", Extension: "AVX", Mode: 2, Opcode: []uint8{42}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 1, VexP: 3},
 	{Name: "VCVTSI2SD", Extension: "AVX", Mode: 1, Opcode: []uint8{42}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 1, VexP: 3},
@@ -1805,24 +1897,23 @@ var insns = []*Insn{
 	{Name: "VPEXTRW", Extension: "AVX", Mode: 3, Opcode: []uint8{21}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Vex: 196, VexMap: 3, VexL: -1, VexNoR: true, VexP: 1},
 	{Name: "VPEXTRW", Extension: "AVX", Mode: 3, Opcode: []uint8{197}, Modrm: true, Mod: 3, Reg: -1, Rm: -1, Imm: 1, Vex: 196, VexMap: 1, VexL: -1, VexNoR: true, VexP: 1},
 	{Name: "VPEXTRQ", Extension: "AVX", Mode: 1, Opcode: []uint8{22}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: 1, Vex: 196, VexMap: 3, VexL: -1, VexNoR: true, VexP: 1},
-	{Name: "VPEXTRD", Extension: "AVX", Mode: 3, Opcode: []uint8{22}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: -1, Vex: 196, VexMap: 3, VexL: -1, VexNoR: true, VexP: 1},
+	{Name: "VPEXTRD", Extension: "AVX", Mode: 1, Opcode: []uint8{22}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: -1, Vex: 196, VexMap: 3, VexL: -1, VexNoR: true, VexP: 1},
+	{Name: "VPEXTRD", Extension: "AVX", Mode: 2, Opcode: []uint8{22}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Vex: 196, VexMap: 3, VexL: -1, VexNoR: true, VexP: 1},
 	{Name: "VPINSRB", Extension: "AVX", Mode: 3, Opcode: []uint8{32}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Vex: 196, VexMap: 3, VexL: -1, VexP: 1},
 	{Name: "VPINSRW", Extension: "AVX", Mode: 3, Opcode: []uint8{196}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Vex: 196, VexMap: 1, VexL: -1, VexP: 1},
-	{Name: "VPINSRD", Extension: "AVX", Mode: 3, Opcode: []uint8{34}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: -1, Vex: 196, VexMap: 3, VexL: -1, VexP: 1},
+	{Name: "VPINSRD", Extension: "AVX", Mode: 1, Opcode: []uint8{34}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: -1, Vex: 196, VexMap: 3, VexL: -1, VexP: 1},
+	{Name: "VPINSRD", Extension: "AVX", Mode: 2, Opcode: []uint8{34}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Vex: 196, VexMap: 3, VexL: -1, VexP: 1},
 	{Name: "VPINSRQ", Extension: "AVX", Mode: 1, Opcode: []uint8{34}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: 1, Vex: 196, VexMap: 3, VexL: -1, VexP: 1},
 	{Name: "VPCMPESTRI", Extension: "AVX", Mode: 2, Opcode: []uint8{97}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Vex: 196, VexMap: 3, VexL: -1, VexNoR: true, VexP: 1},
-	{Name: "VPCMPESTRI", Extension: "AVX", Mode: 1, Opcode: []uint8{97}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: -1, Vex: 196, VexMap: 3, VexL: -1, VexNoR: true, VexP: 1},
-	{Name: "VPCMPESTRI", Extension: "AVX", Mode: 1, Opcode: []uint8{97}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: 1, Vex: 196, VexMap: 3, VexL: -1, VexNoR: true, VexP: 1},
+	{Name: "VPCMPESTRI", Extension: "AVX", Mode: 1, Opcode: []uint8{97}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Vex: 196, VexMap: 3, VexL: -1, VexNoR: true, VexP: 1},
 	{Name: "VPCMPISTRI", Extension: "AVX", Mode: 2, Opcode: []uint8{99}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Vex: 196, VexMap: 3, VexL: -1, VexNoR: true, VexP: 1},
-	{Name: "VPCMPISTRI", Extension: "AVX", Mode: 1, Opcode: []uint8{99}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: -1, Vex: 196, VexMap: 3, VexL: -1, VexNoR: true, VexP: 1},
-	{Name: "VPCMPISTRI", Extension: "AVX", Mode: 1, Opcode: []uint8{99}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: 1, Vex: 196, VexMap: 3, VexL: -1, VexNoR: true, VexP: 1},
+	{Name: "VPCMPISTRI", Extension: "AVX", Mode: 1, Opcode: []uint8{99}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Vex: 196, VexMap: 3, VexL: -1, VexNoR: true, VexP: 1},
 	{Name: "VPCMPESTRM", Extension: "AVX", Mode: 2, Opcode: []uint8{96}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Vex: 196, VexMap: 3, VexL: -1, VexNoR: true, VexP: 1},
-	{Name: "VPCMPESTRM", Extension: "AVX", Mode: 1, Opcode: []uint8{96}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: -1, Vex: 196, VexMap: 3, VexL: -1, VexNoR: true, VexP: 1},
-	{Name: "VPCMPESTRM", Extension: "AVX", Mode: 1, Opcode: []uint8{96}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: 1, Vex: 196, VexMap: 3, VexL: -1, VexNoR: true, VexP: 1},
+	{Name: "VPCMPESTRM", Extension: "AVX", Mode: 1, Opcode: []uint8{96}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Vex: 196, VexMap: 3, VexL: -1, VexNoR: true, VexP: 1},
 	{Name: "VPCMPISTRM", Extension: "AVX", Mode: 3, Opcode: []uint8{98}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Vex: 196, VexMap: 3, VexL: -1, VexNoR: true, VexP: 1},
 	{Name: "VMASKMOVDQU", Extension: "AVX", Mode: 3, Opcode: []uint8{247}, Modrm: true, Mod: 3, Reg: -1, Rm: -1, Vex: 196, VexMap: 1, VexL: -1, VexNoR: true, VexP: 1},
-	{Name: "VLDMXCSR", Extension: "AVX", Mode: 3, Opcode: []uint8{174}, Modrm: true, Mod: -3, Reg: 2, Rm: -1, NoRepPrefix: true, No66Prefix: true, Vex: 196, VexMap: 1, VexL: -1, VexNoR: true},
-	{Name: "VSTMXCSR", Extension: "AVX", Mode: 3, Opcode: []uint8{174}, Modrm: true, Mod: -3, Reg: 3, Rm: -1, NoRepPrefix: true, No66Prefix: true, Vex: 196, VexMap: 1, VexL: -1, VexNoR: true},
+	{Name: "VLDMXCSR", Extension: "AVX", Mode: 3, Opcode: []uint8{174}, Modrm: true, Mod: -3, Reg: 2, Rm: -1, Vex: 196, VexMap: 1, VexL: -1, VexNoR: true},
+	{Name: "VSTMXCSR", Extension: "AVX", Mode: 3, Opcode: []uint8{174}, Modrm: true, Mod: -3, Reg: 3, Rm: -1, Vex: 196, VexMap: 1, VexL: -1, VexNoR: true},
 	{Name: "VPBLENDVB", Extension: "AVX", Mode: 3, Opcode: []uint8{76}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: -1, Vex: 196, VexMap: 3, VexL: -1, VexP: 1},
 	{Name: "VBLENDVPD", Extension: "AVX", Mode: 3, Opcode: []uint8{75}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: -1, Vex: 196, VexMap: 3, VexL: -1, VexP: 1},
 	{Name: "VBLENDVPD", Extension: "AVX", Mode: 3, Opcode: []uint8{75}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: -1, Vex: 196, VexMap: 3, VexL: 1, VexP: 1},
@@ -1846,6 +1937,102 @@ var insns = []*Insn{
 	{Name: "VCVTPH2PS", Extension: "F16C", Mode: 3, Opcode: []uint8{19}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexNoR: true, VexP: 1},
 	{Name: "VCVTPS2PH", Extension: "F16C", Mode: 3, Opcode: []uint8{29}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: -1, Vex: 196, VexMap: 3, VexL: -1, VexNoR: true, VexP: 1},
 	{Name: "VCVTPS2PH", Extension: "F16C", Mode: 3, Opcode: []uint8{29}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: -1, Vex: 196, VexMap: 3, VexL: 1, VexNoR: true, VexP: 1},
+	{Name: "VFMADD132PD", Extension: "FMA", Mode: 3, Opcode: []uint8{152}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
+	{Name: "VFMADD132PD", Extension: "FMA", Mode: 3, Opcode: []uint8{152}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
+	{Name: "VFMADD132PS", Extension: "FMA", Mode: 3, Opcode: []uint8{152}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
+	{Name: "VFMADD132PS", Extension: "FMA", Mode: 3, Opcode: []uint8{152}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
+	{Name: "VFMADD132SD", Extension: "FMA", Mode: 3, Opcode: []uint8{153}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexP: 1},
+	{Name: "VFMADD132SS", Extension: "FMA", Mode: 3, Opcode: []uint8{153}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexP: 1},
+	{Name: "VFMADD213PD", Extension: "FMA", Mode: 3, Opcode: []uint8{168}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
+	{Name: "VFMADD213PD", Extension: "FMA", Mode: 3, Opcode: []uint8{168}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
+	{Name: "VFMADD213PS", Extension: "FMA", Mode: 3, Opcode: []uint8{168}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
+	{Name: "VFMADD213PS", Extension: "FMA", Mode: 3, Opcode: []uint8{168}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
+	{Name: "VFMADD213SD", Extension: "FMA", Mode: 3, Opcode: []uint8{169}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexP: 1},
+	{Name: "VFMADD213SS", Extension: "FMA", Mode: 3, Opcode: []uint8{169}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexP: 1},
+	{Name: "VFMADD231PD", Extension: "FMA", Mode: 3, Opcode: []uint8{184}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
+	{Name: "VFMADD231PD", Extension: "FMA", Mode: 3, Opcode: []uint8{184}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
+	{Name: "VFMADD231PS", Extension: "FMA", Mode: 3, Opcode: []uint8{184}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
+	{Name: "VFMADD231PS", Extension: "FMA", Mode: 3, Opcode: []uint8{184}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
+	{Name: "VFMADD231SD", Extension: "FMA", Mode: 3, Opcode: []uint8{185}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexP: 1},
+	{Name: "VFMADD231SS", Extension: "FMA", Mode: 3, Opcode: []uint8{185}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexP: 1},
+	{Name: "VFMADDSUB132PD", Extension: "FMA", Mode: 3, Opcode: []uint8{150}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
+	{Name: "VFMADDSUB132PD", Extension: "FMA", Mode: 3, Opcode: []uint8{150}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
+	{Name: "VFMADDSUB213PD", Extension: "FMA", Mode: 3, Opcode: []uint8{166}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
+	{Name: "VFMADDSUB213PD", Extension: "FMA", Mode: 3, Opcode: []uint8{166}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
+	{Name: "VFMADDSUB231PD", Extension: "FMA", Mode: 3, Opcode: []uint8{182}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
+	{Name: "VFMADDSUB231PD", Extension: "FMA", Mode: 3, Opcode: []uint8{182}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
+	{Name: "VFMADDSUB132PS", Extension: "FMA", Mode: 3, Opcode: []uint8{150}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
+	{Name: "VFMADDSUB132PS", Extension: "FMA", Mode: 3, Opcode: []uint8{150}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
+	{Name: "VFMADDSUB213PS", Extension: "FMA", Mode: 3, Opcode: []uint8{166}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
+	{Name: "VFMADDSUB213PS", Extension: "FMA", Mode: 3, Opcode: []uint8{166}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
+	{Name: "VFMADDSUB231PS", Extension: "FMA", Mode: 3, Opcode: []uint8{182}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
+	{Name: "VFMADDSUB231PS", Extension: "FMA", Mode: 3, Opcode: []uint8{182}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
+	{Name: "VFMSUBADD132PD", Extension: "FMA", Mode: 3, Opcode: []uint8{151}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
+	{Name: "VFMSUBADD132PD", Extension: "FMA", Mode: 3, Opcode: []uint8{151}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
+	{Name: "VFMSUBADD213PD", Extension: "FMA", Mode: 3, Opcode: []uint8{167}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
+	{Name: "VFMSUBADD213PD", Extension: "FMA", Mode: 3, Opcode: []uint8{167}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
+	{Name: "VFMSUBADD231PD", Extension: "FMA", Mode: 3, Opcode: []uint8{183}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
+	{Name: "VFMSUBADD231PD", Extension: "FMA", Mode: 3, Opcode: []uint8{183}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
+	{Name: "VFMSUBADD132PS", Extension: "FMA", Mode: 3, Opcode: []uint8{151}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
+	{Name: "VFMSUBADD132PS", Extension: "FMA", Mode: 3, Opcode: []uint8{151}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
+	{Name: "VFMSUBADD213PS", Extension: "FMA", Mode: 3, Opcode: []uint8{167}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
+	{Name: "VFMSUBADD213PS", Extension: "FMA", Mode: 3, Opcode: []uint8{167}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
+	{Name: "VFMSUBADD231PS", Extension: "FMA", Mode: 3, Opcode: []uint8{183}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
+	{Name: "VFMSUBADD231PS", Extension: "FMA", Mode: 3, Opcode: []uint8{183}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
+	{Name: "VFMSUB132PD", Extension: "FMA", Mode: 3, Opcode: []uint8{154}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
+	{Name: "VFMSUB132PD", Extension: "FMA", Mode: 3, Opcode: []uint8{154}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
+	{Name: "VFMSUB132PS", Extension: "FMA", Mode: 3, Opcode: []uint8{154}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
+	{Name: "VFMSUB132PS", Extension: "FMA", Mode: 3, Opcode: []uint8{154}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
+	{Name: "VFMSUB132SD", Extension: "FMA", Mode: 3, Opcode: []uint8{155}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexP: 1},
+	{Name: "VFMSUB132SS", Extension: "FMA", Mode: 3, Opcode: []uint8{155}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexP: 1},
+	{Name: "VFMSUB213PD", Extension: "FMA", Mode: 3, Opcode: []uint8{170}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
+	{Name: "VFMSUB213PD", Extension: "FMA", Mode: 3, Opcode: []uint8{170}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
+	{Name: "VFMSUB213PS", Extension: "FMA", Mode: 3, Opcode: []uint8{170}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
+	{Name: "VFMSUB213PS", Extension: "FMA", Mode: 3, Opcode: []uint8{170}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
+	{Name: "VFMSUB213SD", Extension: "FMA", Mode: 3, Opcode: []uint8{171}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexP: 1},
+	{Name: "VFMSUB213SS", Extension: "FMA", Mode: 3, Opcode: []uint8{171}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexP: 1},
+	{Name: "VFMSUB231PD", Extension: "FMA", Mode: 3, Opcode: []uint8{186}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
+	{Name: "VFMSUB231PD", Extension: "FMA", Mode: 3, Opcode: []uint8{186}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
+	{Name: "VFMSUB231PS", Extension: "FMA", Mode: 3, Opcode: []uint8{186}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
+	{Name: "VFMSUB231PS", Extension: "FMA", Mode: 3, Opcode: []uint8{186}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
+	{Name: "VFMSUB231SD", Extension: "FMA", Mode: 3, Opcode: []uint8{187}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexP: 1},
+	{Name: "VFMSUB231SS", Extension: "FMA", Mode: 3, Opcode: []uint8{187}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexP: 1},
+	{Name: "VFNMADD132PD", Extension: "FMA", Mode: 3, Opcode: []uint8{156}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
+	{Name: "VFNMADD132PD", Extension: "FMA", Mode: 3, Opcode: []uint8{156}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
+	{Name: "VFNMADD132PS", Extension: "FMA", Mode: 3, Opcode: []uint8{156}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
+	{Name: "VFNMADD132PS", Extension: "FMA", Mode: 3, Opcode: []uint8{156}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
+	{Name: "VFNMADD132SD", Extension: "FMA", Mode: 3, Opcode: []uint8{157}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexP: 1},
+	{Name: "VFNMADD132SS", Extension: "FMA", Mode: 3, Opcode: []uint8{157}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexP: 1},
+	{Name: "VFNMADD213PD", Extension: "FMA", Mode: 3, Opcode: []uint8{172}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
+	{Name: "VFNMADD213PD", Extension: "FMA", Mode: 3, Opcode: []uint8{172}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
+	{Name: "VFNMADD213PS", Extension: "FMA", Mode: 3, Opcode: []uint8{172}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
+	{Name: "VFNMADD213PS", Extension: "FMA", Mode: 3, Opcode: []uint8{172}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
+	{Name: "VFNMADD213SD", Extension: "FMA", Mode: 3, Opcode: []uint8{173}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexP: 1},
+	{Name: "VFNMADD213SS", Extension: "FMA", Mode: 3, Opcode: []uint8{173}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexP: 1},
+	{Name: "VFNMADD231PD", Extension: "FMA", Mode: 3, Opcode: []uint8{188}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
+	{Name: "VFNMADD231PD", Extension: "FMA", Mode: 3, Opcode: []uint8{188}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
+	{Name: "VFNMADD231PS", Extension: "FMA", Mode: 3, Opcode: []uint8{188}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
+	{Name: "VFNMADD231PS", Extension: "FMA", Mode: 3, Opcode: []uint8{188}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
+	{Name: "VFNMADD231SD", Extension: "FMA", Mode: 3, Opcode: []uint8{189}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexP: 1},
+	{Name: "VFNMADD231SS", Extension: "FMA", Mode: 3, Opcode: []uint8{189}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexP: 1},
+	{Name: "VFNMSUB132PD", Extension: "FMA", Mode: 3, Opcode: []uint8{158}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
+	{Name: "VFNMSUB132PD", Extension: "FMA", Mode: 3, Opcode: []uint8{158}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
+	{Name: "VFNMSUB132PS", Extension: "FMA", Mode: 3, Opcode: []uint8{158}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
+	{Name: "VFNMSUB132PS", Extension: "FMA", Mode: 3, Opcode: []uint8{158}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
+	{Name: "VFNMSUB132SD", Extension: "FMA", Mode: 3, Opcode: []uint8{159}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexP: 1},
+	{Name: "VFNMSUB132SS", Extension: "FMA", Mode: 3, Opcode: []uint8{159}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexP: 1},
+	{Name: "VFNMSUB213PD", Extension: "FMA", Mode: 3, Opcode: []uint8{174}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
+	{Name: "VFNMSUB213PD", Extension: "FMA", Mode: 3, Opcode: []uint8{174}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
+	{Name: "VFNMSUB213PS", Extension: "FMA", Mode: 3, Opcode: []uint8{174}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
+	{Name: "VFNMSUB213PS", Extension: "FMA", Mode: 3, Opcode: []uint8{174}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
+	{Name: "VFNMSUB213SD", Extension: "FMA", Mode: 3, Opcode: []uint8{175}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexP: 1},
+	{Name: "VFNMSUB213SS", Extension: "FMA", Mode: 3, Opcode: []uint8{175}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexP: 1},
+	{Name: "VFNMSUB231PD", Extension: "FMA", Mode: 3, Opcode: []uint8{190}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
+	{Name: "VFNMSUB231PD", Extension: "FMA", Mode: 3, Opcode: []uint8{190}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
+	{Name: "VFNMSUB231PS", Extension: "FMA", Mode: 3, Opcode: []uint8{190}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
+	{Name: "VFNMSUB231PS", Extension: "FMA", Mode: 3, Opcode: []uint8{190}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
+	{Name: "VFNMSUB231SD", Extension: "FMA", Mode: 3, Opcode: []uint8{191}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexP: 1},
+	{Name: "VFNMSUB231SS", Extension: "FMA", Mode: 3, Opcode: []uint8{191}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexP: 1},
 	{Name: "VGATHERDPD", Extension: "AVX2GATHER", Mode: 3, Opcode: []uint8{146}, Modrm: true, Mod: -3, Reg: -1, Rm: 4, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1, Avx2Gather: true},
 	{Name: "VGATHERDPD", Extension: "AVX2GATHER", Mode: 3, Opcode: []uint8{146}, Modrm: true, Mod: -3, Reg: -1, Rm: 4, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1, Avx2Gather: true},
 	{Name: "VGATHERDPS", Extension: "AVX2GATHER", Mode: 3, Opcode: []uint8{146}, Modrm: true, Mod: -3, Reg: -1, Rm: 4, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1, Avx2Gather: true},
@@ -1865,7 +2052,6 @@ var insns = []*Insn{
 	{Name: "VPABSB", Extension: "AVX2", Mode: 3, Opcode: []uint8{28}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 2, VexL: 1, VexNoR: true, VexP: 1},
 	{Name: "VPABSW", Extension: "AVX2", Mode: 3, Opcode: []uint8{29}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 2, VexL: 1, VexNoR: true, VexP: 1},
 	{Name: "VPABSD", Extension: "AVX2", Mode: 3, Opcode: []uint8{30}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 2, VexL: 1, VexNoR: true, VexP: 1},
-	{Name: "VPHMINPOSUW", Extension: "AVX2", Mode: 3, Opcode: []uint8{65}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 2, VexL: 1, VexNoR: true, VexP: 1},
 	{Name: "VPACKSSWB", Extension: "AVX2", Mode: 3, Opcode: []uint8{99}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 1, VexL: 1, VexP: 1},
 	{Name: "VPACKSSDW", Extension: "AVX2", Mode: 3, Opcode: []uint8{107}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 1, VexL: 1, VexP: 1},
 	{Name: "VPACKUSWB", Extension: "AVX2", Mode: 3, Opcode: []uint8{103}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 1, VexL: 1, VexP: 1},
@@ -2007,12 +2193,17 @@ var insns = []*Insn{
 	{Name: "VBROADCASTSS", Extension: "AVX2", Mode: 3, Opcode: []uint8{24}, Modrm: true, Mod: 3, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexNoR: true, VexP: 1},
 	{Name: "VBROADCASTSD", Extension: "AVX2", Mode: 3, Opcode: []uint8{25}, Modrm: true, Mod: 3, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexNoR: true, VexP: 1},
 	{Name: "VBROADCASTI128", Extension: "AVX2", Mode: 3, Opcode: []uint8{90}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexNoR: true, VexP: 1},
-	{Name: "TZCNT", Extension: "BMI1", Mode: 3, Opcode: []uint8{15, 188}, Prefix: []uint8{243}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1},
-	{Name: "BSF", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 188}, Prefix: []uint8{243}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1},
-	{Name: "INVPCID", Extension: "INVPCID", Mode: 1, Priv: true, Opcode: []uint8{15, 56, 130}, Prefix: []uint8{102}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1},
-	{Name: "INVPCID", Extension: "INVPCID", Mode: 2, Priv: true, Opcode: []uint8{15, 56, 130}, Prefix: []uint8{102}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1},
-	{Name: "LZCNT", Extension: "LZCNT", Mode: 15, Opcode: []uint8{15, 189}, Prefix: []uint8{243}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1},
-	{Name: "BSR", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 189}, Prefix: []uint8{243}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1},
+	{Name: "VPSLLVD", Extension: "AVX2", Mode: 3, Opcode: []uint8{71}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
+	{Name: "VPSLLVD", Extension: "AVX2", Mode: 3, Opcode: []uint8{71}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
+	{Name: "VPSLLVQ", Extension: "AVX2", Mode: 3, Opcode: []uint8{71}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
+	{Name: "VPSLLVQ", Extension: "AVX2", Mode: 3, Opcode: []uint8{71}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
+	{Name: "VPSRLVD", Extension: "AVX2", Mode: 3, Opcode: []uint8{69}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
+	{Name: "VPSRLVD", Extension: "AVX2", Mode: 3, Opcode: []uint8{69}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
+	{Name: "VPSRLVQ", Extension: "AVX2", Mode: 3, Opcode: []uint8{69}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
+	{Name: "VPSRLVQ", Extension: "AVX2", Mode: 3, Opcode: []uint8{69}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
+	{Name: "VPSRAVD", Extension: "AVX2", Mode: 3, Opcode: []uint8{70}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
+	{Name: "VPSRAVD", Extension: "AVX2", Mode: 3, Opcode: []uint8{70}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
+	{Name: "VMOVNTDQA", Extension: "AVX2", Mode: 3, Opcode: []uint8{42}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, Vex: 196, VexMap: 2, VexL: 1, VexNoR: true, VexP: 1},
 	{Name: "PDEP", Extension: "BMI2", Mode: 2, Opcode: []uint8{245}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 3},
 	{Name: "PDEP", Extension: "BMI2", Mode: 1, Opcode: []uint8{245}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 3},
 	{Name: "PDEP", Extension: "BMI2", Mode: 1, Opcode: []uint8{245}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 3},
@@ -2052,131 +2243,39 @@ var insns = []*Insn{
 	{Name: "RORX", Extension: "BMI2", Mode: 2, Opcode: []uint8{240}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Vex: 196, VexMap: 3, VexL: -1, VexNoR: true, VexP: 3},
 	{Name: "RORX", Extension: "BMI2", Mode: 1, Opcode: []uint8{240}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: -1, Vex: 196, VexMap: 3, VexL: -1, VexNoR: true, VexP: 3},
 	{Name: "RORX", Extension: "BMI2", Mode: 1, Opcode: []uint8{240}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: 1, Vex: 196, VexMap: 3, VexL: -1, VexNoR: true, VexP: 3},
-	{Name: "VPSLLVD", Extension: "AVX2", Mode: 3, Opcode: []uint8{71}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
-	{Name: "VPSLLVD", Extension: "AVX2", Mode: 3, Opcode: []uint8{71}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
-	{Name: "VPSLLVQ", Extension: "AVX2", Mode: 3, Opcode: []uint8{71}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
-	{Name: "VPSLLVQ", Extension: "AVX2", Mode: 3, Opcode: []uint8{71}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
-	{Name: "VPSRLVD", Extension: "AVX2", Mode: 3, Opcode: []uint8{69}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
-	{Name: "VPSRLVD", Extension: "AVX2", Mode: 3, Opcode: []uint8{69}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
-	{Name: "VPSRLVQ", Extension: "AVX2", Mode: 3, Opcode: []uint8{69}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
-	{Name: "VPSRLVQ", Extension: "AVX2", Mode: 3, Opcode: []uint8{69}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
-	{Name: "VPSRAVD", Extension: "AVX2", Mode: 3, Opcode: []uint8{70}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
-	{Name: "VPSRAVD", Extension: "AVX2", Mode: 3, Opcode: []uint8{70}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
-	{Name: "VMOVNTDQA", Extension: "AVX2", Mode: 3, Opcode: []uint8{42}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, Vex: 196, VexMap: 2, VexL: 1, VexNoR: true, VexP: 1},
+	{Name: "TZCNT", Extension: "BMI1", Mode: 3, Opcode: []uint8{15, 188}, Prefix: []uint8{243}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1},
+	{Name: "BSF", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 188}, Prefix: []uint8{243}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1},
 	{Name: "VMFUNC", Extension: "VMFUNC", Mode: 15, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Reg: 2, Rm: 4, NoRepPrefix: true, No66Prefix: true, VexP: -1},
+	{Name: "INVPCID", Extension: "INVPCID", Mode: 1, Priv: true, Opcode: []uint8{15, 56, 130}, Prefix: []uint8{102}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1},
+	{Name: "INVPCID", Extension: "INVPCID", Mode: 14, Priv: true, Opcode: []uint8{15, 56, 130}, Prefix: []uint8{102}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1},
+	{Name: "LZCNT", Extension: "LZCNT", Mode: 15, Opcode: []uint8{15, 189}, Prefix: []uint8{243}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1},
+	{Name: "BSR", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 189}, Prefix: []uint8{243}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1},
 	{Name: "XBEGIN", Extension: "RTM", Mode: 15, Opcode: []uint8{199}, Modrm: true, Mod: 3, Reg: 7, Imm: -1, VexP: -1},
 	{Name: "XEND", Extension: "RTM", Mode: 15, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Reg: 2, Rm: 5, NoRepPrefix: true, No66Prefix: true, VexP: -1},
 	{Name: "XABORT", Extension: "RTM", Mode: 15, Opcode: []uint8{198}, Modrm: true, Mod: 3, Reg: 7, Imm: 1, VexP: -1},
 	{Name: "XTEST", Extension: "RTM", Mode: 15, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Reg: 2, Rm: 6, NoRepPrefix: true, No66Prefix: true, VexP: -1},
-	{Name: "VFMADD132PD", Extension: "FMA", Mode: 3, Opcode: []uint8{152}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
-	{Name: "VFMADD132PD", Extension: "FMA", Mode: 3, Opcode: []uint8{152}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
-	{Name: "VFMADD132PS", Extension: "FMA", Mode: 3, Opcode: []uint8{152}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
-	{Name: "VFMADD132PS", Extension: "FMA", Mode: 3, Opcode: []uint8{152}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
-	{Name: "VFMADD132SD", Extension: "FMA", Mode: 3, Opcode: []uint8{153}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexP: 1},
-	{Name: "VFMADD132SS", Extension: "FMA", Mode: 3, Opcode: []uint8{153}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexP: 1},
-	{Name: "VFMADD213PD", Extension: "FMA", Mode: 3, Opcode: []uint8{168}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
-	{Name: "VFMADD213PD", Extension: "FMA", Mode: 3, Opcode: []uint8{168}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
-	{Name: "VFMADD213PS", Extension: "FMA", Mode: 3, Opcode: []uint8{168}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
-	{Name: "VFMADD213PS", Extension: "FMA", Mode: 3, Opcode: []uint8{168}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
-	{Name: "VFMADD213SD", Extension: "FMA", Mode: 3, Opcode: []uint8{169}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexP: 1},
-	{Name: "VFMADD213SS", Extension: "FMA", Mode: 3, Opcode: []uint8{169}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexP: 1},
-	{Name: "VFMADD231PD", Extension: "FMA", Mode: 3, Opcode: []uint8{184}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
-	{Name: "VFMADD231PD", Extension: "FMA", Mode: 3, Opcode: []uint8{184}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
-	{Name: "VFMADD231PS", Extension: "FMA", Mode: 3, Opcode: []uint8{184}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
-	{Name: "VFMADD231PS", Extension: "FMA", Mode: 3, Opcode: []uint8{184}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
-	{Name: "VFMADD231SD", Extension: "FMA", Mode: 3, Opcode: []uint8{185}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexP: 1},
-	{Name: "VFMADD231SS", Extension: "FMA", Mode: 3, Opcode: []uint8{185}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexP: 1},
-	{Name: "VFMADDSUB132PD", Extension: "FMA", Mode: 3, Opcode: []uint8{150}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
-	{Name: "VFMADDSUB132PD", Extension: "FMA", Mode: 3, Opcode: []uint8{150}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
-	{Name: "VFMADDSUB213PD", Extension: "FMA", Mode: 3, Opcode: []uint8{166}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
-	{Name: "VFMADDSUB213PD", Extension: "FMA", Mode: 3, Opcode: []uint8{166}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
-	{Name: "VFMADDSUB231PD", Extension: "FMA", Mode: 3, Opcode: []uint8{182}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
-	{Name: "VFMADDSUB231PD", Extension: "FMA", Mode: 3, Opcode: []uint8{182}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
-	{Name: "VFMADDSUB132PS", Extension: "FMA", Mode: 3, Opcode: []uint8{150}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
-	{Name: "VFMADDSUB132PS", Extension: "FMA", Mode: 3, Opcode: []uint8{150}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
-	{Name: "VFMADDSUB213PS", Extension: "FMA", Mode: 3, Opcode: []uint8{166}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
-	{Name: "VFMADDSUB213PS", Extension: "FMA", Mode: 3, Opcode: []uint8{166}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
-	{Name: "VFMADDSUB231PS", Extension: "FMA", Mode: 3, Opcode: []uint8{182}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
-	{Name: "VFMADDSUB231PS", Extension: "FMA", Mode: 3, Opcode: []uint8{182}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
-	{Name: "VFMSUBADD132PD", Extension: "FMA", Mode: 3, Opcode: []uint8{151}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
-	{Name: "VFMSUBADD132PD", Extension: "FMA", Mode: 3, Opcode: []uint8{151}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
-	{Name: "VFMSUBADD213PD", Extension: "FMA", Mode: 3, Opcode: []uint8{167}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
-	{Name: "VFMSUBADD213PD", Extension: "FMA", Mode: 3, Opcode: []uint8{167}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
-	{Name: "VFMSUBADD231PD", Extension: "FMA", Mode: 3, Opcode: []uint8{183}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
-	{Name: "VFMSUBADD231PD", Extension: "FMA", Mode: 3, Opcode: []uint8{183}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
-	{Name: "VFMSUBADD132PS", Extension: "FMA", Mode: 3, Opcode: []uint8{151}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
-	{Name: "VFMSUBADD132PS", Extension: "FMA", Mode: 3, Opcode: []uint8{151}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
-	{Name: "VFMSUBADD213PS", Extension: "FMA", Mode: 3, Opcode: []uint8{167}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
-	{Name: "VFMSUBADD213PS", Extension: "FMA", Mode: 3, Opcode: []uint8{167}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
-	{Name: "VFMSUBADD231PS", Extension: "FMA", Mode: 3, Opcode: []uint8{183}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
-	{Name: "VFMSUBADD231PS", Extension: "FMA", Mode: 3, Opcode: []uint8{183}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
-	{Name: "VFMSUB132PD", Extension: "FMA", Mode: 3, Opcode: []uint8{154}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
-	{Name: "VFMSUB132PD", Extension: "FMA", Mode: 3, Opcode: []uint8{154}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
-	{Name: "VFMSUB132PS", Extension: "FMA", Mode: 3, Opcode: []uint8{154}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
-	{Name: "VFMSUB132PS", Extension: "FMA", Mode: 3, Opcode: []uint8{154}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
-	{Name: "VFMSUB132SD", Extension: "FMA", Mode: 3, Opcode: []uint8{155}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexP: 1},
-	{Name: "VFMSUB132SS", Extension: "FMA", Mode: 3, Opcode: []uint8{155}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexP: 1},
-	{Name: "VFMSUB213PD", Extension: "FMA", Mode: 3, Opcode: []uint8{170}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
-	{Name: "VFMSUB213PD", Extension: "FMA", Mode: 3, Opcode: []uint8{170}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
-	{Name: "VFMSUB213PS", Extension: "FMA", Mode: 3, Opcode: []uint8{170}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
-	{Name: "VFMSUB213PS", Extension: "FMA", Mode: 3, Opcode: []uint8{170}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
-	{Name: "VFMSUB213SD", Extension: "FMA", Mode: 3, Opcode: []uint8{171}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexP: 1},
-	{Name: "VFMSUB213SS", Extension: "FMA", Mode: 3, Opcode: []uint8{171}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexP: 1},
-	{Name: "VFMSUB231PD", Extension: "FMA", Mode: 3, Opcode: []uint8{186}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
-	{Name: "VFMSUB231PD", Extension: "FMA", Mode: 3, Opcode: []uint8{186}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
-	{Name: "VFMSUB231PS", Extension: "FMA", Mode: 3, Opcode: []uint8{186}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
-	{Name: "VFMSUB231PS", Extension: "FMA", Mode: 3, Opcode: []uint8{186}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
-	{Name: "VFMSUB231SD", Extension: "FMA", Mode: 3, Opcode: []uint8{187}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexP: 1},
-	{Name: "VFMSUB231SS", Extension: "FMA", Mode: 3, Opcode: []uint8{187}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexP: 1},
-	{Name: "VFNMADD132PD", Extension: "FMA", Mode: 3, Opcode: []uint8{156}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
-	{Name: "VFNMADD132PD", Extension: "FMA", Mode: 3, Opcode: []uint8{156}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
-	{Name: "VFNMADD132PS", Extension: "FMA", Mode: 3, Opcode: []uint8{156}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
-	{Name: "VFNMADD132PS", Extension: "FMA", Mode: 3, Opcode: []uint8{156}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
-	{Name: "VFNMADD132SD", Extension: "FMA", Mode: 3, Opcode: []uint8{157}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexP: 1},
-	{Name: "VFNMADD132SS", Extension: "FMA", Mode: 3, Opcode: []uint8{157}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexP: 1},
-	{Name: "VFNMADD213PD", Extension: "FMA", Mode: 3, Opcode: []uint8{172}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
-	{Name: "VFNMADD213PD", Extension: "FMA", Mode: 3, Opcode: []uint8{172}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
-	{Name: "VFNMADD213PS", Extension: "FMA", Mode: 3, Opcode: []uint8{172}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
-	{Name: "VFNMADD213PS", Extension: "FMA", Mode: 3, Opcode: []uint8{172}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
-	{Name: "VFNMADD213SD", Extension: "FMA", Mode: 3, Opcode: []uint8{173}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexP: 1},
-	{Name: "VFNMADD213SS", Extension: "FMA", Mode: 3, Opcode: []uint8{173}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexP: 1},
-	{Name: "VFNMADD231PD", Extension: "FMA", Mode: 3, Opcode: []uint8{188}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
-	{Name: "VFNMADD231PD", Extension: "FMA", Mode: 3, Opcode: []uint8{188}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
-	{Name: "VFNMADD231PS", Extension: "FMA", Mode: 3, Opcode: []uint8{188}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
-	{Name: "VFNMADD231PS", Extension: "FMA", Mode: 3, Opcode: []uint8{188}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
-	{Name: "VFNMADD231SD", Extension: "FMA", Mode: 3, Opcode: []uint8{189}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexP: 1},
-	{Name: "VFNMADD231SS", Extension: "FMA", Mode: 3, Opcode: []uint8{189}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexP: 1},
-	{Name: "VFNMSUB132PD", Extension: "FMA", Mode: 3, Opcode: []uint8{158}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
-	{Name: "VFNMSUB132PD", Extension: "FMA", Mode: 3, Opcode: []uint8{158}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
-	{Name: "VFNMSUB132PS", Extension: "FMA", Mode: 3, Opcode: []uint8{158}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
-	{Name: "VFNMSUB132PS", Extension: "FMA", Mode: 3, Opcode: []uint8{158}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
-	{Name: "VFNMSUB132SD", Extension: "FMA", Mode: 3, Opcode: []uint8{159}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexP: 1},
-	{Name: "VFNMSUB132SS", Extension: "FMA", Mode: 3, Opcode: []uint8{159}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexP: 1},
-	{Name: "VFNMSUB213PD", Extension: "FMA", Mode: 3, Opcode: []uint8{174}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
-	{Name: "VFNMSUB213PD", Extension: "FMA", Mode: 3, Opcode: []uint8{174}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
-	{Name: "VFNMSUB213PS", Extension: "FMA", Mode: 3, Opcode: []uint8{174}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
-	{Name: "VFNMSUB213PS", Extension: "FMA", Mode: 3, Opcode: []uint8{174}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
-	{Name: "VFNMSUB213SD", Extension: "FMA", Mode: 3, Opcode: []uint8{175}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexP: 1},
-	{Name: "VFNMSUB213SS", Extension: "FMA", Mode: 3, Opcode: []uint8{175}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexP: 1},
-	{Name: "VFNMSUB231PD", Extension: "FMA", Mode: 3, Opcode: []uint8{190}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
-	{Name: "VFNMSUB231PD", Extension: "FMA", Mode: 3, Opcode: []uint8{190}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
-	{Name: "VFNMSUB231PS", Extension: "FMA", Mode: 3, Opcode: []uint8{190}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
-	{Name: "VFNMSUB231PS", Extension: "FMA", Mode: 3, Opcode: []uint8{190}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
-	{Name: "VFNMSUB231SD", Extension: "FMA", Mode: 3, Opcode: []uint8{191}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexP: 1},
-	{Name: "VFNMSUB231SS", Extension: "FMA", Mode: 3, Opcode: []uint8{191}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexP: 1},
-	{Name: "ADCX", Extension: "BDW", Mode: 15, Opcode: []uint8{15, 56, 246}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, Rexw: -1, VexP: -1},
-	{Name: "ADCX", Extension: "BDW", Mode: 15, Opcode: []uint8{15, 56, 246}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, Rexw: 1, VexP: -1},
-	{Name: "ADOX", Extension: "BDW", Mode: 15, Opcode: []uint8{15, 56, 246}, Prefix: []uint8{243}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, Rexw: -1, VexP: -1},
-	{Name: "ADOX", Extension: "BDW", Mode: 15, Opcode: []uint8{15, 56, 246}, Prefix: []uint8{243}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, Rexw: 1, VexP: -1},
-	{Name: "RDSEED", Extension: "RDSEED", Mode: 15, Opcode: []uint8{15, 199}, Modrm: true, Mod: 3, Reg: 7, Rm: -1, NoRepPrefix: true, VexP: -1},
-	{Name: "CLAC", Extension: "SMAP", Mode: 15, Priv: true, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Reg: 1, Rm: 2, NoRepPrefix: true, No66Prefix: true, VexP: -1},
-	{Name: "STAC", Extension: "SMAP", Mode: 15, Priv: true, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Reg: 1, Rm: 3, NoRepPrefix: true, No66Prefix: true, VexP: -1},
-	{Name: "ENCLU", Extension: "SGX", Mode: 15, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Reg: 2, Rm: 7, NoRepPrefix: true, No66Prefix: true, VexP: -1},
-	{Name: "ENCLS", Extension: "SGX", Mode: 15, Priv: true, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Reg: 1, Rm: 7, NoRepPrefix: true, No66Prefix: true, VexP: -1},
-	{Name: "RDPKRU", Extension: "PKU", Mode: 15, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Reg: 5, Rm: 6, VexP: -1},
-	{Name: "WRPKRU", Extension: "PKU", Mode: 15, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Reg: 5, Rm: 7, VexP: -1},
+	{Name: "ADCX", Extension: "ADOX_ADCX", Mode: 15, Opcode: []uint8{15, 56, 246}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, Rexw: -1, VexP: -1},
+	{Name: "ADCX", Extension: "ADOX_ADCX", Mode: 15, Opcode: []uint8{15, 56, 246}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, Rexw: 1, VexP: -1},
+	{Name: "ADOX", Extension: "ADOX_ADCX", Mode: 15, Opcode: []uint8{15, 56, 246}, Prefix: []uint8{243}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, Rexw: -1, VexP: -1},
+	{Name: "ADOX", Extension: "ADOX_ADCX", Mode: 15, Opcode: []uint8{15, 56, 246}, Prefix: []uint8{243}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, Rexw: 1, VexP: -1},
+	{Name: "RDPKRU", Extension: "PKU", Mode: 15, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Reg: 5, Rm: 6, NoRepPrefix: true, No66Prefix: true, VexP: -1},
+	{Name: "WRPKRU", Extension: "PKU", Mode: 15, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Reg: 5, Rm: 7, NoRepPrefix: true, No66Prefix: true, VexP: -1},
 	{Name: "CLWB", Extension: "CLWB", Mode: 15, Opcode: []uint8{15, 174}, Prefix: []uint8{102}, Modrm: true, Mod: -3, Reg: 6, Rm: -1, NoRepPrefix: true, VexP: -1},
-	{Name: "CLFLUSHOPT", Extension: "CLFLUSHOPT", Mode: 15, Opcode: []uint8{15, 174}, Prefix: []uint8{102}, Modrm: true, Mod: -3, Reg: 7, Rm: -1, NoRepPrefix: true, VexP: -1},
-	{Name: "PTWRITE", Extension: "PT", Mode: 15, Opcode: []uint8{15, 174}, Prefix: []uint8{243}, Modrm: true, Mod: -1, Reg: 4, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1},
 	{Name: "PREFETCHWT1", Extension: "PREFETCHWT1", Mode: 15, Opcode: []uint8{15, 13}, Modrm: true, Mod: -3, Reg: 2, Rm: -1, VexP: -1},
+	{Name: "WBNOINVD", Extension: "WBNOINVD", Mode: 15, Priv: true, Opcode: []uint8{15, 9}, Prefix: []uint8{243}, Mod: -100, Reg: -100, Rm: -100, NoRepPrefix: true, VexP: -1},
+	{Name: "PCONFIG", Extension: "PCONFIG", Mode: 15, Priv: true, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Rm: 5, NoRepPrefix: true, No66Prefix: true, VexP: -1},
+	{Name: "GF2P8AFFINEINVQB", Extension: "GFNI", Mode: 15, Opcode: []uint8{15, 58, 207}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, NoRepPrefix: true, VexP: -1},
+	{Name: "GF2P8AFFINEQB", Extension: "GFNI", Mode: 15, Opcode: []uint8{15, 58, 206}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, NoRepPrefix: true, VexP: -1},
+	{Name: "GF2P8MULB", Extension: "GFNI", Mode: 15, Opcode: []uint8{15, 56, 207}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1},
+	{Name: "VGF2P8AFFINEINVQB", Extension: "GFNI", Mode: 15, Opcode: []uint8{207}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: 1, Vex: 196, VexMap: 3, VexL: -1, VexP: 1},
+	{Name: "VGF2P8AFFINEINVQB", Extension: "GFNI", Mode: 15, Opcode: []uint8{207}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: 1, Vex: 196, VexMap: 3, VexL: 1, VexP: 1},
+	{Name: "VGF2P8AFFINEQB", Extension: "GFNI", Mode: 15, Opcode: []uint8{206}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: 1, Vex: 196, VexMap: 3, VexL: -1, VexP: 1},
+	{Name: "VGF2P8AFFINEQB", Extension: "GFNI", Mode: 15, Opcode: []uint8{206}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: 1, Vex: 196, VexMap: 3, VexL: 1, VexP: 1},
+	{Name: "VGF2P8MULB", Extension: "GFNI", Mode: 15, Opcode: []uint8{207}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1},
+	{Name: "VGF2P8MULB", Extension: "GFNI", Mode: 15, Opcode: []uint8{207}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
+	{Name: "VAESDEC", Extension: "VAES", Mode: 15, Opcode: []uint8{222}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
+	{Name: "VAESDECLAST", Extension: "VAES", Mode: 15, Opcode: []uint8{223}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
+	{Name: "VAESENC", Extension: "VAES", Mode: 15, Opcode: []uint8{220}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
+	{Name: "VAESENCLAST", Extension: "VAES", Mode: 15, Opcode: []uint8{221}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1},
+	{Name: "VPCLMULQDQ", Extension: "VPCLMULQDQ", Mode: 15, Opcode: []uint8{68}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Vex: 196, VexMap: 3, VexL: 1, VexP: 1},
 }
author	Dmitry Vyukov <dvyukov@google.com>	2019-06-23 14:58:12 +0200
committer	Dmitry Vyukov <dvyukov@google.com>	2019-06-23 15:10:27 +0200
commit	472f0082fd8a2f82b85ab0682086e10b71529a51 (patch)
tree	0b74081142e7464da99263f6e1d0076a0e965a29 /pkg
parent	da9246f6d754caed30a65276b41e32a05f0c8fa2 (diff)