From 472f0082fd8a2f82b85ab0682086e10b71529a51 Mon Sep 17 00:00:00 2001 From: Dmitry Vyukov Date: Sun, 23 Jun 2019 14:58:12 +0200 Subject: pkg/ifuzz: update to latest intelxed Update all-enc-instructions.txt to b7231de4c808db821d64f4018d15412640c34113 and regenerate instruction info. --- pkg/ifuzz/gen/all-enc-instructions.txt | 57338 +++++++++++++++++-------------- pkg/ifuzz/gen/gen.go | 11 + pkg/ifuzz/generated/insns.go | 507 +- 3 files changed, 31625 insertions(+), 26231 deletions(-) (limited to 'pkg') diff --git a/pkg/ifuzz/gen/all-enc-instructions.txt b/pkg/ifuzz/gen/all-enc-instructions.txt index 9afe5353b..717ac8ec2 100644 --- a/pkg/ifuzz/gen/all-enc-instructions.txt +++ b/pkg/ifuzz/gen/all-enc-instructions.txt @@ -4,7 +4,7 @@ #BEGIN_LEGAL # -#Copyright (c) 2016 Intel Corporation +#Copyright (c) 2018 Intel Corporation # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -730,7 +730,7 @@ ATTRIBUTES: NOTSX CPL : 3 CATEGORY : FCMOV EXTENSION : X87 -ISA_SET : PPRO +ISA_SET : FCMOV FLAGS : MUST [ cf-tst fc0-u fc1-mod fc2-u fc3-u ] PATTERN : 0xDA MOD[0b11] MOD=3 REG[0b000] RM[nnn] OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP @@ -741,7 +741,7 @@ ATTRIBUTES: NOTSX CPL : 3 CATEGORY : FCMOV EXTENSION : X87 -ISA_SET : PPRO +ISA_SET : FCMOV FLAGS : MUST [ zf-tst fc0-u fc1-mod fc2-u fc3-u ] PATTERN : 0xDA MOD[0b11] MOD=3 REG[0b001] RM[nnn] OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP @@ -752,7 +752,7 @@ ATTRIBUTES: NOTSX CPL : 3 CATEGORY : FCMOV EXTENSION : X87 -ISA_SET : PPRO +ISA_SET : FCMOV FLAGS : MUST [ cf-tst zf-tst fc0-u fc1-mod fc2-u fc3-u ] PATTERN : 0xDA MOD[0b11] MOD=3 REG[0b010] RM[nnn] OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP @@ -763,7 +763,7 @@ ATTRIBUTES: NOTSX CPL : 3 CATEGORY : FCMOV EXTENSION : X87 -ISA_SET : PPRO +ISA_SET : FCMOV FLAGS : MUST [ pf-tst fc0-u fc1-mod fc2-u fc3-u ] PATTERN : 0xDA MOD[0b11] MOD=3 REG[0b011] RM[nnn] OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP @@ -834,7 +834,7 @@ ATTRIBUTES: NOTSX CPL : 3 CATEGORY : FCMOV EXTENSION : X87 -ISA_SET : PPRO +ISA_SET : FCMOV FLAGS : MUST [ cf-tst fc0-u fc1-mod fc2-u fc3-u ] PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b000] RM[nnn] OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP @@ -845,7 +845,7 @@ ATTRIBUTES: NOTSX CPL : 3 CATEGORY : FCMOV EXTENSION : X87 -ISA_SET : PPRO +ISA_SET : FCMOV FLAGS : MUST [ zf-tst fc0-u fc1-mod fc2-u fc3-u ] PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b001] RM[nnn] OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP @@ -856,7 +856,7 @@ ATTRIBUTES: NOTSX CPL : 3 CATEGORY : FCMOV EXTENSION : X87 -ISA_SET : PPRO +ISA_SET : FCMOV FLAGS : MUST [ cf-tst zf-tst fc0-u fc1-mod fc2-u fc3-u ] PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b010] RM[nnn] OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP @@ -867,7 +867,7 @@ ATTRIBUTES: NOTSX CPL : 3 CATEGORY : FCMOV EXTENSION : X87 -ISA_SET : PPRO +ISA_SET : FCMOV FLAGS : MUST [ pf-tst fc0-u fc1-mod fc2-u fc3-u ] PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b011] RM[nnn] OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP @@ -1091,6 +1091,7 @@ ICLASS : FISTTP CPL : 3 CATEGORY : X87_ALU EXTENSION : SSE3 +ISA_SET : SSE3X87 ATTRIBUTES : NOTSX FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() @@ -1361,6 +1362,7 @@ ATTRIBUTES: NOTSX CPL : 3 CATEGORY : X87_ALU EXTENSION : SSE3 +ISA_SET : SSE3X87 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] PATTERN : 0xDF MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() OPERANDS : MEM0:w:mem16int REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP @@ -3795,6 +3797,7 @@ PATTERN : 0xFF MOD[0b11] MOD=3 REG[0b001] RM[nnn] OPERANDS : REG0=GPRv_B():rw IFORM : DEC_GPRv_FFr1 } + { ICLASS : CALL_NEAR DISASM_INTEL: call @@ -3803,25 +3806,38 @@ CPL : 3 CATEGORY : CALL EXTENSION : BASE ISA_SET : I86 -ATTRIBUTES: MPX_PREFIX_ABLE - -PATTERN : 0xE8 not64 BRDISPz() -OPERANDS : RELBR:r:z REG0=XED_REG_STACKPUSH:w:spw:SUPP REG1=rIP():rw:SUPP -PATTERN : 0xE8 mode64 BRDISP32() DF64() FORCE64() -OPERANDS : RELBR:r:d REG0=XED_REG_STACKPUSH:w:spw:SUPP REG1=rIP():rw:SUPP +ATTRIBUTES: MPX_PREFIX_ABLE INDIRECT_BRANCH PATTERN : 0xFF MOD[mm] MOD!=3 REG[0b010] RM[nnn] DF64() IMMUNE66_LOOP64() MODRM() OPERANDS : MEM0:r:v REG0=XED_REG_STACKPUSH:w:spw:SUPP REG1=rIP():rw:SUPP PATTERN : 0xFF MOD[0b11] MOD=3 REG[0b010] RM[nnn] DF64() IMMUNE66_LOOP64() OPERANDS : REG0=GPRv_B():r REG1=XED_REG_STACKPUSH:w:spw:SUPP REG2=rIP():rw:SUPP } +{ +ICLASS : CALL_NEAR +DISASM_INTEL: call +DISASM_ATTSV: call +CPL : 3 +CATEGORY : CALL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: MPX_PREFIX_ABLE + +PATTERN : 0xE8 not64 BRDISPz() +OPERANDS : RELBR:r:z REG0=XED_REG_STACKPUSH:w:spw:SUPP REG1=XED_REG_EIP:rw:SUPP +PATTERN : 0xE8 mode64 BRDISP32() DF64() FORCE64() +OPERANDS : RELBR:r:d REG0=XED_REG_STACKPUSH:w:spw:SUPP REG1=XED_REG_RIP:rw:SUPP +} + + + { ICLASS : JMP CPL : 3 CATEGORY : UNCOND_BR EXTENSION : BASE ISA_SET : I86 -ATTRIBUTES: MPX_PREFIX_ABLE +ATTRIBUTES: MPX_PREFIX_ABLE INDIRECT_BRANCH PATTERN : 0xFF MOD[mm] MOD!=3 REG[0b100] RM[nnn] DF64() IMMUNE66_LOOP64() MODRM() OPERANDS : MEM0:r:v REG0=rIP():w:SUPP PATTERN : 0xFF MOD[0b11] MOD=3 REG[0b100] RM[nnn] DF64() IMMUNE66_LOOP64() @@ -3832,7 +3848,7 @@ ICLASS : JMP_FAR DISASM_INTEL: jmp far DISASM_ATTSV: ljmp CPL : 3 -ATTRIBUTES : FAR_XFER NOTSX +ATTRIBUTES : FAR_XFER NOTSX INDIRECT_BRANCH CATEGORY : UNCOND_BR EXTENSION : BASE ISA_SET : I86 @@ -3959,6 +3975,8 @@ CATEGORY : SYSTEM EXTENSION : BASE ISA_SET : I286REAL ATTRIBUTES: NOTSX +COMMENT : 66 is OSZ; F2/F3 ignored + PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM() OPERANDS : MEM0:r:s64 REG0=XED_REG_GDTR:w:SUPP PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM() @@ -3970,6 +3988,8 @@ CPL : 3 CATEGORY : SYSTEM EXTENSION : BASE ISA_SET : I286REAL +COMMENT : 66 is OSZ; F2/F3 ignored + PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() OPERANDS : MEM0:w:w REG0=XED_REG_CR0:r:SUPP } @@ -3979,6 +3999,8 @@ CPL : 3 CATEGORY : SYSTEM EXTENSION : BASE ISA_SET : I286REAL +COMMENT : 66 is OSZ; F2/F3 ignored + PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn] OPERANDS : REG0=GPRv_B():w REG1=XED_REG_CR0:r:SUPP } @@ -4120,28 +4142,33 @@ OPERANDS : REG0=GPRv_B():rw IMM0:r:b { ICLASS : VMCLEAR -CPL : 3 +CPL : 0 CATEGORY : VTX EXTENSION : VTX ATTRIBUTES: NOTSX +FLAGS : MUST [ cf-mod zf-mod sf-0 of-0 af-0 pf-0 ] PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] osz_refining_prefix REFINING66() MODRM() OPERANDS : MEM0:r:q } { ICLASS : VMPTRLD -CPL : 3 +CPL : 0 CATEGORY : VTX EXTENSION : VTX ATTRIBUTES: NOTSX +FLAGS : MUST [ cf-mod zf-mod sf-0 of-0 af-0 pf-0 ] + PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] no_refining_prefix MODRM() OPERANDS : MEM0:r:q } { ICLASS : VMPTRST -CPL : 3 +CPL : 0 CATEGORY : VTX EXTENSION : VTX ATTRIBUTES: NOTSX +FLAGS : MUST [ cf-mod zf-mod sf-0 of-0 af-0 pf-0 ] + PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b111] RM[nnn] no_refining_prefix MODRM() OPERANDS : MEM0:w:q } @@ -4149,10 +4176,12 @@ OPERANDS : MEM0:w:q { ICLASS : VMXON -CPL : 3 +CPL : 0 CATEGORY : VTX EXTENSION : VTX ATTRIBUTES: PROTECTED_MODE NOTSX +FLAGS : MUST [ cf-mod zf-mod sf-0 of-0 af-0 pf-0 ] + PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] f3_refining_prefix IGNORE66() MODRM() OPERANDS : MEM0:r:q } @@ -4496,7 +4525,7 @@ OPERANDS : MEM0:w:d REG0=XED_REG_MXCSR:r:SUPP ICLASS : PREFETCHNTA CPL : 3 CATEGORY : PREFETCH -ATTRIBUTES: PREFETCH +ATTRIBUTES: PREFETCH NONTEMPORAL EXTENSION : SSE ISA_SET : SSE_PREFETCH PATTERN : 0x0F 0x18 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() @@ -4711,34 +4740,42 @@ CPL : 3 CATEGORY : VTX EXTENSION : VTX ATTRIBUTES: NOTSX -PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b001] +COMMENT : on some execution paths loads all flags from VMCS. Always writes CF/PF/AF/ZF/SF/OF. +FLAGS : MAY [ id-mod vip-mod vif-mod ac-mod vm-tst rf-mod nt-mod iopl-tst iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b001] no_refining_prefix OPERANDS : } { ICLASS : VMLAUNCH -CPL : 3 +CPL : 0 CATEGORY : VTX EXTENSION : VTX ATTRIBUTES: NOTSX -PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b010] +COMMENT : on some execution paths loads all flags from VMCS. Always writes CF/PF/AF/ZF/SF/OF. +FLAGS : MAY [ id-mod vip-mod vif-mod ac-mod vm-tst rf-mod nt-mod iopl-tst iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b010] no_refining_prefix OPERANDS : } { ICLASS : VMRESUME -CPL : 3 +CPL : 0 CATEGORY : VTX EXTENSION : VTX ATTRIBUTES: NOTSX -PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b011] +COMMENT : on some execution paths loads all flags from VMCS. Always writes CF/PF/AF/ZF/SF/OF. +FLAGS : MAY [ id-mod vip-mod vif-mod ac-mod vm-tst rf-mod nt-mod iopl-tst iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b011] no_refining_prefix OPERANDS : } { ICLASS : VMXOFF -CPL : 3 +CPL : 0 CATEGORY : VTX EXTENSION : VTX ATTRIBUTES: NOTSX -PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b100] +FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-mod pf-mod ] + +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b100] no_refining_prefix OPERANDS : } { @@ -4760,6 +4797,7 @@ CATEGORY : SYSTEM EXTENSION : BASE ISA_SET : I286REAL ATTRIBUTES: RING0 NOTSX +COMMENT : 66 is OSZ; F2/F3 ignored PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM() OPERANDS : MEM0:r:s64 REG0=XED_REG_IDTR:w:SUPP PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM() @@ -4769,19 +4807,31 @@ OPERANDS : MEM0:r:s REG0=XED_REG_IDTR:w:SUPP ICLASS : MONITOR CPL : 0 CATEGORY : MISC -EXTENSION : SSE3 +EXTENSION : MONITOR +ISA_SET : MONITOR ATTRIBUTES: RING0 NOTSX -PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b000] + +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b000] no_refining_prefix not64 eamode32 OPERANDS : REG0=XED_REG_EAX:r:SUPP REG1=XED_REG_ECX:r:SUPP REG2=XED_REG_EDX:r:SUPP + +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b000] no_refining_prefix not64 eamode16 +OPERANDS : REG0=XED_REG_AX:r:SUPP REG1=XED_REG_ECX:r:SUPP REG2=XED_REG_EDX:r:SUPP + +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b000] no_refining_prefix mode64 eamode64 +OPERANDS : REG0=XED_REG_RAX:r:SUPP REG1=XED_REG_ECX:r:SUPP REG2=XED_REG_EDX:r:SUPP + +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b000] no_refining_prefix mode64 eamode32 +OPERANDS : REG0=XED_REG_RAX:r:SUPP REG1=XED_REG_ECX:r:SUPP REG2=XED_REG_EDX:r:SUPP } { ICLASS : MWAIT CPL : 0 CATEGORY : MISC -EXTENSION : SSE3 +EXTENSION : MONITOR +ISA_SET : MONITOR ATTRIBUTES: RING0 NOTSX -PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b001] -OPERANDS : REG0=XED_REG_EAX:rw:SUPP REG1=XED_REG_ECX:r:SUPP +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b001] no_refining_prefix +OPERANDS : REG0=XED_REG_EAX:r:SUPP REG1=XED_REG_ECX:r:SUPP } { ICLASS : SIDT @@ -4790,6 +4840,7 @@ CATEGORY : SYSTEM EXTENSION : BASE ISA_SET : I286REAL ATTRIBUTES: NOTSX +COMMENT : 66 is OSZ; F2/F3 ignored PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM() OPERANDS : MEM0:w:s REG0=XED_REG_IDTR:r:SUPP } @@ -4799,6 +4850,7 @@ CPL : 3 CATEGORY : SYSTEM EXTENSION : BASE ISA_SET : I286REAL +COMMENT : 66 is OSZ; F2/F3 ignored PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM() OPERANDS : MEM0:w:s64 REG0=XED_REG_IDTR:r:SUPP } @@ -6125,7 +6177,7 @@ EXTENSION : BASE ISA_SET : I86 PATTERN : 0b0101_1 SRM[rrr] DF64() OPERANDS : REG0=GPRv_SB():w REG1=XED_REG_STACKPOP:r:spw:SUPP -IFORM : POP_GPRv_51 +IFORM : POP_GPRv_58 } { ICLASS : PUSHA @@ -6172,9 +6224,9 @@ CATEGORY : INTERRUPT EXTENSION : BASE ATTRIBUTES: EXCEPTION_BR ISA_SET : I186 -PATTERN : 0x62 mode16 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +PATTERN : 0x62 not64 eosz16 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=GPRv_R():r MEM0:r:a16 -PATTERN : 0x62 mode32 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +PATTERN : 0x62 not64 eosz32 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=GPRv_R():r MEM0:r:a32 } { @@ -6460,9 +6512,9 @@ ISA_SET : I86 FLAGS : READONLY [ of-tst ] ATTRIBUTES: MPX_PREFIX_ABLE PATTERN : 0x70 mode64 FORCE64() BRANCH_HINT() BRDISP8() -OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP PATTERN : 0x70 not64 BRANCH_HINT() BRDISP8() -OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP } { ICLASS : JNO @@ -6473,9 +6525,9 @@ ISA_SET : I86 FLAGS : READONLY [ of-tst ] ATTRIBUTES: MPX_PREFIX_ABLE PATTERN : 0x71 mode64 FORCE64() BRANCH_HINT() BRDISP8() -OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP PATTERN : 0x71 not64 BRANCH_HINT() BRDISP8() -OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP } { ICLASS : JB @@ -6486,9 +6538,9 @@ ISA_SET : I86 FLAGS : READONLY [ cf-tst ] ATTRIBUTES: MPX_PREFIX_ABLE PATTERN : 0x72 mode64 FORCE64() BRANCH_HINT() BRDISP8() -OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP PATTERN : 0x72 not64 BRANCH_HINT() BRDISP8() -OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP } { ICLASS : JNB @@ -6499,9 +6551,9 @@ ISA_SET : I86 FLAGS : READONLY [ cf-tst ] ATTRIBUTES: MPX_PREFIX_ABLE PATTERN : 0x73 mode64 FORCE64() BRANCH_HINT() BRDISP8() -OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP PATTERN : 0x73 not64 BRANCH_HINT() BRDISP8() -OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP } { ICLASS : JZ @@ -6512,9 +6564,9 @@ ISA_SET : I86 FLAGS : READONLY [ zf-tst ] ATTRIBUTES: MPX_PREFIX_ABLE PATTERN : 0x74 mode64 FORCE64() BRANCH_HINT() BRDISP8() -OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP PATTERN : 0x74 not64 BRANCH_HINT() BRDISP8() -OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP } { ICLASS : JNZ @@ -6525,9 +6577,9 @@ ISA_SET : I86 FLAGS : READONLY [ zf-tst ] ATTRIBUTES: MPX_PREFIX_ABLE PATTERN : 0x75 mode64 FORCE64() BRANCH_HINT() BRDISP8() -OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP PATTERN : 0x75 not64 BRANCH_HINT() BRDISP8() -OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP } { ICLASS : JBE @@ -6538,9 +6590,9 @@ ISA_SET : I86 FLAGS : READONLY [ cf-tst zf-tst ] ATTRIBUTES: MPX_PREFIX_ABLE PATTERN : 0x76 mode64 FORCE64() BRANCH_HINT() BRDISP8() -OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP PATTERN : 0x76 not64 BRANCH_HINT() BRDISP8() -OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP } { ICLASS : JNBE @@ -6551,9 +6603,9 @@ ISA_SET : I86 FLAGS : READONLY [ cf-tst zf-tst ] ATTRIBUTES: MPX_PREFIX_ABLE PATTERN : 0x77 mode64 FORCE64() BRANCH_HINT() BRDISP8() -OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP PATTERN : 0x77 not64 BRANCH_HINT() BRDISP8() -OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP } { ICLASS : JS @@ -6564,9 +6616,9 @@ ISA_SET : I86 FLAGS : READONLY [ sf-tst ] ATTRIBUTES: MPX_PREFIX_ABLE PATTERN : 0x78 mode64 FORCE64() BRANCH_HINT() BRDISP8() -OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP PATTERN : 0x78 not64 BRANCH_HINT() BRDISP8() -OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP } { ICLASS : JNS @@ -6577,9 +6629,9 @@ ISA_SET : I86 FLAGS : READONLY [ sf-tst ] ATTRIBUTES: MPX_PREFIX_ABLE PATTERN : 0x79 mode64 FORCE64() BRANCH_HINT() BRDISP8() -OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP PATTERN : 0x79 not64 BRANCH_HINT() BRDISP8() -OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP } { ICLASS : JP @@ -6590,9 +6642,9 @@ ISA_SET : I86 FLAGS : READONLY [ pf-tst ] ATTRIBUTES: MPX_PREFIX_ABLE PATTERN : 0x7A mode64 FORCE64() BRANCH_HINT() BRDISP8() -OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP PATTERN : 0x7A not64 BRANCH_HINT() BRDISP8() -OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP } { ICLASS : JNP @@ -6603,9 +6655,9 @@ ISA_SET : I86 FLAGS : READONLY [ pf-tst ] ATTRIBUTES: MPX_PREFIX_ABLE PATTERN : 0x7B mode64 FORCE64() BRANCH_HINT() BRDISP8() -OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP PATTERN : 0x7B not64 BRANCH_HINT() BRDISP8() -OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP } { ICLASS : JL @@ -6616,9 +6668,9 @@ ISA_SET : I86 FLAGS : READONLY [ sf-tst of-tst ] ATTRIBUTES: MPX_PREFIX_ABLE PATTERN : 0x7C mode64 FORCE64() BRANCH_HINT() BRDISP8() -OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP PATTERN : 0x7C not64 BRANCH_HINT() BRDISP8() -OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP } { ICLASS : JNL @@ -6629,9 +6681,9 @@ ISA_SET : I86 FLAGS : READONLY [ sf-tst of-tst ] ATTRIBUTES: MPX_PREFIX_ABLE PATTERN : 0x7D mode64 FORCE64() BRANCH_HINT() BRDISP8() -OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP PATTERN : 0x7D not64 BRANCH_HINT() BRDISP8() -OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP } { ICLASS : JLE @@ -6642,9 +6694,9 @@ ISA_SET : I86 FLAGS : READONLY [ sf-tst of-tst zf-tst ] ATTRIBUTES: MPX_PREFIX_ABLE PATTERN : 0x7E mode64 FORCE64() BRANCH_HINT() BRDISP8() -OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP PATTERN : 0x7E not64 BRANCH_HINT() BRDISP8() -OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP } { ICLASS : JNLE @@ -6655,9 +6707,9 @@ ISA_SET : I86 FLAGS : READONLY [ sf-tst of-tst zf-tst ] ATTRIBUTES: MPX_PREFIX_ABLE PATTERN : 0x7F mode64 FORCE64() BRANCH_HINT() BRDISP8() -OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP PATTERN : 0x7F not64 BRANCH_HINT() BRDISP8() -OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP } { ICLASS : TEST @@ -6857,9 +6909,10 @@ CATEGORY : DATAXFER EXTENSION : BASE ISA_SET : I86 ATTRIBUTES: NOTSX -COMMENT : MOV to SS Inhibits all interrupts until after next instr +COMMENT : MOV to SS Inhibits all interrupts until after next instr. Cannot write to CS PATTERN : 0x8E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=SEG():w MEM0:r:w +OPERANDS : REG0=SEG_MOV():w MEM0:r:w +IFORM : MOV_SEG_MEMw } { ICLASS : MOV @@ -6868,8 +6921,10 @@ CATEGORY : DATAXFER EXTENSION : BASE ISA_SET : I86 ATTRIBUTES: NOTSX +COMMENT : MOV to SS Inhibits all interrupts until after next instr. Cannot write to CS PATTERN : 0x8E MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=SEG():w REG1=GPR16_B():r +OPERANDS : REG0=SEG_MOV():w REG1=GPR16_B():r +IFORM : MOV_SEG_GPR16 } @@ -6982,15 +7037,34 @@ DISASM_INTEL : call far DISASM_ATTSV : lcall CPL : 3 CATEGORY : CALL -ATTRIBUTES : FAR_XFER NOTSX +ATTRIBUTES : FAR_XFER NOTSX INDIRECT_BRANCH EXTENSION : BASE ISA_SET : I86 + COMMENT : same privilege level does 2 pushes (spw2). inter-privilege level does 4 (not represented) + PATTERN : 0xFF MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() OPERANDS : MEM0:r:p2 REG0=XED_REG_STACKPUSH:w:spw2:SUPP REG1=rIP():w:SUPP +} + + +{ +ICLASS : CALL_FAR +DISASM_INTEL : call far +DISASM_ATTSV : lcall +CPL : 3 +CATEGORY : CALL +ATTRIBUTES : FAR_XFER NOTSX +EXTENSION : BASE +ISA_SET : I86 + +COMMENT : same privilege level does 2 pushes (spw2). inter-privilege level does 4 (not represented) + PATTERN : 0x9A not64 BRDISPz() UIMM16() -OPERANDS : PTR:r:p IMM0:r:w REG0=XED_REG_STACKPUSH:w:spw2:SUPP REG1=rIP():w:SUPP +OPERANDS : PTR:r:p IMM0:r:w REG0=XED_REG_STACKPUSH:w:spw2:SUPP REG1=XED_REG_EIP:w:SUPP } + + { ICLASS : FWAIT CPL : 3 @@ -7816,7 +7890,7 @@ ISA_SET : I86 PATTERN : 0b1011_0 SRM[rrr] UIMM8() OPERANDS : REG0=GPR8_SB():w IMM0:r:b # i had to come up with a partial nibble name -IFORM : MOV_GPR8_IMMb_D0 +IFORM : MOV_GPR8_IMMb_B0 } { ICLASS : MOV @@ -7947,7 +8021,7 @@ EXTENSION : BASE ISA_SET : I86 FLAGS : MUST [ ac-mod vm-tst vm-mod rf-0 nt-mod iopl-tst of-tst if-mod tf-mod ] PATTERN : 0xCE not64 -OPERANDS : REG0=rIP():w:SUPP +OPERANDS : REG0=XED_REG_EIP:w:SUPP } { ICLASS : IRET @@ -7958,7 +8032,7 @@ EXTENSION : BASE ISA_SET : I86 FLAGS : MUST [ id-pop vip-pop vif-pop ac-pop vm-tst vm-pop rf-pop nt-tst nt-pop iopl-tst iopl-pop of-pop df-pop if-pop tf-pop sf-pop zf-pop af-pop pf-pop cf-pop ] PATTERN : 0xCF EOSZ=1 -OPERANDS : REG0=XED_REG_STACKPOP:r:spw3:SUPP REG1=rIP():w:SUPP +OPERANDS : REG0=XED_REG_STACKPOP:r:spw5:SUPP REG1=rIP():w:SUPP } { ICLASS : IRETD @@ -7969,7 +8043,7 @@ EXTENSION : BASE ISA_SET : I386 FLAGS : MUST [ id-pop vip-pop vif-pop ac-pop vm-tst vm-pop rf-pop nt-tst nt-pop iopl-tst iopl-pop of-pop df-pop if-pop tf-pop sf-pop zf-pop af-pop pf-pop cf-pop ] PATTERN : 0xCF EOSZ=2 -OPERANDS : REG0=XED_REG_STACKPOP:r:spw3:SUPP REG1=rIP():w:SUPP +OPERANDS : REG0=XED_REG_STACKPOP:r:spw5:SUPP REG1=rIP():w:SUPP } { ICLASS : IRETQ @@ -7980,7 +8054,7 @@ EXTENSION : LONGMODE FLAGS : MUST [ id-pop vip-pop vif-pop ac-pop vm-tst vm-pop rf-pop nt-tst nt-pop iopl-tst iopl-pop of-pop df-pop if-pop tf-pop sf-pop zf-pop af-pop pf-pop cf-pop ] PATTERN : 0xCF EOSZ=3 mode64 # FIXME: This is only an approximate width for the stack pops -OPERANDS : REG0=XED_REG_STACKPOP:r:spw3:SUPP REG1=rIP():w:SUPP +OPERANDS : REG0=XED_REG_STACKPOP:r:spw5:SUPP REG1=XED_REG_RIP:w:SUPP } { ICLASS : AAM @@ -7989,7 +8063,7 @@ CATEGORY : DECIMAL EXTENSION : BASE ISA_SET : I86 FLAGS : MUST [ of-u sf-mod zf-mod af-u pf-mod cf-u ] -PATTERN : 0xD4 not64 SIMM8() +PATTERN : 0xD4 not64 UIMM8() OPERANDS : IMM0:r:b:i8 REG0=XED_REG_AL:rw:SUPP REG1=XED_REG_AH:w:SUPP } { @@ -7999,7 +8073,7 @@ CATEGORY : DECIMAL EXTENSION : BASE ISA_SET : I86 FLAGS : MUST [ of-u sf-mod zf-mod af-u pf-mod cf-u ] -PATTERN : 0xD5 not64 SIMM8() +PATTERN : 0xD5 not64 UIMM8() OPERANDS : IMM0:r:b:i8 REG0=XED_REG_AL:rw:SUPP REG1=XED_REG_AH:rw:SUPP } { @@ -8039,7 +8113,7 @@ OPERANDS : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP PATTERN : 0xE0 MODEP5=0 DF64() BRDISP8() IMMUNE66_LOOP64() OPERANDS : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP -# REPNE WITH A E1 (LOOPE) makes a LOOPNE on P5-class machines UNDOC +COMMENT : REPNE WITH A E1 (LOOPE) makes a LOOPNE on P5-class machines UNDOC PATTERN : 0xE1 MODEP5=1 REP=2 DF64() BRDISP8() IMMUNE66_LOOP64() OPERANDS : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP } @@ -8057,7 +8131,7 @@ OPERANDS : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP PATTERN : 0xE1 MODEP5=0 DF64() BRDISP8() IMMUNE66_LOOP64() OPERANDS : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP -# REPE WITH A E0 (LOOPNE) makes a LOOPE on P5-class machines UNDOC +COMMENT : REPE WITH A E0 (LOOPNE) makes a LOOPE on P5-class machines UNDOC PATTERN : 0xE0 MODEP5=1 REP=3 DF64() BRDISP8() IMMUNE66_LOOP64() OPERANDS : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP } @@ -8082,7 +8156,7 @@ CATEGORY : COND_BR EXTENSION : BASE ISA_SET : I386 PATTERN : 0xE3 eamode16 BRDISP8() -OPERANDS : RELBR:r:b:i8 REG0=XED_REG_CX:r:SUPP REG1=rIP():rw:SUPP +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_CX:r:SUPP REG1=XED_REG_IP:rw:SUPP } { ICLASS : JECXZ @@ -8091,8 +8165,10 @@ CPL : 3 CATEGORY : COND_BR EXTENSION : BASE ISA_SET : I386 -PATTERN : 0xE3 eamode32 BRDISP8() -OPERANDS : RELBR:r:b:i8 REG0=XED_REG_ECX:r:SUPP REG1=rIP():rw:SUPP +PATTERN : 0xE3 eamode32 not64 BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_ECX:r:SUPP REG1=XED_REG_EIP:rw:SUPP +PATTERN : 0xE3 eamode32 mode64 BRDISP8() FORCE64() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_ECX:r:SUPP REG1=XED_REG_RIP:rw:SUPP } { ICLASS : JRCXZ @@ -8102,7 +8178,7 @@ CATEGORY : COND_BR EXTENSION : BASE ISA_SET : LONGMODE PATTERN : 0xE3 eamode64 BRDISP8() FORCE64() -OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RCX:r:SUPP REG1=rIP():rw:SUPP +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RCX:r:SUPP REG1=XED_REG_RIP:rw:SUPP } { @@ -8113,7 +8189,7 @@ EXTENSION : BASE ISA_SET : I86 ATTRIBUTES : BYTEOP NOTSX FLAGS : READONLY [ iopl-tst ] -PATTERN : 0xE4 UIMM8() IMMUNE_REXW() +PATTERN : 0xE4 UIMM8() OPERANDS : REG0=XED_REG_AL:w:IMPL IMM0:r:b } { @@ -8136,7 +8212,7 @@ EXTENSION : BASE ISA_SET : I86 ATTRIBUTES: NOTSX BYTEOP FLAGS : READONLY [ iopl-tst ] -PATTERN : 0xE6 UIMM8() IMMUNE_REXW() +PATTERN : 0xE6 UIMM8() OPERANDS : IMM0:r:b REG0=XED_REG_AL:r:IMPL } @@ -8160,9 +8236,9 @@ EXTENSION : BASE ISA_SET : I86 ATTRIBUTES: MPX_PREFIX_ABLE PATTERN : 0xE9 not64 BRDISPz() -OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP PATTERN : 0xE9 mode64 FORCE64() BRDISP32() -OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP } { ICLASS : JMP_FAR @@ -8174,7 +8250,7 @@ ATTRIBUTES : FAR_XFER NOTSX EXTENSION : BASE ISA_SET : I86 PATTERN : 0xEA not64 BRDISPz() UIMM16() -OPERANDS : PTR:r:p IMM0:r:w REG0=rIP():w:SUPP +OPERANDS : PTR:r:p IMM0:r:w REG0=XED_REG_EIP:w:SUPP } { ICLASS : JMP @@ -8182,8 +8258,10 @@ CPL : 3 CATEGORY : UNCOND_BR EXTENSION : BASE ISA_SET : I86 -PATTERN : 0xEB DF64() BRDISP8() -OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +PATTERN : 0xEB not64 BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP +PATTERN : 0xEB mode64 FORCE64() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP } { ICLASS : IN @@ -8193,7 +8271,7 @@ EXTENSION : BASE ISA_SET : I86 ATTRIBUTES : BYTEOP FLAGS : READONLY [ iopl-tst ] -PATTERN : 0xEC IMMUNE_REXW() +PATTERN : 0xEC OPERANDS : REG0=XED_REG_AL:w:IMPL REG1=XED_REG_DX:r:IMPL } { @@ -8214,7 +8292,7 @@ EXTENSION : BASE ISA_SET : I86 ATTRIBUTES : BYTEOP FLAGS : READONLY [ iopl-tst ] -PATTERN : 0xEE IMMUNE_REXW() +PATTERN : 0xEE OPERANDS : REG0=XED_REG_DX:r:IMPL REG1=XED_REG_AL:r:IMPL } { @@ -8234,7 +8312,7 @@ CATEGORY : INTERRUPT EXTENSION : BASE ISA_SET : I86 PATTERN : 0xF1 -OPERANDS : +OPERANDS : REG0=rIP():w:SUPP COMMENT : UNDOC by Intel, but in AMD's opcode map } { @@ -8359,7 +8437,7 @@ EXTENSION : LONGMODE ISA_SET : LONGMODE FLAGS : MUST [ id-mod vip-mod vif-mod ac-mod vm-0 rf-0 nt-mod iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ] PATTERN : 0x0F 0x05 mode64 FORCE64() -OPERANDS : REG0=rIP():w:SUPP +OPERANDS : REG0=XED_REG_RIP:w:SUPP REG1=XED_REG_RCX:w:SUPP REG2=XED_REG_R11:w:SUPP COMMENT : 32B VERSION IS ONLY SUPPORTED ON AMD } { @@ -8381,9 +8459,9 @@ EXTENSION : LONGMODE ISA_SET : LONGMODE FLAGS : MUST [ id-mod vip-mod vif-mod ac-mod rf-0 nt-mod iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ] PATTERN : 0x0F 0x07 mode64 eosz64 -OPERANDS : REG0=XED_REG_RIP:w:SUPP -PATTERN : 0x0F 0x07 mode64 eosz32 -OPERANDS : REG0=XED_REG_EIP:w:SUPP +OPERANDS : REG0=XED_REG_RIP:w:SUPP REG1=XED_REG_RCX:r:SUPP REG2=XED_REG_R11:r:SUPP +PATTERN : 0x0F 0x07 mode64 eosznot64 +OPERANDS : REG0=XED_REG_EIP:w:SUPP REG1=XED_REG_ECX:r:SUPP COMMENT : 32B VERSION IS ONLY SUPPORTED ON AMD } { @@ -8414,7 +8492,7 @@ CATEGORY : DATAXFER EXTENSION : SSE EXCEPTIONS: SSE_TYPE_5 ATTRIBUTES : -PATTERN : 0x0F 0x13 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] no_refining_prefix MODRM() +PATTERN : 0x0F 0x13 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : MEM0:w:q:f32 REG0=XMM_R():r:ps:f32 } { @@ -8449,7 +8527,7 @@ CATEGORY : DATAXFER EXTENSION : SSE EXCEPTIONS: SSE_TYPE_5 ATTRIBUTES : -PATTERN : 0x0F 0x17 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] no_refining_prefix MODRM() +PATTERN : 0x0F 0x17 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : MEM0:w:q:f32 REG0=XMM_R():r:ps:f32 } { @@ -8643,10 +8721,10 @@ EXTENSION : BASE ISA_SET : I86 ATTRIBUTES : RING0 NOTSX COMMENT : MODRM.MOD=00/01/10 aliased to MODRM.MOD=11 -PATTERN : 0x0F 0x23 MOD[mm] REG[rrr] RM[nnn] DF64() not64 +PATTERN : 0x0F 0x23 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() not64 OPERANDS : REG0=DR_R():w REG1=GPR32_B():r -PATTERN : 0x0F 0x23 MOD[mm] REG[rrr] RM[nnn] DF64() mode64 +PATTERN : 0x0F 0x23 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() mode64 OPERANDS : REG0=DR_R():w REG1=GPR64_B():r } @@ -8659,10 +8737,10 @@ EXTENSION : BASE ISA_SET : I86 ATTRIBUTES : RING0 COMMENT : MODRM.MOD=00/01/10 aliased to MODRM.MOD=11 -PATTERN : 0x0F 0x21 MOD[mm] REG[rrr] RM[nnn] DF64() not64 +PATTERN : 0x0F 0x21 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() not64 OPERANDS : REG0=GPR32_B():w REG1=DR_R():r -PATTERN : 0x0F 0x21 MOD[mm] REG[rrr] RM[nnn] DF64() mode64 +PATTERN : 0x0F 0x21 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() mode64 OPERANDS : REG0=GPR64_B():w REG1=DR_R():r } @@ -8713,8 +8791,10 @@ EXTENSION : BASE ISA_SET : PPRO ATTRIBUTES: PROTECTED_MODE NOTSX FLAGS : MUST [ vm-0 rf-0 if-0 ] -PATTERN : 0x0F 0x34 -OPERANDS : REG0=rIP():w:SUPP +PATTERN : 0x0F 0x34 not64 +OPERANDS : REG0=XED_REG_EIP:w:SUPP REG1=XED_REG_ESP:w:SUPP +PATTERN : 0x0F 0x34 mode64 +OPERANDS : REG0=XED_REG_RIP:w:SUPP REG1=XED_REG_RSP:w:SUPP COMMENT : AMD does not document support for this in 64b mode } { @@ -8724,8 +8804,10 @@ CATEGORY : SYSRET EXTENSION : BASE ISA_SET : PPRO ATTRIBUTES: PROTECTED_MODE RING0 NOTSX -PATTERN : 0x0F 0x35 -OPERANDS : REG0=rIP():w:SUPP +PATTERN : 0x0F 0x35 not64 +OPERANDS : REG0=XED_REG_EIP:w:SUPP REG1=XED_REG_ESP:w:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_EDX:r:SUPP +PATTERN : 0x0F 0x35 mode64 +OPERANDS : REG0=XED_REG_RIP:w:SUPP REG1=XED_REG_RSP:w:SUPP REG2=XED_REG_RCX:r:SUPP REG3=XED_REG_RDX:r:SUPP COMMENT : AMD does not document support for this in 64b mode } { @@ -8733,7 +8815,7 @@ ICLASS : CMOVO CPL : 3 CATEGORY : CMOV EXTENSION : BASE -ISA_SET : PPRO +ISA_SET : CMOV FLAGS : READONLY [ of-tst ] PATTERN : 0x0F 0x40 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=GPRv_R():cw MEM0:r:v @@ -8745,7 +8827,7 @@ ICLASS : CMOVNO CPL : 3 CATEGORY : CMOV EXTENSION : BASE -ISA_SET : PPRO +ISA_SET : CMOV FLAGS : READONLY [ of-tst ] PATTERN : 0x0F 0x41 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=GPRv_R():cw MEM0:r:v @@ -8757,7 +8839,7 @@ ICLASS : CMOVB CPL : 3 CATEGORY : CMOV EXTENSION : BASE -ISA_SET : PPRO +ISA_SET : CMOV FLAGS : READONLY [ cf-tst ] PATTERN : 0x0F 0x42 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=GPRv_R():cw MEM0:r:v @@ -8769,7 +8851,7 @@ ICLASS : CMOVNB CPL : 3 CATEGORY : CMOV EXTENSION : BASE -ISA_SET : PPRO +ISA_SET : CMOV FLAGS : READONLY [ cf-tst ] PATTERN : 0x0F 0x43 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=GPRv_R():cw MEM0:r:v @@ -8781,7 +8863,7 @@ ICLASS : CMOVZ CPL : 3 CATEGORY : CMOV EXTENSION : BASE -ISA_SET : PPRO +ISA_SET : CMOV FLAGS : READONLY [ zf-tst ] PATTERN : 0x0F 0x44 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=GPRv_R():cw MEM0:r:v @@ -8793,7 +8875,7 @@ ICLASS : CMOVNZ CPL : 3 CATEGORY : CMOV EXTENSION : BASE -ISA_SET : PPRO +ISA_SET : CMOV FLAGS : READONLY [ zf-tst ] PATTERN : 0x0F 0x45 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=GPRv_R():cw MEM0:r:v @@ -8805,7 +8887,7 @@ ICLASS : CMOVBE CPL : 3 CATEGORY : CMOV EXTENSION : BASE -ISA_SET : PPRO +ISA_SET : CMOV FLAGS : READONLY [ cf-tst zf-tst ] PATTERN : 0x0F 0x46 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=GPRv_R():cw MEM0:r:v @@ -8817,7 +8899,7 @@ ICLASS : CMOVNBE CPL : 3 CATEGORY : CMOV EXTENSION : BASE -ISA_SET : PPRO +ISA_SET : CMOV FLAGS : READONLY [ cf-tst zf-tst ] PATTERN : 0x0F 0x47 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=GPRv_R():cw MEM0:r:v @@ -8877,9 +8959,9 @@ EXTENSION : SSE EXCEPTIONS: SSE_TYPE_4 ATTRIBUTES : REQUIRES_ALIGNMENT PATTERN : 0x0F 0x54 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps +OPERANDS : REG0=XMM_R():rw:xud MEM0:r:xud PATTERN : 0x0F 0x54 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps +OPERANDS : REG0=XMM_R():rw:xud REG1=XMM_B():r:xud } { ICLASS : ANDNPS @@ -8889,9 +8971,9 @@ EXTENSION : SSE EXCEPTIONS: SSE_TYPE_4 ATTRIBUTES : REQUIRES_ALIGNMENT PATTERN : 0x0F 0x55 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps +OPERANDS : REG0=XMM_R():rw:xud MEM0:r:xud PATTERN : 0x0F 0x55 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps +OPERANDS : REG0=XMM_R():rw:xud REG1=XMM_B():r:xud } { ICLASS : ORPS @@ -8901,9 +8983,9 @@ EXTENSION : SSE EXCEPTIONS: SSE_TYPE_4 ATTRIBUTES : REQUIRES_ALIGNMENT PATTERN : 0x0F 0x56 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps +OPERANDS : REG0=XMM_R():rw:xud MEM0:r:xud PATTERN : 0x0F 0x56 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps +OPERANDS : REG0=XMM_R():rw:xud REG1=XMM_B():r:xud } { ICLASS : XORPS @@ -8913,9 +8995,9 @@ EXTENSION : SSE EXCEPTIONS: SSE_TYPE_4 ATTRIBUTES : REQUIRES_ALIGNMENT PATTERN : 0x0F 0x57 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps +OPERANDS : REG0=XMM_R():rw:xud MEM0:r:xud PATTERN : 0x0F 0x57 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps +OPERANDS : REG0=XMM_R():rw:xud REG1=XMM_B():r:xud } { ICLASS : SQRTSS @@ -8982,9 +9064,9 @@ EXTENSION : SSE2 EXCEPTIONS: SSE_TYPE_4 ATTRIBUTES : REQUIRES_ALIGNMENT PATTERN : 0x0F 0x54 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() -OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd +OPERANDS : REG0=XMM_R():rw:xuq MEM0:r:xuq PATTERN : 0x0F 0x54 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() -OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd +OPERANDS : REG0=XMM_R():rw:xuq REG1=XMM_B():r:xuq } { ICLASS : ANDNPD @@ -8994,9 +9076,9 @@ EXTENSION : SSE2 EXCEPTIONS: SSE_TYPE_4 ATTRIBUTES : REQUIRES_ALIGNMENT PATTERN : 0x0F 0x55 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() -OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd +OPERANDS : REG0=XMM_R():rw:xuq MEM0:r:xuq PATTERN : 0x0F 0x55 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() -OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd +OPERANDS : REG0=XMM_R():rw:xuq REG1=XMM_B():r:xuq } { ICLASS : ORPD @@ -9006,9 +9088,9 @@ EXTENSION : SSE2 EXCEPTIONS: SSE_TYPE_4 ATTRIBUTES : REQUIRES_ALIGNMENT PATTERN : 0x0F 0x56 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() -OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd +OPERANDS : REG0=XMM_R():rw:xuq MEM0:r:xuq PATTERN : 0x0F 0x56 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() -OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd +OPERANDS : REG0=XMM_R():rw:xuq REG1=XMM_B():r:xuq } { ICLASS : XORPD @@ -9018,9 +9100,9 @@ EXTENSION : SSE2 EXCEPTIONS: SSE_TYPE_4 ATTRIBUTES : REQUIRES_ALIGNMENT PATTERN : 0x0F 0x57 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() -OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd +OPERANDS : REG0=XMM_R():rw:xuq MEM0:r:xuq PATTERN : 0x0F 0x57 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() -OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd +OPERANDS : REG0=XMM_R():rw:xuq REG1=XMM_B():r:xuq } { ICLASS : SQRTSD @@ -9421,7 +9503,7 @@ FLAGS : READONLY [ of-tst ] ATTRIBUTES: MPX_PREFIX_ABLE PATTERN : 0x0F 0x80 mode64 FORCE64() BRANCH_HINT() BRDISP32() -OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP } { ICLASS : JO @@ -9432,7 +9514,7 @@ ISA_SET : I86 FLAGS : READONLY [ of-tst ] ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE PATTERN : 0x0F 0x80 not64 BRANCH_HINT() BRDISPz() -OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP } @@ -9445,7 +9527,7 @@ ISA_SET : I86 FLAGS : READONLY [ of-tst ] ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE PATTERN : 0x0F 0x81 not64 BRANCH_HINT() BRDISPz() -OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP } { ICLASS : JNO @@ -9457,7 +9539,7 @@ FLAGS : READONLY [ of-tst ] ATTRIBUTES: MPX_PREFIX_ABLE PATTERN : 0x0F 0x81 mode64 FORCE64() BRANCH_HINT() BRDISP32() -OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP } @@ -9470,7 +9552,7 @@ ISA_SET : I86 FLAGS : READONLY [ cf-tst ] ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE PATTERN : 0x0F 0x82 not64 BRANCH_HINT() BRDISPz() -OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP } { ICLASS : JB @@ -9482,7 +9564,7 @@ FLAGS : READONLY [ cf-tst ] ATTRIBUTES: MPX_PREFIX_ABLE PATTERN : 0x0F 0x82 mode64 FORCE64() BRANCH_HINT() BRDISP32() -OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP } @@ -9496,7 +9578,7 @@ ISA_SET : I86 FLAGS : READONLY [ cf-tst ] ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE PATTERN : 0x0F 0x83 not64 BRANCH_HINT() BRDISPz() -OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP } { @@ -9509,7 +9591,7 @@ FLAGS : READONLY [ cf-tst ] ATTRIBUTES: MPX_PREFIX_ABLE PATTERN : 0x0F 0x83 mode64 FORCE64() BRANCH_HINT() BRDISP32() -OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP } @@ -9522,7 +9604,7 @@ ISA_SET : I86 FLAGS : READONLY [ zf-tst ] ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE PATTERN : 0x0F 0x84 not64 BRANCH_HINT() BRDISPz() -OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP } { ICLASS : JZ @@ -9534,7 +9616,7 @@ FLAGS : READONLY [ zf-tst ] ATTRIBUTES: MPX_PREFIX_ABLE PATTERN : 0x0F 0x84 mode64 FORCE64() BRANCH_HINT() BRDISP32() -OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP } @@ -9547,7 +9629,7 @@ ISA_SET : I86 FLAGS : READONLY [ zf-tst ] ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE PATTERN : 0x0F 0x85 not64 BRANCH_HINT() BRDISPz() -OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP } { @@ -9560,7 +9642,7 @@ FLAGS : READONLY [ zf-tst ] ATTRIBUTES: MPX_PREFIX_ABLE PATTERN : 0x0F 0x85 mode64 FORCE64() BRANCH_HINT() BRDISP32() -OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP } @@ -9574,7 +9656,7 @@ ISA_SET : I86 FLAGS : READONLY [ cf-tst zf-tst ] ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE PATTERN : 0x0F 0x86 not64 BRANCH_HINT() BRDISPz() -OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP } { ICLASS : JBE @@ -9586,7 +9668,7 @@ FLAGS : READONLY [ cf-tst zf-tst ] ATTRIBUTES: MPX_PREFIX_ABLE PATTERN : 0x0F 0x86 mode64 FORCE64() BRANCH_HINT() BRDISP32() -OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP } @@ -9600,7 +9682,7 @@ ISA_SET : I86 FLAGS : READONLY [ cf-tst zf-tst ] ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE PATTERN : 0x0F 0x87 not64 BRANCH_HINT() BRDISPz() -OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP } { ICLASS : JNBE @@ -9612,7 +9694,7 @@ FLAGS : READONLY [ cf-tst zf-tst ] ATTRIBUTES: MPX_PREFIX_ABLE PATTERN : 0x0F 0x87 mode64 FORCE64() BRANCH_HINT() BRDISP32() -OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP } @@ -10008,7 +10090,7 @@ ICLASS : MOVNTI CPL : 3 CATEGORY : DATAXFER EXTENSION : SSE2 -ATTRIBUTES : IGNORES_OSFXSR NOTSX +ATTRIBUTES : IGNORES_OSFXSR NOTSX NONTEMPORAL PATTERN : 0x0F 0xC3 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] EOSZ!=3 MODRM() OPERANDS : MEM0:w:d REG0=GPR32_R():r PATTERN : 0x0F 0xC3 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] EOSZ=3 MODRM() @@ -10193,6 +10275,7 @@ ATTRIBUTES: NOTSX CPL : 3 CATEGORY : MMX EXTENSION : SSE2 +ISA_SET : SSE2MMX PATTERN : 0x0F 0xD4 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=MMX_R():rw:q:u64 MEM0:r:q:u64 PATTERN : 0x0F 0xD4 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] @@ -10500,7 +10583,7 @@ OPERANDS : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q:i16 { ICLASS : MOVNTQ EXCEPTIONS: mmx-nofp2 -ATTRIBUTES: NOTSX +ATTRIBUTES: NOTSX NONTEMPORAL CPL : 3 CATEGORY : DATAXFER EXTENSION : MMX @@ -10620,7 +10703,7 @@ OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:pd:f64 } { ICLASS : MOVNTDQ -ATTRIBUTES: REQUIRES_ALIGNMENT NOTSX +ATTRIBUTES: REQUIRES_ALIGNMENT NOTSX NONTEMPORAL CPL : 3 CATEGORY : DATAXFER EXTENSION : SSE2 @@ -10698,6 +10781,7 @@ ATTRIBUTES: NOTSX CPL : 3 CATEGORY : MMX EXTENSION : SSE2 +ISA_SET : SSE2MMX PATTERN : 0x0F 0xF4 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=MMX_R():rw:q:u32 MEM0:r:q:u32 PATTERN : 0x0F 0xF4 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] @@ -10736,7 +10820,7 @@ CPL : 3 CATEGORY : DATAXFER EXTENSION : MMX ISA_SET : PENTIUMMMX -ATTRIBUTES : fixed_base0 maskop NOTSX +ATTRIBUTES : fixed_base0 maskop NOTSX NONTEMPORAL PATTERN : 0x0F 0xF7 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] OVERRIDE_SEG0() OPERANDS : REG0=MMX_R():r:q:u8 REG1=MMX_B():r:q:i8 MEM0:w:q:SUPP BASE0=ArDI():r:SUPP SEG0=FINAL_DSEG():r:SUPP } @@ -10855,7 +10939,7 @@ CPL : 3 CATEGORY : DATAXFER EXTENSION : SSE2 EXCEPTIONS: SSE_TYPE_4 -ATTRIBUTES : fixed_base0 maskop NOTSX +ATTRIBUTES : fixed_base0 maskop NOTSX NONTEMPORAL PATTERN : 0x0F 0xF7 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() OVERRIDE_SEG0() OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq MEM0:w:dq:SUPP BASE0=ArDI():r:SUPP SEG0=FINAL_DSEG():r:SUPP } @@ -10890,6 +10974,31 @@ PATTERN : 0x0F 0x09 OPERANDS : } { +ICLASS : UD0 +CPL : 3 +CATEGORY : MISC +EXTENSION : BASE +ISA_SET : PPRO +ATTRIBUTES: NOTSX +COMMENT : Older processors (before NHM) did not take a MODRM byte sequence. +PATTERN : 0x0F 0xFF MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR32_R():r MEM0:r:d +PATTERN : 0x0F 0xFF MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():r REG1=GPR32_B():r +} +{ +ICLASS : UD1 +CPL : 3 +CATEGORY : MISC +EXTENSION : BASE +ISA_SET : PPRO +ATTRIBUTES: NOTSX +PATTERN : 0x0F 0xB9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR32_R():r MEM0:r:d +PATTERN : 0x0F 0xB9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():r REG1=GPR32_B():r +} +{ ICLASS : UD2 CPL : 3 CATEGORY : MISC @@ -10935,7 +11044,7 @@ OPERANDS : REG0=XMM_R():w:q:f32 REG1=MMX_B():r:q:i32 } { ICLASS : MOVNTPS -ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT NONTEMPORAL CPL : 3 CATEGORY : DATAXFER EXTENSION : SSE @@ -10963,9 +11072,9 @@ CATEGORY : CONVERT EXTENSION : SSE ATTRIBUTES : MXCSR MMX_EXCEPT NOTSX PATTERN : 0x0F 0x2D no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=MMX_R():w:q:f32 MEM0:r:q:i32 +OPERANDS : REG0=MMX_R():w:q:i32 MEM0:r:q:f32 PATTERN : 0x0F 0x2D no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=MMX_R():w:q:f32 REG1=XMM_B():r:q:i32 +OPERANDS : REG0=MMX_R():w:q:i32 REG1=XMM_B():r:q:f32 } { ICLASS : UCOMISS @@ -11076,7 +11185,7 @@ OPERANDS : REG0=XMM_R():w:pd:f64 REG1=MMX_B():r:q:i32 } { ICLASS : MOVNTPD -ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT NONTEMPORAL CPL : 3 CATEGORY : DATAXFER EXTENSION : SSE2 @@ -11187,7 +11296,7 @@ ICLASS : CMOVS CPL : 3 CATEGORY : CMOV EXTENSION : BASE -ISA_SET : PPRO +ISA_SET : CMOV FLAGS : READONLY [ sf-tst ] PATTERN : 0x0F 0x48 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=GPRv_R():cw MEM0:r:v @@ -11197,7 +11306,7 @@ ICLASS : CMOVS CPL : 3 CATEGORY : CMOV EXTENSION : BASE -ISA_SET : PPRO +ISA_SET : CMOV FLAGS : READONLY [ sf-tst ] PATTERN : 0x0F 0x48 MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r @@ -11207,7 +11316,7 @@ ICLASS : CMOVNS CPL : 3 CATEGORY : CMOV EXTENSION : BASE -ISA_SET : PPRO +ISA_SET : CMOV FLAGS : READONLY [ sf-tst ] PATTERN : 0x0F 0x49 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=GPRv_R():cw MEM0:r:v @@ -11217,7 +11326,7 @@ ICLASS : CMOVNS CPL : 3 CATEGORY : CMOV EXTENSION : BASE -ISA_SET : PPRO +ISA_SET : CMOV FLAGS : READONLY [ sf-tst ] PATTERN : 0x0F 0x49 MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r @@ -11227,7 +11336,7 @@ ICLASS : CMOVP CPL : 3 CATEGORY : CMOV EXTENSION : BASE -ISA_SET : PPRO +ISA_SET : CMOV FLAGS : READONLY [ pf-tst ] PATTERN : 0x0F 0x4A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=GPRv_R():cw MEM0:r:v @@ -11237,7 +11346,7 @@ ICLASS : CMOVP CPL : 3 CATEGORY : CMOV EXTENSION : BASE -ISA_SET : PPRO +ISA_SET : CMOV FLAGS : READONLY [ pf-tst ] PATTERN : 0x0F 0x4A MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r @@ -11247,7 +11356,7 @@ ICLASS : CMOVNP CPL : 3 CATEGORY : CMOV EXTENSION : BASE -ISA_SET : PPRO +ISA_SET : CMOV FLAGS : READONLY [ pf-tst ] PATTERN : 0x0F 0x4B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=GPRv_R():cw MEM0:r:v @@ -11257,7 +11366,7 @@ ICLASS : CMOVNP CPL : 3 CATEGORY : CMOV EXTENSION : BASE -ISA_SET : PPRO +ISA_SET : CMOV FLAGS : READONLY [ pf-tst ] PATTERN : 0x0F 0x4B MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r @@ -11267,7 +11376,7 @@ ICLASS : CMOVL CPL : 3 CATEGORY : CMOV EXTENSION : BASE -ISA_SET : PPRO +ISA_SET : CMOV FLAGS : READONLY [ sf-tst of-tst ] PATTERN : 0x0F 0x4C MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=GPRv_R():cw MEM0:r:v @@ -11277,7 +11386,7 @@ ICLASS : CMOVL CPL : 3 CATEGORY : CMOV EXTENSION : BASE -ISA_SET : PPRO +ISA_SET : CMOV FLAGS : READONLY [ sf-tst of-tst ] PATTERN : 0x0F 0x4C MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r @@ -11287,7 +11396,7 @@ ICLASS : CMOVNL CPL : 3 CATEGORY : CMOV EXTENSION : BASE -ISA_SET : PPRO +ISA_SET : CMOV FLAGS : READONLY [ sf-tst of-tst ] PATTERN : 0x0F 0x4D MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=GPRv_R():cw MEM0:r:v @@ -11297,7 +11406,7 @@ ICLASS : CMOVNL CPL : 3 CATEGORY : CMOV EXTENSION : BASE -ISA_SET : PPRO +ISA_SET : CMOV FLAGS : READONLY [ sf-tst of-tst ] PATTERN : 0x0F 0x4D MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r @@ -11307,7 +11416,7 @@ ICLASS : CMOVLE CPL : 3 CATEGORY : CMOV EXTENSION : BASE -ISA_SET : PPRO +ISA_SET : CMOV FLAGS : READONLY [ sf-tst of-tst zf-tst ] PATTERN : 0x0F 0x4E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=GPRv_R():cw MEM0:r:v @@ -11317,7 +11426,7 @@ ICLASS : CMOVLE CPL : 3 CATEGORY : CMOV EXTENSION : BASE -ISA_SET : PPRO +ISA_SET : CMOV FLAGS : READONLY [ sf-tst of-tst zf-tst ] PATTERN : 0x0F 0x4E MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r @@ -11327,7 +11436,7 @@ ICLASS : CMOVNLE CPL : 3 CATEGORY : CMOV EXTENSION : BASE -ISA_SET : PPRO +ISA_SET : CMOV FLAGS : READONLY [ sf-tst of-tst zf-tst ] PATTERN : 0x0F 0x4F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=GPRv_R():cw MEM0:r:v @@ -11337,7 +11446,7 @@ ICLASS : CMOVNLE CPL : 3 CATEGORY : CMOV EXTENSION : BASE -ISA_SET : PPRO +ISA_SET : CMOV FLAGS : READONLY [ sf-tst of-tst zf-tst ] PATTERN : 0x0F 0x4F MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r @@ -12009,26 +12118,30 @@ IFORM : MOVDQU_XMMdq_XMMdq_0F7F } { ICLASS : VMREAD -CPL : 3 +CPL : 0 CATEGORY : VTX EXTENSION : VTX +FLAGS : MUST [ cf-mod zf-mod sf-0 of-0 af-0 pf-0 ] + PATTERN : 0x0F 0x78 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 MODRM() CR_WIDTH() -OPERANDS : MEM0:rw:q REG0=GPR64_R():r +OPERANDS : MEM0:w:q REG0=GPR64_R():r PATTERN : 0x0F 0x78 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 CR_WIDTH() -OPERANDS : REG0=GPR64_B():rw REG1=GPR64_R():r +OPERANDS : REG0=GPR64_B():w REG1=GPR64_R():r PATTERN : 0x0F 0x78 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() CR_WIDTH() -OPERANDS : MEM0:rw:d REG0=GPR32_R():r +OPERANDS : MEM0:w:d REG0=GPR32_R():r PATTERN : 0x0F 0x78 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 CR_WIDTH() -OPERANDS : REG0=GPR32_B():rw REG1=GPR32_R():r +OPERANDS : REG0=GPR32_B():w REG1=GPR32_R():r } { ICLASS : VMWRITE -CPL : 3 +CPL : 0 CATEGORY : VTX EXTENSION : VTX +FLAGS : MUST [ cf-mod zf-mod sf-0 of-0 af-0 pf-0 ] + PATTERN : 0x0F 0x79 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 MODRM() CR_WIDTH() OPERANDS : REG0=GPR64_R():r MEM0:r:q @@ -12119,7 +12232,7 @@ ISA_SET : I86 FLAGS : READONLY [ sf-tst ] ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE PATTERN : 0x0F 0x88 not64 BRANCH_HINT() BRDISPz() -OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP } { ICLASS : JS @@ -12131,7 +12244,7 @@ FLAGS : READONLY [ sf-tst ] ATTRIBUTES: MPX_PREFIX_ABLE PATTERN : 0x0F 0x88 mode64 FORCE64() BRANCH_HINT() BRDISP32() -OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP } @@ -12144,7 +12257,7 @@ ISA_SET : I86 FLAGS : READONLY [ sf-tst ] ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE PATTERN : 0x0F 0x89 not64 BRANCH_HINT() BRDISPz() -OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP } { ICLASS : JNS @@ -12156,7 +12269,7 @@ FLAGS : READONLY [ sf-tst ] ATTRIBUTES: MPX_PREFIX_ABLE PATTERN : 0x0F 0x89 mode64 FORCE64() BRANCH_HINT() BRDISP32() -OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP } @@ -12170,7 +12283,7 @@ ISA_SET : I86 FLAGS : READONLY [ pf-tst ] ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE PATTERN : 0x0F 0x8A not64 BRANCH_HINT() BRDISPz() -OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP } { ICLASS : JP @@ -12182,7 +12295,7 @@ FLAGS : READONLY [ pf-tst ] ATTRIBUTES: MPX_PREFIX_ABLE PATTERN : 0x0F 0x8A mode64 FORCE64() BRANCH_HINT() BRDISP32() -OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP } @@ -12195,7 +12308,7 @@ ISA_SET : I86 FLAGS : READONLY [ pf-tst ] ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE PATTERN : 0x0F 0x8B not64 BRANCH_HINT() BRDISPz() -OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP } { ICLASS : JNP @@ -12207,7 +12320,7 @@ FLAGS : READONLY [ pf-tst ] ATTRIBUTES: MPX_PREFIX_ABLE PATTERN : 0x0F 0x8B mode64 FORCE64() BRANCH_HINT() BRDISP32() -OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP } @@ -12220,7 +12333,7 @@ ISA_SET : I86 FLAGS : READONLY [ sf-tst of-tst ] ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE PATTERN : 0x0F 0x8C not64 BRANCH_HINT() BRDISPz() -OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP } { ICLASS : JL @@ -12232,7 +12345,7 @@ FLAGS : READONLY [ sf-tst of-tst ] ATTRIBUTES: MPX_PREFIX_ABLE PATTERN : 0x0F 0x8C mode64 FORCE64() BRANCH_HINT() BRDISP32() -OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP } @@ -12246,7 +12359,7 @@ ISA_SET : I86 FLAGS : READONLY [ sf-tst of-tst ] ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE PATTERN : 0x0F 0x8D not64 BRANCH_HINT() BRDISPz() -OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP } { ICLASS : JNL @@ -12258,7 +12371,7 @@ FLAGS : READONLY [ sf-tst of-tst ] ATTRIBUTES: MPX_PREFIX_ABLE PATTERN : 0x0F 0x8D mode64 FORCE64() BRANCH_HINT() BRDISP32() -OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP } @@ -12272,7 +12385,7 @@ ISA_SET : I86 FLAGS : READONLY [ sf-tst of-tst zf-tst ] ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE PATTERN : 0x0F 0x8E not64 BRANCH_HINT() BRDISPz() -OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP } { ICLASS : JLE @@ -12284,7 +12397,7 @@ FLAGS : READONLY [ sf-tst of-tst zf-tst ] ATTRIBUTES: MPX_PREFIX_ABLE PATTERN : 0x0F 0x8E mode64 FORCE64() BRANCH_HINT() BRDISP32() -OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP } @@ -12298,7 +12411,7 @@ ISA_SET : I86 FLAGS : READONLY [ sf-tst of-tst zf-tst ] ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE PATTERN : 0x0F 0x8F not64 BRANCH_HINT() BRDISPz() -OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP } { ICLASS : JNLE @@ -12310,7 +12423,7 @@ FLAGS : READONLY [ sf-tst of-tst zf-tst ] ATTRIBUTES: MPX_PREFIX_ABLE PATTERN : 0x0F 0x8F mode64 FORCE64() BRANCH_HINT() BRDISP32() -OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP +OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP } @@ -13176,6 +13289,7 @@ ATTRIBUTES: NOTSX CPL : 3 CATEGORY : MMX EXTENSION : SSE2 +ISA_SET : SSE2MMX PATTERN : 0x0F 0xFB no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=MMX_R():rw:q MEM0:r:q PATTERN : 0x0F 0xFB no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] @@ -13311,6 +13425,7 @@ ATTRIBUTES: NOTSX CPL : 3 CATEGORY : MMX EXTENSION : SSSE3 +ISA_SET : SSSE3MMX PATTERN : 0x0F 0x38 0x01 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=MMX_R():rw:q MEM0:r:q PATTERN : 0x0F 0x38 0x01 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] @@ -13335,6 +13450,7 @@ ATTRIBUTES: NOTSX CPL : 3 CATEGORY : MMX EXTENSION : SSSE3 +ISA_SET : SSSE3MMX PATTERN : 0x0F 0x38 0x02 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=MMX_R():rw:q MEM0:r:q PATTERN : 0x0F 0x38 0x02 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] @@ -13359,6 +13475,7 @@ ATTRIBUTES: NOTSX CPL : 3 CATEGORY : MMX EXTENSION : SSSE3 +ISA_SET : SSSE3MMX PATTERN : 0x0F 0x38 0x03 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=MMX_R():rw:q MEM0:r:q PATTERN : 0x0F 0x38 0x03 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] @@ -13383,6 +13500,7 @@ ATTRIBUTES: NOTSX CPL : 3 CATEGORY : MMX EXTENSION : SSSE3 +ISA_SET : SSSE3MMX PATTERN : 0x0F 0x38 0x05 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=MMX_R():rw:q MEM0:r:q PATTERN : 0x0F 0x38 0x05 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] @@ -13407,6 +13525,7 @@ ATTRIBUTES: NOTSX CPL : 3 CATEGORY : MMX EXTENSION : SSSE3 +ISA_SET : SSSE3MMX PATTERN : 0x0F 0x38 0x06 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=MMX_R():rw:q MEM0:r:q PATTERN : 0x0F 0x38 0x06 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] @@ -13431,6 +13550,7 @@ ATTRIBUTES: NOTSX CPL : 3 CATEGORY : MMX EXTENSION : SSSE3 +ISA_SET : SSSE3MMX PATTERN : 0x0F 0x38 0x07 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=MMX_R():rw:q MEM0:r:q PATTERN : 0x0F 0x38 0x07 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] @@ -13454,6 +13574,7 @@ EXCEPTIONS: mmx-mem CPL : 3 CATEGORY : MMX EXTENSION : SSSE3 +ISA_SET : SSSE3MMX ATTRIBUTES : DOUBLE_WIDE_OUTPUT NOTSX PATTERN : 0x0F 0x38 0x04 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=MMX_R():rw:q:i8 MEM0:r:q:i8 @@ -13479,6 +13600,7 @@ ATTRIBUTES: NOTSX CPL : 3 CATEGORY : MMX EXTENSION : SSSE3 +ISA_SET : SSSE3MMX PATTERN : 0x0F 0x38 0x0B no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=MMX_R():rw:q MEM0:r:q PATTERN : 0x0F 0x38 0x0B no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] @@ -13503,6 +13625,7 @@ ATTRIBUTES: NOTSX CPL : 3 CATEGORY : MMX EXTENSION : SSSE3 +ISA_SET : SSSE3MMX PATTERN : 0x0F 0x38 0x00 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=MMX_R():rw:q MEM0:r:q PATTERN : 0x0F 0x38 0x00 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] @@ -13527,6 +13650,7 @@ ATTRIBUTES: NOTSX CPL : 3 CATEGORY : MMX EXTENSION : SSSE3 +ISA_SET : SSSE3MMX PATTERN : 0x0F 0x38 0x08 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=MMX_R():rw:q MEM0:r:q PATTERN : 0x0F 0x38 0x08 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] @@ -13551,6 +13675,7 @@ ATTRIBUTES: NOTSX CPL : 3 CATEGORY : MMX EXTENSION : SSSE3 +ISA_SET : SSSE3MMX PATTERN : 0x0F 0x38 0x09 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=MMX_R():rw:q MEM0:r:q PATTERN : 0x0F 0x38 0x09 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] @@ -13574,6 +13699,7 @@ ATTRIBUTES: NOTSX CPL : 3 CATEGORY : MMX EXTENSION : SSSE3 +ISA_SET : SSSE3MMX EXCEPTIONS: mmx-mem PATTERN : 0x0F 0x38 0x0A no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=MMX_R():rw:q MEM0:r:q @@ -13599,6 +13725,7 @@ ATTRIBUTES: NOTSX CPL : 3 CATEGORY : MMX EXTENSION : SSSE3 +ISA_SET : SSSE3MMX PATTERN : 0x0F 0x3A 0x0F no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() OPERANDS : REG0=MMX_R():rw:q MEM0:r:q IMM0:r:b PATTERN : 0x0F 0x3A 0x0F no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() @@ -13623,6 +13750,7 @@ ATTRIBUTES: NOTSX CPL : 3 CATEGORY : MMX EXTENSION : SSSE3 +ISA_SET : SSSE3MMX PATTERN : 0x0F 0x38 0x1C no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=MMX_R():w:q MEM0:r:q PATTERN : 0x0F 0x38 0x1C no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] @@ -13647,6 +13775,7 @@ ATTRIBUTES: NOTSX CPL : 3 CATEGORY : MMX EXTENSION : SSSE3 +ISA_SET : SSSE3MMX PATTERN : 0x0F 0x38 0x1D no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=MMX_R():w:q MEM0:r:q PATTERN : 0x0F 0x38 0x1D no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] @@ -13671,6 +13800,7 @@ CPL : 3 ATTRIBUTES : simd_scalar NOTSX CATEGORY : MMX EXTENSION : SSSE3 +ISA_SET : SSSE3MMX PATTERN : 0x0F 0x38 0x1E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=MMX_R():w:q MEM0:r:q } @@ -13680,6 +13810,7 @@ CPL : 3 ATTRIBUTES : simd_scalar NOTSX CATEGORY : MMX EXTENSION : SSSE3 +ISA_SET : SSSE3MMX PATTERN : 0x0F 0x38 0x1E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=MMX_R():w:q REG1=MMX_B():r:q } @@ -13868,7 +13999,7 @@ CPL : 3 CATEGORY : SSE EXTENSION : SSE4 EXCEPTIONS: SSE_TYPE_1 -ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX +ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX NONTEMPORAL PATTERN : 0x0F 0x38 0x2A osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq } @@ -14433,16 +14564,26 @@ EXCEPTIONS: SSE_TYPE_4 ATTRIBUTES: FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] -PATTERN : 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +PATTERN : 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() EOSZ=2 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_EDX:r:SUPP REG3=XED_REG_ECX:w:SUPP -PATTERN : 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +PATTERN : 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() EOSZ=2 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_ECX:w:SUPP +} +{ +ICLASS : PCMPESTRI +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +ISA_SET : SSE42 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES: +FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] -PATTERN : 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +PATTERN : 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() EOSZ=3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_RAX:r:SUPP REG2=XED_REG_RDX:r:SUPP REG3=XED_REG_RCX:w:SUPP -PATTERN : 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +PATTERN : 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() EOSZ=3 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_RAX:r:SUPP REG3=XED_REG_RDX:r:SUPP REG4=XED_REG_RCX:w:SUPP } { @@ -14455,16 +14596,26 @@ EXCEPTIONS: SSE_TYPE_4 ATTRIBUTES: FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] -PATTERN : 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +PATTERN : 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() EOSZ=2 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_ECX:w:SUPP -PATTERN : 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +PATTERN : 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() EOSZ=2 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_ECX:w:SUPP +} +{ +ICLASS : PCMPISTRI +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +ISA_SET : SSE42 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES: +FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] -PATTERN : 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +PATTERN : 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() EOSZ=3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_RCX:w:SUPP -PATTERN : 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +PATTERN : 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() EOSZ=3 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_RCX:w:SUPP } @@ -14478,16 +14629,26 @@ EXCEPTIONS: SSE_TYPE_4 ATTRIBUTES: FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] -PATTERN : 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +PATTERN : 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() EOSZ=2 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_EDX:r:SUPP REG3=XED_REG_XMM0:w:dq:SUPP -PATTERN : 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +PATTERN : 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() EOSZ=2 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_XMM0:w:dq:SUPP +} +{ +ICLASS : PCMPESTRM +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +ISA_SET : SSE42 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES: +FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] -PATTERN : 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +PATTERN : 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() EOSZ=3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_RAX:r:SUPP REG2=XED_REG_RDX:r:SUPP REG3=XED_REG_XMM0:w:dq:SUPP -PATTERN : 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +PATTERN : 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() EOSZ=3 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_RAX:r:SUPP REG3=XED_REG_RDX:r:SUPP REG4=XED_REG_XMM0:w:dq:SUPP } @@ -14532,18 +14693,18 @@ ICLASS : XSAVE CPL : 3 CATEGORY : XSAVE EXTENSION : XSAVE -COMMENT : variable length store +COMMENT : Variable length store and conditional reg read. Reads/writes XSTATE_BV from header. ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b100] RM[nnn] no_refining_prefix norexw_prefix MODRM() #FIXME 2007-06-25 need a meaningful width code for XSAVE/XRSTOR -OPERANDS : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP +OPERANDS : MEM0:rw:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP } { ICLASS : XRSTOR CPL : 3 CATEGORY : XSAVE EXTENSION : XSAVE -COMMENT : variable length load and conditianal reg write +COMMENT : variable length load and conditional reg write ATTRIBUTES : xmm_state_cw REQUIRES_ALIGNMENT x87_mmx_state_cw NOTSX SPECIAL_AGEN_REQUIRED PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b101] RM[nnn] no_refining_prefix norexw_prefix MODRM() #FIXME 2007-06-25 need a meaningful width code for XSAVE/XRSTOR @@ -14556,11 +14717,11 @@ ICLASS : XSAVE64 CPL : 3 CATEGORY : XSAVE EXTENSION : XSAVE -COMMENT : variable length store +COMMENT : Variable length store and conditional reg read. Reads/writes XSTATE_BV from header. ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b100] RM[nnn] no_refining_prefix rexw_prefix MODRM() #FIXME 2007-06-25 need a meaningful width code for XSAVE/XRSTOR -OPERANDS : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP +OPERANDS : MEM0:rw:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP } { @@ -14568,7 +14729,7 @@ ICLASS : XRSTOR64 CPL : 3 CATEGORY : XSAVE EXTENSION : XSAVE -COMMENT : variable length load and conditianal reg write +COMMENT : variable length load and conditional reg write ATTRIBUTES : xmm_state_cw REQUIRES_ALIGNMENT x87_mmx_state_cw NOTSX SPECIAL_AGEN_REQUIRED PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b101] RM[nnn] no_refining_prefix rexw_prefix MODRM() #FIXME 2007-06-25 need a meaningful width code for XSAVE/XRSTOR @@ -14603,7 +14764,7 @@ CPL : 3 CATEGORY : SYSTEM ATTRIBUTES: PROTECTED_MODE NOTSX EXTENSION : SMX -PATTERN : 0x0F 0x37 +PATTERN : 0x0F 0x37 no_refining_prefix OPERANDS : REG0=XED_REG_EAX:rcw:SUPP REG1=XED_REG_EBX:r:SUPP } @@ -14703,9 +14864,10 @@ CPL : 0 CATEGORY : VTX EXTENSION : VTX ATTRIBUTES : RING0 NOTSX +FLAGS : MUST [ cf-mod zf-mod sf-0 of-0 af-0 pf-0 ] PATTERN : 0x0F 0x38 0x80 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode64 MODRM() CR_WIDTH() OPERANDS : REG0=GPR64_R():r MEM0:r:dq -PATTERN : 0x0F 0x38 0x80 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode32 MODRM() CR_WIDTH() +PATTERN : 0x0F 0x38 0x80 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() not64 MODRM() CR_WIDTH() OPERANDS : REG0=GPR32_R():r MEM0:r:dq COMMENT : SDM rev 27 } @@ -14715,9 +14877,10 @@ CPL : 0 CATEGORY : VTX EXTENSION : VTX ATTRIBUTES : RING0 NOTSX +FLAGS : MUST [ cf-mod zf-mod sf-0 of-0 af-0 pf-0 ] PATTERN : 0x0F 0x38 0x81 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode64 MODRM() CR_WIDTH() OPERANDS : REG0=GPR64_R():r MEM0:r:dq -PATTERN : 0x0F 0x38 0x81 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode32 MODRM() CR_WIDTH() +PATTERN : 0x0F 0x38 0x81 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() not64 MODRM() CR_WIDTH() OPERANDS : REG0=GPR32_R():r MEM0:r:dq COMMENT : SDM rev 27 } @@ -14731,7 +14894,7 @@ COMMENT : SDM rev 27 #BEGIN_LEGAL # -#Copyright (c) 2016 Intel Corporation +#Copyright (c) 2018 Intel Corporation # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -14840,7 +15003,7 @@ IFORM : PREFETCH_RESERVED_0F0Dr7 #BEGIN_LEGAL # -#Copyright (c) 2016 Intel Corporation +#Copyright (c) 2018 Intel Corporation # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -14932,11 +15095,179 @@ OPERANDS : } +###FILE: ../xed/datafiles/via-padlock-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2018 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +{ +ICLASS : XSTORE +CPL : 3 +CATEGORY : VIA_PADLOCK +EXTENSION : VIA_PADLOCK_RNG +ISA_SET : VIA_PADLOCK_RNG +PATTERN : 0x0F 0xA7 MOD[0b11] REG[0b000] RM[0b000] not_refining +OPERANDS : MEM0:w:SUPP:b REG0=OrCX():r:SUPP REG1=OrDX():rw:SUPP REG2=OrAX():w:SUPP BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP +} + + +{ +ICLASS : REP_XSTORE +DISASM : xstore +CPL : 3 +CATEGORY : VIA_PADLOCK +EXTENSION : VIA_PADLOCK_RNG +ISA_SET : VIA_PADLOCK_RNG +ATTRIBUTES : REP FIXED_BASE0 BYTEOP +PATTERN : 0x0F 0xA7 MOD[0b11] REG[0b000] RM[0b000] f3_refining_prefix +OPERANDS : MEM0:w:SUPP:b REG0=OrCX():rw:SUPP REG1=OrDX():rw:SUPP REG2=OrAX():w:SUPP BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP +} + + +{ +ICLASS : REP_XCRYPTECB +DISASM : xcryptecb +CPL : 3 +CATEGORY : VIA_PADLOCK +EXTENSION : VIA_PADLOCK_AES +ISA_SET : VIA_PADLOCK_AES +ATTRIBUTES : REP FIXED_BASE0 BYTEOP +PATTERN : 0x0F 0xA7 MOD[0b11] REG[0b001] RM[0b000] f3_refining_prefix +OPERANDS : MEM0:w:SUPP:b REG0=OrCX():rw:SUPP REG1=OrDX():r:SUPP REG2=OrBX():r:SUPP BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:b BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP +} + +{ +ICLASS : REP_XCRYPTCBC +DISASM : xcryptcbc +CPL : 3 +CATEGORY : VIA_PADLOCK +EXTENSION : VIA_PADLOCK_AES +ISA_SET : VIA_PADLOCK_AES +ATTRIBUTES : REP FIXED_BASE0 BYTEOP +PATTERN : 0x0F 0xA7 MOD[0b11] REG[0b010] RM[0b000] f3_refining_prefix +COMMENT : rAX contains a pointer to memory using ES segment. +OPERANDS : MEM0:w:SUPP:b REG0=OrCX():rw:SUPP REG1=OrDX():r:SUPP REG2=OrBX():r:SUPP REG3=ArAX():r:SUPP BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:b BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP +} + + +{ +ICLASS : REP_XCRYPTCTR +DISASM : xcryptctr +CPL : 3 +CATEGORY : VIA_PADLOCK +EXTENSION : VIA_PADLOCK_AES +ISA_SET : VIA_PADLOCK_AES +ATTRIBUTES : REP FIXED_BASE0 BYTEOP +PATTERN : 0x0F 0xA7 MOD[0b11] REG[0b011] RM[0b000] f3_refining_prefix +COMMENT : rAX contains a pointer to memory using ES segment. +OPERANDS : MEM0:w:SUPP:b REG0=OrCX():rw:SUPP REG1=OrDX():r:SUPP REG2=OrBX():r:SUPP REG3=ArAX():r:SUPP BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:b BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP +} +{ +ICLASS : REP_XCRYPTCFB +DISASM : xcryptcfb +CPL : 3 +CATEGORY : VIA_PADLOCK +EXTENSION : VIA_PADLOCK_AES +ISA_SET : VIA_PADLOCK_AES +ATTRIBUTES : REP FIXED_BASE0 BYTEOP +PATTERN : 0x0F 0xA7 MOD[0b11] REG[0b100] RM[0b000] f3_refining_prefix +COMMENT : rAX contains a pointer to memory using ES segment. +OPERANDS : MEM0:w:SUPP:b REG0=OrCX():rw:SUPP REG1=OrDX():r:SUPP REG2=OrBX():r:SUPP REG3=ArAX():r:SUPP BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:b BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP +} +{ +ICLASS : REP_XCRYPTOFB +DISASM : xcryptofb +CPL : 3 +CATEGORY : VIA_PADLOCK +EXTENSION : VIA_PADLOCK_AES +ISA_SET : VIA_PADLOCK_AES +ATTRIBUTES : REP FIXED_BASE0 BYTEOP +PATTERN : 0x0F 0xA7 MOD[0b11] REG[0b101] RM[0b000] f3_refining_prefix +COMMENT : rAX contains a pointer to memory using ES segment. +OPERANDS : MEM0:w:SUPP:b REG0=OrCX():rw:SUPP REG1=OrDX():r:SUPP REG2=OrBX():r:SUPP REG3=ArAX():r:SUPP BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:b BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP +} + + + +{ +ICLASS : REP_XSHA1 +DISASM : xsha1 +CPL : 3 +CATEGORY : VIA_PADLOCK +EXTENSION : VIA_PADLOCK_SHA +ISA_SET : VIA_PADLOCK_SHA +ATTRIBUTES : REP FIXED_BASE0 BYTEOP +PATTERN : 0x0F 0xA6 MOD[0b11] REG[0b001] RM[0b000] f3_refining_prefix +OPERANDS : REG0=ArAX():rcw:SUPP REG1=OrCX():rcw:SUPP MEM0:w:SUPP:b BASE0=ArSI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:r:SUPP:b BASE1=ArDI():r:SUPP SEG1=FINAL_ESEG1():r:SUPP +} + + + +{ +ICLASS : REP_XSHA256 +DISASM : xsha256 +CPL : 3 +CATEGORY : VIA_PADLOCK +EXTENSION : VIA_PADLOCK_SHA +ISA_SET : VIA_PADLOCK_SHA +ATTRIBUTES : REP FIXED_BASE0 BYTEOP +PATTERN : 0x0F 0xA6 MOD[0b11] REG[0b010] RM[0b000] f3_refining_prefix +OPERANDS : REG0=ArAX():rcw:SUPP REG1=OrCX():rcw:SUPP MEM0:w:SUPP:b BASE0=ArSI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:r:SUPP:b BASE1=ArDI():r:SUPP SEG1=FINAL_ESEG1():r:SUPP +} + + + +{ +ICLASS : REP_MONTMUL +DISASM : montmul +CPL : 3 +CATEGORY : VIA_PADLOCK +EXTENSION : VIA_PADLOCK_MONTMUL +ISA_SET : VIA_PADLOCK_MONTMUL +ATTRIBUTES : REP FIXED_BASE0 +COMMENT : EAX output value undefined, so list as write. + +PATTERN : 0x0F 0xA6 MOD[0b11] REG[0b000] RM[0b000] f3_refining_prefix eamode16 +OPERANDS : REG0=XED_REG_EAX:rw:SUPP \ + REG1=XED_REG_ECX:rw:SUPP \ + REG2=XED_REG_EDX:w:SUPP \ + MEM0:rw:SUPP:pmmsz16 \ + BASE0=ArSI():r:SUPP \ + SEG0=FINAL_ESEG():r:SUPP + +PATTERN : 0x0F 0xA6 MOD[0b11] REG[0b000] RM[0b000] f3_refining_prefix eamode32 +OPERANDS : REG0=XED_REG_EAX:rw:SUPP \ + REG1=XED_REG_ECX:rw:SUPP \ + REG2=XED_REG_EDX:w:SUPP \ + MEM0:rw:SUPP:pmmsz32 \ + BASE0=ArSI():r:SUPP \ + SEG0=FINAL_ESEG():r:SUPP +} + + + + + ###FILE: ../xed/datafiles/xed-amd-3dnow.txt #BEGIN_LEGAL # -#Copyright (c) 2016 Intel Corporation +#Copyright (c) 2018 Intel Corporation # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -14958,7 +15289,7 @@ ICLASS : FEMMS CPL : 3 CATEGORY : MMX EXTENSION : 3DNOW -ATTRIBUTES : x87_mmx_state_w +ATTRIBUTES : x87_mmx_state_w AMDONLY PATTERN : 0x0F 0x0E OPERANDS : } @@ -14967,6 +15298,7 @@ ICLASS : PI2FW CPL : 3 CATEGORY : 3DNOW EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x0C OPERANDS : REG0=MMX_R():rw:q MEM0:r:q } @@ -14975,6 +15307,7 @@ ICLASS : PI2FW CPL : 3 CATEGORY : 3DNOW EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x0C OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q } @@ -14983,6 +15316,7 @@ ICLASS : PI2FD CPL : 3 CATEGORY : 3DNOW EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x0D OPERANDS : REG0=MMX_R():rw:q MEM0:r:q } @@ -14991,6 +15325,7 @@ ICLASS : PI2FD CPL : 3 CATEGORY : 3DNOW EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x0D OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q } @@ -14999,6 +15334,7 @@ ICLASS : PF2IW CPL : 3 CATEGORY : 3DNOW EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x1C OPERANDS : REG0=MMX_R():rw:q MEM0:r:q } @@ -15007,6 +15343,7 @@ ICLASS : PF2IW CPL : 3 CATEGORY : 3DNOW EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x1C OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q } @@ -15015,6 +15352,7 @@ ICLASS : PF2ID CPL : 3 CATEGORY : 3DNOW EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x1D OPERANDS : REG0=MMX_R():rw:q MEM0:r:q } @@ -15023,6 +15361,7 @@ ICLASS : PF2ID CPL : 3 CATEGORY : 3DNOW EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x1D OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q } @@ -15031,6 +15370,7 @@ ICLASS : PFNACC CPL : 3 CATEGORY : 3DNOW EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x8A OPERANDS : REG0=MMX_R():rw:q MEM0:r:q } @@ -15039,6 +15379,7 @@ ICLASS : PFNACC CPL : 3 CATEGORY : 3DNOW EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x8A OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q } @@ -15047,6 +15388,7 @@ ICLASS : PFPNACC CPL : 3 CATEGORY : 3DNOW EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x8E OPERANDS : REG0=MMX_R():rw:q MEM0:r:q } @@ -15055,6 +15397,7 @@ ICLASS : PFPNACC CPL : 3 CATEGORY : 3DNOW EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x8E OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q } @@ -15063,6 +15406,7 @@ ICLASS : PFCMPGE CPL : 3 CATEGORY : 3DNOW EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x90 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q } @@ -15071,6 +15415,7 @@ ICLASS : PFCMPGE CPL : 3 CATEGORY : 3DNOW EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x90 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q } @@ -15079,6 +15424,7 @@ ICLASS : PFMIN CPL : 3 CATEGORY : 3DNOW EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x94 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q } @@ -15087,6 +15433,7 @@ ICLASS : PFMIN CPL : 3 CATEGORY : 3DNOW EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x94 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q } @@ -15095,6 +15442,7 @@ ICLASS : PFRCP CPL : 3 CATEGORY : 3DNOW EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x96 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q } @@ -15103,22 +15451,25 @@ ICLASS : PFRCP CPL : 3 CATEGORY : 3DNOW EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x96 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q } { -ICLASS : PFSQRT +ICLASS : PFRSQRT CPL : 3 CATEGORY : 3DNOW EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x97 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q } { -ICLASS : PFSQRT +ICLASS : PFRSQRT CPL : 3 CATEGORY : 3DNOW EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x97 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q } @@ -15127,6 +15478,7 @@ ICLASS : PFSUB CPL : 3 CATEGORY : 3DNOW EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x9A OPERANDS : REG0=MMX_R():rw:q MEM0:r:q } @@ -15135,6 +15487,7 @@ ICLASS : PFSUB CPL : 3 CATEGORY : 3DNOW EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x9A OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q } @@ -15143,6 +15496,7 @@ ICLASS : PFADD CPL : 3 CATEGORY : 3DNOW EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x9E OPERANDS : REG0=MMX_R():rw:q MEM0:r:q } @@ -15151,6 +15505,7 @@ ICLASS : PFADD CPL : 3 CATEGORY : 3DNOW EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x9E OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q } @@ -15159,6 +15514,7 @@ ICLASS : PFCMPGT CPL : 3 CATEGORY : 3DNOW EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xA0 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q } @@ -15167,6 +15523,7 @@ ICLASS : PFCMPGT CPL : 3 CATEGORY : 3DNOW EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xA0 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q } @@ -15175,6 +15532,7 @@ ICLASS : PFMAX CPL : 3 CATEGORY : 3DNOW EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xA4 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q } @@ -15183,22 +15541,25 @@ ICLASS : PFMAX CPL : 3 CATEGORY : 3DNOW EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xA4 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q } { -ICLASS : PFCPIT1 +ICLASS : PFRCPIT1 CPL : 3 CATEGORY : 3DNOW EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xA6 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q } { -ICLASS : PFCPIT1 +ICLASS : PFRCPIT1 CPL : 3 CATEGORY : 3DNOW EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xA6 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q } @@ -15207,6 +15568,7 @@ ICLASS : PFRSQIT1 CPL : 3 CATEGORY : 3DNOW EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xA7 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q } @@ -15215,6 +15577,7 @@ ICLASS : PFRSQIT1 CPL : 3 CATEGORY : 3DNOW EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xA7 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q } @@ -15223,6 +15586,7 @@ ICLASS : PFSUBR CPL : 3 CATEGORY : 3DNOW EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xAA OPERANDS : REG0=MMX_R():rw:q MEM0:r:q } @@ -15231,6 +15595,7 @@ ICLASS : PFSUBR CPL : 3 CATEGORY : 3DNOW EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xAA OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q } @@ -15239,6 +15604,7 @@ ICLASS : PFACC CPL : 3 CATEGORY : 3DNOW EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xAE OPERANDS : REG0=MMX_R():rw:q MEM0:r:q } @@ -15247,6 +15613,7 @@ ICLASS : PFACC CPL : 3 CATEGORY : 3DNOW EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xAE OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q } @@ -15255,6 +15622,7 @@ ICLASS : PFCMPEQ CPL : 3 CATEGORY : 3DNOW EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xB0 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q } @@ -15263,6 +15631,7 @@ ICLASS : PFCMPEQ CPL : 3 CATEGORY : 3DNOW EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xB0 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q } @@ -15271,6 +15640,7 @@ ICLASS : PFMUL CPL : 3 CATEGORY : 3DNOW EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xB4 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q } @@ -15279,6 +15649,7 @@ ICLASS : PFMUL CPL : 3 CATEGORY : 3DNOW EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xB4 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q } @@ -15287,6 +15658,7 @@ ICLASS : PFRCPIT2 CPL : 3 CATEGORY : 3DNOW EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xB6 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q } @@ -15295,6 +15667,7 @@ ICLASS : PFRCPIT2 CPL : 3 CATEGORY : 3DNOW EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xB6 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q } @@ -15303,6 +15676,7 @@ ICLASS : PMULHRW CPL : 3 CATEGORY : 3DNOW EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xB7 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q } @@ -15311,6 +15685,7 @@ ICLASS : PMULHRW CPL : 3 CATEGORY : 3DNOW EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xB7 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q } @@ -15319,6 +15694,7 @@ ICLASS : PSWAPD CPL : 3 CATEGORY : 3DNOW EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xBB OPERANDS : REG0=MMX_R():rw:q MEM0:r:q } @@ -15327,6 +15703,7 @@ ICLASS : PSWAPD CPL : 3 CATEGORY : 3DNOW EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xBB OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q } @@ -15335,6 +15712,7 @@ ICLASS : PAVGUSB CPL : 3 CATEGORY : 3DNOW EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xBF OPERANDS : REG0=MMX_R():rw:q MEM0:r:q } @@ -15343,6 +15721,7 @@ ICLASS : PAVGUSB CPL : 3 CATEGORY : 3DNOW EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xBF OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q } @@ -15352,7 +15731,7 @@ OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q #BEGIN_LEGAL # -#Copyright (c) 2016 Intel Corporation +#Copyright (c) 2018 Intel Corporation # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -15379,6 +15758,7 @@ CPL : 3 CATEGORY : SYSCALL EXTENSION : BASE ISA_SET : AMD +ATTRIBUTES : AMDONLY FLAGS : MUST [ id-mod vip-mod vif-mod ac-mod vm-0 rf-0 nt-mod iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ] PATTERN : 0x0F 0x05 not64 IGNORE66() OPERANDS : REG0=rIP():w:SUPP @@ -15390,9 +15770,10 @@ ICLASS : SYSRET_AMD DISASM : sysret CPL : 0 CATEGORY : SYSRET -ATTRIBUTES: PROTECTED_MODE RING0 +ATTRIBUTES: PROTECTED_MODE RING0 AMDONLY EXTENSION : BASE ISA_SET : AMD + FLAGS : MUST [ id-mod vip-mod vif-mod ac-mod rf-0 nt-mod iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ] PATTERN : 0x0F 0x07 not64 OPERANDS : REG0=XED_REG_EIP:w:SUPP @@ -15403,7 +15784,7 @@ OPERANDS : REG0=XED_REG_EIP:w:SUPP #BEGIN_LEGAL # -#Copyright (c) 2016 Intel Corporation +#Copyright (c) 2018 Intel Corporation # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -15424,15 +15805,16 @@ ICLASS : VMRUN CPL : 3 CATEGORY : SYSTEM EXTENSION : SVM -ATTRIBUTES: PROTECTED_MODE +ATTRIBUTES: PROTECTED_MODE AMDONLY PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000] -OPERANDS : REG0=OrAX():r:IMPL +OPERANDS : REG0=ArAX():r:IMPL } { ICLASS : VMMCALL CPL : 3 CATEGORY : SYSTEM EXTENSION : SVM +ATTRIBUTES : AMDONLY PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001] OPERANDS : } @@ -15441,16 +15823,16 @@ ICLASS : VMLOAD CPL : 3 CATEGORY : SYSTEM EXTENSION : SVM -ATTRIBUTES: PROTECTED_MODE +ATTRIBUTES: PROTECTED_MODE AMDONLY PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010] -OPERANDS : REG0=OrAX():r:IMPL +OPERANDS : REG0=ArAX():r:IMPL } { ICLASS : VMSAVE CPL : 3 CATEGORY : SYSTEM EXTENSION : SVM -ATTRIBUTES: PROTECTED_MODE +ATTRIBUTES: PROTECTED_MODE AMDONLY PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011] OPERANDS : } @@ -15459,7 +15841,7 @@ ICLASS : STGI CPL : 3 CATEGORY : SYSTEM EXTENSION : SVM -ATTRIBUTES: PROTECTED_MODE +ATTRIBUTES: PROTECTED_MODE AMDONLY PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100] OPERANDS : } @@ -15468,7 +15850,7 @@ ICLASS : CLGI CPL : 3 CATEGORY : SYSTEM EXTENSION : SVM -ATTRIBUTES: PROTECTED_MODE +ATTRIBUTES: PROTECTED_MODE AMDONLY PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101] OPERANDS : } @@ -15477,7 +15859,7 @@ ICLASS : SKINIT CPL : 3 CATEGORY : SYSTEM EXTENSION : SVM -ATTRIBUTES: PROTECTED_MODE +ATTRIBUTES: PROTECTED_MODE AMDONLY PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110] OPERANDS : REG0=XED_REG_EAX:r:IMPL } @@ -15486,9 +15868,9 @@ ICLASS : INVLPGA CPL : 0 CATEGORY : SYSTEM EXTENSION : SVM -ATTRIBUTES: PROTECTED_MODE +ATTRIBUTES: PROTECTED_MODE AMDONLY PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111] -OPERANDS : REG0=OrAX():r:IMPL REG1=XED_REG_ECX:r:IMPL +OPERANDS : REG0=ArAX():r:IMPL REG1=XED_REG_ECX:r:IMPL } @@ -15496,7 +15878,7 @@ OPERANDS : REG0=OrAX():r:IMPL REG1=XED_REG_ECX:r:IMPL #BEGIN_LEGAL # -#Copyright (c) 2016 Intel Corporation +#Copyright (c) 2018 Intel Corporation # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -15519,9 +15901,9 @@ ICLASS : EXTRQ CPL : 3 CATEGORY : BITBYTE EXTENSION : SSE4a -ATTRIBUTES : ATT_OPERAND_ORDER_EXCEPTION +ATTRIBUTES : ATT_OPERAND_ORDER_EXCEPTION AMDONLY PATTERN : 0x0F 0x78 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM8() UIMM8_1() -OPERANDS : REG0=XMM_R():w:q IMM0:r:b IMM1:r:b +OPERANDS : REG0=XMM_B():w:q IMM0:r:b IMM1:r:b PATTERN : 0x0F 0x79 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=XMM_R():w:q REG1=XMM_B():r:dq } @@ -15534,7 +15916,7 @@ ICLASS : INSERTQ CPL : 3 CATEGORY : BITBYTE EXTENSION : SSE4a -ATTRIBUTES : ATT_OPERAND_ORDER_EXCEPTION +ATTRIBUTES : ATT_OPERAND_ORDER_EXCEPTION AMDONLY PATTERN : 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1() OPERANDS : REG0=XMM_R():w:q REG1=XMM_B():r:q IMM0:r:b IMM1:r:b PATTERN : 0x0F 0x79 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] @@ -15550,6 +15932,7 @@ ICLASS : MOVNTSD CPL : 3 CATEGORY : DATAXFER EXTENSION : SSE4a +ATTRIBUTES: NONTEMPORAL AMDONLY PATTERN : 0x0F 0x2B f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : MEM0:w:q REG0=XMM_R():r:q } @@ -15558,6 +15941,7 @@ ICLASS : MOVNTSS CPL : 3 CATEGORY : DATAXFER EXTENSION : SSE4a +ATTRIBUTES: NONTEMPORAL AMDONLY PATTERN : 0x0F 0x2B f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : MEM0:w:d REG0=XMM_R():r:d } @@ -15603,7 +15987,7 @@ OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r #BEGIN_LEGAL # -#Copyright (c) 2016 Intel Corporation +#Copyright (c) 2018 Intel Corporation # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -15624,17 +16008,71 @@ ICLASS : CLZERO CPL : 3 CATEGORY : CLZERO EXTENSION : CLZERO +ATTRIBUTES : AMDONLY + PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100] -OPERANDS : REG0=OrAX():r:IMPL +OPERANDS : REG0=ArAX():r:SUPP COMMENT : AMD "Zen" ~2016 (expected) CPU } +###FILE: ../xed/datafiles/xed-amd-monitorx.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2018 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +{ +ICLASS : MONITORX +CPL : 3 +CATEGORY : MISC +EXTENSION : MONITORX +ISA_SET : MONITORX +ATTRIBUTES: AMDONLY + +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b010] no_refining_prefix not64 eamode32 +OPERANDS : REG0=XED_REG_EAX:r:SUPP REG1=XED_REG_ECX:r:SUPP REG2=XED_REG_EDX:r:SUPP + +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b010] no_refining_prefix not64 eamode16 +OPERANDS : REG0=XED_REG_AX:r:SUPP REG1=XED_REG_ECX:r:SUPP REG2=XED_REG_EDX:r:SUPP + +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b010] no_refining_prefix mode64 eamode64 +OPERANDS : REG0=XED_REG_RAX:r:SUPP REG1=XED_REG_ECX:r:SUPP REG2=XED_REG_EDX:r:SUPP + +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b010] no_refining_prefix mode64 eamode32 +OPERANDS : REG0=XED_REG_EAX:r:SUPP REG1=XED_REG_ECX:r:SUPP REG2=XED_REG_EDX:r:SUPP +} +{ +ICLASS : MWAITX +CPL : 3 +CATEGORY : MISC +EXTENSION : MONITORX +ISA_SET : MONITORX +ATTRIBUTES: AMDONLY +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b011] no_refining_prefix +OPERANDS : REG0=XED_REG_EAX:rw:SUPP REG1=XED_REG_ECX:r:SUPP +} + + ###FILE: ../xed/datafiles/amdxop/amd-xop-isa.txt #BEGIN_LEGAL # -#Copyright (c) 2016 Intel Corporation +#Copyright (c) 2018 Intel Corporation # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -15657,6 +16095,7 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY PATTERN: XOPV 0x85 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i16 @@ -15671,6 +16110,7 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY PATTERN: XOPV 0x86 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i32 @@ -15685,6 +16125,7 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY PATTERN: XOPV 0x87 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 REG2=XMM_SE():r:dq:i64 @@ -15699,6 +16140,7 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY PATTERN: XOPV 0x95 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i16 @@ -15713,6 +16155,7 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY PATTERN: XOPV 0x96 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i32 @@ -15727,6 +16170,7 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY PATTERN: XOPV 0x97 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 REG2=XMM_SE():r:dq:i64 @@ -15741,6 +16185,7 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY PATTERN: XOPV 0xA2 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() OPERANDS: REG0=XMM_R():w:dq:i1 REG1=XMM_N():r:dq:i1 MEM0:r:dq:i1 REG2=XMM_SE():r:dq:i1 @@ -15773,6 +16218,7 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY PATTERN: XOPV 0xA3 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i16 @@ -15793,6 +16239,7 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY PATTERN: XOPV 0xA6 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i32 @@ -15807,6 +16254,7 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY PATTERN: XOPV 0xB6 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i32 @@ -15821,6 +16269,7 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY PATTERN: XOPV 0xC0 VNP W0 VL128 NOVSR XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() OPERANDS: REG0=XMM_R():w:dq:u8 MEM0:r:dq:u8 IMM0:r:b:u8 @@ -15835,12 +16284,13 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY PATTERN: XOPV 0xC1 VNP W0 VL128 NOVSR XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() -OPERANDS: REG0=XMM_R():w:dq:u16 MEM0:r:dq:u16 IMM0:r:b:u16 +OPERANDS: REG0=XMM_R():w:dq:u16 MEM0:r:dq:u16 IMM0:r:b:u8 PATTERN: XOPV 0xC1 VNP W0 VL128 NOVSR XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() -OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:dq:u16 IMM0:r:b:u16 +OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:dq:u16 IMM0:r:b:u8 } { @@ -15849,12 +16299,13 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY PATTERN: XOPV 0xC2 VNP W0 VL128 NOVSR XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() -OPERANDS: REG0=XMM_R():w:dq:u32 MEM0:r:dq:u32 IMM0:r:b:u32 +OPERANDS: REG0=XMM_R():w:dq:u32 MEM0:r:dq:u32 IMM0:r:b:u8 PATTERN: XOPV 0xC2 VNP W0 VL128 NOVSR XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() -OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:dq:u32 IMM0:r:b:u32 +OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:dq:u32 IMM0:r:b:u8 } { @@ -15863,12 +16314,13 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY PATTERN: XOPV 0xC3 VNP W0 VL128 NOVSR XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() -OPERANDS: REG0=XMM_R():w:dq:u64 MEM0:r:dq:u64 IMM0:r:b:u64 +OPERANDS: REG0=XMM_R():w:dq:u64 MEM0:r:dq:u64 IMM0:r:b:u8 PATTERN: XOPV 0xC3 VNP W0 VL128 NOVSR XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() -OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:dq:u64 IMM0:r:b:u64 +OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:dq:u64 IMM0:r:b:u8 } { @@ -15877,6 +16329,7 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY PATTERN: XOPV 0x8E VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 REG2=XMM_SE():r:dq:i32 @@ -15891,6 +16344,7 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY PATTERN: XOPV 0x8F VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 REG2=XMM_SE():r:dq:i64 @@ -15905,6 +16359,7 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY PATTERN: XOPV 0x9E VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 REG2=XMM_SE():r:dq:i32 @@ -15919,6 +16374,7 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY PATTERN: XOPV 0x9F VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 REG2=XMM_SE():r:dq:i64 @@ -15933,12 +16389,13 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY PATTERN: XOPV 0xCC VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() -OPERANDS: REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 IMM0:r:b:i8 +OPERANDS: REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 IMM0:r:b:u8 PATTERN: XOPV 0xCC VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() -OPERANDS: REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 IMM0:r:b:i8 +OPERANDS: REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 IMM0:r:b:u8 } { @@ -15947,12 +16404,13 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY PATTERN: XOPV 0xCD VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() -OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 IMM0:r:b:i16 +OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 IMM0:r:b:u8 PATTERN: XOPV 0xCD VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() -OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 IMM0:r:b:i16 +OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 IMM0:r:b:u8 } { @@ -15961,12 +16419,13 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY PATTERN: XOPV 0xCE VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() -OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 IMM0:r:b:i32 +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 IMM0:r:b:u8 PATTERN: XOPV 0xCE VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() -OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 IMM0:r:b:i32 +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 IMM0:r:b:u8 } { @@ -15975,12 +16434,13 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY PATTERN: XOPV 0xCF VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() -OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 MEM0:r:dq:i64 IMM0:r:b:i64 +OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 MEM0:r:dq:i64 IMM0:r:b:u8 PATTERN: XOPV 0xCF VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() -OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 REG2=XMM_B():r:dq:i64 IMM0:r:b:i64 +OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 REG2=XMM_B():r:dq:i64 IMM0:r:b:u8 } { @@ -15989,6 +16449,7 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY PATTERN: XOPV 0xEC VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 IMM0:r:b:u8 @@ -16003,12 +16464,13 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY PATTERN: XOPV 0xED VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() -OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 IMM0:r:b:u16 +OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 IMM0:r:b:u8 PATTERN: XOPV 0xED VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() -OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 IMM0:r:b:u16 +OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 IMM0:r:b:u8 } { @@ -16017,12 +16479,13 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY PATTERN: XOPV 0xEE VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() -OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 IMM0:r:b:u32 +OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 IMM0:r:b:u8 PATTERN: XOPV 0xEE VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() -OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 IMM0:r:b:u32 +OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 IMM0:r:b:u8 } { @@ -16031,12 +16494,13 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY PATTERN: XOPV 0xEF VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() -OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 IMM0:r:b:u64 +OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 IMM0:r:b:u8 PATTERN: XOPV 0xEF VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() -OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 IMM0:r:b:u64 +OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 IMM0:r:b:u8 } { @@ -16045,7 +16509,7 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP -ATTRIBUTES: MXCSR +ATTRIBUTES: MXCSR AMDONLY PATTERN: XOPV 0x80 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS: REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32 @@ -16066,7 +16530,7 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP -ATTRIBUTES: MXCSR +ATTRIBUTES: MXCSR AMDONLY PATTERN: XOPV 0x81 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS: REG0=XMM_R():w:dq:f64 MEM0:r:dq:f64 @@ -16087,7 +16551,7 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP -ATTRIBUTES: SIMD_SCALAR MXCSR +ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY PATTERN: XOPV 0x82 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS: REG0=XMM_R():w:dq:f32 MEM0:r:d:f32 @@ -16102,7 +16566,7 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP -ATTRIBUTES: SIMD_SCALAR MXCSR +ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY PATTERN: XOPV 0x83 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS: REG0=XMM_R():w:dq:f64 MEM0:r:q:f64 @@ -16117,6 +16581,7 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY PATTERN: XOPV 0x90 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS: REG0=XMM_R():w:dq:u8 MEM0:r:dq:u8 REG1=XMM_N():r:dq:u8 @@ -16137,6 +16602,7 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY PATTERN: XOPV 0x91 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS: REG0=XMM_R():w:dq:u16 MEM0:r:dq:u16 REG1=XMM_N():r:dq:u16 @@ -16157,6 +16623,7 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY PATTERN: XOPV 0x92 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS: REG0=XMM_R():w:dq:u32 MEM0:r:dq:u32 REG1=XMM_N():r:dq:u32 @@ -16177,6 +16644,7 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY PATTERN: XOPV 0x93 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS: REG0=XMM_R():w:dq:u64 MEM0:r:dq:u64 REG1=XMM_N():r:dq:u64 @@ -16197,6 +16665,7 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY PATTERN: XOPV 0x94 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS: REG0=XMM_R():w:dq:u8 MEM0:r:dq:u8 REG1=XMM_N():r:dq:u8 @@ -16217,6 +16686,7 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY PATTERN: XOPV 0x95 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS: REG0=XMM_R():w:dq:u16 MEM0:r:dq:u16 REG1=XMM_N():r:dq:u16 @@ -16237,6 +16707,7 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY PATTERN: XOPV 0x96 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS: REG0=XMM_R():w:dq:u32 MEM0:r:dq:u32 REG1=XMM_N():r:dq:u32 @@ -16257,6 +16728,7 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY PATTERN: XOPV 0x97 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS: REG0=XMM_R():w:dq:u64 MEM0:r:dq:u64 REG1=XMM_N():r:dq:u64 @@ -16277,6 +16749,7 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY PATTERN: XOPV 0xC1 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS: REG0=XMM_R():w:dq:i8 MEM0:r:dq:i8 @@ -16291,6 +16764,7 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY PATTERN: XOPV 0xC2 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS: REG0=XMM_R():w:dq:i32 MEM0:r:dq:i8 @@ -16305,6 +16779,7 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY PATTERN: XOPV 0xC3 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS: REG0=XMM_R():w:dq:i64 MEM0:r:dq:i8 @@ -16319,6 +16794,7 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY PATTERN: XOPV 0xC6 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS: REG0=XMM_R():w:dq:i32 MEM0:r:dq:i16 @@ -16333,6 +16809,7 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY PATTERN: XOPV 0xC7 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS: REG0=XMM_R():w:dq:i64 MEM0:r:dq:i16 @@ -16347,6 +16824,7 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY PATTERN: XOPV 0xD1 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS: REG0=XMM_R():w:dq:u16 MEM0:r:dq:u8 @@ -16361,6 +16839,7 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY PATTERN: XOPV 0xD2 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS: REG0=XMM_R():w:dq:u32 MEM0:r:dq:u8 @@ -16375,6 +16854,7 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY PATTERN: XOPV 0xD3 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS: REG0=XMM_R():w:dq:u64 MEM0:r:dq:u8 @@ -16389,6 +16869,7 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY PATTERN: XOPV 0xD6 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS: REG0=XMM_R():w:dq:u32 MEM0:r:dq:u16 @@ -16403,6 +16884,7 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY PATTERN: XOPV 0xD7 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS: REG0=XMM_R():w:dq:u64 MEM0:r:dq:u16 @@ -16417,6 +16899,7 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY PATTERN: XOPV 0xE1 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS: REG0=XMM_R():w:dq:i16 MEM0:r:dq:i8 @@ -16431,6 +16914,7 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY PATTERN: XOPV 0xE2 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS: REG0=XMM_R():w:dq:i32 MEM0:r:dq:i16 @@ -16445,6 +16929,7 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY PATTERN: XOPV 0xE3 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS: REG0=XMM_R():w:dq:i64 MEM0:r:dq:i32 @@ -16459,6 +16944,7 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY PATTERN: XOPV 0x98 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS: REG0=XMM_R():w:dq:i8 MEM0:r:dq:i8 REG1=XMM_N():r:dq:i8 @@ -16479,6 +16965,7 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY PATTERN: XOPV 0x99 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS: REG0=XMM_R():w:dq:i16 MEM0:r:dq:i16 REG1=XMM_N():r:dq:i16 @@ -16499,6 +16986,7 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY PATTERN: XOPV 0x9A VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS: REG0=XMM_R():w:dq:i32 MEM0:r:dq:i32 REG1=XMM_N():r:dq:i32 @@ -16519,6 +17007,7 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY PATTERN: XOPV 0x9B VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS: REG0=XMM_R():w:dq:i64 MEM0:r:dq:i64 REG1=XMM_N():r:dq:i64 @@ -16539,6 +17028,7 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY PATTERN: XOPV 0xCB VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS: REG0=XMM_R():w:dq:i64 MEM0:r:dq:i32 @@ -16553,6 +17043,7 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY PATTERN: XOPV 0xDB VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS: REG0=XMM_R():w:dq:u64 MEM0:r:dq:u32 @@ -16563,16 +17054,23 @@ OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:dq:u32 { ICLASS: BEXTR_XOP +DISASM: bextr CPL: 3 CATEGORY: TBM ISA_SET: TBM EXTENSION: TBM +ATTRIBUTES: AMDONLY + FLAGS: MUST [ cf-0 pf-u af-u zf-mod sf-u of-0 ] -PATTERN: XOPV 0x10 VNP W0 VL128 NOVSR XMAPA MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM32() +PATTERN: XOPV 0x10 VNP not64 VL128 NOVSR XMAPA MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM32() +OPERANDS: REG0=GPR32_R():w:d MEM0:r:d IMM0:r:d +PATTERN: XOPV 0x10 VNP mode64 VL128 NOVSR XMAPA MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM32() OPERANDS: REG0=GPRy_R():w:y MEM0:r:y IMM0:r:d -PATTERN: XOPV 0x10 VNP W0 VL128 NOVSR XMAPA MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM32() +PATTERN: XOPV 0x10 VNP not64 VL128 NOVSR XMAPA MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM32() +OPERANDS: REG0=GPR32_R():w:d REG1=GPR32_B():r:d IMM0:r:d +PATTERN: XOPV 0x10 VNP mode64 VL128 NOVSR XMAPA MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM32() OPERANDS: REG0=GPRy_R():w:y REG1=GPRy_B():r:y IMM0:r:d } @@ -16582,13 +17080,19 @@ CPL: 3 CATEGORY: TBM ISA_SET: TBM EXTENSION: TBM +ATTRIBUTES: AMDONLY + FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ] -PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() -OPERANDS: REG0=GPRy_N():w:y MEM0:r:y +PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d +PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y -PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn] -OPERANDS: REG0=GPRy_N():w:y REG1=GPRv_B():r:y +PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS: REG0=VGPR32_N():w:d REG1=GPR32_B():r:d +PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS: REG0=VGPRy_N():w:y REG1=GPRy_B():r:y } { @@ -16597,13 +17101,19 @@ CPL: 3 CATEGORY: TBM ISA_SET: TBM EXTENSION: TBM +ATTRIBUTES: AMDONLY + FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ] -PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() -OPERANDS: REG0=GPRy_N():w:y MEM0:r:y +PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d +PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y -PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b010] RM[nnn] -OPERANDS: REG0=GPRy_N():w:y REG1=GPRv_B():r:y +PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS: REG0=VGPR32_N():w:d REG1=GPR32_B():r:d +PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS: REG0=VGPRy_N():w:y REG1=GPRy_B():r:y } { @@ -16612,13 +17122,19 @@ CPL: 3 CATEGORY: TBM ISA_SET: TBM EXTENSION: TBM +ATTRIBUTES: AMDONLY + FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ] -PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() -OPERANDS: REG0=GPRy_N():w:y MEM0:r:y +PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d +PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y -PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b011] RM[nnn] -OPERANDS: REG0=GPRy_N():w:y REG1=GPRv_B():r:y +PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS: REG0=VGPR32_N():w:d REG1=GPR32_B():r:d +PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS: REG0=VGPRy_N():w:y REG1=GPRy_B():r:y } { @@ -16627,13 +17143,19 @@ CPL: 3 CATEGORY: TBM ISA_SET: TBM EXTENSION: TBM +ATTRIBUTES: AMDONLY + FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ] -PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() -OPERANDS: REG0=GPRy_N():w:y MEM0:r:y +PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d +PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y -PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b100] RM[nnn] -OPERANDS: REG0=GPRy_N():w:y REG1=GPRv_B():r:y +PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b100] RM[nnn] +OPERANDS: REG0=VGPR32_N():w:d REG1=GPR32_B():r:d +PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b100] RM[nnn] +OPERANDS: REG0=VGPRy_N():w:y REG1=GPRy_B():r:y } { @@ -16642,13 +17164,19 @@ CPL: 3 CATEGORY: TBM ISA_SET: TBM EXTENSION: TBM +ATTRIBUTES: AMDONLY + FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ] -PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() -OPERANDS: REG0=GPRy_N():w:y MEM0:r:y +PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d +PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y -PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b101] RM[nnn] -OPERANDS: REG0=GPRy_N():w:y REG1=GPRv_B():r:y +PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b101] RM[nnn] +OPERANDS: REG0=VGPR32_N():w:d REG1=GPR32_B():r:d +PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b101] RM[nnn] +OPERANDS: REG0=VGPRy_N():w:y REG1=GPRy_B():r:y } { @@ -16657,13 +17185,19 @@ CPL: 3 CATEGORY: TBM ISA_SET: TBM EXTENSION: TBM +ATTRIBUTES: AMDONLY + FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ] -PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() -OPERANDS: REG0=GPRy_N():w:y MEM0:r:y +PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d +PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y -PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn] -OPERANDS: REG0=GPRy_N():w:y REG1=GPRv_B():r:y +PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn] +OPERANDS: REG0=VGPR32_N():w:d REG1=GPR32_B():r:d +PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn] +OPERANDS: REG0=VGPRy_N():w:y REG1=GPRy_B():r:y } { @@ -16672,13 +17206,19 @@ CPL: 3 CATEGORY: TBM ISA_SET: TBM EXTENSION: TBM +ATTRIBUTES: AMDONLY + FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ] -PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() -OPERANDS: REG0=GPRy_N():w:y MEM0:r:y +PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d +PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y -PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b111] RM[nnn] -OPERANDS: REG0=GPRy_N():w:y REG1=GPRv_B():r:y +PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b111] RM[nnn] +OPERANDS: REG0=VGPR32_N():w:d REG1=GPR32_B():r:d +PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b111] RM[nnn] +OPERANDS: REG0=VGPRy_N():w:y REG1=GPRy_B():r:y } { @@ -16687,13 +17227,19 @@ CPL: 3 CATEGORY: TBM ISA_SET: TBM EXTENSION: TBM +ATTRIBUTES: AMDONLY + FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ] -PATTERN: XOPV 0x02 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() -OPERANDS: REG0=GPRy_N():w:y MEM0:r:y +PATTERN: XOPV 0x02 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d +PATTERN: XOPV 0x02 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y -PATTERN: XOPV 0x02 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn] -OPERANDS: REG0=GPRy_N():w:y REG1=GPRv_B():r:y +PATTERN: XOPV 0x02 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS: REG0=VGPR32_N():w:d REG1=GPR32_B():r:d +PATTERN: XOPV 0x02 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS: REG0=VGPRy_N():w:y REG1=GPRy_B():r:y } { @@ -16702,13 +17248,19 @@ CPL: 3 CATEGORY: TBM ISA_SET: TBM EXTENSION: TBM +ATTRIBUTES: AMDONLY + FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ] -PATTERN: XOPV 0x02 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() -OPERANDS: REG0=GPRy_N():w:y MEM0:r:y +PATTERN: XOPV 0x02 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d +PATTERN: XOPV 0x02 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y -PATTERN: XOPV 0x02 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn] -OPERANDS: REG0=GPRy_N():w:y REG1=GPRv_B():r:y +PATTERN: XOPV 0x02 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn] +OPERANDS: REG0=VGPR32_N():w:d REG1=GPR32_B():r:d +PATTERN: XOPV 0x02 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn] +OPERANDS: REG0=VGPRy_N():w:y REG1=GPRy_B():r:y } { @@ -16717,8 +17269,9 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY -PATTERN: XOPV 0x12 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[0b000] RM[nnn] +PATTERN: XOPV 0x12 VNP VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[0b000] RM[nnn] OPERANDS: REG0=GPRy_B():w:y } @@ -16728,8 +17281,9 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY -PATTERN: XOPV 0x12 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +PATTERN: XOPV 0x12 VNP VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn] OPERANDS: REG0=GPRy_B():w:y } @@ -16739,13 +17293,15 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY + FLAGS: MUST [ cf-mod ] -PATTERN: XOPV 0x12 VNP W0 VL128 XMAPA MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() UIMM32() -OPERANDS: REG0=GPRy_N():w:y MEM0:r:d IMM0:r:d +PATTERN: XOPV 0x12 VNP VL128 XMAPA MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() UIMM32() +OPERANDS: REG0=VGPRy_N():w:y MEM0:r:d IMM0:r:d -PATTERN: XOPV 0x12 VNP W0 VL128 XMAPA MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM32() -OPERANDS: REG0=GPRy_N():w:y REG1=GPRv_B():r:d IMM0:r:d +PATTERN: XOPV 0x12 VNP VL128 XMAPA MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM32() +OPERANDS: REG0=VGPRy_N():w:y REG1=GPR32_B():r:y IMM0:r:d } { @@ -16754,12 +17310,13 @@ CPL: 3 CATEGORY: XOP ISA_SET: XOP EXTENSION: XOP +ATTRIBUTES: AMDONLY -PATTERN: XOPV 0x12 VNP W0 VL128 XMAPA MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() UIMM32() -OPERANDS: REG0=GPRy_N():w:y MEM0:r:d IMM0:r:d +PATTERN: XOPV 0x12 VNP VL128 XMAPA MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() UIMM32() +OPERANDS: REG0=VGPRy_N():w:y MEM0:r:d IMM0:r:d -PATTERN: XOPV 0x12 VNP W0 VL128 XMAPA MOD[0b11] MOD=3 REG[0b001] RM[nnn] UIMM32() -OPERANDS: REG0=GPRy_N():w:y REG1=GPRv_B():r:d IMM0:r:d +PATTERN: XOPV 0x12 VNP VL128 XMAPA MOD[0b11] MOD=3 REG[0b001] RM[nnn] UIMM32() +OPERANDS: REG0=VGPRy_N():w:y REG1=GPR32_B():r:y IMM0:r:d } @@ -16767,7 +17324,7 @@ OPERANDS: REG0=GPRy_N():w:y REG1=GPRv_B():r:d IMM0:r:d #BEGIN_LEGAL # -#Copyright (c) 2016 Intel Corporation +#Copyright (c) 2018 Intel Corporation # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -16790,7 +17347,7 @@ CPL: 3 CATEGORY: FMA4 ISA_SET: FMA4 EXTENSION: FMA4 -ATTRIBUTES: MXCSR +ATTRIBUTES: MXCSR AMDONLY PATTERN: VV1 0x5C V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:f32 @@ -16823,7 +17380,7 @@ CPL: 3 CATEGORY: FMA4 ISA_SET: FMA4 EXTENSION: FMA4 -ATTRIBUTES: MXCSR +ATTRIBUTES: MXCSR AMDONLY PATTERN: VV1 0x5D V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:f64 @@ -16856,7 +17413,7 @@ CPL: 3 CATEGORY: FMA4 ISA_SET: FMA4 EXTENSION: FMA4 -ATTRIBUTES: MXCSR +ATTRIBUTES: MXCSR AMDONLY PATTERN: VV1 0x5E V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:f32 @@ -16889,7 +17446,7 @@ CPL: 3 CATEGORY: FMA4 ISA_SET: FMA4 EXTENSION: FMA4 -ATTRIBUTES: MXCSR +ATTRIBUTES: MXCSR AMDONLY PATTERN: VV1 0x5F V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:f64 @@ -16922,7 +17479,7 @@ CPL: 3 CATEGORY: FMA4 ISA_SET: FMA4 EXTENSION: FMA4 -ATTRIBUTES: MXCSR +ATTRIBUTES: MXCSR AMDONLY PATTERN: VV1 0x68 V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:f32 @@ -16955,7 +17512,7 @@ CPL: 3 CATEGORY: FMA4 ISA_SET: FMA4 EXTENSION: FMA4 -ATTRIBUTES: MXCSR +ATTRIBUTES: MXCSR AMDONLY PATTERN: VV1 0x69 V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:f64 @@ -16988,19 +17545,19 @@ CPL: 3 CATEGORY: FMA4 ISA_SET: FMA4 EXTENSION: FMA4 -ATTRIBUTES: SIMD_SCALAR MXCSR +ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY PATTERN: VV1 0x6A V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() -OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 REG2=XMM_SE():r:dq:f32 +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 REG2=XMM_SE():r:d:f32 PATTERN: VV1 0x6A V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() -OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 REG3=XMM_SE():r:dq:f32 +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 REG3=XMM_SE():r:d:f32 PATTERN: VV1 0x6A V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() -OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:d:f32 +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_SE():r:d:f32 MEM0:r:d:f32 PATTERN: VV1 0x6A V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() -OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:d:f32 +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_SE():r:d:f32 REG3=XMM_B():r:d:f32 } { @@ -17009,19 +17566,19 @@ CPL: 3 CATEGORY: FMA4 ISA_SET: FMA4 EXTENSION: FMA4 -ATTRIBUTES: SIMD_SCALAR MXCSR +ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY PATTERN: VV1 0x6B V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() -OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 REG2=XMM_SE():r:dq:f64 +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 REG2=XMM_SE():r:q:f64 PATTERN: VV1 0x6B V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() -OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 REG3=XMM_SE():r:dq:f64 +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 REG3=XMM_SE():r:q:f64 PATTERN: VV1 0x6B V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() -OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:q:f64 +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_SE():r:q:f64 MEM0:r:q:f64 PATTERN: VV1 0x6B V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() -OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:q:f64 +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_SE():r:q:f64 REG3=XMM_B():r:q:f64 } { @@ -17030,7 +17587,7 @@ CPL: 3 CATEGORY: FMA4 ISA_SET: FMA4 EXTENSION: FMA4 -ATTRIBUTES: MXCSR +ATTRIBUTES: MXCSR AMDONLY PATTERN: VV1 0x6C V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:f32 @@ -17063,7 +17620,7 @@ CPL: 3 CATEGORY: FMA4 ISA_SET: FMA4 EXTENSION: FMA4 -ATTRIBUTES: MXCSR +ATTRIBUTES: MXCSR AMDONLY PATTERN: VV1 0x6D V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:f64 @@ -17096,19 +17653,19 @@ CPL: 3 CATEGORY: FMA4 ISA_SET: FMA4 EXTENSION: FMA4 -ATTRIBUTES: SIMD_SCALAR MXCSR +ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY PATTERN: VV1 0x6E V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() -OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 REG2=XMM_SE():r:dq:f32 +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 REG2=XMM_SE():r:d:f32 PATTERN: VV1 0x6E V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() -OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 REG3=XMM_SE():r:dq:f32 +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 REG3=XMM_SE():r:d:f32 PATTERN: VV1 0x6E V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() -OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:d:f32 +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_SE():r:d:f32 MEM0:r:d:f32 PATTERN: VV1 0x6E V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() -OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:d:f32 +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_SE():r:d:f32 REG3=XMM_B():r:d:f32 } { @@ -17117,19 +17674,19 @@ CPL: 3 CATEGORY: FMA4 ISA_SET: FMA4 EXTENSION: FMA4 -ATTRIBUTES: SIMD_SCALAR MXCSR +ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY PATTERN: VV1 0x6F V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() -OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 REG2=XMM_SE():r:dq:f64 +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 REG2=XMM_SE():r:q:f64 PATTERN: VV1 0x6F V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() -OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 REG3=XMM_SE():r:dq:f64 +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 REG3=XMM_SE():r:q:f64 PATTERN: VV1 0x6F V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() -OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:q:f64 +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_SE():r:q:f64 MEM0:r:q:f64 PATTERN: VV1 0x6F V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() -OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:q:f64 +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_SE():r:q:f64 REG3=XMM_B():r:q:f64 } { @@ -17138,7 +17695,7 @@ CPL: 3 CATEGORY: FMA4 ISA_SET: FMA4 EXTENSION: FMA4 -ATTRIBUTES: MXCSR +ATTRIBUTES: MXCSR AMDONLY PATTERN: VV1 0x78 V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:f32 @@ -17171,7 +17728,7 @@ CPL: 3 CATEGORY: FMA4 ISA_SET: FMA4 EXTENSION: FMA4 -ATTRIBUTES: MXCSR +ATTRIBUTES: MXCSR AMDONLY PATTERN: VV1 0x79 V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:f64 @@ -17204,19 +17761,19 @@ CPL: 3 CATEGORY: FMA4 ISA_SET: FMA4 EXTENSION: FMA4 -ATTRIBUTES: SIMD_SCALAR MXCSR +ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY PATTERN: VV1 0x7A V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() -OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 REG2=XMM_SE():r:dq:f32 +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 REG2=XMM_SE():r:d:f32 PATTERN: VV1 0x7A V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() -OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 REG3=XMM_SE():r:dq:f32 +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 REG3=XMM_SE():r:d:f32 PATTERN: VV1 0x7A V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() -OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:d:f32 +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_SE():r:d:f32 MEM0:r:d:f32 PATTERN: VV1 0x7A V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() -OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:d:f32 +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_SE():r:d:f32 REG3=XMM_B():r:d:f32 } { @@ -17225,19 +17782,19 @@ CPL: 3 CATEGORY: FMA4 ISA_SET: FMA4 EXTENSION: FMA4 -ATTRIBUTES: SIMD_SCALAR MXCSR +ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY PATTERN: VV1 0x7B V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() -OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 REG2=XMM_SE():r:dq:f64 +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 REG2=XMM_SE():r:q:f64 PATTERN: VV1 0x7B V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() -OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 REG3=XMM_SE():r:dq:f64 +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 REG3=XMM_SE():r:q:f64 PATTERN: VV1 0x7B V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() -OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:q:f64 +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_SE():r:q:f64 MEM0:r:q:f64 PATTERN: VV1 0x7B V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() -OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:q:f64 +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_SE():r:q:f64 REG3=XMM_B():r:q:f64 } { @@ -17246,7 +17803,7 @@ CPL: 3 CATEGORY: FMA4 ISA_SET: FMA4 EXTENSION: FMA4 -ATTRIBUTES: MXCSR +ATTRIBUTES: MXCSR AMDONLY PATTERN: VV1 0x7C V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:f32 @@ -17279,7 +17836,7 @@ CPL: 3 CATEGORY: FMA4 ISA_SET: FMA4 EXTENSION: FMA4 -ATTRIBUTES: MXCSR +ATTRIBUTES: MXCSR AMDONLY PATTERN: VV1 0x7D V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:f64 @@ -17312,19 +17869,19 @@ CPL: 3 CATEGORY: FMA4 ISA_SET: FMA4 EXTENSION: FMA4 -ATTRIBUTES: SIMD_SCALAR MXCSR +ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY PATTERN: VV1 0x7E V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() -OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 REG2=XMM_SE():r:dq:f32 +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 REG2=XMM_SE():r:d:f32 PATTERN: VV1 0x7E V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() -OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 REG3=XMM_SE():r:dq:f32 +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 REG3=XMM_SE():r:d:f32 PATTERN: VV1 0x7E V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() -OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:d:f32 +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_SE():r:d:f32 MEM0:r:d:f32 PATTERN: VV1 0x7E V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() -OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:d:f32 +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_SE():r:d:f32 REG3=XMM_B():r:d:f32 } { @@ -17333,19 +17890,19 @@ CPL: 3 CATEGORY: FMA4 ISA_SET: FMA4 EXTENSION: FMA4 -ATTRIBUTES: SIMD_SCALAR MXCSR +ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY PATTERN: VV1 0x7F V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() -OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 REG2=XMM_SE():r:dq:f64 +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 REG2=XMM_SE():r:q:f64 PATTERN: VV1 0x7F V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() -OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 REG3=XMM_SE():r:dq:f64 +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 REG3=XMM_SE():r:q:f64 PATTERN: VV1 0x7F V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() -OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:q:f64 +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_SE():r:q:f64 MEM0:r:q:f64 PATTERN: VV1 0x7F V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() -OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:q:f64 +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_SE():r:q:f64 REG3=XMM_B():r:q:f64 } @@ -17353,7 +17910,7 @@ OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG #BEGIN_LEGAL # -#Copyright (c) 2016 Intel Corporation +#Copyright (c) 2018 Intel Corporation # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -17378,6 +17935,7 @@ CPL : 3 CATEGORY : XOP EXTENSION : XOP ISA_SET : XOP +ATTRIBUTES : AMDONLY # 128b W0 PATTERN : VV1 0x48 VL128 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() @@ -17417,6 +17975,7 @@ CPL : 3 CATEGORY : XOP EXTENSION : XOP ISA_SET : XOP +ATTRIBUTES : AMDONLY # 128b W0 PATTERN : VV1 0x49 VL128 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() @@ -17450,11 +18009,11 @@ OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 R -###FILE: ../xed/datafiles/xsaveopt/xsaveopt-isa.txt +###FILE: ../xed/datafiles/mpx/mpx-isa.txt #BEGIN_LEGAL # -#Copyright (c) 2016 Intel Corporation +#Copyright (c) 2018 Intel Corporation # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -17469,39 +18028,221 @@ OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 R # limitations under the License. # #END_LEGAL + + INSTRUCTIONS():: + +UDELETE: NOP0F1A +UDELETE: NOP0F1B + + + { -ICLASS : XSAVEOPT +ICLASS: BNDMK +EXTENSION: MPX +CATEGORY: MPX +ISA_SET: MPX +ATTRIBUTES: NO_RIP_REL +PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix +OPERANDS: REG0=BND_R():w AGEN:r +} + + + + +{ +ICLASS: BNDCL +EXTENSION: MPX +CATEGORY: MPX +ISA_SET: MPX +ATTRIBUTES: EXCEPTION_BR +COMMENT: 67 prefixes will be misinterpreted on MPX NI. XED cannot ignore them. +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix +OPERANDS: REG0=BND_R():r AGEN:r + +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix mode64 +OPERANDS: REG0=BND_R():r REG1=GPR64_B():r +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix not64 +OPERANDS: REG0=BND_R():r REG1=GPR32_B():r +} + +{ +ICLASS: BNDCU +EXTENSION: MPX +CATEGORY: MPX +ISA_SET: MPX +ATTRIBUTES: EXCEPTION_BR +COMMENT: 67 prefixes will be misinterpreted on MPX NI. XED cannot ignore them. +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix +OPERANDS: REG0=BND_R():r AGEN:r + +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix mode64 +OPERANDS: REG0=BND_R():r REG1=GPR64_B():r +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix not64 +OPERANDS: REG0=BND_R():r REG1=GPR32_B():r +} + +{ +ICLASS: BNDCN +EXTENSION: MPX +CATEGORY: MPX +ISA_SET: MPX +ATTRIBUTES: EXCEPTION_BR +COMMENT: 67 prefixes will be misinterpreted on MPX NI. XED cannot ignore them. +PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix +OPERANDS: REG0=BND_R():r AGEN:r + +PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix mode64 +OPERANDS: REG0=BND_R():r REG1=GPR64_B():r +PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix not64 +OPERANDS: REG0=BND_R():r REG1=GPR32_B():r + +} + +{ +ICLASS: BNDMOV +EXTENSION: MPX +CATEGORY: MPX +ISA_SET: MPX +ATTRIBUTES: +COMMENT: load form + +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix REFINING66() +OPERANDS: REG0=BND_R():w REG1=BND_B():r + +# 16b refs 64b memop (2x32b) but only if EASZ=32b! +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode16 eamode32 +OPERANDS: REG0=BND_R():w MEM0:r:q:u32 + +# 32b refs 64b memop (2x32b) +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode32 eamode32 +OPERANDS: REG0=BND_R():w MEM0:r:q:u32 + +# 64b refs 128b memop (2x64b) +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode64 +OPERANDS: REG0=BND_R():w MEM0:r:dq:u64 + + + +} + +{ +ICLASS: BNDMOV +EXTENSION: MPX +CATEGORY: MPX +ISA_SET: MPX +ATTRIBUTES: +COMMENT: store form + +PATTERN: 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix REFINING66() +OPERANDS: REG0=BND_B():w REG1=BND_R():r + +# 16b refs 64b memop (2x32b) but only if EASZ=32b! +PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode16 eamode32 +OPERANDS: MEM0:w:q:u32 REG0=BND_R():r + +# 32b refs 64b memop (2x32b) +PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode32 +OPERANDS: MEM0:w:q:u32 REG0=BND_R():r + +# 64b refs 128b memop (2x64b) +PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode64 +OPERANDS: MEM0:w:dq:u64 REG0=BND_R():r +} + + +{ +ICLASS: BNDLDX +EXTENSION: MPX +CATEGORY: MPX +ISA_SET: MPX +ATTRIBUTES: EXCEPTION_BR SPECIAL_AGEN_REQUIRED INDEX_REG_IS_POINTER NO_RIP_REL +COMMENT: RIP (mode64, easz64, MOD=0, RM=5) mode disallowed in 64b And 16/32b is easize32 only +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix not64 eamode32 +OPERANDS: REG0=BND_R():w MEM0:r:bnd32 +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=0 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 # RM!=5 +OPERANDS: REG0=BND_R():w MEM0:r:bnd64 +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=1 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 +OPERANDS: REG0=BND_R():w MEM0:r:bnd64 +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=2 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 +OPERANDS: REG0=BND_R():w MEM0:r:bnd64 +} + +{ +ICLASS: BNDSTX +EXTENSION: MPX +CATEGORY: MPX +ISA_SET: MPX +ATTRIBUTES: EXCEPTION_BR SPECIAL_AGEN_REQUIRED INDEX_REG_IS_POINTER NO_RIP_REL +COMMENT: RIP (mode64, easz64, MOD=0, RM=5) mode disallowed in 64b And 16/32b is easize32 only +PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix not64 eamode32 +OPERANDS: MEM0:w:bnd32 REG0=BND_R():r +PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=0 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 # RM!=5 +OPERANDS: MEM0:w:bnd64 REG0=BND_R():r +PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=1 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 +OPERANDS: MEM0:w:bnd64 REG0=BND_R():r +PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=2 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 +OPERANDS: MEM0:w:bnd64 REG0=BND_R():r +} + +{ +ICLASS : NOP CPL : 3 -CATEGORY : XSAVEOPT -EXTENSION : XSAVEOPT -ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX -PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] no_refining_prefix norexw_prefix MODRM() -#FIXME 2007-06-25 need a meaningful width code for XSAVE/XSAVEOPT/XRSTOR -OPERANDS : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP +CATEGORY : WIDENOP +ATTRIBUTES: NOP +EXTENSION : BASE +ISA_SET : PPRO +COMMENT : MPXMODE=1: some of the reg/reg forms of these NOPs are still NOPs. + +PATTERN : 0x0F 0x1A MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1A + +PATTERN : 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1B + +PATTERN : 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1B } { -ICLASS : XSAVEOPT64 +ICLASS : NOP CPL : 3 -CATEGORY : XSAVEOPT -EXTENSION : XSAVEOPT -ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX +CATEGORY : WIDENOP +ATTRIBUTES: NOP +EXTENSION : BASE +ISA_SET : PPRO +COMMENT : For MPXMODE=0 operation -PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] no_refining_prefix rexw_prefix MODRM() -#FIXME 2007-06-25 need a meaningful width code for XSAVE/XSAVEOPT/XRSTOR -OPERANDS : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP +PATTERN : 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1A + +PATTERN : 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1B + +PATTERN : 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_B():r MEM0:r:v +IFORM : NOP_GPRv_MEMv_0F1A + +PATTERN : 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_B():r MEM0:r:v +IFORM : NOP_GPRv_MEM_0F1B } -###FILE: ../xed/datafiles/mpx/mpx-isa.txt + +###FILE: ../xed/datafiles/cet/cet-nop-remove.xed.txt #BEGIN_LEGAL # -#Copyright (c) 2016 Intel Corporation +#Copyright (c) 2018 Intel Corporation # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -17520,209 +18261,394 @@ OPERANDS : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=X INSTRUCTIONS():: +UDELETE: NOP0F1E -UDELETE: NOP0F1A -UDELETE: NOP0F1B +{ +ICLASS : NOP +#UNAME : NOP0F1E +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +ATTRIBUTES: NOP +ISA_SET : PPRO +COMMENT : reg form MODRM.MOD=3 & MODRM.REG=0b001 f3 prefix is RDSSP{D,Q} +# mem forms +PATTERN : 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F1E -{ -ICLASS: BNDMK -EXTENSION: MPX -CATEGORY: MPX -ISA_SET: MPX -ATTRIBUTES: NO_RIP_REL -PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix -OPERANDS: REG0=BND_R():w AGEN:r -} +# reg forms +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E + +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E + + + + + + +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E + +# ... +# F3 with MODRM.REG=0b001 is for CET for all values of RM. +# ... + +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E + + +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b000] f3_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b001] f3_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E + +# ... +# F3 with MODRM.REG=0b111 with RM=2 or RM=3 is for CET +# ... + +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b100] f3_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b101] f3_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b110] f3_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b111] f3_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E -{ -ICLASS: BNDCL -EXTENSION: MPX -CATEGORY: MPX -ISA_SET: MPX -ATTRIBUTES: EXCEPTION_BR -COMMENT: 67 prefixes will be misinterpreted on MPX NI. XED cannot ignore them. -PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix -OPERANDS: REG0=BND_R():r AGEN:r -PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix mode64 -OPERANDS: REG0=BND_R():r REG1=GPR64_B():r -PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix not64 -OPERANDS: REG0=BND_R():r REG1=GPR32_B():r } + +# REPLACE CERTAIN NOPS WITH MODAL OPTIONS basd on CET=0/1 { -ICLASS: BNDCU -EXTENSION: MPX -CATEGORY: MPX -ISA_SET: MPX -ATTRIBUTES: EXCEPTION_BR -COMMENT: 67 prefixes will be misinterpreted on MPX NI. XED cannot ignore them. -PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix -OPERANDS: REG0=BND_R():r AGEN:r +ICLASS : NOP +#UNAME : NOP0F1E +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +ATTRIBUTES: NOP +ISA_SET : PPRO -PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix mode64 -OPERANDS: REG0=BND_R():r REG1=GPR64_B():r -PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix not64 -OPERANDS: REG0=BND_R():r REG1=GPR32_B():r +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix CET=0 +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E + +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b011] f3_refining_prefix CET=0 +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E } + { -ICLASS: BNDCN -EXTENSION: MPX -CATEGORY: MPX -ISA_SET: MPX -ATTRIBUTES: EXCEPTION_BR -COMMENT: 67 prefixes will be misinterpreted on MPX NI. XED cannot ignore them. -PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix -OPERANDS: REG0=BND_R():r AGEN:r +ICLASS : NOP +#UNAME : NOP0F1E +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +ATTRIBUTES: NOP +ISA_SET : PPRO -PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix mode64 -OPERANDS: REG0=BND_R():r REG1=GPR64_B():r -PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix not64 -OPERANDS: REG0=BND_R():r REG1=GPR32_B():r +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=0 +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W1 mode64 CET=0 +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E } + +###FILE: ../xed/datafiles/cet/cet-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2018 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +INSTRUCTIONS():: +# EMITTING CLRSSBSY (CLRSSBSY-N/A-1) { -ICLASS: BNDMOV -EXTENSION: MPX -CATEGORY: MPX -ISA_SET: MPX -ATTRIBUTES: -COMMENT: load form +ICLASS: CLRSSBSY +CPL: 3 +CATEGORY: CET +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: Y +PATTERN: 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] f3_refining_prefix MODRM() +OPERANDS: MEM0:rw:q:u64 +IFORM: CLRSSBSY_MEMu64 +} -PATTERN: 0x0F 0x1A MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix REFINING66() -OPERANDS: REG0=BND_R():w REG1=BND_B():r -# 16b refs 64b memop (2x32b) but only if EASZ=32b! -PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode16 eamode32 -OPERANDS: REG0=BND_R():w MEM0:r:q:u32 +# EMITTING ENDBR32 (ENDBR32-N/A-1) +{ +ICLASS: ENDBR32 +CPL: 3 +CATEGORY: CET +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: Y +PATTERN: 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b011] f3_refining_prefix CET=1 +OPERANDS: +IFORM: ENDBR32 +} -# 32b refs 64b memop (2x32b) -PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode32 -OPERANDS: REG0=BND_R():w MEM0:r:q:u32 -# 64b refs 128b memop (2x64b) -PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode64 -OPERANDS: REG0=BND_R():w MEM0:r:dq:u64 +# EMITTING ENDBR64 (ENDBR64-N/A-1) +{ +ICLASS: ENDBR64 +CPL: 3 +CATEGORY: CET +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: Y +PATTERN: 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix CET=1 +OPERANDS: +IFORM: ENDBR64 +} + +# EMITTING INCSSPD (INCSSPD-N/A-1) +{ +ICLASS: INCSSPD +CPL: 3 +CATEGORY: CET +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: Y +PATTERN: 0x0F 0xAE MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix W0 +OPERANDS: REG0=GPR32_B():r:d:u8 REG1=XED_REG_SSP:rw:SUPP:u64 +IFORM: INCSSPD_GPR32u8 +} +# EMITTING INCSSPQ (INCSSPQ-N/A-1) +{ +ICLASS: INCSSPQ +CPL: 3 +CATEGORY: CET +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: Y +PATTERN: 0x0F 0xAE MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix W1 mode64 +OPERANDS: REG0=GPR64_B():r:q:u8 REG1=XED_REG_SSP:rw:SUPP:u64 +IFORM: INCSSPQ_GPR64u8 } + +# EMITTING RDSSPD (RDSSPD-N/A-1) { -ICLASS: BNDMOV -EXTENSION: MPX -CATEGORY: MPX -ISA_SET: MPX -ATTRIBUTES: -COMMENT: store form +ICLASS: RDSSPD +CPL: 3 +CATEGORY: CET +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: Y +PATTERN: 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1 +OPERANDS: REG0=GPR32_B():w:d:u32 REG1=XED_REG_SSP:r:SUPP:u64 +IFORM: RDSSPD_GPR32u32 +} -PATTERN: 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix REFINING66() -OPERANDS: REG0=BND_B():w REG1=BND_R():r -# 16b refs 64b memop (2x32b) but only if EASZ=32b! -PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode16 eamode32 -OPERANDS: MEM0:w:q:u32 REG0=BND_R():r +# EMITTING RDSSPQ (RDSSPQ-N/A-1) +{ +ICLASS: RDSSPQ +CPL: 3 +CATEGORY: CET +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: Y +PATTERN: 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W1 mode64 CET=1 +OPERANDS: REG0=GPR64_B():w:q:u64 REG1=XED_REG_SSP:r:SUPP:u64 +IFORM: RDSSPQ_GPR64u64 +} -# 32b refs 64b memop (2x32b) -PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode32 -OPERANDS: MEM0:w:q:u32 REG0=BND_R():r -# 64b refs 128b memop (2x64b) -PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode64 -OPERANDS: MEM0:w:dq:u64 REG0=BND_R():r +# EMITTING RSTORSSP (RSTORSSP-N/A-1) +{ +ICLASS: RSTORSSP +CPL: 3 +CATEGORY: CET +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: Y +PATTERN: 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix +OPERANDS: MEM0:rw:q:u64 REG0=XED_REG_SSP:w:SUPP:u64 +IFORM: RSTORSSP_MEMu64 } +# EMITTING SAVEPREVSSP (SAVEPREVSSP-N/A-1) { -ICLASS: BNDLDX -EXTENSION: MPX -CATEGORY: MPX -ISA_SET: MPX -ATTRIBUTES: EXCEPTION_BR SPECIAL_AGEN_REQUIRED INDEX_REG_IS_POINTER NO_RIP_REL -COMMENT: RIP (mode64, easz64, MOD=0, RM=5) mode disallowed in 64b And 16/32b is easize32 only -PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix not64 eamode32 -OPERANDS: REG0=BND_R():w MEM0:r:bnd32 -PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=0 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 # RM!=5 -OPERANDS: REG0=BND_R():w MEM0:r:bnd64 -PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=1 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 -OPERANDS: REG0=BND_R():w MEM0:r:bnd64 -PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=2 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 -OPERANDS: REG0=BND_R():w MEM0:r:bnd64 +ICLASS: SAVEPREVSSP +CPL: 3 +CATEGORY: CET +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: Y +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b010] f3_refining_prefix +OPERANDS: REG0=XED_REG_SSP:r:SUPP:u64 +IFORM: SAVEPREVSSP } + +# EMITTING SETSSBSY (SETSSBSY-N/A-1) { -ICLASS: BNDSTX -EXTENSION: MPX -CATEGORY: MPX -ISA_SET: MPX -ATTRIBUTES: EXCEPTION_BR SPECIAL_AGEN_REQUIRED INDEX_REG_IS_POINTER NO_RIP_REL -COMMENT: RIP (mode64, easz64, MOD=0, RM=5) mode disallowed in 64b And 16/32b is easize32 only -PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix not64 eamode32 -OPERANDS: MEM0:w:bnd32 REG0=BND_R():r -PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=0 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 # RM!=5 -OPERANDS: MEM0:w:bnd64 REG0=BND_R():r -PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=1 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 -OPERANDS: MEM0:w:bnd64 REG0=BND_R():r -PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=2 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 -OPERANDS: MEM0:w:bnd64 REG0=BND_R():r +ICLASS: SETSSBSY +CPL: 3 +CATEGORY: CET +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: Y +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] f3_refining_prefix +OPERANDS: +IFORM: SETSSBSY } + +# EMITTING WRSSD (WRSSD-N/A-1) { -ICLASS : NOP -CPL : 3 -CATEGORY : WIDENOP -ATTRIBUTES: NOP -EXTENSION : BASE -ISA_SET : PPRO -COMMENT : MPXMODE=1: some of the reg/reg forms of these NOPs are still NOPs. +ICLASS: WRSSD +CPL: 3 +CATEGORY: CET +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: Y +PATTERN: 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix W0 +OPERANDS: MEM0:w:d:u32 REG0=GPR32_R():r:d:u32 +IFORM: WRSSD_MEMu32_GPR32u32 +} -PATTERN : 0x0F 0x1A MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix -OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r -IFORM : NOP_GPRv_GPRv_0F1A -PATTERN : 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix -OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r -IFORM : NOP_GPRv_GPRv_0F1B +# EMITTING WRSSQ (WRSSQ-N/A-1) +{ +ICLASS: WRSSQ +CPL: 3 +CATEGORY: CET +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: Y +PATTERN: 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix W1 mode64 +OPERANDS: MEM0:w:q:u64 REG0=GPR64_R():r:q:u64 +IFORM: WRSSQ_MEMu64_GPR64u64 +} -PATTERN : 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix -OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r -IFORM : NOP_GPRv_GPRv_0F1B + +# EMITTING WRUSSD (WRUSSD-N/A-1) +{ +ICLASS: WRUSSD +CPL: 3 +CATEGORY: CET +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: Y +PATTERN: 0x0F 0x38 0xF5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix W0 +OPERANDS: MEM0:w:d:u32 REG0=GPR32_R():r:d:u32 +IFORM: WRUSSD_MEMu32_GPR32u32 } +# EMITTING WRUSSQ (WRUSSQ-N/A-1) { -ICLASS : NOP -CPL : 3 -CATEGORY : WIDENOP -ATTRIBUTES: NOP -EXTENSION : BASE -ISA_SET : PPRO -COMMENT : For MPXMODE=0 operation +ICLASS: WRUSSQ +CPL: 3 +CATEGORY: CET +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: Y +PATTERN: 0x0F 0x38 0xF5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix W1 mode64 +OPERANDS: MEM0:w:q:u64 REG0=GPR64_R():r:q:u64 +IFORM: WRUSSQ_MEMu64_GPR64u64 +} -PATTERN : 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r -IFORM : NOP_GPRv_GPRv_0F1A -PATTERN : 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r -IFORM : NOP_GPRv_GPRv_0F1B -PATTERN : 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=GPRv_B():r MEM0:r:v -IFORM : NOP_GPRv_MEMv_0F1A -PATTERN : 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=GPRv_B():r MEM0:r:v -IFORM : NOP_GPRv_MEM_0F1B -} +###FILE: ../xed/datafiles/rdrand/rdrand-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2018 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: +{ +ICLASS : RDRAND +CPL : 3 +CATEGORY : RDRAND +EXTENSION : RDRAND +ISA_SET : RDRAND +FLAGS : MUST [ cf-mod zf-0 of-0 af-0 pf-0 sf-0 ] +PATTERN : 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b110] RM[nnn] not_refining +OPERANDS : REG0=GPRv_B():w +} @@ -17730,7 +18656,7 @@ IFORM : NOP_GPRv_MEM_0F1B #BEGIN_LEGAL # -#Copyright (c) 2016 Intel Corporation +#Copyright (c) 2018 Intel Corporation # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -17960,45 +18886,11 @@ IFORM: SHA256RNDS2_XMMi32_MEMi32_SHA -###FILE: ../xed/datafiles/ivbint/ivb-int-isa.txt - -#BEGIN_LEGAL -# -#Copyright (c) 2016 Intel Corporation -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -#END_LEGAL -INSTRUCTIONS():: - -{ -ICLASS : RDRAND -CPL : 3 -CATEGORY : RDRAND -EXTENSION : RDRAND -ISA_SET : RDRAND -FLAGS : MUST [ cf-mod zf-0 of-0 af-0 pf-0 sf-0 ] -PATTERN : 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b110] RM[nnn] not_refining -OPERANDS : REG0=GPRv_B():w -} - - - -###FILE: ../xed/datafiles/ivbint/fsgsbase-isa.txt +###FILE: ../xed/datafiles/xsaveopt/xsaveopt-isa.txt #BEGIN_LEGAL # -#Copyright (c) 2016 Intel Corporation +#Copyright (c) 2018 Intel Corporation # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -18015,59 +18907,38 @@ OPERANDS : REG0=GPRv_B():w #END_LEGAL INSTRUCTIONS():: - -{ -ICLASS : RDFSBASE -CPL : 3 -CATEGORY : RDWRFSGS -EXTENSION : RDWRFSGS - -PATTERN : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b000] RM[nnn] mode64 f3_refining_prefix no66_prefix -OPERANDS : REG0=GPRy_B():w REG1=XED_REG_FSBASE:r:SUPP:y - -} { -ICLASS : RDGSBASE +ICLASS : XSAVEOPT CPL : 3 -CATEGORY : RDWRFSGS -EXTENSION : RDWRFSGS - -PATTERN : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b001] RM[nnn] mode64 f3_refining_prefix no66_prefix -OPERANDS : REG0=GPRy_B():w REG1=XED_REG_GSBASE:r:SUPP:y - +CATEGORY : XSAVEOPT +EXTENSION : XSAVEOPT +ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX +COMMENT : Variable length Store and conditional reg read. reads/modifies header. +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] no_refining_prefix norexw_prefix MODRM() +#FIXME 2007-06-25 need a meaningful width code for XSAVE/XSAVEOPT/XRSTOR +OPERANDS : MEM0:rw:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP } - { -ICLASS : WRFSBASE +ICLASS : XSAVEOPT64 CPL : 3 -CATEGORY : RDWRFSGS -EXTENSION : RDWRFSGS -ATTRIBUTES: NOTSX - -PATTERN : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b010] RM[nnn] mode64 f3_refining_prefix no66_prefix -OPERANDS : REG0=GPRy_B():r REG1=XED_REG_FSBASE:w:SUPP:y - +CATEGORY : XSAVEOPT +EXTENSION : XSAVEOPT +ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX +COMMENT : Variable length Store and conditional reg read. reads/modifies header. +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] no_refining_prefix rexw_prefix MODRM() +#FIXME 2007-06-25 need a meaningful width code for XSAVE/XSAVEOPT/XRSTOR +OPERANDS : MEM0:rw:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP } -{ -ICLASS : WRGSBASE -CPL : 3 -CATEGORY : RDWRFSGS -EXTENSION : RDWRFSGS -ATTRIBUTES: NOTSX - -PATTERN : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b011] RM[nnn] mode64 f3_refining_prefix no66_prefix -OPERANDS : REG0=GPRy_B():r REG1=XED_REG_GSBASE:w:SUPP:y -} ###FILE: ../xed/datafiles/xsaves/xsaves-isa.txt #BEGIN_LEGAL # -#Copyright (c) 2016 Intel Corporation +#Copyright (c) 2018 Intel Corporation # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -18089,7 +18960,7 @@ ICLASS : XSAVES CPL : 0 CATEGORY : XSAVE EXTENSION : XSAVES -COMMENT : variable length load and conditianal reg write +COMMENT : variable length store and conditional reg read. does not read header ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() norexw_prefix no_refining_prefix OPERANDS : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP @@ -18101,7 +18972,7 @@ ICLASS : XSAVES64 CPL : 0 CATEGORY : XSAVE EXTENSION : XSAVES -COMMENT : variable length load and conditianal reg write +COMMENT : variable length store and conditional reg read. does not read header ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() rexw_prefix no_refining_prefix OPERANDS : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP @@ -18116,7 +18987,7 @@ ICLASS : XRSTORS CPL : 0 CATEGORY : XSAVE EXTENSION : XSAVES -COMMENT : variable length load and conditianal reg write +COMMENT : variable length load and conditional reg write. ATTRIBUTES : xmm_state_w REQUIRES_ALIGNMENT x87_mmx_state_w NOTSX SPECIAL_AGEN_REQUIRED PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() norexw_prefix no_refining_prefix OPERANDS : MEM0:r:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP @@ -18128,7 +18999,7 @@ ICLASS : XRSTORS64 CPL : 0 CATEGORY : XSAVE EXTENSION : XSAVES -COMMENT : variable length load and conditianal reg write +COMMENT : variable length load and conditional reg write ATTRIBUTES : xmm_state_w REQUIRES_ALIGNMENT x87_mmx_state_w NOTSX SPECIAL_AGEN_REQUIRED PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() rexw_prefix no_refining_prefix OPERANDS : MEM0:r:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP @@ -18140,7 +19011,7 @@ OPERANDS : MEM0:r:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=X #BEGIN_LEGAL # -#Copyright (c) 2016 Intel Corporation +#Copyright (c) 2018 Intel Corporation # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -18162,7 +19033,7 @@ ICLASS : XSAVEC CPL : 3 CATEGORY : XSAVE EXTENSION : XSAVEC -COMMENT : variable length store +COMMENT : Variable length store and conditional reg read. does not read header ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() norexw_prefix no_refining_prefix OPERANDS : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP @@ -18175,7 +19046,7 @@ ICLASS : XSAVEC64 CPL : 3 CATEGORY : XSAVE EXTENSION : XSAVEC -COMMENT : variable length store +COMMENT : Variable length store and conditional reg read. does not read header ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() rexw_prefix no_refining_prefix OPERANDS : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP @@ -18184,11 +19055,11 @@ OPERANDS : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=X -###FILE: ../xed/datafiles/avx/avx-isa.txt +###FILE: ../xed/datafiles/clflushopt/clflushopt.xed.txt #BEGIN_LEGAL # -#Copyright (c) 2016 Intel Corporation +#Copyright (c) 2018 Intel Corporation # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -18204,405 +19075,1120 @@ OPERANDS : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=X # #END_LEGAL -# The neat thing is we can just end a nonterminal by starting a new one. +INSTRUCTIONS():: -AVX_INSTRUCTIONS():: { -ICLASS : VADDPD -EXCEPTIONS: avx-type-2 -CPL : 3 -CATEGORY : AVX -EXTENSION : AVX -ATTRIBUTES: MXCSR -PATTERN : VV1 0x58 V66 VL128 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +ICLASS: CLFLUSHOPT +CPL: 3 +CATEGORY: CLFLUSHOPT +EXTENSION: CLFLUSHOPT +ISA_SET: CLFLUSHOPT +ATTRIBUTES: PREFETCH # check TSX-friendlyness +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b111] RM[nnn] osz_refining_prefix REFINING66() MODRM() +OPERANDS : MEM0:r:mprefetch +} -PATTERN : VV1 0x58 V66 VL128 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 -PATTERN : VV1 0x58 V66 VL256 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 -PATTERN : VV1 0x58 V66 VL256 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 -} +###FILE: ../xed/datafiles/rdseed/rdseed-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2018 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: { -ICLASS : VADDPS -EXCEPTIONS: avx-type-2 +ICLASS : RDSEED CPL : 3 -CATEGORY : AVX -EXTENSION : AVX -ATTRIBUTES: MXCSR -PATTERN : VV1 0x58 VNP VL128 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +CATEGORY : RDSEED +EXTENSION : RDSEED +ISA_SET : RDSEED +FLAGS : MUST [ cf-mod zf-0 of-0 af-0 pf-0 sf-0 ] +PATTERN : 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] not_refining +OPERANDS : REG0=GPRv_B():w +} -PATTERN : VV1 0x58 VNP VL128 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 -PATTERN : VV1 0x58 VNP VL256 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 -PATTERN : VV1 0x58 VNP VL256 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 -} +###FILE: ../xed/datafiles/fsgsbase/fsgsbase-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2018 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: { -ICLASS : VADDSD -EXCEPTIONS: avx-type-3 +ICLASS : RDFSBASE CPL : 3 -ATTRIBUTES : simd_scalar MXCSR -CATEGORY : AVX -EXTENSION : AVX -PATTERN : VV1 0x58 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 +CATEGORY : RDWRFSGS +EXTENSION : RDWRFSGS -PATTERN : VV1 0x58 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 -} +PATTERN : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b000] RM[nnn] mode64 f3_refining_prefix +OPERANDS : REG0=GPRy_B():w REG1=XED_REG_FSBASE:r:SUPP:y +} { -ICLASS : VADDSS -EXCEPTIONS: avx-type-3 +ICLASS : RDGSBASE CPL : 3 -ATTRIBUTES : simd_scalar MXCSR -CATEGORY : AVX -EXTENSION : AVX -PATTERN : VV1 0x58 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 +CATEGORY : RDWRFSGS +EXTENSION : RDWRFSGS + +PATTERN : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b001] RM[nnn] mode64 f3_refining_prefix +OPERANDS : REG0=GPRy_B():w REG1=XED_REG_GSBASE:r:SUPP:y -PATTERN : VV1 0x58 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 } + { -ICLASS : VADDSUBPD -EXCEPTIONS: avx-type-2 +ICLASS : WRFSBASE CPL : 3 -CATEGORY : AVX -EXTENSION : AVX -ATTRIBUTES: MXCSR -PATTERN : VV1 0xD0 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 - -PATTERN : VV1 0xD0 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 +CATEGORY : RDWRFSGS +EXTENSION : RDWRFSGS +ATTRIBUTES: NOTSX -PATTERN : VV1 0xD0 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +PATTERN : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b010] RM[nnn] mode64 f3_refining_prefix +OPERANDS : REG0=GPRy_B():r REG1=XED_REG_FSBASE:w:SUPP:y -PATTERN : VV1 0xD0 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 } - { -ICLASS : VADDSUBPS -EXCEPTIONS: avx-type-2 +ICLASS : WRGSBASE CPL : 3 -CATEGORY : AVX -EXTENSION : AVX -ATTRIBUTES: MXCSR -PATTERN : VV1 0xD0 VL128 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 - -PATTERN : VV1 0xD0 VL128 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 +CATEGORY : RDWRFSGS +EXTENSION : RDWRFSGS +ATTRIBUTES: NOTSX -PATTERN : VV1 0xD0 VL256 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +PATTERN : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b011] RM[nnn] mode64 f3_refining_prefix +OPERANDS : REG0=GPRy_B():r REG1=XED_REG_GSBASE:w:SUPP:y -PATTERN : VV1 0xD0 VL256 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 } -{ -ICLASS : VANDPD -EXCEPTIONS: avx-type-4 -CPL : 3 -CATEGORY : LOGICAL_FP -EXTENSION : AVX -PATTERN : VV1 0x54 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 +###FILE: ../xed/datafiles/smap/smap-isa.xed.txt -PATTERN : VV1 0x54 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 +#BEGIN_LEGAL +# +#Copyright (c) 2018 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL -PATTERN : VV1 0x54 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 +INSTRUCTIONS():: -PATTERN : VV1 0x54 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 +{ +ICLASS : CLAC +CPL : 0 +CATEGORY : SMAP +EXTENSION : SMAP +FLAGS : MUST [ ac-0 ] +# 0F 01 CA = 1100_1010 = 11_001_010 +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b010] no_refining_prefix +OPERANDS : } - - { -ICLASS : VANDPS -EXCEPTIONS: avx-type-4 -CPL : 3 -CATEGORY : LOGICAL_FP -EXTENSION : AVX -PATTERN : VV1 0x54 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq - -PATTERN : VV1 0x54 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq +ICLASS : STAC +CPL : 0 +CATEGORY : SMAP +EXTENSION : SMAP +FLAGS : MUST [ ac-1 ] +# 0F 01 CB = 1100_1011 = 11_001_011 +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b011] no_refining_prefix +OPERANDS : +} -PATTERN : VV1 0x54 VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq -PATTERN : VV1 0x54 VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq -} +###FILE: ../xed/datafiles/sgx/sgx-isa.xed.txt -{ -ICLASS : VANDNPD -EXCEPTIONS: avx-type-4 -CPL : 3 -CATEGORY : LOGICAL_FP -EXTENSION : AVX -PATTERN : VV1 0x55 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 +#BEGIN_LEGAL +# +#Copyright (c) 2018 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL -PATTERN : VV1 0x55 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 +INSTRUCTIONS():: -PATTERN : VV1 0x55 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 +# Both read EAX +# Both may read or write or r/w RBX, RCX, RDX +# ENCLU 0f 01 D7 +# D7 = 1101 0111 -PATTERN : VV1 0x55 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 -} +# ENCLS 0f 01 CF +# CF = 1100_1111 { -ICLASS : VANDNPS -EXCEPTIONS: avx-type-4 -CPL : 3 -CATEGORY : LOGICAL_FP -EXTENSION : AVX -PATTERN : VV1 0x55 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq +ICLASS: ENCLU +CPL: 3 +CATEGORY: SGX +EXTENSION: SGX +ISA_SET: SGX +COMMENT: May set flags +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b111] no_refining_prefix +OPERANDS: REG0=XED_REG_EAX:r:SUPP \ + REG1=XED_REG_RBX:crw:SUPP \ + REG2=XED_REG_RCX:crw:SUPP \ + REG3=XED_REG_RDX:crw:SUPP +} -PATTERN : VV1 0x55 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq +{ -PATTERN : VV1 0x55 VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq +ICLASS: ENCLS +CPL: 0 +CATEGORY: SGX +EXTENSION: SGX +ISA_SET: SGX +COMMENT: May set flags +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b111] no_refining_prefix +OPERANDS: REG0=XED_REG_EAX:r:SUPP \ + REG1=XED_REG_RBX:crw:SUPP \ + REG2=XED_REG_RCX:crw:SUPP \ + REG3=XED_REG_RDX:crw:SUPP -PATTERN : VV1 0x55 VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq } +###FILE: ../xed/datafiles/rdpid/rdpid-isa.xed.txt +#BEGIN_LEGAL +# +#Copyright (c) 2018 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +INSTRUCTIONS():: +# EMITTING RDPID (RDPID-N/A-1-32) { -ICLASS : VBLENDPD -EXCEPTIONS: avx-type-4 -CPL : 3 -CATEGORY : AVX -EXTENSION : AVX -PATTERN : VV1 0x0D VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() -OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 IMM0:r:b - -PATTERN : VV1 0x0D VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() -OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 IMM0:r:b - -PATTERN : VV1 0x0D VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() -OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 IMM0:r:b - -PATTERN : VV1 0x0D VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() -OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 IMM0:r:b +ICLASS: RDPID +CPL: 3 +CATEGORY: RDPID +EXTENSION: RDPID +ISA_SET: RDPID +REAL_OPCODE: Y +PATTERN: 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] f3_refining_prefix not64 +OPERANDS: REG0=GPR32_B():w:d:u32 REG1=XED_REG_TSCAUX:r:SUPP:d:u32 +IFORM: RDPID_GPR32u32 } +# EMITTING RDPID (RDPID-N/A-1-64) { -ICLASS : VBLENDPS -EXCEPTIONS: avx-type-4 -CPL : 3 -CATEGORY : AVX -EXTENSION : AVX -PATTERN : VV1 0x0C VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() -OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 IMM0:r:b - -PATTERN : VV1 0x0C VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() -OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 IMM0:r:b - -PATTERN : VV1 0x0C VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() -OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 IMM0:r:b - -PATTERN : VV1 0x0C VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() -OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 IMM0:r:b +ICLASS: RDPID +CPL: 3 +CATEGORY: RDPID +EXTENSION: RDPID +ISA_SET: RDPID +REAL_OPCODE: Y +PATTERN: 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] f3_refining_prefix mode64 +OPERANDS: REG0=GPR64_B():w:q:u64 REG1=XED_REG_TSCAUX:r:SUPP:d:u32 +IFORM: RDPID_GPR64u64 } +###FILE: ../xed/datafiles/pt/intelpt-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2018 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: { -ICLASS : VCMPPD -EXCEPTIONS: avx-type-2 +ICLASS : PTWRITE CPL : 3 -CATEGORY : AVX -EXTENSION : AVX -ATTRIBUTES: MXCSR -PATTERN : VV1 0xC2 V66 VL128 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() -OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 IMM0:r:b - -PATTERN : VV1 0xC2 V66 VL128 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() -OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 IMM0:r:b - -PATTERN : VV1 0xC2 V66 VL256 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() -OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 IMM0:r:b +CATEGORY : PT +EXTENSION : PT +PATTERN : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix no66_prefix +OPERANDS : REG0=GPRy_B():r +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b100] RM[nnn] f3_refining_prefix no66_prefix MODRM() +OPERANDS : MEM0:r:y -PATTERN : VV1 0xC2 V66 VL256 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() -OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 IMM0:r:b } +###FILE: ../xed/datafiles/movdir/movdir-isa.xed.txt +#BEGIN_LEGAL +# +#Copyright (c) 2018 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +INSTRUCTIONS():: +# EMITTING MOVDIR64B (MOVDIR64B-N/A-1) { -ICLASS : VCMPPS -EXCEPTIONS: avx-type-2 -CPL : 3 -CATEGORY : AVX -EXTENSION : AVX -ATTRIBUTES: MXCSR -PATTERN : VV1 0xC2 VNP VL128 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() -OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 IMM0:r:b +ICLASS: MOVDIR64B +CPL: 3 +CATEGORY: MOVDIR +EXTENSION: MOVDIR +ISA_SET: MOVDIR +REAL_OPCODE: Y +ATTRIBUTES: REQUIRES_ALIGNMENT +PATTERN: 0x0F 0x38 0xF8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix not64 +OPERANDS: REG0=A_GPR_R():r MEM0:r:zd:u32 MEM1:w:zd:SUPP BASE1=A_GPR_R():r:SUPP SEG1=XED_REG_ES:r:SUPP +IFORM: MOVDIR64B_GPRa_MEM -PATTERN : VV1 0xC2 VNP VL128 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() -OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 IMM0:r:b +PATTERN: 0x0F 0x38 0xF8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix mode64 +OPERANDS: REG0=A_GPR_R():r MEM0:r:zd:u32 MEM1:w:zd:SUPP BASE1=A_GPR_R():r:SUPP +IFORM: MOVDIR64B_GPRa_MEM +} -PATTERN : VV1 0xC2 VNP VL256 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() -OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 IMM0:r:b -PATTERN : VV1 0xC2 VNP VL256 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() -OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 IMM0:r:b +# EMITTING MOVDIRI (MOVDIRI-N/A-1-32) +{ +ICLASS: MOVDIRI +CPL: 3 +CATEGORY: MOVDIR +EXTENSION: MOVDIR +ISA_SET: MOVDIR +REAL_OPCODE: Y +PATTERN: 0x0F 0x38 0xF9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix norexw_prefix +OPERANDS: MEM0:w:d:u32 REG0=GPR32_R():r:d:u32 +IFORM: MOVDIRI_MEMu32_GPR32u32 } - +# EMITTING MOVDIRI (MOVDIRI-N/A-1-64) { -ICLASS : VCMPSD -EXCEPTIONS: avx-type-3 -CPL : 3 -CATEGORY : AVX -EXTENSION : AVX -ATTRIBUTES : simd_scalar MXCSR -PATTERN : VV1 0xC2 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() -OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 IMM0:r:b - -PATTERN : VV1 0xC2 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() -OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 IMM0:r:b +ICLASS: MOVDIRI +CPL: 3 +CATEGORY: MOVDIR +EXTENSION: MOVDIR +ISA_SET: MOVDIR +REAL_OPCODE: Y +PATTERN: 0x0F 0x38 0xF9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 rexw_prefix +OPERANDS: MEM0:w:q:u64 REG0=GPR64_R():r:q:u64 +IFORM: MOVDIRI_MEMu64_GPR64u64 } -{ -ICLASS : VCMPSS -EXCEPTIONS: avx-type-3 -CPL : 3 -CATEGORY : AVX -EXTENSION : AVX - -ATTRIBUTES : simd_scalar MXCSR -PATTERN : VV1 0xC2 VF3 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() -OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 IMM0:r:b +###FILE: ../xed/datafiles/waitpkg/waitpkg-isa.xed.txt -PATTERN : VV1 0xC2 VF3 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() -OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 IMM0:r:b +#BEGIN_LEGAL +# +#Copyright (c) 2018 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +INSTRUCTIONS():: +# EMITTING TPAUSE (TPAUSE-N/A-1-32) +{ +ICLASS: TPAUSE +CPL: 3 +CATEGORY: WAITPKG +EXTENSION: WAITPKG +ISA_SET: WAITPKG +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-0 pf-0 af-0 sf-0 of-0 ] +PATTERN: 0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] osz_refining_prefix norexw_prefix +OPERANDS: REG0=GPR32_B():r:d:u32 REG1=XED_REG_EDX:r:SUPP:d:u32 REG2=XED_REG_EAX:r:SUPP:d:u32 +IFORM: TPAUSE_GPR32u32 } +# EMITTING TPAUSE (TPAUSE-N/A-1-64) { -ICLASS : VCOMISD -EXCEPTIONS: avx-type-3 -CPL : 3 -CATEGORY : AVX -EXTENSION : AVX -ATTRIBUTES : simd_scalar MXCSR +ICLASS: TPAUSE +CPL: 3 +CATEGORY: WAITPKG +EXTENSION: WAITPKG +ISA_SET: WAITPKG +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-0 pf-0 af-0 sf-0 of-0 ] +PATTERN: 0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] osz_refining_prefix mode64 rexw_prefix +OPERANDS: REG0=GPR64_B():r:q:u64 REG1=XED_REG_EDX:r:SUPP:d:u32 REG2=XED_REG_EAX:r:SUPP:d:u32 +IFORM: TPAUSE_GPR64u64 +} -FLAGS : MUST [ zf-mod pf-mod cf-mod of-0 af-0 sf-0 ] -PATTERN : VV1 0x2F V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():r:q:f64 MEM0:r:q:f64 -PATTERN : VV1 0x2F V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():r:q:f64 REG1=XMM_B():r:q:f64 +# EMITTING UMONITOR (UMONITOR-N/A-1) +{ +ICLASS: UMONITOR +CPL: 3 +CATEGORY: WAITPKG +EXTENSION: WAITPKG +ISA_SET: WAITPKG +REAL_OPCODE: Y +PATTERN: 0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix +OPERANDS: REG0=A_GPR_B():r +IFORM: UMONITOR_GPRa } + +# EMITTING UMWAIT (UMWAIT-N/A-1-32) { -ICLASS : VCOMISS -EXCEPTIONS: avx-type-3 -CPL : 3 -CATEGORY : AVX -EXTENSION : AVX -ATTRIBUTES : simd_scalar MXCSR +ICLASS: UMWAIT +CPL: 3 +CATEGORY: WAITPKG +EXTENSION: WAITPKG +ISA_SET: WAITPKG +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-0 pf-0 af-0 sf-0 of-0 ] +PATTERN: 0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] f2_refining_prefix norexw_prefix +OPERANDS: REG0=GPR32_B():r:d:u32 REG1=XED_REG_EDX:r:SUPP:d:u32 REG2=XED_REG_EAX:r:SUPP:d:u32 +IFORM: UMWAIT_GPR32 +} -FLAGS : MUST [ zf-mod pf-mod cf-mod of-0 af-0 sf-0 ] -PATTERN : VV1 0x2F VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():r:d:f32 MEM0:r:d:f32 -PATTERN : VV1 0x2F VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():r:d:f32 REG1=XMM_B():r:d:f32 +# EMITTING UMWAIT (UMWAIT-N/A-1-64) +{ +ICLASS: UMWAIT +CPL: 3 +CATEGORY: WAITPKG +EXTENSION: WAITPKG +ISA_SET: WAITPKG +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-0 pf-0 af-0 sf-0 of-0 ] +PATTERN: 0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] f2_refining_prefix mode64 rexw_prefix +OPERANDS: REG0=GPR64_B():r:q:u64 REG1=XED_REG_EDX:r:SUPP:d:u32 REG2=XED_REG_EAX:r:SUPP:d:u32 +IFORM: UMWAIT_GPR64 } -{ -ICLASS : VCVTDQ2PD -EXCEPTIONS: avx-type-5 -CPL : 3 -CATEGORY : CONVERT -EXTENSION : AVX -ATTRIBUTES: MXCSR -PATTERN : VV1 0xE6 VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:q:i32 -PATTERN : VV1 0xE6 VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:q:i32 -PATTERN : VV1 0xE6 VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:dq:i32 +###FILE: ../xed/datafiles/cldemote/cldemote-nop-mod.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2018 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL -PATTERN : VV1 0xE6 VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:f64 REG1=XMM_B():r:dq:i32 -} + +INSTRUCTIONS():: + +UDELETE: NOP0F1C { -ICLASS : VCVTDQ2PS -EXCEPTIONS: avx-type-2 +ICLASS : NOP +#UNAME : NOP0F1C CPL : 3 -CATEGORY : CONVERT -EXTENSION : AVX -ATTRIBUTES: MXCSR -PATTERN : VV1 0x5B VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:i32 - -PATTERN : VV1 0x5B VL128 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:i32 +CATEGORY : WIDENOP +EXTENSION : BASE +ATTRIBUTES: NOP +ISA_SET : PPRO +COMMENT : memory form with MODRM.REG=0b000 and no refining prefix is CLDEMOTE +PATTERN : 0x0F 0x1C MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() f2_refining_prefix +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F1C +PATTERN : 0x0F 0x1C MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() f3_refining_prefix +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F1C +PATTERN : 0x0F 0x1C MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() osz_refining_prefix +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F1C -PATTERN : VV1 0x5B VL256 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:i32 -PATTERN : VV1 0x5B VL256 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:i32 +PATTERN : 0x0F 0x1C MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F1C +PATTERN : 0x0F 0x1C MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F1C +PATTERN : 0x0F 0x1C MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F1C +PATTERN : 0x0F 0x1C MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F1C +PATTERN : 0x0F 0x1C MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F1C +PATTERN : 0x0F 0x1C MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F1C +PATTERN : 0x0F 0x1C MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F1C } +# re-defined by another contemporaneous ISA extension { -ICLASS : VCVTPD2DQ -EXCEPTIONS: avx-type-2 +ICLASS : NOP +UNAME : NOP0F1C_REG CPL : 3 -CATEGORY : CONVERT -EXTENSION : AVX -ATTRIBUTES: MXCSR +CATEGORY : WIDENOP +EXTENSION : BASE +ATTRIBUTES: NOP +ISA_SET : PPRO + +# reg form +PATTERN : 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1C +} + +{ +ICLASS : NOP +UNAME : NOP0F1C_MEM +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +ATTRIBUTES: NOP +ISA_SET : PPRO + +PATTERN : 0x0F 0x1C MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() no_refining_prefix CLDEMOTE=0 +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F1C +} + + + +###FILE: ../xed/datafiles/cldemote/cldemote-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2018 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +INSTRUCTIONS():: +# EMITTING CLDEMOTE (CLDEMOTE-N/A-1) +{ +ICLASS: CLDEMOTE +CPL: 3 +CATEGORY: CLDEMOTE +EXTENSION: CLDEMOTE +ISA_SET: CLDEMOTE +REAL_OPCODE: Y +PATTERN: 0x0F 0x1C MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() no_refining_prefix CLDEMOTE=1 +OPERANDS: MEM0:r:b:u8 +IFORM: CLDEMOTE_MEMu8 +} + + + + +###FILE: ../xed/datafiles/sgx-enclv/sgx-enclv-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2018 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +INSTRUCTIONS():: +# EMITTING ENCLV (ENCLV-N/A-1) +{ +ICLASS: ENCLV +CPL: 3 +CATEGORY: SGX +EXTENSION: SGX_ENCLV +ISA_SET: SGX_ENCLV +REAL_OPCODE: Y +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b000] no_refining_prefix +OPERANDS: REG0=XED_REG_EAX:r:SUPP:d:u32 REG1=XED_REG_RBX:crw:SUPP:q:u64 REG2=XED_REG_RCX:crw:SUPP:q:u64 REG3=XED_REG_RDX:crw:SUPP:q:u64 +IFORM: ENCLV +} + + + + +###FILE: ../xed/datafiles/avx/avx-isa.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2018 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +# The neat thing is we can just end a nonterminal by starting a new one. + +AVX_INSTRUCTIONS():: +{ +ICLASS : VADDPD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x58 V66 VL128 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 + +PATTERN : VV1 0x58 V66 VL128 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + +PATTERN : VV1 0x58 V66 VL256 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 + +PATTERN : VV1 0x58 V66 VL256 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} + + +{ +ICLASS : VADDPS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x58 VNP VL128 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0x58 VNP VL128 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +PATTERN : VV1 0x58 VNP VL256 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x58 VNP VL256 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} + + +{ +ICLASS : VADDSD +EXCEPTIONS: avx-type-3 +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x58 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 + +PATTERN : VV1 0x58 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 +} + +{ +ICLASS : VADDSS +EXCEPTIONS: avx-type-3 +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x58 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 + +PATTERN : VV1 0x58 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 +} + + +{ +ICLASS : VADDSUBPD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0xD0 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 + +PATTERN : VV1 0xD0 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + +PATTERN : VV1 0xD0 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 + +PATTERN : VV1 0xD0 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} + +{ +ICLASS : VADDSUBPS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0xD0 VL128 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0xD0 VL128 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +PATTERN : VV1 0xD0 VL256 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0xD0 VL256 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} + + +{ +ICLASS : VANDPD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : AVX +PATTERN : VV1 0x54 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 + +PATTERN : VV1 0x54 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 + +PATTERN : VV1 0x54 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 + +PATTERN : VV1 0x54 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 +} + + + +{ +ICLASS : VANDPS +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : AVX +PATTERN : VV1 0x54 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq + +PATTERN : VV1 0x54 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq + +PATTERN : VV1 0x54 VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq + +PATTERN : VV1 0x54 VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq +} + + +{ +ICLASS : VANDNPD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : AVX +PATTERN : VV1 0x55 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 + +PATTERN : VV1 0x55 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 + +PATTERN : VV1 0x55 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 + +PATTERN : VV1 0x55 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 +} + + + +{ +ICLASS : VANDNPS +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : AVX +PATTERN : VV1 0x55 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq + +PATTERN : VV1 0x55 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq + +PATTERN : VV1 0x55 VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq + +PATTERN : VV1 0x55 VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq +} + + + +{ +ICLASS : VBLENDPD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x0D VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 IMM0:r:b + +PATTERN : VV1 0x0D VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 IMM0:r:b + +PATTERN : VV1 0x0D VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 IMM0:r:b + +PATTERN : VV1 0x0D VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 IMM0:r:b +} + + +{ +ICLASS : VBLENDPS +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x0C VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 IMM0:r:b + +PATTERN : VV1 0x0C VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 IMM0:r:b + +PATTERN : VV1 0x0C VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 IMM0:r:b + +PATTERN : VV1 0x0C VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 IMM0:r:b +} + + + + + + +{ +ICLASS : VCMPPD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0xC2 V66 VL128 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 IMM0:r:b + +PATTERN : VV1 0xC2 V66 VL128 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 IMM0:r:b + +PATTERN : VV1 0xC2 V66 VL256 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 IMM0:r:b + +PATTERN : VV1 0xC2 V66 VL256 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 IMM0:r:b +} + + + +{ +ICLASS : VCMPPS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0xC2 VNP VL128 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 IMM0:r:b + +PATTERN : VV1 0xC2 VNP VL128 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 IMM0:r:b + +PATTERN : VV1 0xC2 VNP VL256 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 IMM0:r:b + +PATTERN : VV1 0xC2 VNP VL256 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 IMM0:r:b +} + + + +{ +ICLASS : VCMPSD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR +PATTERN : VV1 0xC2 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 IMM0:r:b + +PATTERN : VV1 0xC2 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 IMM0:r:b +} + + + +{ +ICLASS : VCMPSS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX + +ATTRIBUTES : simd_scalar MXCSR + +PATTERN : VV1 0xC2 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 IMM0:r:b + +PATTERN : VV1 0xC2 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 IMM0:r:b +} + + +{ +ICLASS : VCOMISD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR + +FLAGS : MUST [ zf-mod pf-mod cf-mod of-0 af-0 sf-0 ] +PATTERN : VV1 0x2F V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():r:q:f64 MEM0:r:q:f64 + +PATTERN : VV1 0x2F V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():r:q:f64 REG1=XMM_B():r:q:f64 +} + +{ +ICLASS : VCOMISS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR + +FLAGS : MUST [ zf-mod pf-mod cf-mod of-0 af-0 sf-0 ] +PATTERN : VV1 0x2F VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():r:d:f32 MEM0:r:d:f32 + +PATTERN : VV1 0x2F VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():r:d:f32 REG1=XMM_B():r:d:f32 +} + + +{ +ICLASS : VCVTDQ2PD +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : CONVERT +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0xE6 VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:q:i32 + +PATTERN : VV1 0xE6 VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:q:i32 + +PATTERN : VV1 0xE6 VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:dq:i32 + +PATTERN : VV1 0xE6 VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=XMM_B():r:dq:i32 +} + +{ +ICLASS : VCVTDQ2PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : CONVERT +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x5B VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:i32 + +PATTERN : VV1 0x5B VL128 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:i32 + +PATTERN : VV1 0x5B VL256 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:i32 + +PATTERN : VV1 0x5B VL256 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:i32 +} + +{ +ICLASS : VCVTPD2DQ +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : CONVERT +EXTENSION : AVX +ATTRIBUTES: MXCSR PATTERN : VV1 0xE6 VL128 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:dq:f64 @@ -18728,26 +20314,27 @@ CPL : 3 CATEGORY : CONVERT EXTENSION : AVX ATTRIBUTES : simd_scalar MXCSR +COMMENT : SNB/IVB/HSW require VEX.L=128. Later processors are LIG -PATTERN : VV1 0x2D VF2 V0F VL128 NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +PATTERN : VV1 0x2D VF2 V0F NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:q:f64 -PATTERN : VV1 0x2D VF2 V0F VL128 NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +PATTERN : VV1 0x2D VF2 V0F NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:q:f64 -PATTERN : VV1 0x2D VF2 V0F VL128 NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +PATTERN : VV1 0x2D VF2 V0F NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:q:f64 -PATTERN : VV1 0x2D VF2 V0F VL128 NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +PATTERN : VV1 0x2D VF2 V0F NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:q:f64 -PATTERN : VV1 0x2D VF2 V0F VL128 NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +PATTERN : VV1 0x2D VF2 V0F NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=GPR64_R():w:q:i64 MEM0:r:q:f64 -PATTERN : VV1 0x2D VF2 V0F VL128 NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +PATTERN : VV1 0x2D VF2 V0F NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:q:f64 } @@ -18758,27 +20345,29 @@ CPL : 3 CATEGORY : CONVERT EXTENSION : AVX ATTRIBUTES : simd_scalar MXCSR +COMMENT : SNB/IVB/HSW require VEX.L=128. Later processors are LIG + -PATTERN : VV1 0x2C VF2 V0F VL128 NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +PATTERN : VV1 0x2C VF2 V0F NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:q:f64 -PATTERN : VV1 0x2C VF2 V0F VL128 NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +PATTERN : VV1 0x2C VF2 V0F NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:q:f64 -PATTERN : VV1 0x2C VF2 V0F VL128 NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +PATTERN : VV1 0x2C VF2 V0F NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:q:f64 -PATTERN : VV1 0x2C VF2 V0F VL128 NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +PATTERN : VV1 0x2C VF2 V0F NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:q:f64 -PATTERN : VV1 0x2C VF2 V0F VL128 NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +PATTERN : VV1 0x2C VF2 V0F NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=GPR64_R():w:q:i64 MEM0:r:q:f64 -PATTERN : VV1 0x2C VF2 V0F VL128 NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +PATTERN : VV1 0x2C VF2 V0F NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:q:f64 } @@ -18792,26 +20381,27 @@ CPL : 3 CATEGORY : CONVERT EXTENSION : AVX ATTRIBUTES : simd_scalar MXCSR +COMMENT : SNB/IVB/HSW require VEX.L=128. Later processors are LIG -PATTERN : VV1 0x2D VF3 V0F VL128 NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +PATTERN : VV1 0x2D VF3 V0F NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:d:f32 -PATTERN : VV1 0x2D VF3 V0F VL128 NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +PATTERN : VV1 0x2D VF3 V0F NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:d:f32 -PATTERN : VV1 0x2D VF3 V0F VL128 NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +PATTERN : VV1 0x2D VF3 V0F NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:d:f32 -PATTERN : VV1 0x2D VF3 V0F VL128 NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +PATTERN : VV1 0x2D VF3 V0F NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:d:f32 -PATTERN : VV1 0x2D VF3 V0F VL128 NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +PATTERN : VV1 0x2D VF3 V0F NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=GPR64_R():w:q:i64 MEM0:r:d:f32 -PATTERN : VV1 0x2D VF3 V0F VL128 NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +PATTERN : VV1 0x2D VF3 V0F NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:d:f32 } @@ -18822,28 +20412,29 @@ CPL : 3 CATEGORY : CONVERT EXTENSION : AVX ATTRIBUTES : simd_scalar MXCSR +COMMENT : SNB/IVB/HSW require VEX.L=128. Later processors are LIG -PATTERN : VV1 0x2C VF3 V0F VL128 NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +PATTERN : VV1 0x2C VF3 V0F NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:d:f32 -PATTERN : VV1 0x2C VF3 V0F VL128 NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +PATTERN : VV1 0x2C VF3 V0F NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:d:f32 -PATTERN : VV1 0x2C VF3 V0F VL128 NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +PATTERN : VV1 0x2C VF3 V0F NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:d:f32 -PATTERN : VV1 0x2C VF3 V0F VL128 NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +PATTERN : VV1 0x2C VF3 V0F NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:d:f32 -PATTERN : VV1 0x2C VF3 V0F VL128 NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +PATTERN : VV1 0x2C VF3 V0F NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=GPR64_R():w:q:i64 MEM0:r:d:f32 -PATTERN : VV1 0x2C VF3 V0F VL128 NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +PATTERN : VV1 0x2C VF3 V0F NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:d:f32 } @@ -19378,7 +20969,7 @@ EXCEPTIONS: avx-type-6 CPL : 3 CATEGORY : AVX EXTENSION : AVX -ATTRIBUTES : maskop +ATTRIBUTES : maskop NONTEMPORAL # load forms PATTERN : VV1 0x2C V66 VL128 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq MEM0:r:dq:f32 @@ -22266,9 +23857,9 @@ EXCEPTIONS: avx-type-5 CPL : 3 CATEGORY : AVX EXTENSION : AVX -PATTERN : VV1 0x16 VL128 V66 V0F3A rexw_prefix mode64 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +PATTERN : VV1 0x16 VL128 V66 V0F3A mode64 rexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() OPERANDS : MEM0:w:q REG0=XMM_R():r:dq:u64 IMM0:r:b -PATTERN : VV1 0x16 VL128 V66 V0F3A rexw_prefix mode64 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +PATTERN : VV1 0x16 VL128 V66 V0F3A mode64 rexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() OPERANDS : REG0=GPR64_B():w:q REG1=XMM_R():r:dq:u64 IMM0:r:b } ############################################################################ @@ -22278,10 +23869,20 @@ EXCEPTIONS: avx-type-5 CPL : 3 CATEGORY : AVX EXTENSION : AVX -PATTERN : VV1 0x16 VL128 V66 V0F3A norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() -OPERANDS : MEM0:w:d REG0=XMM_R():r:dq:u32 IMM0:r:b -PATTERN : VV1 0x16 VL128 V66 V0F3A norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +COMMENT : SNB had an errata where it would #UD of VEX.W=1 outside of 64b mode. Not modeled. + +# 64b mode +PATTERN : VV1 0x16 VL128 V66 V0F3A mode64 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:w:d REG0=XMM_R():r:dq:u32 IMM0:r:b +PATTERN : VV1 0x16 VL128 V66 V0F3A mode64 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=GPR32_B():w:d REG1=XMM_R():r:dq:u32 IMM0:r:b + +# not64b mode +PATTERN : VV1 0x16 VL128 V66 V0F3A not64 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:w:d REG0=XMM_R():r:dq:u32 IMM0:r:b +PATTERN : VV1 0x16 VL128 V66 V0F3A not64 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() OPERANDS : REG0=GPR32_B():w:d REG1=XMM_R():r:dq:u32 IMM0:r:b + } ############################################################################ @@ -22323,9 +23924,17 @@ EXCEPTIONS: avx-type-5 CPL : 3 CATEGORY : AVX EXTENSION : AVX -PATTERN : VV1 0x22 VL128 V66 V0F3A norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +COMMENT : SNB had an errata where it would #UD of VEX.W=1 outside of 64b mode. Not modeled +# 64b mode +PATTERN : VV1 0x22 VL128 V66 V0F3A mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:d:u32 IMM0:r:b +PATTERN : VV1 0x22 VL128 V66 V0F3A mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=GPR32_B():r:d:u32 IMM0:r:b + +# 32b mode +PATTERN : VV1 0x22 VL128 V66 V0F3A not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:d:u32 IMM0:r:b -PATTERN : VV1 0x22 VL128 V66 V0F3A norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +PATTERN : VV1 0x22 VL128 V66 V0F3A not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=GPR32_B():r:d:u32 IMM0:r:b } { @@ -22334,9 +23943,9 @@ EXCEPTIONS: avx-type-5 CPL : 3 CATEGORY : AVX EXTENSION : AVX -PATTERN : VV1 0x22 VL128 V66 V0F3A rexw_prefix mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +PATTERN : VV1 0x22 VL128 V66 V0F3A mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:q:u64 IMM0:r:b -PATTERN : VV1 0x22 VL128 V66 V0F3A rexw_prefix mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +PATTERN : VV1 0x22 VL128 V66 V0F3A mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=GPR64_B():r:q:u64 IMM0:r:b } @@ -22361,14 +23970,23 @@ PATTERN : VV1 0x61 VL128 V66 V0F3A NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_ECX:w:SUPP # in 64b mode, vex.w changes the behavior for GPRs -PATTERN : VV1 0x61 VL128 V66 V0F3A NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +PATTERN : VV1 0x61 VL128 V66 V0F3A NOVSR mode64 EOSZ=2 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_EDX:r:SUPP REG3=XED_REG_ECX:w:SUPP -PATTERN : VV1 0x61 VL128 V66 V0F3A NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +PATTERN : VV1 0x61 VL128 V66 V0F3A NOVSR mode64 EOSZ=2 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_ECX:w:SUPP +} +{ +ICLASS : VPCMPESTRI + +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : STTNI +EXTENSION : AVX +FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] -PATTERN : VV1 0x61 VL128 V66 V0F3A NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +PATTERN : VV1 0x61 VL128 V66 V0F3A NOVSR mode64 EOSZ=3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_RAX:r:SUPP REG2=XED_REG_RDX:r:SUPP REG3=XED_REG_RCX:w:SUPP -PATTERN : VV1 0x61 VL128 V66 V0F3A NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +PATTERN : VV1 0x61 VL128 V66 V0F3A NOVSR mode64 EOSZ=3 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_RAX:r:SUPP REG3=XED_REG_RDX:r:SUPP REG4=XED_REG_RCX:w:SUPP } { @@ -22386,14 +24004,22 @@ PATTERN : VV1 0x63 VL128 V66 V0F3A NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nn OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_ECX:w:SUPP # in 64b mode, vex.w changes the behavior for GPRs -PATTERN : VV1 0x63 VL128 V66 V0F3A NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +PATTERN : VV1 0x63 VL128 V66 V0F3A NOVSR mode64 EOSZ=2 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_ECX:w:SUPP -PATTERN : VV1 0x63 VL128 V66 V0F3A NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +PATTERN : VV1 0x63 VL128 V66 V0F3A NOVSR mode64 EOSZ=2 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_ECX:w:SUPP +} +{ +ICLASS : VPCMPISTRI +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : STTNI +EXTENSION : AVX +FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] -PATTERN : VV1 0x63 VL128 V66 V0F3A NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +PATTERN : VV1 0x63 VL128 V66 V0F3A NOVSR mode64 EOSZ=3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_RCX:w:SUPP -PATTERN : VV1 0x63 VL128 V66 V0F3A NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +PATTERN : VV1 0x63 VL128 V66 V0F3A NOVSR mode64 EOSZ=3 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_RCX:w:SUPP } @@ -22412,14 +24038,23 @@ PATTERN : VV1 0x60 VL128 V66 V0F3A NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_XMM0:w:dq:SUPP # in 64b mode, vex.w changes the behavior for GPRs -PATTERN : VV1 0x60 VL128 V66 V0F3A NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +PATTERN : VV1 0x60 VL128 V66 V0F3A NOVSR mode64 EOSZ=2 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_EDX:r:SUPP REG3=XED_REG_XMM0:w:dq:SUPP -PATTERN : VV1 0x60 VL128 V66 V0F3A NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +PATTERN : VV1 0x60 VL128 V66 V0F3A NOVSR mode64 EOSZ=2 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_XMM0:w:dq:SUPP +} + +{ +ICLASS : VPCMPESTRM +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : STTNI +EXTENSION : AVX +FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] -PATTERN : VV1 0x60 VL128 V66 V0F3A NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +PATTERN : VV1 0x60 VL128 V66 V0F3A NOVSR mode64 EOSZ=3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_RAX:r:SUPP REG2=XED_REG_RDX:r:SUPP REG3=XED_REG_XMM0:w:dq:SUPP -PATTERN : VV1 0x60 VL128 V66 V0F3A NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +PATTERN : VV1 0x60 VL128 V66 V0F3A NOVSR mode64 EOSZ=3 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_RAX:r:SUPP REG3=XED_REG_RDX:r:SUPP REG4=XED_REG_XMM0:w:dq:SUPP } @@ -22444,9 +24079,10 @@ OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_XMM0:w ICLASS : VMASKMOVDQU EXCEPTIONS: avx-type-4 CPL : 3 + CATEGORY : AVX EXTENSION : AVX -ATTRIBUTES : maskop fixed_base0 NOTSX +ATTRIBUTES : maskop fixed_base0 NOTSX NONTEMPORAL PATTERN : VV1 0xF7 V0F V66 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] OPERANDS : REG0=XMM_R():r:dq:u8 REG1=XMM_B():r:dq:u8 MEM0:w:SUPP:dq:u8 BASE0=ArDI():r:SUPP SEG0=FINAL_DSEG():r:SUPP } @@ -22459,7 +24095,7 @@ CPL : 3 CATEGORY : AVX EXTENSION : AVX ATTRIBUTES: MXCSR -PATTERN : VV1 0xAE VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[0b010] RM[nnn] no_refining_prefix MODRM() +PATTERN : VV1 0xAE VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() OPERANDS : MEM0:r:d REG0=XED_REG_MXCSR:w:SUPP } { @@ -22469,7 +24105,7 @@ CPL : 3 CATEGORY : AVX EXTENSION : AVX ATTRIBUTES: MXCSR_RD -PATTERN : VV1 0xAE VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[0b011] RM[nnn] no_refining_prefix MODRM() +PATTERN : VV1 0xAE VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() OPERANDS : MEM0:w:d REG0=XED_REG_MXCSR:r:SUPP } ####################################################################################### @@ -22544,7 +24180,7 @@ EXCEPTIONS: avx-type-1 CPL : 3 CATEGORY : DATAXFER EXTENSION : AVX -ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX +ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX NONTEMPORAL PATTERN : VV1 0x2A V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq @@ -22560,7 +24196,7 @@ EXCEPTIONS: avx-type-1 CPL : 3 CATEGORY : DATAXFER EXTENSION : AVX -ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX +ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX NONTEMPORAL PATTERN : VV1 0xE7 V66 V0F VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : MEM0:w:dq:i32 REG0=XMM_R():r:dq:i32 @@ -22571,7 +24207,7 @@ EXCEPTIONS: avx-type-1 CPL : 3 CATEGORY : DATAXFER EXTENSION : AVX -ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX +ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX NONTEMPORAL PATTERN : VV1 0x2B V66 V0F VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : MEM0:w:dq:f64 REG0=XMM_R():r:dq:f64 @@ -22582,7 +24218,7 @@ EXCEPTIONS: avx-type-1 CPL : 3 CATEGORY : DATAXFER EXTENSION : AVX -ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX +ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX NONTEMPORAL PATTERN : VV1 0x2B VNP V0F VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : MEM0:w:dq:f32 REG0=XMM_R():r:dq:f32 @@ -22594,7 +24230,7 @@ OPERANDS : MEM0:w:dq:f32 REG0=XMM_R():r:dq:f32 #BEGIN_LEGAL # -#Copyright (c) 2016 Intel Corporation +#Copyright (c) 2018 Intel Corporation # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -22618,7 +24254,7 @@ EXCEPTIONS: avx-type-1 CPL : 3 CATEGORY : DATAXFER EXTENSION : AVX -ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX +ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX NONTEMPORAL PATTERN : VV1 0xE7 V66 V0F VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : MEM0:w:qq:i32 REG0=YMM_R():r:qq:i32 @@ -22629,7 +24265,7 @@ EXCEPTIONS: avx-type-1 CPL : 3 CATEGORY : DATAXFER EXTENSION : AVX -ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX +ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX NONTEMPORAL PATTERN : VV1 0x2B V66 V0F VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : MEM0:w:qq:f64 REG0=YMM_R():r:qq:f64 @@ -22640,7 +24276,7 @@ EXCEPTIONS: avx-type-1 CPL : 3 CATEGORY : DATAXFER EXTENSION : AVX -ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX +ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX NONTEMPORAL PATTERN : VV1 0x2B VNP V0F VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : MEM0:w:qq:f32 REG0=YMM_R():r:qq:f32 @@ -22652,7 +24288,7 @@ OPERANDS : MEM0:w:qq:f32 REG0=YMM_R():r:qq:f32 #BEGIN_LEGAL # -#Copyright (c) 2016 Intel Corporation +#Copyright (c) 2018 Intel Corporation # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -22742,7 +24378,7 @@ OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq #BEGIN_LEGAL # -#Copyright (c) 2016 Intel Corporation +#Copyright (c) 2018 Intel Corporation # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -22775,7 +24411,7 @@ OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 IMM0:r:b #BEGIN_LEGAL # -#Copyright (c) 2016 Intel Corporation +#Copyright (c) 2018 Intel Corporation # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -22846,11 +24482,11 @@ OPERANDS : REG0=XMM_B():w:dq:f16 REG1=YMM_R():r:qq:f32 IMM0:r:b -###FILE: ../xed/datafiles/avxhsw/gather-isa.txt +###FILE: ../xed/datafiles/hswavx/avx-fma-isa.xed.txt #BEGIN_LEGAL # -#Copyright (c) 2016 Intel Corporation +#Copyright (c) 2018 Intel Corporation # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -22867,2537 +24503,3263 @@ OPERANDS : REG0=XMM_B():w:dq:f16 REG1=YMM_R():r:qq:f32 IMM0:r:b #END_LEGAL AVX_INSTRUCTIONS():: +# Issues: encoder is at a loss for vmaddps xmm0,xmm0,xmm0,xmm0. +# Encoder must enforce equality between two parameters. Never had to do this before. +# Extra check? +# Decoder must rip off suffixes _DDMR, _DDRM, _DRMD in disassembly (eventually) +############################################################################################# +# Operand orders: +# A = B * C + D +#Type 1) reg0 reg0 mem/reg1 reg2 DDMR 312 or 132 +#Type 2) reg0 reg0 reg1 mem/reg2 DDRM 123 or 213 +#Type 3) reg0 reg1 mem/reg2 reg0 DRMD 321 or 231 -# DEST in MODRM.REG -# BASE in SIB.base -# INDEX in SIB.index -# MASK in VEX.VVVV -- NOTE mask is a signed integer!!! - -# VL = 128 VL = 256 -# dest/mask index memsz dest/mask index memsz -# qps/qd xmm xmm 2*32=64b xmm* ymm* 4*32=128b -# dps/dd xmm xmm 4*32=128b ymm ymm 8*32=256b -# dpd/dq xmm xmm 2*64=128b ymm* xmm* 4*64=256b -# qpd/qq xmm xmm 2*64=128b ymm ymm 4*64=256b +# dst is in MODRM.REG +# regsrc is in VEX.vvvv +# memop is in MODRM.RM +############################################################################################ -{ -ICLASS : VGATHERDPD -CPL : 3 -CATEGORY : AVX2GATHER -EXTENSION : AVX2GATHER -ATTRIBUTES : gather DWORD_INDICES ELEMENT_SIZE_q SPECIAL_AGEN_REQUIRED -EXCEPTIONS: avx-type-12 -# VL = 256 - when data/mask differ from index size see asterisks in above chart. -PATTERN : VV1 0x92 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 -OPERANDS : REG0=YMM_R():crw:qq:f64 MEM0:r:qq:f64 REG1=YMM_N():rw:qq:i64 -IFORM: VGATHERDPD_YMMf64_MEMqq_YMMi64_VL256 -# VL = 128 - index, mask and dest are all XMMs -PATTERN : VV1 0x92 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 -OPERANDS : REG0=XMM_R():crw:dq:f64 MEM0:r:dq:f64 REG1=XMM_N():rw:dq:i64 -IFORM: VGATHERDPD_XMMf64_MEMdq_XMMi64_VL128 -COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz -} -{ -ICLASS : VGATHERDPS -CPL : 3 -CATEGORY : AVX2GATHER -EXTENSION : AVX2GATHER -ATTRIBUTES : gather DWORD_INDICES ELEMENT_SIZE_d SPECIAL_AGEN_REQUIRED -EXCEPTIONS: avx-type-12 -# VL = 256 - when data/mask differ from index size see asterisks in above chart. -PATTERN : VV1 0x92 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16 -OPERANDS : REG0=YMM_R():crw:qq:f32 MEM0:r:qq:f32 REG1=YMM_N():rw:qq:i32 -IFORM: VGATHERDPS_YMMf32_MEMqq_YMMi32_VL256 -# VL = 128 - index, mask and dest are all XMMs -PATTERN : VV1 0x92 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 -OPERANDS : REG0=XMM_R():crw:dq:f32 MEM0:r:dq:f32 REG1=XMM_N():rw:dq:i32 -IFORM: VGATHERDPS_XMMf32_MEMdq_XMMi32_VL128 -COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz -} -{ -ICLASS : VGATHERQPD -CPL : 3 -CATEGORY : AVX2GATHER -EXTENSION : AVX2GATHER -ATTRIBUTES : gather QWORD_INDICES ELEMENT_SIZE_q SPECIAL_AGEN_REQUIRED -EXCEPTIONS: avx-type-12 -# VL = 256 - when data/mask differ from index size see asterisks in above chart. -PATTERN : VV1 0x93 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16 -OPERANDS : REG0=YMM_R():crw:qq:f64 MEM0:r:qq:f64 REG1=YMM_N():rw:qq:i64 -IFORM: VGATHERQPD_YMMf64_MEMqq_YMMi64_VL256 +########################################################## -# VL = 128 - index, mask and dest are all XMMs -PATTERN : VV1 0x93 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 -OPERANDS : REG0=XMM_R():crw:dq:f64 MEM0:r:dq:f64 REG1=XMM_N():rw:dq:i64 -IFORM: VGATHERQPD_XMMf64_MEMdq_XMMi64_VL128 -COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz -} -{ -ICLASS : VGATHERQPS -CPL : 3 -CATEGORY : AVX2GATHER -EXTENSION : AVX2GATHER -ATTRIBUTES : gather QWORD_INDICES ELEMENT_SIZE_d SPECIAL_AGEN_REQUIRED -EXCEPTIONS: avx-type-12 -# VL = 256 - when data/mask differ from index size see asterisks in above chart. -PATTERN : VV1 0x93 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16 -OPERANDS : REG0=XMM_R():crw:dq:f32 MEM0:r:dq:f32 REG1=XMM_N():rw:dq:i32 -IFORM: VGATHERQPS_XMMf32_MEMdq_XMMi32_VL256 -# VL = 128 - index, mask and dest are all XMMs -PATTERN : VV1 0x93 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 -OPERANDS : REG0=XMM_R():crw:q:f32 MEM0:r:q:f32 REG1=XMM_N():rw:q:i32 -IFORM: VGATHERQPS_XMMf32_MEMq_XMMi32_VL128 -COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz -} -{ -ICLASS : VPGATHERDQ -CPL : 3 -CATEGORY : AVX2GATHER -EXTENSION : AVX2GATHER -ATTRIBUTES : gather DWORD_INDICES ELEMENT_SIZE_q SPECIAL_AGEN_REQUIRED -EXCEPTIONS: avx-type-12 -# VL = 256 - when data/mask differ from index size see asterisks in above chart. -PATTERN : VV1 0x90 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 -OPERANDS : REG0=YMM_R():crw:qq:u64 MEM0:r:qq:u64 REG1=YMM_N():rw:qq:i64 -IFORM: VPGATHERDQ_YMMu64_MEMqq_YMMi64_VL256 -# VL = 128 - index, mask and dest are all XMMs -PATTERN : VV1 0x90 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 -OPERANDS : REG0=XMM_R():crw:dq:u64 MEM0:r:dq:u64 REG1=XMM_N():rw:dq:i64 -IFORM: VPGATHERDQ_XMMu64_MEMdq_XMMi64_VL128 -COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz -} -{ -ICLASS : VPGATHERDD -CPL : 3 -CATEGORY : AVX2GATHER -EXTENSION : AVX2GATHER -ATTRIBUTES : gather DWORD_INDICES ELEMENT_SIZE_d SPECIAL_AGEN_REQUIRED -EXCEPTIONS: avx-type-12 -# VL = 256 - when data/mask differ from index size see asterisks in above chart. -PATTERN : VV1 0x90 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16 -OPERANDS : REG0=YMM_R():crw:qq:u32 MEM0:r:qq:u32 REG1=YMM_N():rw:qq:i32 -IFORM: VPGATHERDD_YMMu32_MEMqq_YMMi32_VL256 -# VL = 128 - index, mask and dest are all XMMs -PATTERN : VV1 0x90 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 -OPERANDS : REG0=XMM_R():crw:dq:u32 MEM0:r:dq:u32 REG1=XMM_N():rw:dq:i32 -IFORM: VPGATHERDD_XMMu32_MEMdq_XMMi32_VL128 +################################################################## -COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz -} -{ -ICLASS : VPGATHERQQ -CPL : 3 -CATEGORY : AVX2GATHER -EXTENSION : AVX2GATHER -ATTRIBUTES : gather QWORD_INDICES ELEMENT_SIZE_q SPECIAL_AGEN_REQUIRED -EXCEPTIONS: avx-type-12 -# VL = 256 - when data/mask differ from index size see asterisks in above chart. -PATTERN : VV1 0x91 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16 -OPERANDS : REG0=YMM_R():crw:qq:u64 MEM0:r:qq:u64 REG1=YMM_N():rw:qq:i64 -IFORM: VPGATHERQQ_YMMu64_MEMqq_YMMi64_VL256 -# VL = 128 - index, mask and dest are all XMMs -PATTERN : VV1 0x91 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 -OPERANDS : REG0=XMM_R():crw:dq:u64 MEM0:r:dq:u64 REG1=XMM_N():rw:dq:i64 -IFORM: VPGATHERQQ_XMMu64_MEMdq_XMMi64_VL128 -COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz -} -{ -ICLASS : VPGATHERQD -CPL : 3 -CATEGORY : AVX2GATHER -EXTENSION : AVX2GATHER -ATTRIBUTES : gather QWORD_INDICES ELEMENT_SIZE_d SPECIAL_AGEN_REQUIRED -EXCEPTIONS: avx-type-12 -# VL = 256 - when data/mask differ from index size see asterisks in above chart. -PATTERN : VV1 0x91 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16 -OPERANDS : REG0=XMM_R():crw:dq:u32 MEM0:r:dq:u32 REG1=XMM_N():rw:dq:i32 -IFORM: VPGATHERQD_XMMu32_MEMdq_XMMi32_VL256 -# VL = 128 - index, mask and dest are all XMMs -PATTERN : VV1 0x91 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 -OPERANDS : REG0=XMM_R():crw:q:u32 MEM0:r:q:u32 REG1=XMM_N():rw:q:i32 -IFORM: VPGATHERQD_XMMu32_MEMq_XMMi32_VL128 -COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz -} -###FILE: ../xed/datafiles/avxhsw/hsw-int256-isa.txt -#BEGIN_LEGAL -# -#Copyright (c) 2016 Intel Corporation -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -#END_LEGAL -AVX_INSTRUCTIONS():: +################################################################## { -ICLASS : VPABSB +ICLASS : VFMADD132PD +EXCEPTIONS: avx-type-2 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0x1C VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u8 MEM0:r:qq:i8 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0x98 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0x98 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 -PATTERN : VV1 0x1C VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_B():r:qq:i8 + +# R/M 256 +PATTERN : VV1 0x98 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0x98 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 } { -ICLASS : VPABSW +ICLASS : VFMADD132PS +EXCEPTIONS: avx-type-2 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0x1D VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u16 MEM0:r:qq:i16 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0x98 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0x98 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 -PATTERN : VV1 0x1D VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_B():r:qq:i16 + +# R/M 256 +PATTERN : VV1 0x98 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0x98 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 } { -ICLASS : VPABSD +ICLASS : VFMADD132SD +EXCEPTIONS: avx-type-3 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0x1E VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u32 MEM0:r:qq:i32 - -PATTERN : VV1 0x1E VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_B():r:qq:i32 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0x99 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 +# R/R 128 +PATTERN : VV1 0x99 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 } { -ICLASS : VPHMINPOSUW +ICLASS : VFMADD132SS +EXCEPTIONS: avx-type-3 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0x41 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u16 MEM0:r:qq:u16 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0x99 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 +# R/R 128 +PATTERN : VV1 0x99 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 -PATTERN : VV1 0x41 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_B():r:qq:u16 } - - - - - - - - - { -ICLASS : VPACKSSWB +ICLASS : VFMADD213PD +EXCEPTIONS: avx-type-2 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0x63 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xA8 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0xA8 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 -PATTERN : VV1 0x63 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 -} -{ -ICLASS : VPACKSSDW -CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0x6B VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 -PATTERN : VV1 0x6B VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 +# R/M 256 +PATTERN : VV1 0xA8 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0xA8 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 } { -ICLASS : VPACKUSWB +ICLASS : VFMADD213PS +EXCEPTIONS: avx-type-2 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0x67 V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xA8 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0xA8 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 -PATTERN : VV1 0x67 V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 -} -{ -ICLASS : VPACKUSDW -CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0x2B V66 V0F38 VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 -PATTERN : VV1 0x2B V66 V0F38 VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 +# R/M 256 +PATTERN : VV1 0xA8 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0xA8 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 } - { -ICLASS : VPSLLW +ICLASS : VFMADD213SD +EXCEPTIONS: avx-type-3 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0xF1 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:dq:u64 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xA9 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 +# R/R 128 +PATTERN : VV1 0xA9 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 -PATTERN : VV1 0xF1 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=XMM_B():r:q:u64 } { -ICLASS : VPSLLD +ICLASS : VFMADD213SS +EXCEPTIONS: avx-type-3 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0xF2 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:dq:u64 - -PATTERN : VV1 0xF2 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=XMM_B():r:q:u64 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xA9 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 +# R/R 128 +PATTERN : VV1 0xA9 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 } + { -ICLASS : VPSLLQ +ICLASS : VFMADD231PD +EXCEPTIONS: avx-type-2 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0xF3 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:dq:u64 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xB8 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0xB8 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 -PATTERN : VV1 0xF3 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=XMM_B():r:q:u64 -} -{ -ICLASS : VPSRLW -CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0xD1 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:dq:u64 +# R/M 256 +PATTERN : VV1 0xB8 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0xB8 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 -PATTERN : VV1 0xD1 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=XMM_B():r:q:u64 } { -ICLASS : VPSRLD +ICLASS : VFMADD231PS +EXCEPTIONS: avx-type-2 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0xD2 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:dq:u64 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xB8 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0xB8 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 -PATTERN : VV1 0xD2 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=XMM_B():r:q:u64 -} -{ -ICLASS : VPSRLQ -CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0xD3 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:dq:u64 +# R/M 256 +PATTERN : VV1 0xB8 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0xB8 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 -PATTERN : VV1 0xD3 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=XMM_B():r:q:u64 } - { -ICLASS : VPSRAW +ICLASS : VFMADD231SD +EXCEPTIONS: avx-type-3 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0xE1 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:dq:u64 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xB9 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 +# R/R 128 +PATTERN : VV1 0xB9 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 -PATTERN : VV1 0xE1 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=XMM_B():r:q:u64 } { -ICLASS : VPSRAD +ICLASS : VFMADD231SS +EXCEPTIONS: avx-type-3 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0xE2 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:dq:u64 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xB9 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 +# R/R 128 +PATTERN : VV1 0xB9 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 -PATTERN : VV1 0xE2 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=XMM_B():r:q:u64 } +################################################### { -ICLASS : VPADDB +ICLASS : VFMADDSUB132PD +EXCEPTIONS: avx-type-2 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0xFC VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0x96 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0x96 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 -PATTERN : VV1 0xFC VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 -} -{ -ICLASS : VPADDW -CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0xFD VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 -PATTERN : VV1 0xFD VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +# R/M 256 +PATTERN : VV1 0x96 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0x96 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 } { -ICLASS : VPADDD +ICLASS : VFMADDSUB213PD +EXCEPTIONS: avx-type-2 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0xFE VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xA6 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0xA6 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 -PATTERN : VV1 0xFE VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 + +# R/M 256 +PATTERN : VV1 0xA6 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0xA6 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 } { -ICLASS : VPADDQ +ICLASS : VFMADDSUB231PD +EXCEPTIONS: avx-type-2 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0xD4 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i64 MEM0:r:qq:i64 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xB6 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0xB6 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 -PATTERN : VV1 0xD4 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i64 REG2=YMM_B():r:qq:i64 -} -{ -ICLASS : VPADDSB -CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0xEC VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 +# R/M 256 +PATTERN : VV1 0xB6 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0xB6 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 -PATTERN : VV1 0xEC VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 } + { -ICLASS : VPADDSW +ICLASS : VFMADDSUB132PS +EXCEPTIONS: avx-type-2 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0xED VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0x96 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0x96 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 -PATTERN : VV1 0xED VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 -} +# R/M 256 +PATTERN : VV1 0x96 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0x96 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} { -ICLASS : VPADDUSB +ICLASS : VFMADDSUB213PS +EXCEPTIONS: avx-type-2 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0xDC VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xA6 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0xA6 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 -PATTERN : VV1 0xDC VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 + +# R/M 256 +PATTERN : VV1 0xA6 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0xA6 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 } { -ICLASS : VPADDUSW +ICLASS : VFMADDSUB231PS +EXCEPTIONS: avx-type-2 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0xDD VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xB6 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0xB6 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +# R/M 256 +PATTERN : VV1 0xB6 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0xB6 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 -PATTERN : VV1 0xDD VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 } +################################################### { -ICLASS : VPAVGB +ICLASS : VFMSUBADD132PD +EXCEPTIONS: avx-type-2 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0xE0 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0x97 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0x97 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 -PATTERN : VV1 0xE0 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 + +# R/M 256 +PATTERN : VV1 0x97 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0x97 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 } { -ICLASS : VPAVGW +ICLASS : VFMSUBADD213PD +EXCEPTIONS: avx-type-2 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0xE3 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 - -PATTERN : VV1 0xE3 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 -} +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xA7 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0xA7 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 +# R/M 256 +PATTERN : VV1 0xA7 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0xA7 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} { -ICLASS : VPCMPEQB +ICLASS : VFMSUBADD231PD +EXCEPTIONS: avx-type-2 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0x74 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xB7 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0xB7 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0xB7 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0xB7 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 -PATTERN : VV1 0x74 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 } + { -ICLASS : VPCMPEQW +ICLASS : VFMSUBADD132PS +EXCEPTIONS: avx-type-2 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0x75 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0x97 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0x97 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 -PATTERN : VV1 0x75 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 + +# R/M 256 +PATTERN : VV1 0x97 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0x97 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 } { -ICLASS : VPCMPEQD +ICLASS : VFMSUBADD213PS +EXCEPTIONS: avx-type-2 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0x76 V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xA7 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0xA7 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 -PATTERN : VV1 0x76 V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 + +# R/M 256 +PATTERN : VV1 0xA7 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0xA7 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 } { -ICLASS : VPCMPEQQ +ICLASS : VFMSUBADD231PS +EXCEPTIONS: avx-type-2 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0x29 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xB7 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0xB7 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +# R/M 256 +PATTERN : VV1 0xB7 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0xB7 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 -PATTERN : VV1 0x29 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 } + +################################################### + { -ICLASS : VPCMPGTB +ICLASS : VFMSUB132PD +EXCEPTIONS: avx-type-2 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0x64 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0x9A VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0x9A VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 -PATTERN : VV1 0x64 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 + +# R/M 256 +PATTERN : VV1 0x9A VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0x9A VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 } { -ICLASS : VPCMPGTW +ICLASS : VFMSUB132PS +EXCEPTIONS: avx-type-2 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0x65 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0x9A VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0x9A VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 -PATTERN : VV1 0x65 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 + +# R/M 256 +PATTERN : VV1 0x9A VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0x9A VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 } { -ICLASS : VPCMPGTD +ICLASS : VFMSUB132SD +EXCEPTIONS: avx-type-3 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0x66 V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 - -PATTERN : VV1 0x66 V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0x9B V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 +# R/R 128 +PATTERN : VV1 0x9B V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 } { -ICLASS : VPCMPGTQ +ICLASS : VFMSUB132SS +EXCEPTIONS: avx-type-3 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0x37 V66 V0F38 VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i64 MEM0:r:qq:i64 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0x9B V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 +# R/R 128 +PATTERN : VV1 0x9B V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 -PATTERN : VV1 0x37 V66 V0F38 VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i64 REG2=YMM_B():r:qq:i64 } - { -ICLASS : VPHADDW +ICLASS : VFMSUB213PD +EXCEPTIONS: avx-type-2 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0x01 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xAA VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0xAA VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 -PATTERN : VV1 0x01 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 -} -{ -ICLASS : VPHADDD -CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0x02 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 -PATTERN : VV1 0x02 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 +# R/M 256 +PATTERN : VV1 0xAA VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0xAA VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 } { -ICLASS : VPHADDSW +ICLASS : VFMSUB213PS +EXCEPTIONS: avx-type-2 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0x03 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xAA VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0xAA VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 -PATTERN : VV1 0x03 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 + +# R/M 256 +PATTERN : VV1 0xAA VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0xAA VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 } { -ICLASS : VPHSUBW +ICLASS : VFMSUB213SD +EXCEPTIONS: avx-type-3 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0x05 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xAB V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 +# R/R 128 +PATTERN : VV1 0xAB V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 -PATTERN : VV1 0x05 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 } { -ICLASS : VPHSUBD +ICLASS : VFMSUB213SS +EXCEPTIONS: avx-type-3 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0x06 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 - -PATTERN : VV1 0x06 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xAB V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 +# R/R 128 +PATTERN : VV1 0xAB V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 } + { -ICLASS : VPHSUBSW +ICLASS : VFMSUB231PD +EXCEPTIONS: avx-type-2 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0x07 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xBA VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0xBA VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 -PATTERN : VV1 0x07 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 -} -{ -ICLASS : VPMADDWD -CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0xF5 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 +# R/M 256 +PATTERN : VV1 0xBA VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0xBA VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 -PATTERN : VV1 0xF5 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 } { -ICLASS : VPMADDUBSW +ICLASS : VFMSUB231PS +EXCEPTIONS: avx-type-2 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0x04 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:u8 MEM0:r:qq:i8 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xBA VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0xBA VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 -PATTERN : VV1 0x04 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:i8 -} +# R/M 256 +PATTERN : VV1 0xBA VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0xBA VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} { -ICLASS : VPMAXSB +ICLASS : VFMSUB231SD +EXCEPTIONS: avx-type-3 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0x3C VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xBB V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 +# R/R 128 +PATTERN : VV1 0xBB V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 -PATTERN : VV1 0x3C VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 } { -ICLASS : VPMAXSW +ICLASS : VFMSUB231SS +EXCEPTIONS: avx-type-3 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0xEE VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xBB V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 +# R/R 128 +PATTERN : VV1 0xBB V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 -PATTERN : VV1 0xEE VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 } + +################################################### + + { -ICLASS : VPMAXSD +ICLASS : VFNMADD132PD +EXCEPTIONS: avx-type-2 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0x3D VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0x9C VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0x9C VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 -PATTERN : VV1 0x3D VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 -} +# R/M 256 +PATTERN : VV1 0x9C VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0x9C VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} { -ICLASS : VPMAXUB +ICLASS : VFNMADD132PS +EXCEPTIONS: avx-type-2 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0xDE VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0x9C VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0x9C VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 -PATTERN : VV1 0xDE VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 + +# R/M 256 +PATTERN : VV1 0x9C VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0x9C VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 } { -ICLASS : VPMAXUW +ICLASS : VFNMADD132SD +EXCEPTIONS: avx-type-3 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0x3E VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 - -PATTERN : VV1 0x3E VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0x9D V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 +# R/R 128 +PATTERN : VV1 0x9D V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 } { -ICLASS : VPMAXUD +ICLASS : VFNMADD132SS +EXCEPTIONS: avx-type-3 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0x3F VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0x9D V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 +# R/R 128 +PATTERN : VV1 0x9D V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 -PATTERN : VV1 0x3F VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 } { -ICLASS : VPMINSB +ICLASS : VFNMADD213PD +EXCEPTIONS: avx-type-2 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0x38 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xAC VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0xAC VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 -PATTERN : VV1 0x38 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 + +# R/M 256 +PATTERN : VV1 0xAC VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0xAC VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 } { -ICLASS : VPMINSW +ICLASS : VFNMADD213PS +EXCEPTIONS: avx-type-2 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0xEA VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xAC VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0xAC VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 -PATTERN : VV1 0xEA VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 + +# R/M 256 +PATTERN : VV1 0xAC VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0xAC VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 } { -ICLASS : VPMINSD +ICLASS : VFNMADD213SD +EXCEPTIONS: avx-type-3 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0x39 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xAD V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 +# R/R 128 +PATTERN : VV1 0xAD V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 -PATTERN : VV1 0x39 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 } - { -ICLASS : VPMINUB +ICLASS : VFNMADD213SS +EXCEPTIONS: avx-type-3 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0xDA VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 - -PATTERN : VV1 0xDA VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xAD V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 +# R/R 128 +PATTERN : VV1 0xAD V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 } + { -ICLASS : VPMINUW +ICLASS : VFNMADD231PD +EXCEPTIONS: avx-type-2 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0x3A V66 V0F38 VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xBC VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0xBC VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0xBC VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0xBC VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 -PATTERN : VV1 0x3A V66 V0F38 VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 } { -ICLASS : VPMINUD +ICLASS : VFNMADD231PS +EXCEPTIONS: avx-type-2 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0x3B V66 V0F38 VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xBC VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0xBC VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 -PATTERN : VV1 0x3B V66 V0F38 VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 -} +# R/M 256 +PATTERN : VV1 0xBC VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0xBC VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} { -ICLASS : VPMULHUW +ICLASS : VFNMADD231SD +EXCEPTIONS: avx-type-3 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0xE4 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xBD V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 +# R/R 128 +PATTERN : VV1 0xBD V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 -PATTERN : VV1 0xE4 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 } { -ICLASS : VPMULHRSW +ICLASS : VFNMADD231SS +EXCEPTIONS: avx-type-3 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0x0B VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xBD V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 +# R/R 128 +PATTERN : VV1 0xBD V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 -PATTERN : VV1 0x0B VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 } -{ -ICLASS : VPMULHW -CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0xE5 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 +################################################### + -PATTERN : VV1 0xE5 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 -} { -ICLASS : VPMULLW +ICLASS : VFNMSUB132PD +EXCEPTIONS: avx-type-2 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0xD5 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0x9E VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0x9E VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 -PATTERN : VV1 0xD5 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 + +# R/M 256 +PATTERN : VV1 0x9E VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0x9E VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 } { -ICLASS : VPMULLD +ICLASS : VFNMSUB132PS +EXCEPTIONS: avx-type-2 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0x40 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0x9E VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0x9E VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 -PATTERN : VV1 0x40 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 -} +# R/M 256 +PATTERN : VV1 0x9E VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0x9E VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} { -ICLASS : VPMULUDQ +ICLASS : VFNMSUB132SD +EXCEPTIONS: avx-type-3 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0xF4 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 - -PATTERN : VV1 0xF4 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0x9F V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 +# R/R 128 +PATTERN : VV1 0x9F V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 } { -ICLASS : VPMULDQ +ICLASS : VFNMSUB132SS +EXCEPTIONS: avx-type-3 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0x28 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0x9F V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 +# R/R 128 +PATTERN : VV1 0x9F V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 -PATTERN : VV1 0x28 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 } { -ICLASS : VPSADBW +ICLASS : VFNMSUB213PD +EXCEPTIONS: avx-type-2 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0xF6 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xAE VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0xAE VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 -PATTERN : VV1 0xF6 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 + +# R/M 256 +PATTERN : VV1 0xAE VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0xAE VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 } { -ICLASS : VPSHUFB +ICLASS : VFNMSUB213PS +EXCEPTIONS: avx-type-2 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0x00 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xAE VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0xAE VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 -PATTERN : VV1 0x00 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 + +# R/M 256 +PATTERN : VV1 0xAE VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0xAE VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 } +{ +ICLASS : VFNMSUB213SD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xAF V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 +# R/R 128 +PATTERN : VV1 0xAF V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 +} { -ICLASS : VPSIGNB +ICLASS : VFNMSUB213SS +EXCEPTIONS: avx-type-3 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0x08 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xAF V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 +# R/R 128 +PATTERN : VV1 0xAF V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 +} + +{ +ICLASS : VFNMSUB231PD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xBE VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0xBE VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0xBE VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0xBE VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 -PATTERN : VV1 0x08 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 } { -ICLASS : VPSIGNW +ICLASS : VFNMSUB231PS +EXCEPTIONS: avx-type-2 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0x09 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xBE VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0xBE VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +# R/M 256 +PATTERN : VV1 0xBE VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0xBE VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 -PATTERN : VV1 0x09 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 } { -ICLASS : VPSIGND +ICLASS : VFNMSUB231SD +EXCEPTIONS: avx-type-3 CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0x0A VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xBF V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 +# R/R 128 +PATTERN : VV1 0xBF V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 + +} +{ +ICLASS : VFNMSUB231SS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xBF V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 +# R/R 128 +PATTERN : VV1 0xBF V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 -PATTERN : VV1 0x0A VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 } +################################################### + + + + + + +###FILE: ../xed/datafiles/hswavx/gather-isa.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2018 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +AVX_INSTRUCTIONS():: + + +# DEST in MODRM.REG +# BASE in SIB.base +# INDEX in SIB.index +# MASK in VEX.VVVV -- NOTE mask is a signed integer!!! + +# VL = 128 VL = 256 +# dest/mask index memsz dest/mask index memsz +# qps/qd xmm xmm 2*32=64b xmm* ymm* 4*32=128b +# dps/dd xmm xmm 4*32=128b ymm ymm 8*32=256b +# dpd/dq xmm xmm 2*64=128b ymm* xmm* 4*64=256b +# qpd/qq xmm xmm 2*64=128b ymm ymm 4*64=256b + + { -ICLASS : VPSUBSB +ICLASS : VGATHERDPD CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0xE8 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 +CATEGORY : AVX2GATHER +EXTENSION : AVX2GATHER +ATTRIBUTES : gather DWORD_INDICES ELEMENT_SIZE_q SPECIAL_AGEN_REQUIRED +EXCEPTIONS: avx-type-12 -PATTERN : VV1 0xE8 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 + +# VL = 256 - when data/mask differ from index size see asterisks in above chart. +PATTERN : VV1 0x92 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 +OPERANDS : REG0=YMM_R():crw:qq:f64 MEM0:r:q:f64 REG1=YMM_N():rw:qq:i64 +IFORM: VGATHERDPD_YMMf64_MEMf64_YMMi64_VL256 + +# VL = 128 - index, mask and dest are all XMMs +PATTERN : VV1 0x92 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 +OPERANDS : REG0=XMM_R():crw:dq:f64 MEM0:r:q:f64 REG1=XMM_N():rw:dq:i64 +IFORM: VGATHERDPD_XMMf64_MEMf64_XMMi64_VL128 + +COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz } { -ICLASS : VPSUBSW +ICLASS : VGATHERDPS CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0xE9 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 +CATEGORY : AVX2GATHER +EXTENSION : AVX2GATHER +ATTRIBUTES : gather DWORD_INDICES ELEMENT_SIZE_d SPECIAL_AGEN_REQUIRED +EXCEPTIONS: avx-type-12 -PATTERN : VV1 0xE9 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 + +# VL = 256 - when data/mask differ from index size see asterisks in above chart. +PATTERN : VV1 0x92 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16 +OPERANDS : REG0=YMM_R():crw:qq:f32 MEM0:r:d:f32 REG1=YMM_N():rw:qq:i32 +IFORM: VGATHERDPS_YMMf32_MEMf32_YMMi32_VL256 + +# VL = 128 - index, mask and dest are all XMMs +PATTERN : VV1 0x92 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 +OPERANDS : REG0=XMM_R():crw:dq:f32 MEM0:r:d:f32 REG1=XMM_N():rw:dq:i32 +IFORM: VGATHERDPS_XMMf32_MEMf32_XMMi32_VL128 + +COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz } +{ +ICLASS : VGATHERQPD +CPL : 3 +CATEGORY : AVX2GATHER +EXTENSION : AVX2GATHER +ATTRIBUTES : gather QWORD_INDICES ELEMENT_SIZE_q SPECIAL_AGEN_REQUIRED +EXCEPTIONS: avx-type-12 + +# VL = 256 - when data/mask differ from index size see asterisks in above chart. +PATTERN : VV1 0x93 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16 +OPERANDS : REG0=YMM_R():crw:qq:f64 MEM0:r:q:f64 REG1=YMM_N():rw:qq:i64 +IFORM: VGATHERQPD_YMMf64_MEMf64_YMMi64_VL256 +# VL = 128 - index, mask and dest are all XMMs +PATTERN : VV1 0x93 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 +OPERANDS : REG0=XMM_R():crw:dq:f64 MEM0:r:q:f64 REG1=XMM_N():rw:dq:i64 +IFORM: VGATHERQPD_XMMf64_MEMf64_XMMi64_VL128 + +COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz +} { -ICLASS : VPSUBUSB +ICLASS : VGATHERQPS CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0xD8 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 +CATEGORY : AVX2GATHER +EXTENSION : AVX2GATHER +ATTRIBUTES : gather QWORD_INDICES ELEMENT_SIZE_d SPECIAL_AGEN_REQUIRED +EXCEPTIONS: avx-type-12 -PATTERN : VV1 0xD8 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 + +# VL = 256 - when data/mask differ from index size see asterisks in above chart. +PATTERN : VV1 0x93 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16 +OPERANDS : REG0=XMM_R():crw:dq:f32 MEM0:r:d:f32 REG1=XMM_N():rw:dq:i32 +IFORM: VGATHERQPS_XMMf32_MEMf32_XMMi32_VL256 + +# VL = 128 - index, mask and dest are all XMMs +PATTERN : VV1 0x93 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 +OPERANDS : REG0=XMM_R():crw:q:f32 MEM0:r:d:f32 REG1=XMM_N():rw:q:i32 +IFORM: VGATHERQPS_XMMf32_MEMf32_XMMi32_VL128 + +COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz } + { -ICLASS : VPSUBUSW +ICLASS : VPGATHERDQ CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0xD9 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 +CATEGORY : AVX2GATHER +EXTENSION : AVX2GATHER +ATTRIBUTES : gather DWORD_INDICES ELEMENT_SIZE_q SPECIAL_AGEN_REQUIRED +EXCEPTIONS: avx-type-12 -PATTERN : VV1 0xD9 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 +# VL = 256 - when data/mask differ from index size see asterisks in above chart. +PATTERN : VV1 0x90 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 +OPERANDS : REG0=YMM_R():crw:qq:u64 MEM0:r:q:u64 REG1=YMM_N():rw:qq:i64 +IFORM: VPGATHERDQ_YMMu64_MEMq_YMMi64_VL256 + +# VL = 128 - index, mask and dest are all XMMs +PATTERN : VV1 0x90 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 +OPERANDS : REG0=XMM_R():crw:dq:u64 MEM0:r:q:u64 REG1=XMM_N():rw:dq:i64 +IFORM: VPGATHERDQ_XMMu64_MEMq_XMMi64_VL128 + +COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz } +{ +ICLASS : VPGATHERDD +CPL : 3 +CATEGORY : AVX2GATHER +EXTENSION : AVX2GATHER +ATTRIBUTES : gather DWORD_INDICES ELEMENT_SIZE_d SPECIAL_AGEN_REQUIRED +EXCEPTIONS: avx-type-12 + +# VL = 256 - when data/mask differ from index size see asterisks in above chart. +PATTERN : VV1 0x90 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16 +OPERANDS : REG0=YMM_R():crw:qq:u32 MEM0:r:d:u32 REG1=YMM_N():rw:qq:i32 +IFORM: VPGATHERDD_YMMu32_MEMd_YMMi32_VL256 + +# VL = 128 - index, mask and dest are all XMMs +PATTERN : VV1 0x90 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 +OPERANDS : REG0=XMM_R():crw:dq:u32 MEM0:r:d:u32 REG1=XMM_N():rw:dq:i32 +IFORM: VPGATHERDD_XMMu32_MEMd_XMMi32_VL128 +COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz +} { -ICLASS : VPSUBB +ICLASS : VPGATHERQQ CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0xF8 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 +CATEGORY : AVX2GATHER +EXTENSION : AVX2GATHER +ATTRIBUTES : gather QWORD_INDICES ELEMENT_SIZE_q SPECIAL_AGEN_REQUIRED +EXCEPTIONS: avx-type-12 -PATTERN : VV1 0xF8 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 +# VL = 256 - when data/mask differ from index size see asterisks in above chart. +PATTERN : VV1 0x91 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16 +OPERANDS : REG0=YMM_R():crw:qq:u64 MEM0:r:q:u64 REG1=YMM_N():rw:qq:i64 +IFORM: VPGATHERQQ_YMMu64_MEMq_YMMi64_VL256 + +# VL = 128 - index, mask and dest are all XMMs +PATTERN : VV1 0x91 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 +OPERANDS : REG0=XMM_R():crw:dq:u64 MEM0:r:q:u64 REG1=XMM_N():rw:dq:i64 +IFORM: VPGATHERQQ_XMMu64_MEMq_XMMi64_VL128 + +COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz } { -ICLASS : VPSUBW +ICLASS : VPGATHERQD CPL : 3 -CATEGORY : AVX2 -EXTENSION : AVX2 -EXCEPTIONS: avx-type-4 -PATTERN : VV1 0xF9 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 +CATEGORY : AVX2GATHER +EXTENSION : AVX2GATHER +ATTRIBUTES : gather QWORD_INDICES ELEMENT_SIZE_d SPECIAL_AGEN_REQUIRED +EXCEPTIONS: avx-type-12 -PATTERN : VV1 0xF9 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +# VL = 256 - when data/mask differ from index size see asterisks in above chart. +PATTERN : VV1 0x91 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16 +OPERANDS : REG0=XMM_R():crw:dq:u32 MEM0:r:d:u32 REG1=XMM_N():rw:dq:i32 +IFORM: VPGATHERQD_XMMu32_MEMd_XMMi32_VL256 + +# VL = 128 - index, mask and dest are all XMMs +PATTERN : VV1 0x91 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 +OPERANDS : REG0=XMM_R():crw:q:u32 MEM0:r:d:u32 REG1=XMM_N():rw:q:i32 +IFORM: VPGATHERQD_XMMu32_MEMd_XMMi32_VL128 + +COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz } + + + +###FILE: ../xed/datafiles/hswavx/hsw-int256-isa.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2018 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +AVX_INSTRUCTIONS():: + + { -ICLASS : VPSUBD +ICLASS : VPABSB CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 -PATTERN : VV1 0xFA VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 +PATTERN : VV1 0x1C VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u8 MEM0:r:qq:i8 -PATTERN : VV1 0xFA VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 +PATTERN : VV1 0x1C VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_B():r:qq:i8 } { -ICLASS : VPSUBQ +ICLASS : VPABSW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 -PATTERN : VV1 0xFB VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i64 MEM0:r:qq:i64 +PATTERN : VV1 0x1D VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 MEM0:r:qq:i16 -PATTERN : VV1 0xFB VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i64 REG2=YMM_B():r:qq:i64 +PATTERN : VV1 0x1D VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_B():r:qq:i16 } - { -ICLASS : VPUNPCKHBW +ICLASS : VPABSD CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 -PATTERN : VV1 0x68 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 +PATTERN : VV1 0x1E VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u32 MEM0:r:qq:i32 -PATTERN : VV1 0x68 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 +PATTERN : VV1 0x1E VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_B():r:qq:i32 } + + + + + + + + + { -ICLASS : VPUNPCKHWD +ICLASS : VPACKSSWB CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 -PATTERN : VV1 0x69 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 +PATTERN : VV1 0x63 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 -PATTERN : VV1 0x69 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 +PATTERN : VV1 0x63 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 } { -ICLASS : VPUNPCKHDQ +ICLASS : VPACKSSDW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 -PATTERN : VV1 0x6A VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 +PATTERN : VV1 0x6B VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 -PATTERN : VV1 0x6A VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 +PATTERN : VV1 0x6B VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 } { -ICLASS : VPUNPCKHQDQ +ICLASS : VPACKUSWB CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 -PATTERN : VV1 0x6D VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 +PATTERN : VV1 0x67 V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 -PATTERN : VV1 0x6D VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 +PATTERN : VV1 0x67 V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 } - { -ICLASS : VPUNPCKLBW +ICLASS : VPACKUSDW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 -PATTERN : VV1 0x60 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 +PATTERN : VV1 0x2B V66 V0F38 VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 -PATTERN : VV1 0x60 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 +PATTERN : VV1 0x2B V66 V0F38 VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 } + { -ICLASS : VPUNPCKLWD +ICLASS : VPSLLW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 -PATTERN : VV1 0x61 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 +PATTERN : VV1 0xF1 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:dq:u64 -PATTERN : VV1 0x61 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 +PATTERN : VV1 0xF1 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=XMM_B():r:q:u64 } { -ICLASS : VPUNPCKLDQ +ICLASS : VPSLLD CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 -PATTERN : VV1 0x62 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 +PATTERN : VV1 0xF2 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:dq:u64 -PATTERN : VV1 0x62 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 +PATTERN : VV1 0xF2 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=XMM_B():r:q:u64 } { -ICLASS : VPUNPCKLQDQ +ICLASS : VPSLLQ CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 -PATTERN : VV1 0x6C VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 +PATTERN : VV1 0xF3 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:dq:u64 -PATTERN : VV1 0x6C VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 +PATTERN : VV1 0xF3 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=XMM_B():r:q:u64 } - { -ICLASS : VPALIGNR +ICLASS : VPSRLW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 -PATTERN : VV1 0x0F VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() -OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 IMM0:r:b +PATTERN : VV1 0xD1 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:dq:u64 -PATTERN : VV1 0x0F VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() -OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 IMM0:r:b +PATTERN : VV1 0xD1 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=XMM_B():r:q:u64 } { -ICLASS : VPBLENDW +ICLASS : VPSRLD CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 -PATTERN : VV1 0x0E VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() -OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 IMM0:r:b +PATTERN : VV1 0xD2 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:dq:u64 -PATTERN : VV1 0x0E VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() -OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 IMM0:r:b +PATTERN : VV1 0xD2 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=XMM_B():r:q:u64 } { -ICLASS : VMPSADBW +ICLASS : VPSRLQ CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 -PATTERN : VV1 0x42 VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() -OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 IMM0:r:b +PATTERN : VV1 0xD3 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:dq:u64 -PATTERN : VV1 0x42 VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() -OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 IMM0:r:b +PATTERN : VV1 0xD3 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=XMM_B():r:q:u64 } - - { -ICLASS : VPOR +ICLASS : VPSRAW CPL : 3 -CATEGORY : LOGICAL +CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 -PATTERN : VV1 0xEB VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 MEM0:r:qq:u256 +PATTERN : VV1 0xE1 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:dq:u64 -PATTERN : VV1 0xEB VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 REG2=YMM_B():r:qq:u256 +PATTERN : VV1 0xE1 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=XMM_B():r:q:u64 } { -ICLASS : VPAND +ICLASS : VPSRAD CPL : 3 -CATEGORY : LOGICAL +CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 -PATTERN : VV1 0xDB VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 MEM0:r:qq:u256 +PATTERN : VV1 0xE2 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:dq:u64 -PATTERN : VV1 0xDB VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 REG2=YMM_B():r:qq:u256 +PATTERN : VV1 0xE2 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=XMM_B():r:q:u64 } + + { -ICLASS : VPANDN +ICLASS : VPADDB CPL : 3 -CATEGORY : LOGICAL +CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 -PATTERN : VV1 0xDF VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 MEM0:r:qq:u256 +PATTERN : VV1 0xFC VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 -PATTERN : VV1 0xDF VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 REG2=YMM_B():r:qq:u256 +PATTERN : VV1 0xFC VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 } { -ICLASS : VPXOR +ICLASS : VPADDW CPL : 3 -CATEGORY : LOGICAL +CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 -PATTERN : VV1 0xEF VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 MEM0:r:qq:u256 +PATTERN : VV1 0xFD VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 -PATTERN : VV1 0xEF VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 REG2=YMM_B():r:qq:u256 +PATTERN : VV1 0xFD VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 } - - - { -ICLASS : VPBLENDVB +ICLASS : VPADDD CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 -PATTERN : VV1 0x4C VL256 V66 V0F3A norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() -OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 REG2=YMM_SE():r:qq:u8 +PATTERN : VV1 0xFE VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 -PATTERN : VV1 0x4C VL256 V66 V0F3A norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() -OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 REG3=YMM_SE():r:qq:u8 +PATTERN : VV1 0xFE VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 } - - - - { -ICLASS : VPMOVMSKB +ICLASS : VPADDQ CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 -EXCEPTIONS: avx-type-7 -PATTERN : VV1 0xD7 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=GPR32_R():w:d:u32 REG1=YMM_B():r:qq:i8 -} - +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xD4 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i64 MEM0:r:qq:i64 +PATTERN : VV1 0xD4 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i64 REG2=YMM_B():r:qq:i64 +} { -ICLASS : VPSHUFD +ICLASS : VPADDSB CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 -PATTERN : VV1 0x70 VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() -OPERANDS : REG0=YMM_R():w:qq:u32 MEM0:r:qq:u32 IMM0:r:b +PATTERN : VV1 0xEC VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 -PATTERN : VV1 0x70 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() -OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_B():r:qq:u32 IMM0:r:b +PATTERN : VV1 0xEC VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 } { -ICLASS : VPSHUFHW +ICLASS : VPADDSW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 -PATTERN : VV1 0x70 VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() -OPERANDS : REG0=YMM_R():w:qq:u16 MEM0:r:qq:u16 IMM0:r:b +PATTERN : VV1 0xED VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 -PATTERN : VV1 0x70 VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() -OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_B():r:qq:u16 IMM0:r:b +PATTERN : VV1 0xED VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 } + { -ICLASS : VPSHUFLW +ICLASS : VPADDUSB CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 -PATTERN : VV1 0x70 VL256 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() -OPERANDS : REG0=YMM_R():w:qq:u16 MEM0:r:qq:u16 IMM0:r:b +PATTERN : VV1 0xDC VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 -PATTERN : VV1 0x70 VL256 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() -OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_B():r:qq:u16 IMM0:r:b +PATTERN : VV1 0xDC VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 } +{ +ICLASS : VPADDUSW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xDD VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 - +PATTERN : VV1 0xDD VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 +} { -ICLASS : VPSRLDQ +ICLASS : VPAVGB CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 -EXCEPTIONS: avx-type-7 -PATTERN : VV1 0x73 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b011] RM[nnn] UIMM8() -OPERANDS : REG0=YMM_N():w:qq:u128 REG1=YMM_B():r:qq:u128 IMM0:r:b # NDD +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xE0 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 + +PATTERN : VV1 0xE0 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 } { -ICLASS : VPSLLDQ +ICLASS : VPAVGW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 -EXCEPTIONS: avx-type-7 -PATTERN : VV1 0x73 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b111] RM[nnn] UIMM8() -OPERANDS : REG0=YMM_N():w:qq:u128 REG1=YMM_B():r:qq:u128 IMM0:r:b # NDD +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xE3 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 + +PATTERN : VV1 0xE3 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 } -############################################## { -ICLASS : VPSLLW +ICLASS : VPCMPEQB CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 -EXCEPTIONS: avx-type-7 -PATTERN : VV1 0x71 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() -OPERANDS : REG0=YMM_N():w:qq:u16 REG1=YMM_B():r:qq:u16 IMM0:r:b # NDD +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x74 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 + +PATTERN : VV1 0x74 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 } { -ICLASS : VPSLLD +ICLASS : VPCMPEQW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 -EXCEPTIONS: avx-type-7 -PATTERN : VV1 0x72 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() -OPERANDS : REG0=YMM_N():w:qq:u32 REG1=YMM_B():r:qq:u32 IMM0:r:b #NDD +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x75 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 + +PATTERN : VV1 0x75 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 } { -ICLASS : VPSLLQ +ICLASS : VPCMPEQD CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 -EXCEPTIONS: avx-type-7 -PATTERN : VV1 0x73 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() -OPERANDS : REG0=YMM_N():w:qq:u64 REG1=YMM_B():r:qq:u64 IMM0:r:b # NDD -} +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x76 V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 +PATTERN : VV1 0x76 V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 +} { -ICLASS : VPSRAW +ICLASS : VPCMPEQQ CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 -EXCEPTIONS: avx-type-7 -PATTERN : VV1 0x71 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() -OPERANDS : REG0=YMM_N():w:qq:i16 REG1=YMM_B():r:qq:i16 IMM0:r:b # NDD +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x29 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 + +PATTERN : VV1 0x29 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 } + { -ICLASS : VPSRAD +ICLASS : VPCMPGTB CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 -EXCEPTIONS: avx-type-7 -PATTERN : VV1 0x72 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() -OPERANDS : REG0=YMM_N():w:qq:i32 REG1=YMM_B():r:qq:i32 IMM0:r:b # NDD +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x64 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 + +PATTERN : VV1 0x64 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 } { -ICLASS : VPSRLW +ICLASS : VPCMPGTW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 -EXCEPTIONS: avx-type-7 -PATTERN : VV1 0x71 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() -OPERANDS : REG0=YMM_N():w:qq:u16 REG1=YMM_B():r:qq:u16 IMM0:r:b # NDD +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x65 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0x65 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 } { -ICLASS : VPSRLD +ICLASS : VPCMPGTD CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 -EXCEPTIONS: avx-type-7 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x66 V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 -PATTERN : VV1 0x72 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() -OPERANDS : REG0=YMM_N():w:qq:u32 REG1=YMM_B():r:qq:u32 IMM0:r:b # NDD +PATTERN : VV1 0x66 V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 } { -ICLASS : VPSRLQ +ICLASS : VPCMPGTQ CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 -EXCEPTIONS: avx-type-7 -PATTERN : VV1 0x73 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() -OPERANDS : REG0=YMM_N():w:qq:u64 REG1=YMM_B():r:qq:u64 IMM0:r:b # NDD -} - +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x37 V66 V0F38 VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i64 MEM0:r:qq:i64 +PATTERN : VV1 0x37 V66 V0F38 VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i64 REG2=YMM_B():r:qq:i64 +} -############################################################################ -# SX versions -############################################################################ { -ICLASS : VPMOVSXBW +ICLASS : VPHADDW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 -EXCEPTIONS: avx-type-5 -PATTERN : VV1 0x20 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:i16 REG1=XMM_B():r:dq:i8 -PATTERN : VV1 0x20 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:i16 MEM0:r:dq:i8 -} +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x01 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 -############################################################################ +PATTERN : VV1 0x01 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} { -ICLASS : VPMOVSXBD +ICLASS : VPHADDD CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 -EXCEPTIONS: avx-type-5 -PATTERN : VV1 0x21 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:i32 REG1=XMM_B():r:q:i8 -PATTERN : VV1 0x21 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:i32 MEM0:r:q:i8 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x02 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 + +PATTERN : VV1 0x02 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 } -############################################################################ { -ICLASS : VPMOVSXBQ +ICLASS : VPHADDSW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 -EXCEPTIONS: avx-type-5 -PATTERN : VV1 0x22 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:i64 REG1=XMM_B():r:d:i8 -PATTERN : VV1 0x22 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:i64 MEM0:r:d:i8 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x03 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0x03 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 } -############################################################################ { -ICLASS : VPMOVSXWD +ICLASS : VPHSUBW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 -EXCEPTIONS: avx-type-5 -PATTERN : VV1 0x23 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:i32 REG1=XMM_B():r:dq:i16 -PATTERN : VV1 0x23 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:i32 MEM0:r:dq:i16 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x05 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0x05 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 } -############################################################################ { -ICLASS : VPMOVSXWQ +ICLASS : VPHSUBD CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 -EXCEPTIONS: avx-type-5 -PATTERN : VV1 0x24 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:i64 REG1=XMM_B():r:q:i16 -PATTERN : VV1 0x24 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:i64 MEM0:r:q:i16 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x06 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 + +PATTERN : VV1 0x06 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 } -############################################################################ { -ICLASS : VPMOVSXDQ +ICLASS : VPHSUBSW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 -EXCEPTIONS: avx-type-5 -PATTERN : VV1 0x25 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:i64 REG1=XMM_B():r:dq:i32 -PATTERN : VV1 0x25 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:i64 MEM0:r:dq:i32 -} - - - +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x07 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 +PATTERN : VV1 0x07 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} -############################################################################ -# ZX versions -############################################################################ +{ +ICLASS : VPMADDWD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xF5 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 +PATTERN : VV1 0xF5 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} { -ICLASS : VPMOVZXBW +ICLASS : VPMADDUBSW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 -EXCEPTIONS: avx-type-5 -PATTERN : VV1 0x30 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u16 REG1=XMM_B():r:dq:u8 -PATTERN : VV1 0x30 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u16 MEM0:r:dq:u8 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x04 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:u8 MEM0:r:qq:i8 + +PATTERN : VV1 0x04 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:i8 } -############################################################################ { -ICLASS : VPMOVZXBD +ICLASS : VPMAXSB CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 -EXCEPTIONS: avx-type-5 -PATTERN : VV1 0x31 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u32 REG1=XMM_B():r:q:u8 -PATTERN : VV1 0x31 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u32 MEM0:r:q:u8 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x3C VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 + +PATTERN : VV1 0x3C VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 } -############################################################################ { -ICLASS : VPMOVZXBQ +ICLASS : VPMAXSW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 -EXCEPTIONS: avx-type-5 -PATTERN : VV1 0x32 V66 V0F38 VL256 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u64 REG1=XMM_B():r:d:u8 -PATTERN : VV1 0x32 V66 V0F38 VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u64 MEM0:r:d:u8 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xEE VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0xEE VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 } -############################################################################ { -ICLASS : VPMOVZXWD +ICLASS : VPMAXSD CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 -EXCEPTIONS: avx-type-5 -PATTERN : VV1 0x33 V66 V0F38 VL256 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u32 REG1=XMM_B():r:dq:u16 -PATTERN : VV1 0x33 V66 V0F38 VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u32 MEM0:r:dq:u16 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x3D VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 + +PATTERN : VV1 0x3D VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 } -############################################################################ + { -ICLASS : VPMOVZXWQ +ICLASS : VPMAXUB CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 -EXCEPTIONS: avx-type-5 -PATTERN : VV1 0x34 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u64 REG1=XMM_B():r:q:u16 -PATTERN : VV1 0x34 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u64 MEM0:r:q:u16 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xDE VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 + +PATTERN : VV1 0xDE VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 } -############################################################################ { -ICLASS : VPMOVZXDQ +ICLASS : VPMAXUW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 -EXCEPTIONS: avx-type-5 -PATTERN : VV1 0x35 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u64 REG1=XMM_B():r:dq:u32 -PATTERN : VV1 0x35 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u64 MEM0:r:dq:u32 -} - - -################################## -# newer stuff 2009-08-14 - +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x3E VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 +PATTERN : VV1 0x3E VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 +} { -ICLASS : VINSERTI128 +ICLASS : VPMAXUD CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 -EXCEPTIONS: avx-type-6 -PATTERN : VV1 0x38 VL256 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() -OPERANDS : REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 MEM0:r:dq:u128 IMM0:r:b +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x3F VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 -PATTERN : VV1 0x38 VL256 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() -OPERANDS : REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 REG2=XMM_B():r:dq:u128 IMM0:r:b +PATTERN : VV1 0x3F VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 } - - - - { -ICLASS : VEXTRACTI128 +ICLASS : VPMINSB CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 -EXCEPTIONS: avx-type-6 -PATTERN : VV1 0x39 VL256 V66 V0F3A W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() -OPERANDS : MEM0:w:dq:u128 REG0=YMM_R():r:qq:u128 IMM0:r:b +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x38 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 -PATTERN : VV1 0x39 VL256 V66 V0F3A W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() -OPERANDS : REG0=XMM_B():w:dq:u128 REG1=YMM_R():r:qq:u128 IMM0:r:b +PATTERN : VV1 0x38 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 } - - -########################################################################### - -### # VPMASKMOVD masked load and store -### # VPMASKMOVQ masked load and store - - - - { -ICLASS : VPMASKMOVD +ICLASS : VPMINSW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 -ATTRIBUTES: maskop -EXCEPTIONS: avx-type-6 -PATTERN : VV1 0x8C VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 - +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xEA VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 -PATTERN : VV1 0x8C VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 +PATTERN : VV1 0xEA VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 } { -ICLASS : VPMASKMOVQ +ICLASS : VPMINSD CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 -ATTRIBUTES: maskop -EXCEPTIONS: avx-type-6 - -PATTERN : VV1 0x8C VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 - +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x39 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 -PATTERN : VV1 0x8C VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 +PATTERN : VV1 0x39 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 } { -ICLASS : VPMASKMOVD +ICLASS : VPMINUB CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 -ATTRIBUTES: maskop -EXCEPTIONS: avx-type-6 -PATTERN : VV1 0x8E VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : MEM0:w:dq:u32 REG0=XMM_N():r:dq:u32 REG1=XMM_R():r:dq:u32 - +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xDA VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 -PATTERN : VV1 0x8E VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : MEM0:w:qq:u32 REG0=YMM_N():r:qq:u32 REG1=YMM_R():r:qq:u32 +PATTERN : VV1 0xDA VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 } { -ICLASS : VPMASKMOVQ +ICLASS : VPMINUW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 -ATTRIBUTES: maskop -EXCEPTIONS: avx-type-6 -PATTERN : VV1 0x8E VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : MEM0:w:dq:u64 REG0=XMM_N():r:dq:u64 REG1=XMM_R():r:dq:u64 - +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x3A V66 V0F38 VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 -PATTERN : VV1 0x8E VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : MEM0:w:qq:u64 REG0=YMM_N():r:qq:u64 REG1=YMM_R():r:qq:u64 +PATTERN : VV1 0x3A V66 V0F38 VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 } -########################################################################### - - -### # VPERM2I128 256b only - { -ICLASS : VPERM2I128 +ICLASS : VPMINUD CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 -EXCEPTIONS: avx-type-6 # Note: vperm2f128 is type 4... - -PATTERN : VV1 0x46 VL256 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() -OPERANDS : REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 MEM0:r:qq:u128 IMM0:r:b +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x3B V66 V0F38 VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 -PATTERN : VV1 0x46 VL256 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() -OPERANDS : REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 REG2=YMM_B():r:qq:u128 IMM0:r:b +PATTERN : VV1 0x3B V66 V0F38 VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 } - { -ICLASS : VPERMQ +ICLASS : VPMULHUW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xE4 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 -PATTERN : VV1 0x00 VL256 V0F3A V66 W1 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() -OPERANDS : REG0=YMM_R():w:qq:u64 MEM0:r:qq:u64 IMM0:r:b - -PATTERN : VV1 0x00 VL256 V0F3A V66 W1 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() -OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_B():r:qq:u64 IMM0:r:b +PATTERN : VV1 0xE4 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 } - { -ICLASS : VPERMPD +ICLASS : VPMULHRSW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x0B VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 -PATTERN : VV1 0x01 VL256 V0F3A V66 W1 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() -OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:qq:f64 IMM0:r:b - -PATTERN : VV1 0x01 VL256 V0F3A V66 W1 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() -OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_B():r:qq:f64 IMM0:r:b +PATTERN : VV1 0x0B VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 } - - - - - - - { -ICLASS : VPERMD +ICLASS : VPMULHW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xE5 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 - -PATTERN : VV1 0x36 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 - -PATTERN : VV1 0x36 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 +PATTERN : VV1 0xE5 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 } { -ICLASS : VPERMPS +ICLASS : VPMULLW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xD5 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 -PATTERN : VV1 0x16 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 - -PATTERN : VV1 0x16 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +PATTERN : VV1 0xD5 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 } +{ +ICLASS : VPMULLD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x40 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 +PATTERN : VV1 0x40 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 +} -########################################################################### - - -### # VPBLENDD imm 128/256 +{ +ICLASS : VPMULUDQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xF4 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 +PATTERN : VV1 0xF4 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 +} +{ +ICLASS : VPMULDQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x28 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 +PATTERN : VV1 0x28 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 +} { -ICLASS : VPBLENDD +ICLASS : VPSADBW CPL : 3 CATEGORY : AVX2 EXTENSION : AVX2 EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xF6 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 -PATTERN : VV1 0x02 VL128 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() -OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 IMM0:r:b - -PATTERN : VV1 0x02 VL128 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() -OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 IMM0:r:b +PATTERN : VV1 0xF6 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 +} +{ +ICLASS : VPSHUFB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x00 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 +PATTERN : VV1 0x00 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 +} -PATTERN : VV1 0x02 VL256 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() -OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 IMM0:r:b +{ +ICLASS : VPSIGNB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x08 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 -PATTERN : VV1 0x02 VL256 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() -OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 IMM0:r:b +PATTERN : VV1 0x08 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 } +{ +ICLASS : VPSIGNW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x09 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 +PATTERN : VV1 0x09 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} +{ +ICLASS : VPSIGND +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x0A VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 +PATTERN : VV1 0x0A VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 +} -########################################################################### { -ICLASS : VPBROADCASTB -COMMENT : gpr 128/256 +ICLASS : VPSUBSB CPL : 3 -CATEGORY : BROADCAST +CATEGORY : AVX2 EXTENSION : AVX2 -EXCEPTIONS: avx-type-6 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xE8 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 -PATTERN : VV1 0x78 VL128 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():w:dq:u8 MEM0:r:b:u8 EMX_BROADCAST_1TO16_8 +PATTERN : VV1 0xE8 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 +} +{ +ICLASS : VPSUBSW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xE9 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 -PATTERN : VV1 0x78 VL128 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_B():r:b:u8 EMX_BROADCAST_1TO16_8 +PATTERN : VV1 0xE9 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} -PATTERN : VV1 0x78 VL256 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u8 MEM0:r:b:u8 EMX_BROADCAST_1TO32_8 +{ +ICLASS : VPSUBUSB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xD8 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 -PATTERN : VV1 0x78 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u8 REG1=XMM_B():r:b:u8 EMX_BROADCAST_1TO32_8 +PATTERN : VV1 0xD8 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 +} +{ +ICLASS : VPSUBUSW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xD9 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 +PATTERN : VV1 0xD9 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 } +{ +ICLASS : VPSUBB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xF8 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 +PATTERN : VV1 0xF8 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 +} +{ +ICLASS : VPSUBW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xF9 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 +PATTERN : VV1 0xF9 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} +{ +ICLASS : VPSUBD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xFA VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 +PATTERN : VV1 0xFA VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 +} { -ICLASS : VPBROADCASTW -COMMENT : gpr 128/256 +ICLASS : VPSUBQ CPL : 3 -CATEGORY : BROADCAST +CATEGORY : AVX2 EXTENSION : AVX2 -EXCEPTIONS: avx-type-6 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xFB VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i64 MEM0:r:qq:i64 -PATTERN : VV1 0x79 VL128 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():w:dq:u16 MEM0:r:w:u16 EMX_BROADCAST_1TO8_16 +PATTERN : VV1 0xFB VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i64 REG2=YMM_B():r:qq:i64 +} -PATTERN : VV1 0x79 VL128 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:w:u16 EMX_BROADCAST_1TO8_16 +{ +ICLASS : VPUNPCKHBW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x68 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 -PATTERN : VV1 0x79 VL256 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u16 MEM0:r:w:u16 EMX_BROADCAST_1TO16_16 +PATTERN : VV1 0x68 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 +} +{ +ICLASS : VPUNPCKHWD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x69 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 -PATTERN : VV1 0x79 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u16 REG1=XMM_B():r:w:u16 EMX_BROADCAST_1TO16_16 +PATTERN : VV1 0x69 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 } +{ +ICLASS : VPUNPCKHDQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x6A VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 +PATTERN : VV1 0x6A VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 +} +{ +ICLASS : VPUNPCKHQDQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x6D VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 +PATTERN : VV1 0x6D VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 +} +{ +ICLASS : VPUNPCKLBW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x60 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 -### # VPBROADCASTD gpr/mem +PATTERN : VV1 0x60 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 +} +{ +ICLASS : VPUNPCKLWD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x61 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 +PATTERN : VV1 0x61 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 +} +{ +ICLASS : VPUNPCKLDQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x62 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 +PATTERN : VV1 0x62 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 +} { -ICLASS : VPBROADCASTD -COMMENT : gpr 128/256 +ICLASS : VPUNPCKLQDQ CPL : 3 -CATEGORY : BROADCAST +CATEGORY : AVX2 EXTENSION : AVX2 -EXCEPTIONS: avx-type-6 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x6C VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 -PATTERN : VV1 0x58 VL128 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():w:dq:u32 MEM0:r:d:u32 EMX_BROADCAST_1TO4_32 +PATTERN : VV1 0x6C VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 +} -PATTERN : VV1 0x58 VL128 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:d:u32 EMX_BROADCAST_1TO4_32 +{ +ICLASS : VPALIGNR +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x0F VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 IMM0:r:b -PATTERN : VV1 0x58 VL256 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u32 MEM0:r:d:u32 EMX_BROADCAST_1TO8_32 +PATTERN : VV1 0x0F VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 IMM0:r:b +} +{ +ICLASS : VPBLENDW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x0E VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 IMM0:r:b -PATTERN : VV1 0x58 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u32 REG1=XMM_B():r:d:u32 EMX_BROADCAST_1TO8_32 +PATTERN : VV1 0x0E VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 IMM0:r:b } +{ +ICLASS : VMPSADBW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x42 VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 IMM0:r:b +PATTERN : VV1 0x42 VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 IMM0:r:b +} -### # VPBROADCASTQ gpr/mem { -ICLASS : VPBROADCASTQ -COMMENT : gpr 128/256 +ICLASS : VPOR CPL : 3 -CATEGORY : BROADCAST +CATEGORY : LOGICAL EXTENSION : AVX2 -EXCEPTIONS: avx-type-6 - -PATTERN : VV1 0x59 VL128 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():w:dq:u64 MEM0:r:q:u64 EMX_BROADCAST_1TO2_64 - -PATTERN : VV1 0x59 VL128 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:q:u64 EMX_BROADCAST_1TO2_64 - -PATTERN : VV1 0x59 VL256 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u64 MEM0:r:q:u64 EMX_BROADCAST_1TO4_64 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xEB VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 MEM0:r:qq:u256 -PATTERN : VV1 0x59 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:u64 REG1=XMM_B():r:q:u64 EMX_BROADCAST_1TO4_64 +PATTERN : VV1 0xEB VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 REG2=YMM_B():r:qq:u256 } +{ +ICLASS : VPAND +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xDB VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 MEM0:r:qq:u256 +PATTERN : VV1 0xDB VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 REG2=YMM_B():r:qq:u256 +} +{ +ICLASS : VPANDN +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xDF VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 MEM0:r:qq:u256 +PATTERN : VV1 0xDF VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 REG2=YMM_B():r:qq:u256 +} +{ +ICLASS : VPXOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xEF VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 MEM0:r:qq:u256 +PATTERN : VV1 0xEF VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 REG2=YMM_B():r:qq:u256 +} { -ICLASS : VBROADCASTSS +ICLASS : VPBLENDVB CPL : 3 -CATEGORY : BROADCAST +CATEGORY : AVX2 EXTENSION : AVX2 -EXCEPTIONS: avx-type-6 -COMMENT : xmm,xmm and ymm,xmm -PATTERN : VV1 0x18 VL128 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 EMX_BROADCAST_1TO4_32 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x4C VL256 V66 V0F3A norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 REG2=YMM_SE():r:qq:u8 -PATTERN : VV1 0x18 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:f32 REG1=XMM_B():r:dq:f32 EMX_BROADCAST_1TO8_32 +PATTERN : VV1 0x4C VL256 V66 V0F3A norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 REG3=YMM_SE():r:qq:u8 } + + { -ICLASS : VBROADCASTSD +ICLASS : VPMOVMSKB CPL : 3 -CATEGORY : BROADCAST +CATEGORY : AVX2 EXTENSION : AVX2 -EXCEPTIONS: avx-type-6 -COMMENT : ymm,xmm only -PATTERN : VV1 0x19 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():w:qq:f64 REG1=XMM_B():r:dq:f64 EMX_BROADCAST_1TO4_64 +EXCEPTIONS: avx-type-7 +PATTERN : VV1 0xD7 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():w:d:u32 REG1=YMM_B():r:qq:i8 } { -ICLASS : VBROADCASTI128 +ICLASS : VPSHUFD CPL : 3 -CATEGORY : BROADCAST +CATEGORY : AVX2 EXTENSION : AVX2 -EXCEPTIONS: avx-type-6 -COMMENT : memonly 256 -- FIXME: make types u64 like in AVX1? -PATTERN : VV1 0x5A VL256 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():w:qq:u128 MEM0:r:dq:u128 EMX_BROADCAST_2TO4_64 -} - - -###FILE: ../xed/datafiles/avxhsw/hsw-isa.txt - -#BEGIN_LEGAL -# -#Copyright (c) 2016 Intel Corporation -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -#END_LEGAL -INSTRUCTIONS():: +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x70 VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u32 MEM0:r:qq:u32 IMM0:r:b +PATTERN : VV1 0x70 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_B():r:qq:u32 IMM0:r:b +} { -ICLASS : TZCNT +ICLASS : VPSHUFHW CPL : 3 -CATEGORY : BMI1 -EXTENSION : BMI1 -FLAGS : MUST [ of-u sf-u zf-mod af-u pf-u cf-mod ] -PATTERN : 0x0F 0xBC refining_f3 TZCNT=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=GPRv_R():w MEM0:r:v +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x70 VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u16 MEM0:r:qq:u16 IMM0:r:b -PATTERN : 0x0F 0xBC refining_f3 TZCNT=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=GPRv_R():w REG1=GPRv_B():r +PATTERN : VV1 0x70 VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_B():r:qq:u16 IMM0:r:b } - { -ICLASS : BSF -VERSION : 1 -COMMENT : AMD reused 0FBC for TZCNT and made BSF not have a refining prefix. This version replaces the normal version of BSF +ICLASS : VPSHUFLW CPL : 3 -CATEGORY : BITBYTE -EXTENSION : BASE -ISA_SET : I386 -FLAGS : MUST [ of-u sf-u zf-mod af-u pf-u cf-u ] +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x70 VL256 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u16 MEM0:r:qq:u16 IMM0:r:b -PATTERN : 0x0F 0xBC not_refining_f3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=GPRv_R():cw MEM0:r:v +PATTERN : VV1 0x70 VL256 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_B():r:qq:u16 IMM0:r:b +} -PATTERN : 0x0F 0xBC not_refining_f3 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r -PATTERN : 0x0F 0xBC refining_f3 TZCNT=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=GPRv_R():cw MEM0:r:v -PATTERN : 0x0F 0xBC refining_f3 TZCNT=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +{ +ICLASS : VPSRLDQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-7 +PATTERN : VV1 0x73 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b011] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_N():w:qq:u128 REG1=YMM_B():r:qq:u128 IMM0:r:b # NDD } - { -ICLASS : INVPCID -CPL : 0 -CATEGORY : MISC -EXTENSION : INVPCID -ISA_SET : INVPCID -ATTRIBUTES : RING0 NOTSX -PATTERN : 0x0F 0x38 0x82 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode64 MODRM() CR_WIDTH() -OPERANDS : REG0=GPR64_R():r MEM0:r:dq -PATTERN : 0x0F 0x38 0x82 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode32 MODRM() CR_WIDTH() -OPERANDS : REG0=GPR32_R():r MEM0:r:dq -COMMENT : +ICLASS : VPSLLDQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-7 +PATTERN : VV1 0x73 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b111] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_N():w:qq:u128 REG1=YMM_B():r:qq:u128 IMM0:r:b # NDD } - -###FILE: ../xed/datafiles/avxhsw/hsw-lzcnt.txt - -#BEGIN_LEGAL -# -#Copyright (c) 2016 Intel Corporation -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -#END_LEGAL -INSTRUCTIONS():: - -# LZCNT reg16, reg/mem16 F30FBD /r -# LZCNT reg32, reg/mem32 F30FBD /r -# LZCNT reg64, reg/mem64 F30FBD /r +############################################## { -ICLASS : LZCNT -# This replace the AMD version in LZCNT builds -VERSION : 2 +ICLASS : VPSLLW CPL : 3 -CATEGORY : LZCNT -EXTENSION : LZCNT -COMMENT: : These next one WAS introduced first by AMD circa SSE4a. -FLAGS : MUST [ cf-mod zf-mod of-u af-u pf-u sf-u ] -PATTERN : 0x0F 0xBD f3_refining_prefix LZCNT=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=GPRv_R():w:v MEM0:r:v -PATTERN : 0x0F 0xBD f3_refining_prefix LZCNT=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=GPRv_R():w:v REG1=GPRv_B():r:v +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-7 +PATTERN : VV1 0x71 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_N():w:qq:u16 REG1=YMM_B():r:qq:u16 IMM0:r:b # NDD } - - { -ICLASS : BSR -VERSION : 2 -COMMENT : AMD reused 0FBD for LZCNT and made BSR not have a refining prefix. This version replaces the normal version of BSR +ICLASS : VPSLLD CPL : 3 -CATEGORY : BITBYTE -EXTENSION : BASE -ISA_SET : I386 -FLAGS : MUST [ of-u sf-u zf-mod af-u pf-u cf-u ] -PATTERN : 0x0F 0xBD not_refining_f3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=GPRv_R():cw MEM0:r:v - -PATTERN : 0x0F 0xBD not_refining_f3 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-7 +PATTERN : VV1 0x72 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_N():w:qq:u32 REG1=YMM_B():r:qq:u32 IMM0:r:b #NDD +} +{ +ICLASS : VPSLLQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-7 +PATTERN : VV1 0x73 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_N():w:qq:u64 REG1=YMM_B():r:qq:u64 IMM0:r:b # NDD +} -PATTERN : 0x0F 0xBD refining_f3 LZCNT=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=GPRv_R():cw MEM0:r:v +{ +ICLASS : VPSRAW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-7 +PATTERN : VV1 0x71 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_N():w:qq:i16 REG1=YMM_B():r:qq:i16 IMM0:r:b # NDD +} +{ +ICLASS : VPSRAD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-7 +PATTERN : VV1 0x72 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_N():w:qq:i32 REG1=YMM_B():r:qq:i32 IMM0:r:b # NDD +} +{ +ICLASS : VPSRLW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-7 +PATTERN : VV1 0x71 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_N():w:qq:u16 REG1=YMM_B():r:qq:u16 IMM0:r:b # NDD +} +{ +ICLASS : VPSRLD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-7 -PATTERN : 0x0F 0xBD refining_f3 LZCNT=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +PATTERN : VV1 0x72 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_N():w:qq:u32 REG1=YMM_B():r:qq:u32 IMM0:r:b # NDD +} +{ +ICLASS : VPSRLQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-7 +PATTERN : VV1 0x73 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_N():w:qq:u64 REG1=YMM_B():r:qq:u64 IMM0:r:b # NDD } -###FILE: ../xed/datafiles/avxhsw/hsw-vex-gpr-isa.txt -#BEGIN_LEGAL -# -#Copyright (c) 2016 Intel Corporation -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -#END_LEGAL +############################################################################ +# SX versions +############################################################################ -AVX_INSTRUCTIONS():: +{ +ICLASS : VPMOVSXBW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-5 +PATTERN : VV1 0x20 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=XMM_B():r:dq:i8 +PATTERN : VV1 0x20 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 MEM0:r:dq:i8 +} +############################################################################ { -ICLASS : PDEP +ICLASS : VPMOVSXBD CPL : 3 -CATEGORY : BMI2 -EXTENSION : BMI2 -FLAGS : MUST [ of-u sf-u zf-mod af-u pf-u cf-mod ] +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-5 +PATTERN : VV1 0x21 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=XMM_B():r:q:i8 +PATTERN : VV1 0x21 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 MEM0:r:q:i8 +} +############################################################################ +{ +ICLASS : VPMOVSXBQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-5 +PATTERN : VV1 0x22 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i64 REG1=XMM_B():r:d:i8 +PATTERN : VV1 0x22 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i64 MEM0:r:d:i8 +} +############################################################################ +{ +ICLASS : VPMOVSXWD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-5 +PATTERN : VV1 0x23 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=XMM_B():r:dq:i16 +PATTERN : VV1 0x23 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 MEM0:r:dq:i16 +} +############################################################################ +{ +ICLASS : VPMOVSXWQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-5 +PATTERN : VV1 0x24 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i64 REG1=XMM_B():r:q:i16 +PATTERN : VV1 0x24 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i64 MEM0:r:q:i16 +} +############################################################################ +{ +ICLASS : VPMOVSXDQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-5 +PATTERN : VV1 0x25 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i64 REG1=XMM_B():r:dq:i32 +PATTERN : VV1 0x25 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i64 MEM0:r:dq:i32 +} -#32b -PATTERN : VV1 0xF5 V0F38 VF2 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d MEM0:r:d -PATTERN : VV1 0xF5 V0F38 VF2 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d MEM0:r:d -PATTERN : VV1 0xF5 V0F38 VF2 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d -PATTERN : VV1 0xF5 V0F38 VF2 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d -# 64b -PATTERN : VV1 0xF5 V0F38 VF2 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=VGPR64_R():rw:q REG1=VGPR64_N():r:q MEM0:r:q +############################################################################ +# ZX versions +############################################################################ -PATTERN : VV1 0xF5 V0F38 VF2 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=VGPR64_R():rw:q REG1=VGPR64_N():r:q REG2=VGPR64_B():r:q +{ +ICLASS : VPMOVZXBW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-5 +PATTERN : VV1 0x30 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=XMM_B():r:dq:u8 +PATTERN : VV1 0x30 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 MEM0:r:dq:u8 } +############################################################################ { -ICLASS : PEXT +ICLASS : VPMOVZXBD CPL : 3 -CATEGORY : BMI2 -EXTENSION : BMI2 -FLAGS : MUST [ of-u sf-u zf-mod af-u pf-u cf-mod ] - - -#32b -PATTERN : VV1 0xF5 V0F38 VF3 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d MEM0:r:d - -PATTERN : VV1 0xF5 V0F38 VF3 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d MEM0:r:d - -PATTERN : VV1 0xF5 V0F38 VF3 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d - -PATTERN : VV1 0xF5 V0F38 VF3 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-5 +PATTERN : VV1 0x31 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=XMM_B():r:q:u8 +PATTERN : VV1 0x31 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u32 MEM0:r:q:u8 +} +############################################################################ +{ +ICLASS : VPMOVZXBQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-5 +PATTERN : VV1 0x32 V66 V0F38 VL256 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=XMM_B():r:d:u8 +PATTERN : VV1 0x32 V66 V0F38 VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 MEM0:r:d:u8 +} +############################################################################ +{ +ICLASS : VPMOVZXWD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-5 +PATTERN : VV1 0x33 V66 V0F38 VL256 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=XMM_B():r:dq:u16 +PATTERN : VV1 0x33 V66 V0F38 VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u32 MEM0:r:dq:u16 +} +############################################################################ +{ +ICLASS : VPMOVZXWQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-5 +PATTERN : VV1 0x34 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=XMM_B():r:q:u16 +PATTERN : VV1 0x34 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 MEM0:r:q:u16 +} +############################################################################ +{ +ICLASS : VPMOVZXDQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-5 +PATTERN : VV1 0x35 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=XMM_B():r:dq:u32 +PATTERN : VV1 0x35 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 MEM0:r:dq:u32 +} -# 64b -PATTERN : VV1 0xF5 V0F38 VF3 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=VGPR64_R():rw:q REG1=VGPR64_N():r:q MEM0:r:q -PATTERN : VV1 0xF5 V0F38 VF3 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=VGPR64_R():rw:q REG1=VGPR64_N():r:q REG2=VGPR64_B():r:q -} +################################## +# newer stuff 2009-08-14 { -ICLASS : ANDN +ICLASS : VINSERTI128 CPL : 3 -CATEGORY : BMI1 -EXTENSION : BMI1 -FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] - -# 32b -PATTERN : VV1 0xF2 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d MEM0:r:d +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-6 +PATTERN : VV1 0x38 VL256 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 MEM0:r:dq:u128 IMM0:r:b -PATTERN : VV1 0xF2 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d MEM0:r:d +PATTERN : VV1 0x38 VL256 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 REG2=XMM_B():r:dq:u128 IMM0:r:b +} -PATTERN : VV1 0xF2 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d -PATTERN : VV1 0xF2 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d -# 64b -PATTERN : VV1 0xF2 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=VGPR64_R():rw:q REG1=VGPR64_N():r:q MEM0:r:q -PATTERN : VV1 0xF2 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=VGPR64_R():rw:q REG1=VGPR64_N():r:q REG2=VGPR64_B():r:q -} { -ICLASS : BLSR +ICLASS : VEXTRACTI128 CPL : 3 -CATEGORY : BMI1 -EXTENSION : BMI1 -FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-u cf-mod ] +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-6 +PATTERN : VV1 0x39 VL256 V66 V0F3A W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:w:dq:u128 REG0=YMM_R():r:qq:u128 IMM0:r:b -# 32b -PATTERN : VV1 0xF3 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() -OPERANDS : REG0=VGPR32_N():w:d MEM0:r:d +PATTERN : VV1 0x39 VL256 V66 V0F3A W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_B():w:dq:u128 REG1=YMM_R():r:qq:u128 IMM0:r:b +} -PATTERN : VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() -OPERANDS : REG0=VGPR32_N():w:d MEM0:r:d -PATTERN : VV1 0xF3 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[0b001] RM[nnn] -OPERANDS : REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d +########################################################################### -PATTERN : VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[0b001] RM[nnn] -OPERANDS : REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d +### # VPMASKMOVD masked load and store +### # VPMASKMOVQ masked load and store -# 64b -PATTERN : VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() -OPERANDS : REG0=VGPR64_N():w:q MEM0:r:q -PATTERN : VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[0b001] RM[nnn] -OPERANDS : REG0=VGPR64_N():w:q REG1=VGPR64_B():r:q -} { -ICLASS : BLSMSK +ICLASS : VPMASKMOVD CPL : 3 -CATEGORY : BMI1 -EXTENSION : BMI1 -FLAGS : MUST [ of-0 sf-mod zf-0 af-u pf-u cf-mod ] - -#32b -PATTERN : VV1 0xF3 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() -OPERANDS : REG0=VGPR32_N():w:d MEM0:r:d +CATEGORY : AVX2 +EXTENSION : AVX2 +ATTRIBUTES: maskop +EXCEPTIONS: avx-type-6 +PATTERN : VV1 0x8C VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 -PATTERN : VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() -OPERANDS : REG0=VGPR32_N():w:d MEM0:r:d -PATTERN : VV1 0xF3 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[0b010] RM[nnn] -OPERANDS : REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d +PATTERN : VV1 0x8C VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 +} +{ +ICLASS : VPMASKMOVQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +ATTRIBUTES: maskop +EXCEPTIONS: avx-type-6 -PATTERN : VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[0b010] RM[nnn] -OPERANDS : REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d +PATTERN : VV1 0x8C VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 -#64b -PATTERN : VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() -OPERANDS : REG0=VGPR64_N():w:q MEM0:r:q -PATTERN : VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[0b010] RM[nnn] -OPERANDS : REG0=VGPR64_N():w:q REG1=VGPR64_B():r:q +PATTERN : VV1 0x8C VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 } { -ICLASS : BLSI +ICLASS : VPMASKMOVD CPL : 3 -CATEGORY : BMI1 -EXTENSION : BMI1 -FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-u cf-0 ] +CATEGORY : AVX2 +EXTENSION : AVX2 +ATTRIBUTES: maskop +EXCEPTIONS: avx-type-6 +PATTERN : VV1 0x8E VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:dq:u32 REG0=XMM_N():r:dq:u32 REG1=XMM_R():r:dq:u32 -# 32b -PATTERN : VV1 0xF3 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() -OPERANDS : REG0=VGPR32_N():w:d MEM0:r:d -PATTERN : VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() -OPERANDS : REG0=VGPR32_N():w:d MEM0:r:d +PATTERN : VV1 0x8E VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:qq:u32 REG0=YMM_N():r:qq:u32 REG1=YMM_R():r:qq:u32 +} +{ +ICLASS : VPMASKMOVQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +ATTRIBUTES: maskop +EXCEPTIONS: avx-type-6 +PATTERN : VV1 0x8E VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:dq:u64 REG0=XMM_N():r:dq:u64 REG1=XMM_R():r:dq:u64 -PATTERN : VV1 0xF3 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[0b011] RM[nnn] -OPERANDS : REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d -PATTERN : VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[0b011] RM[nnn] -OPERANDS : REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d +PATTERN : VV1 0x8E VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:qq:u64 REG0=YMM_N():r:qq:u64 REG1=YMM_R():r:qq:u64 +} +########################################################################### -# 64b -PATTERN : VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() -OPERANDS : REG0=VGPR64_N():w:q MEM0:r:q -PATTERN : VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[0b011] RM[nnn] -OPERANDS : REG0=VGPR64_N():w:q REG1=VGPR64_B():r:q -} +### # VPERM2I128 256b only { -ICLASS : BZHI +ICLASS : VPERM2I128 CPL : 3 -CATEGORY : BMI2 -EXTENSION : BMI2 -FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-mod ] +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-6 # Note: vperm2f128 is type 4... -# 32b -PATTERN : VV1 0xF5 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d +PATTERN : VV1 0x46 VL256 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 MEM0:r:qq:u128 IMM0:r:b -PATTERN : VV1 0xF5 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d +PATTERN : VV1 0x46 VL256 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 REG2=YMM_B():r:qq:u128 IMM0:r:b +} -PATTERN : VV1 0xF5 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d -PATTERN : VV1 0xF5 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d +{ +ICLASS : VPERMQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 -# 64b -PATTERN : VV1 0xF5 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=VGPR64_R():w:q MEM0:r:q REG1=VGPR64_N():r:q +PATTERN : VV1 0x00 VL256 V0F3A V66 W1 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u64 MEM0:r:qq:u64 IMM0:r:b -PATTERN : VV1 0xF5 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_B():r:q REG2=VGPR64_N():r:q +PATTERN : VV1 0x00 VL256 V0F3A V66 W1 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_B():r:qq:u64 IMM0:r:b } { -ICLASS : BEXTR +ICLASS : VPERMPD CPL : 3 -CATEGORY : BMI1 -EXTENSION : BMI1 -FLAGS : MUST [ of-u sf-u zf-mod af-u pf-u cf-u ] +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 -# 32b -PATTERN : VV1 0xF7 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d +PATTERN : VV1 0x01 VL256 V0F3A V66 W1 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:qq:f64 IMM0:r:b + +PATTERN : VV1 0x01 VL256 V0F3A V66 W1 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_B():r:qq:f64 IMM0:r:b +} -PATTERN : VV1 0xF7 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d -PATTERN : VV1 0xF7 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d -PATTERN : VV1 0xF7 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d -# 64b -PATTERN : VV1 0xF7 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=VGPR64_R():w:q MEM0:r:q REG1=VGPR64_N():r:q -PATTERN : VV1 0xF7 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_B():r:q REG2=VGPR64_N():r:q -} { -ICLASS : SHLX +ICLASS : VPERMD CPL : 3 -CATEGORY : BMI2 -EXTENSION : BMI2 - -# 32b -PATTERN : VV1 0xF7 V0F38 V66 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 -PATTERN : VV1 0xF7 V0F38 V66 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d -PATTERN : VV1 0xF7 V0F38 V66 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d +PATTERN : VV1 0x36 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 -PATTERN : VV1 0xF7 V0F38 V66 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d +PATTERN : VV1 0x36 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 +} +{ +ICLASS : VPERMPS +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 -# 64b -PATTERN : VV1 0xF7 V0F38 V66 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=VGPR64_R():w:q MEM0:r:q REG1=VGPR64_N():r:q +PATTERN : VV1 0x16 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 -PATTERN : VV1 0xF7 V0F38 V66 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_B():r:q REG2=VGPR64_N():r:q +PATTERN : VV1 0x16 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 } + + +########################################################################### + + +### # VPBLENDD imm 128/256 + + + { -ICLASS : SARX +ICLASS : VPBLENDD CPL : 3 -CATEGORY : BMI2 -EXTENSION : BMI2 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 -# 32b -PATTERN : VV1 0xF7 V0F38 VF3 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d +PATTERN : VV1 0x02 VL128 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 IMM0:r:b -PATTERN : VV1 0xF7 V0F38 VF3 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d +PATTERN : VV1 0x02 VL128 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 IMM0:r:b -PATTERN : VV1 0xF7 V0F38 VF3 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d -PATTERN : VV1 0xF7 V0F38 VF3 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d +PATTERN : VV1 0x02 VL256 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 IMM0:r:b -# 64b -PATTERN : VV1 0xF7 V0F38 VF3 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=VGPR64_R():w:q MEM0:r:q REG1=VGPR64_N():r:q +PATTERN : VV1 0x02 VL256 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 IMM0:r:b +} + + + +########################################################################### + +{ +ICLASS : VPBROADCASTB +COMMENT : gpr 128/256 +CPL : 3 +CATEGORY : BROADCAST +EXTENSION : AVX2 +EXCEPTIONS: avx-type-6 + +PATTERN : VV1 0x78 VL128 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u8 MEM0:r:b:u8 EMX_BROADCAST_1TO16_8 + +PATTERN : VV1 0x78 VL128 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_B():r:b:u8 EMX_BROADCAST_1TO16_8 + +PATTERN : VV1 0x78 VL256 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u8 MEM0:r:b:u8 EMX_BROADCAST_1TO32_8 + +PATTERN : VV1 0x78 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=XMM_B():r:b:u8 EMX_BROADCAST_1TO32_8 -PATTERN : VV1 0xF7 V0F38 VF3 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_B():r:q REG2=VGPR64_N():r:q } + + + + { -ICLASS : SHRX +ICLASS : VPBROADCASTW +COMMENT : gpr 128/256 CPL : 3 -CATEGORY : BMI2 -EXTENSION : BMI2 +CATEGORY : BROADCAST +EXTENSION : AVX2 +EXCEPTIONS: avx-type-6 -# 32b -PATTERN : VV1 0xF7 V0F38 VF2 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d +PATTERN : VV1 0x79 VL128 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u16 MEM0:r:w:u16 EMX_BROADCAST_1TO8_16 -PATTERN : VV1 0xF7 V0F38 VF2 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d +PATTERN : VV1 0x79 VL128 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:w:u16 EMX_BROADCAST_1TO8_16 -PATTERN : VV1 0xF7 V0F38 VF2 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d +PATTERN : VV1 0x79 VL256 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 MEM0:r:w:u16 EMX_BROADCAST_1TO16_16 -PATTERN : VV1 0xF7 V0F38 VF2 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d +PATTERN : VV1 0x79 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=XMM_B():r:w:u16 EMX_BROADCAST_1TO16_16 +} -# 64b -PATTERN : VV1 0xF7 V0F38 VF2 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=VGPR64_R():w:q MEM0:r:q REG1=VGPR64_N():r:q -PATTERN : VV1 0xF7 V0F38 VF2 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_B():r:q REG2=VGPR64_N():r:q + + +### # VPBROADCASTD gpr/mem + + +{ +ICLASS : VPBROADCASTD +COMMENT : gpr 128/256 +CPL : 3 +CATEGORY : BROADCAST +EXTENSION : AVX2 +EXCEPTIONS: avx-type-6 + +PATTERN : VV1 0x58 VL128 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u32 MEM0:r:d:u32 EMX_BROADCAST_1TO4_32 + +PATTERN : VV1 0x58 VL128 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:d:u32 EMX_BROADCAST_1TO4_32 + + +PATTERN : VV1 0x58 VL256 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u32 MEM0:r:d:u32 EMX_BROADCAST_1TO8_32 + +PATTERN : VV1 0x58 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=XMM_B():r:d:u32 EMX_BROADCAST_1TO8_32 } +### # VPBROADCASTQ gpr/mem + { -ICLASS : MULX +ICLASS : VPBROADCASTQ +COMMENT : gpr 128/256 CPL : 3 -CATEGORY : BMI2 -EXTENSION : BMI2 +CATEGORY : BROADCAST +EXTENSION : AVX2 +EXCEPTIONS: avx-type-6 -# reg:w vvvv:w rm:r rdx:r -# 32b -PATTERN : VV1 0xF6 VF2 V0F38 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():w:d REG2=VGPR32_B():r:d REG3=XED_REG_EDX:r:SUPP +PATTERN : VV1 0x59 VL128 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 MEM0:r:q:u64 EMX_BROADCAST_1TO2_64 -PATTERN : VV1 0xF6 VF2 V0F38 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():w:d REG2=VGPR32_B():r:d REG3=XED_REG_EDX:r:SUPP -PATTERN : VV1 0xF6 VF2 V0F38 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():w:d MEM0:r:d REG2=XED_REG_EDX:r:SUPP +PATTERN : VV1 0x59 VL128 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:q:u64 EMX_BROADCAST_1TO2_64 -PATTERN : VV1 0xF6 VF2 V0F38 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():w:d MEM0:r:d REG2=XED_REG_EDX:r:SUPP +PATTERN : VV1 0x59 VL256 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 MEM0:r:q:u64 EMX_BROADCAST_1TO4_64 -# 64b -PATTERN : VV1 0xF6 VF2 V0F38 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_N():w:q REG2=VGPR64_B():r:q REG3=XED_REG_RDX:r:SUPP -PATTERN : VV1 0xF6 VF2 V0F38 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_N():w:q MEM0:r:q REG2=XED_REG_RDX:r:SUPP +PATTERN : VV1 0x59 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=XMM_B():r:q:u64 EMX_BROADCAST_1TO4_64 } + + + + + { -ICLASS : RORX +ICLASS : VBROADCASTSS CPL : 3 -CATEGORY : BMI2 -EXTENSION : BMI2 +CATEGORY : BROADCAST +EXTENSION : AVX2 +EXCEPTIONS: avx-type-6 +COMMENT : xmm,xmm and ymm,xmm +PATTERN : VV1 0x18 VL128 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 EMX_BROADCAST_1TO4_32 -# reg(w) rm(r) / vvvv must be 1111. / 2010-01-08 CART change +PATTERN : VV1 0x18 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=XMM_B():r:dq:f32 EMX_BROADCAST_1TO8_32 +} -# 32b -PATTERN : VV1 0xF0 VF2 V0F3A not64 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() -OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d IMM0:r:b -PATTERN : VV1 0xF0 VF2 V0F3A W0 mode64 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() -OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d IMM0:r:b -PATTERN : VV1 0xF0 VF2 V0F3A not64 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() -OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d IMM0:r:b +{ +ICLASS : VBROADCASTSD +CPL : 3 +CATEGORY : BROADCAST +EXTENSION : AVX2 +EXCEPTIONS: avx-type-6 +COMMENT : ymm,xmm only +PATTERN : VV1 0x19 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=XMM_B():r:dq:f64 EMX_BROADCAST_1TO4_64 +} -PATTERN : VV1 0xF0 VF2 V0F3A W0 mode64 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() -OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d IMM0:r:b -# 64b -PATTERN : VV1 0xF0 VF2 V0F3A W1 VL128 NOVSR mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() -OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_B():r:q IMM0:r:b -PATTERN : VV1 0xF0 VF2 V0F3A W1 VL128 NOVSR mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() -OPERANDS : REG0=VGPR64_R():w:q MEM0:r:q IMM0:r:b + +{ +ICLASS : VBROADCASTI128 +CPL : 3 +CATEGORY : BROADCAST +EXTENSION : AVX2 +EXCEPTIONS: avx-type-6 +COMMENT : memonly 256 -- FIXME: make types u64 like in AVX1? +PATTERN : VV1 0x5A VL256 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u128 MEM0:r:dq:u128 EMX_BROADCAST_2TO4_64 } -###FILE: ../xed/datafiles/avxhsw/hsw-vshift-isa.txt +###FILE: ../xed/datafiles/hswavx/hsw-vshift-isa.txt #BEGIN_LEGAL # -#Copyright (c) 2016 Intel Corporation +#Copyright (c) 2018 Intel Corporation # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -25518,11 +27880,11 @@ OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq -###FILE: ../xed/datafiles/avxhsw/movnt-load-isa.txt +###FILE: ../xed/datafiles/hswavx/movnt-load-isa.txt #BEGIN_LEGAL # -#Copyright (c) 2016 Intel Corporation +#Copyright (c) 2018 Intel Corporation # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -25546,7 +27908,7 @@ CPL : 3 CATEGORY : DATAXFER EXTENSION : AVX2 EXCEPTIONS: avx-type-1 -ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX +ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX NONTEMPORAL PATTERN : VV1 0x2A V66 V0F38 VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() OPERANDS : REG0=YMM_R():w:qq MEM0:r:qq @@ -25556,11 +27918,11 @@ OPERANDS : REG0=YMM_R():w:qq MEM0:r:qq -###FILE: ../xed/datafiles/avxhsw/vmfunc-isa.txt +###FILE: ../xed/datafiles/hswbmi/hsw-bmi-vex-isa.xed.txt #BEGIN_LEGAL # -#Copyright (c) 2016 Intel Corporation +#Copyright (c) 2018 Intel Corporation # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -25575,1351 +27937,704 @@ OPERANDS : REG0=YMM_R():w:qq MEM0:r:qq # limitations under the License. # #END_LEGAL -INSTRUCTIONS():: + +AVX_INSTRUCTIONS():: { -ICLASS : VMFUNC +ICLASS : PDEP CPL : 3 -CATEGORY : VTX -EXTENSION : VMFUNC -ISA_SET : VMFUNC -ATTRIBUTES : -PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b100] no_refining_prefix -OPERANDS : -} +CATEGORY : BMI2 +EXTENSION : BMI2 +#32b +PATTERN : VV1 0xF5 V0F38 VF2 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d MEM0:r:d -###FILE: ../xed/datafiles/avxhsw/rtm.xed +PATTERN : VV1 0xF5 V0F38 VF2 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d MEM0:r:d -#BEGIN_LEGAL -# -#Copyright (c) 2016 Intel Corporation -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -#END_LEGAL -INSTRUCTIONS():: +PATTERN : VV1 0xF5 V0F38 VF2 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d -{ -ICLASS : XBEGIN -CPL : 3 -CATEGORY : COND_BR -EXTENSION : RTM -COMMENT : Not always a branch. If aborts, then branches & eax is written +PATTERN : VV1 0xF5 V0F38 VF2 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d -PATTERN : 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[0b000] BRDISPz() -OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP REG1=XED_REG_EAX:cw:SUPP -} +# 64b +PATTERN : VV1 0xF5 V0F38 VF2 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_N():r:q MEM0:r:q -{ -ICLASS : XEND -CPL : 3 -CATEGORY : COND_BR -EXTENSION : RTM -COMMENT : Transaction end. may branch -PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b101] no_refining_prefix -OPERANDS : +PATTERN : VV1 0xF5 V0F38 VF2 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_N():r:q REG2=VGPR64_B():r:q } { -ICLASS : XABORT +ICLASS : PEXT CPL : 3 -CATEGORY : UNCOND_BR -EXTENSION : RTM -COMMENT : Transaction abort. Branches. NOP outside of transaction; Thus eax is rcw. -PATTERN : 0xC6 MOD[0b11] MOD=3 REG[0b111] RM[0b000] UIMM8() -OPERANDS : REG0=XED_REG_EAX:rcw:SUPP IMM0:r:b -} - +CATEGORY : BMI2 +EXTENSION : BMI2 -{ -ICLASS : XTEST -CPL : 3 -CATEGORY : LOGICAL -EXTENSION : RTM -COMMENT : test if in RTM transaction mode -FLAGS : MUST [ of-0 sf-0 zf-mod af-0 pf-0 cf-0 ] -PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b110] no_refining_prefix -OPERANDS : -} +#32b +PATTERN : VV1 0xF5 V0F38 VF3 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d MEM0:r:d -###FILE: ../xed/datafiles/avx/avx-fma-isa.txt +PATTERN : VV1 0xF5 V0F38 VF3 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d MEM0:r:d -#BEGIN_LEGAL -# -#Copyright (c) 2016 Intel Corporation -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -#END_LEGAL -AVX_INSTRUCTIONS():: +PATTERN : VV1 0xF5 V0F38 VF3 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d -# Issues: encoder is at a loss for vmaddps xmm0,xmm0,xmm0,xmm0. -# Encoder must enforce equality between two parameters. Never had to do this before. -# Extra check? -# Decoder must rip off suffixes _DDMR, _DDRM, _DRMD in disassembly (eventually) -############################################################################################# -# Operand orders: -# A = B * C + D -#Type 1) reg0 reg0 mem/reg1 reg2 DDMR 312 or 132 -#Type 2) reg0 reg0 reg1 mem/reg2 DDRM 123 or 213 -#Type 3) reg0 reg1 mem/reg2 reg0 DRMD 321 or 231 +PATTERN : VV1 0xF5 V0F38 VF3 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d -# dst is in MODRM.REG -# regsrc is in VEX.vvvv -# memop is in MODRM.RM -############################################################################################ +# 64b +PATTERN : VV1 0xF5 V0F38 VF3 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_N():r:q MEM0:r:q +PATTERN : VV1 0xF5 V0F38 VF3 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_N():r:q REG2=VGPR64_B():r:q +} +{ +ICLASS : ANDN +CPL : 3 +CATEGORY : BMI1 +EXTENSION : BMI1 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-u cf-0 ] +# 32b +PATTERN : VV1 0xF2 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d MEM0:r:d +PATTERN : VV1 0xF2 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d MEM0:r:d +PATTERN : VV1 0xF2 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d +PATTERN : VV1 0xF2 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d +# 64b +PATTERN : VV1 0xF2 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_N():r:q MEM0:r:q +PATTERN : VV1 0xF2 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_N():r:q REG2=VGPR64_B():r:q +} +{ +ICLASS : BLSR +CPL : 3 +CATEGORY : BMI1 +EXTENSION : BMI1 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-u cf-mod ] +# 32b +PATTERN : VV1 0xF3 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_N():w:d MEM0:r:d -########################################################## - +PATTERN : VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_N():w:d MEM0:r:d +PATTERN : VV1 0xF3 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS : REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d +PATTERN : VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS : REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d +# 64b +PATTERN : VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS : REG0=VGPR64_N():w:q MEM0:r:q +PATTERN : VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS : REG0=VGPR64_N():w:q REG1=VGPR64_B():r:q +} +{ +ICLASS : BLSMSK +CPL : 3 +CATEGORY : BMI1 +EXTENSION : BMI1 +FLAGS : MUST [ of-0 sf-mod zf-0 af-u pf-u cf-mod ] +#32b +PATTERN : VV1 0xF3 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_N():w:d MEM0:r:d +PATTERN : VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_N():w:d MEM0:r:d +PATTERN : VV1 0xF3 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS : REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d +PATTERN : VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS : REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d -################################################################## +#64b +PATTERN : VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : REG0=VGPR64_N():w:q MEM0:r:q +PATTERN : VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS : REG0=VGPR64_N():w:q REG1=VGPR64_B():r:q +} +{ +ICLASS : BLSI +CPL : 3 +CATEGORY : BMI1 +EXTENSION : BMI1 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-u cf-0 ] +# 32b +PATTERN : VV1 0xF3 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_N():w:d MEM0:r:d +PATTERN : VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_N():w:d MEM0:r:d +PATTERN : VV1 0xF3 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS : REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d +PATTERN : VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS : REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d +# 64b +PATTERN : VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : REG0=VGPR64_N():w:q MEM0:r:q +PATTERN : VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS : REG0=VGPR64_N():w:q REG1=VGPR64_B():r:q +} +{ +ICLASS : BZHI +CPL : 3 +CATEGORY : BMI2 +EXTENSION : BMI2 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-u cf-mod ] +# 32b +PATTERN : VV1 0xF5 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d +PATTERN : VV1 0xF5 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d +PATTERN : VV1 0xF5 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d -################################################################## -{ -ICLASS : VFMADD132PD -EXCEPTIONS: avx-type-2 -CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR -# R/M 128 -PATTERN : VV1 0x98 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 -# R/R 128 -PATTERN : VV1 0x98 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 +PATTERN : VV1 0xF5 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d +# 64b +PATTERN : VV1 0xF5 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR64_R():w:q MEM0:r:q REG1=VGPR64_N():r:q -# R/M 256 -PATTERN : VV1 0x98 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 -# R/R 256 -PATTERN : VV1 0x98 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +PATTERN : VV1 0xF5 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_B():r:q REG2=VGPR64_N():r:q } + { -ICLASS : VFMADD132PS -EXCEPTIONS: avx-type-2 +ICLASS : BEXTR CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR -# R/M 128 -PATTERN : VV1 0x98 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 -# R/R 128 -PATTERN : VV1 0x98 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 +CATEGORY : BMI1 +EXTENSION : BMI1 +FLAGS : MUST [ of-u sf-u zf-mod af-u pf-u cf-u ] +# 32b +PATTERN : VV1 0xF7 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d -# R/M 256 -PATTERN : VV1 0x98 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 -# R/R 256 -PATTERN : VV1 0x98 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 -} -{ -ICLASS : VFMADD132SD -EXCEPTIONS: avx-type-3 -CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR simd_scalar -# R/M 128 -PATTERN : VV1 0x99 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 -# R/R 128 -PATTERN : VV1 0x99 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 -} -{ -ICLASS : VFMADD132SS -EXCEPTIONS: avx-type-3 -CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR simd_scalar -# R/M 128 -PATTERN : VV1 0x99 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 -# R/R 128 -PATTERN : VV1 0x99 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 +PATTERN : VV1 0xF7 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d -} +PATTERN : VV1 0xF7 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d -{ -ICLASS : VFMADD213PD -EXCEPTIONS: avx-type-2 -CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR -# R/M 128 -PATTERN : VV1 0xA8 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 -# R/R 128 -PATTERN : VV1 0xA8 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 +PATTERN : VV1 0xF7 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d +# 64b +PATTERN : VV1 0xF7 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR64_R():w:q MEM0:r:q REG1=VGPR64_N():r:q -# R/M 256 -PATTERN : VV1 0xA8 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 -# R/R 256 -PATTERN : VV1 0xA8 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +PATTERN : VV1 0xF7 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_B():r:q REG2=VGPR64_N():r:q } -{ -ICLASS : VFMADD213PS -EXCEPTIONS: avx-type-2 -CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR -# R/M 128 -PATTERN : VV1 0xA8 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 -# R/R 128 -PATTERN : VV1 0xA8 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 -# R/M 256 -PATTERN : VV1 0xA8 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 -# R/R 256 -PATTERN : VV1 0xA8 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 -} -{ -ICLASS : VFMADD213SD -EXCEPTIONS: avx-type-3 -CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR simd_scalar -# R/M 128 -PATTERN : VV1 0xA9 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 -# R/R 128 -PATTERN : VV1 0xA9 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 -} { -ICLASS : VFMADD213SS -EXCEPTIONS: avx-type-3 +ICLASS : SHLX CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR simd_scalar -# R/M 128 -PATTERN : VV1 0xA9 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 -# R/R 128 -PATTERN : VV1 0xA9 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 -} +CATEGORY : BMI2 +EXTENSION : BMI2 -{ -ICLASS : VFMADD231PD -EXCEPTIONS: avx-type-2 -CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR -# R/M 128 -PATTERN : VV1 0xB8 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 -# R/R 128 -PATTERN : VV1 0xB8 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 +# 32b +PATTERN : VV1 0xF7 V0F38 V66 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d +PATTERN : VV1 0xF7 V0F38 V66 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d -# R/M 256 -PATTERN : VV1 0xB8 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 -# R/R 256 -PATTERN : VV1 0xB8 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +PATTERN : VV1 0xF7 V0F38 V66 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d -} -{ -ICLASS : VFMADD231PS -EXCEPTIONS: avx-type-2 -CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR -# R/M 128 -PATTERN : VV1 0xB8 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 -# R/R 128 -PATTERN : VV1 0xB8 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 +PATTERN : VV1 0xF7 V0F38 V66 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d -# R/M 256 -PATTERN : VV1 0xB8 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 -# R/R 256 -PATTERN : VV1 0xB8 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +# 64b +PATTERN : VV1 0xF7 V0F38 V66 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR64_R():w:q MEM0:r:q REG1=VGPR64_N():r:q +PATTERN : VV1 0xF7 V0F38 V66 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_B():r:q REG2=VGPR64_N():r:q } { -ICLASS : VFMADD231SD -EXCEPTIONS: avx-type-3 +ICLASS : SARX CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR simd_scalar -# R/M 128 -PATTERN : VV1 0xB9 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 -# R/R 128 -PATTERN : VV1 0xB9 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 +CATEGORY : BMI2 +EXTENSION : BMI2 -} -{ -ICLASS : VFMADD231SS -EXCEPTIONS: avx-type-3 -CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR simd_scalar -# R/M 128 -PATTERN : VV1 0xB9 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 -# R/R 128 -PATTERN : VV1 0xB9 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 +# 32b +PATTERN : VV1 0xF7 V0F38 VF3 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d -} +PATTERN : VV1 0xF7 V0F38 VF3 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d +PATTERN : VV1 0xF7 V0F38 VF3 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d -################################################### -{ -ICLASS : VFMADDSUB132PD -EXCEPTIONS: avx-type-2 -CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR -# R/M 128 -PATTERN : VV1 0x96 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 -# R/R 128 -PATTERN : VV1 0x96 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 +PATTERN : VV1 0xF7 V0F38 VF3 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d +# 64b +PATTERN : VV1 0xF7 V0F38 VF3 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR64_R():w:q MEM0:r:q REG1=VGPR64_N():r:q -# R/M 256 -PATTERN : VV1 0x96 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 -# R/R 256 -PATTERN : VV1 0x96 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +PATTERN : VV1 0xF7 V0F38 VF3 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_B():r:q REG2=VGPR64_N():r:q } { -ICLASS : VFMADDSUB213PD -EXCEPTIONS: avx-type-2 +ICLASS : SHRX CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR -# R/M 128 -PATTERN : VV1 0xA6 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 -# R/R 128 -PATTERN : VV1 0xA6 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 +CATEGORY : BMI2 +EXTENSION : BMI2 +# 32b +PATTERN : VV1 0xF7 V0F38 VF2 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d -# R/M 256 -PATTERN : VV1 0xA6 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 -# R/R 256 -PATTERN : VV1 0xA6 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 -} -{ -ICLASS : VFMADDSUB231PD -EXCEPTIONS: avx-type-2 -CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR -# R/M 128 -PATTERN : VV1 0xB6 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 -# R/R 128 -PATTERN : VV1 0xB6 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 +PATTERN : VV1 0xF7 V0F38 VF2 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d +PATTERN : VV1 0xF7 V0F38 VF2 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d -# R/M 256 -PATTERN : VV1 0xB6 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 -# R/R 256 -PATTERN : VV1 0xB6 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +PATTERN : VV1 0xF7 V0F38 VF2 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d + +# 64b +PATTERN : VV1 0xF7 V0F38 VF2 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR64_R():w:q MEM0:r:q REG1=VGPR64_N():r:q +PATTERN : VV1 0xF7 V0F38 VF2 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_B():r:q REG2=VGPR64_N():r:q } -{ -ICLASS : VFMADDSUB132PS -EXCEPTIONS: avx-type-2 -CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR -# R/M 128 -PATTERN : VV1 0x96 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 -# R/R 128 -PATTERN : VV1 0x96 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 -# R/M 256 -PATTERN : VV1 0x96 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 -# R/R 256 -PATTERN : VV1 0x96 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 -} { -ICLASS : VFMADDSUB213PS -EXCEPTIONS: avx-type-2 +ICLASS : MULX CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR -# R/M 128 -PATTERN : VV1 0xA6 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 -# R/R 128 -PATTERN : VV1 0xA6 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 +CATEGORY : BMI2 +EXTENSION : BMI2 +# reg:w vvvv:w rm:r rdx:r +# 32b +PATTERN : VV1 0xF6 VF2 V0F38 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():w:d REG2=VGPR32_B():r:d REG3=XED_REG_EDX:r:SUPP -# R/M 256 -PATTERN : VV1 0xA6 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 -# R/R 256 -PATTERN : VV1 0xA6 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 -} -{ -ICLASS : VFMADDSUB231PS -EXCEPTIONS: avx-type-2 -CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR -# R/M 128 -PATTERN : VV1 0xB6 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 -# R/R 128 -PATTERN : VV1 0xB6 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 +PATTERN : VV1 0xF6 VF2 V0F38 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():w:d REG2=VGPR32_B():r:d REG3=XED_REG_EDX:r:SUPP +PATTERN : VV1 0xF6 VF2 V0F38 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():w:d MEM0:r:d REG2=XED_REG_EDX:r:SUPP -# R/M 256 -PATTERN : VV1 0xB6 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 -# R/R 256 -PATTERN : VV1 0xB6 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +PATTERN : VV1 0xF6 VF2 V0F38 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():w:d MEM0:r:d REG2=XED_REG_EDX:r:SUPP +# 64b +PATTERN : VV1 0xF6 VF2 V0F38 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_N():w:q REG2=VGPR64_B():r:q REG3=XED_REG_RDX:r:SUPP +PATTERN : VV1 0xF6 VF2 V0F38 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_N():w:q MEM0:r:q REG2=XED_REG_RDX:r:SUPP } -################################################### { -ICLASS : VFMSUBADD132PD -EXCEPTIONS: avx-type-2 +ICLASS : RORX CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR -# R/M 128 -PATTERN : VV1 0x97 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 -# R/R 128 -PATTERN : VV1 0x97 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 +CATEGORY : BMI2 +EXTENSION : BMI2 +# reg(w) rm(r) / vvvv must be 1111. / 2010-01-08 CART change -# R/M 256 -PATTERN : VV1 0x97 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 -# R/R 256 -PATTERN : VV1 0x97 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 -} -{ -ICLASS : VFMSUBADD213PD -EXCEPTIONS: avx-type-2 -CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR -# R/M 128 -PATTERN : VV1 0xA7 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 -# R/R 128 -PATTERN : VV1 0xA7 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 +# 32b +PATTERN : VV1 0xF0 VF2 V0F3A not64 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d IMM0:r:b + +PATTERN : VV1 0xF0 VF2 V0F3A W0 mode64 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d IMM0:r:b +PATTERN : VV1 0xF0 VF2 V0F3A not64 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d IMM0:r:b +PATTERN : VV1 0xF0 VF2 V0F3A W0 mode64 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d IMM0:r:b -# R/M 256 -PATTERN : VV1 0xA7 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 -# R/R 256 -PATTERN : VV1 0xA7 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +# 64b +PATTERN : VV1 0xF0 VF2 V0F3A W1 VL128 NOVSR mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_B():r:q IMM0:r:b +PATTERN : VV1 0xF0 VF2 V0F3A W1 VL128 NOVSR mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=VGPR64_R():w:q MEM0:r:q IMM0:r:b } -{ -ICLASS : VFMSUBADD231PD -EXCEPTIONS: avx-type-2 -CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR -# R/M 128 -PATTERN : VV1 0xB7 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 -# R/R 128 -PATTERN : VV1 0xB7 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 -# R/M 256 -PATTERN : VV1 0xB7 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 -# R/R 256 -PATTERN : VV1 0xB7 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +###FILE: ../xed/datafiles/hswbmi/tzcnt-isa.xed.txt -} +#BEGIN_LEGAL +# +#Copyright (c) 2018 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: { -ICLASS : VFMSUBADD132PS -EXCEPTIONS: avx-type-2 +ICLASS : TZCNT CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR -# R/M 128 -PATTERN : VV1 0x97 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 -# R/R 128 -PATTERN : VV1 0x97 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 - +CATEGORY : BMI1 +EXTENSION : BMI1 +FLAGS : MUST [ of-u sf-u zf-mod af-u pf-u cf-mod ] +PATTERN : 0x0F 0xBC refining_f3 TZCNT=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():w MEM0:r:v -# R/M 256 -PATTERN : VV1 0x97 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 -# R/R 256 -PATTERN : VV1 0x97 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +PATTERN : 0x0F 0xBC refining_f3 TZCNT=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():w REG1=GPRv_B():r } + { -ICLASS : VFMSUBADD213PS -EXCEPTIONS: avx-type-2 +ICLASS : BSF +VERSION : 1 +COMMENT : AMD reused 0FBC for TZCNT and made BSF not have a refining prefix. This version replaces the normal version of BSF CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR -# R/M 128 -PATTERN : VV1 0xA7 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 -# R/R 128 -PATTERN : VV1 0xA7 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MUST [ of-u sf-u zf-mod af-u pf-u cf-u ] +PATTERN : 0x0F 0xBC not_refining_f3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v -# R/M 256 -PATTERN : VV1 0xA7 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 -# R/R 256 -PATTERN : VV1 0xA7 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 -} -{ -ICLASS : VFMSUBADD231PS -EXCEPTIONS: avx-type-2 -CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR -# R/M 128 -PATTERN : VV1 0xB7 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 -# R/R 128 -PATTERN : VV1 0xB7 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 +PATTERN : 0x0F 0xBC not_refining_f3 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r -# R/M 256 -PATTERN : VV1 0xB7 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 -# R/R 256 -PATTERN : VV1 0xB7 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +PATTERN : 0x0F 0xBC refining_f3 TZCNT=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v +PATTERN : 0x0F 0xBC refining_f3 TZCNT=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r } -################################################### +###FILE: ../xed/datafiles/hsw/vmfunc-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2018 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: { -ICLASS : VFMSUB132PD -EXCEPTIONS: avx-type-2 +ICLASS : VMFUNC CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR -# R/M 128 -PATTERN : VV1 0x9A VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 -# R/R 128 -PATTERN : VV1 0x9A VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 +CATEGORY : VTX +EXTENSION : VMFUNC +ISA_SET : VMFUNC +ATTRIBUTES : +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b100] no_refining_prefix +OPERANDS : REG0=XED_REG_EAX:r:SUPP +} -# R/M 256 -PATTERN : VV1 0x9A VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 -# R/R 256 -PATTERN : VV1 0x9A VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 -} -{ -ICLASS : VFMSUB132PS -EXCEPTIONS: avx-type-2 -CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR -# R/M 128 -PATTERN : VV1 0x9A VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 -# R/R 128 -PATTERN : VV1 0x9A VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 +###FILE: ../xed/datafiles/hsw/invpcid-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2018 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: -# R/M 256 -PATTERN : VV1 0x9A VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 -# R/R 256 -PATTERN : VV1 0x9A VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 -} { -ICLASS : VFMSUB132SD -EXCEPTIONS: avx-type-3 -CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR simd_scalar -# R/M 128 -PATTERN : VV1 0x9B V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 -# R/R 128 -PATTERN : VV1 0x9B V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 +ICLASS : INVPCID +CPL : 0 +CATEGORY : MISC +EXTENSION : INVPCID +ISA_SET : INVPCID +ATTRIBUTES : RING0 NOTSX +PATTERN : 0x0F 0x38 0x82 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode64 MODRM() CR_WIDTH() +OPERANDS : REG0=GPR64_R():r MEM0:r:dq +PATTERN : 0x0F 0x38 0x82 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() not64 MODRM() CR_WIDTH() +OPERANDS : REG0=GPR32_R():r MEM0:r:dq +COMMENT : } -{ -ICLASS : VFMSUB132SS -EXCEPTIONS: avx-type-3 -CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR simd_scalar -# R/M 128 -PATTERN : VV1 0x9B V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 -# R/R 128 -PATTERN : VV1 0x9B V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 -} + +###FILE: ../xed/datafiles/hsw/lzcnt-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2018 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: + +# LZCNT reg16, reg/mem16 F30FBD /r +# LZCNT reg32, reg/mem32 F30FBD /r +# LZCNT reg64, reg/mem64 F30FBD /r { -ICLASS : VFMSUB213PD -EXCEPTIONS: avx-type-2 +ICLASS : LZCNT +# This replace the AMD version in LZCNT builds +VERSION : 2 CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR -# R/M 128 -PATTERN : VV1 0xAA VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 -# R/R 128 -PATTERN : VV1 0xAA VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 +CATEGORY : LZCNT +EXTENSION : LZCNT +COMMENT: : These next one WAS introduced first by AMD circa SSE4a. +FLAGS : MUST [ cf-mod zf-mod of-u af-u pf-u sf-u ] +PATTERN : 0x0F 0xBD f3_refining_prefix LZCNT=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():w:v MEM0:r:v +PATTERN : 0x0F 0xBD f3_refining_prefix LZCNT=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():w:v REG1=GPRv_B():r:v +} -# R/M 256 -PATTERN : VV1 0xAA VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 -# R/R 256 -PATTERN : VV1 0xAA VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 -} { -ICLASS : VFMSUB213PS -EXCEPTIONS: avx-type-2 +ICLASS : BSR +VERSION : 2 +COMMENT : AMD reused 0FBD for LZCNT and made BSR not have a refining prefix. This version replaces the normal version of BSR CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR -# R/M 128 -PATTERN : VV1 0xAA VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 -# R/R 128 -PATTERN : VV1 0xAA VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MUST [ of-u sf-u zf-mod af-u pf-u cf-u ] +PATTERN : 0x0F 0xBD not_refining_f3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v +PATTERN : 0x0F 0xBD not_refining_f3 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r -# R/M 256 -PATTERN : VV1 0xAA VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 -# R/R 256 -PATTERN : VV1 0xAA VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +PATTERN : 0x0F 0xBD refining_f3 LZCNT=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v + +PATTERN : 0x0F 0xBD refining_f3 LZCNT=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r } + + +###FILE: ../xed/datafiles/hsw/rtm-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2018 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: + { -ICLASS : VFMSUB213SD -EXCEPTIONS: avx-type-3 +ICLASS : XBEGIN CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR simd_scalar -# R/M 128 -PATTERN : VV1 0xAB V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 -# R/R 128 -PATTERN : VV1 0xAB V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 +CATEGORY : COND_BR +EXTENSION : RTM +COMMENT : Not always a branch. If aborts, then branches & eax is written +PATTERN : 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[0b000] BRDISPz() +OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP REG1=XED_REG_EAX:cw:SUPP } + { -ICLASS : VFMSUB213SS -EXCEPTIONS: avx-type-3 +ICLASS : XEND CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR simd_scalar -# R/M 128 -PATTERN : VV1 0xAB V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 -# R/R 128 -PATTERN : VV1 0xAB V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 +CATEGORY : COND_BR +EXTENSION : RTM +COMMENT : Transaction end. may branch +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b101] no_refining_prefix +OPERANDS : } { -ICLASS : VFMSUB231PD -EXCEPTIONS: avx-type-2 +ICLASS : XABORT CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR -# R/M 128 -PATTERN : VV1 0xBA VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 -# R/R 128 -PATTERN : VV1 0xBA VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 - +CATEGORY : UNCOND_BR +EXTENSION : RTM +COMMENT : Transaction abort. Branches. NOP outside of transaction; Thus eax is rcw. +PATTERN : 0xC6 MOD[0b11] MOD=3 REG[0b111] RM[0b000] UIMM8() +OPERANDS : REG0=XED_REG_EAX:rcw:SUPP IMM0:r:b +} -# R/M 256 -PATTERN : VV1 0xBA VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 -# R/R 256 -PATTERN : VV1 0xBA VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 -} { -ICLASS : VFMSUB231PS -EXCEPTIONS: avx-type-2 +ICLASS : XTEST CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR -# R/M 128 -PATTERN : VV1 0xBA VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 -# R/R 128 -PATTERN : VV1 0xBA VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 +CATEGORY : LOGICAL +EXTENSION : RTM +COMMENT : test if in RTM transaction mode +FLAGS : MUST [ of-0 sf-0 zf-mod af-0 pf-0 cf-0 ] +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b110] no_refining_prefix +OPERANDS : +} -# R/M 256 -PATTERN : VV1 0xBA VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 -# R/R 256 -PATTERN : VV1 0xBA VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 -} -{ -ICLASS : VFMSUB231SD -EXCEPTIONS: avx-type-3 -CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR simd_scalar -# R/M 128 -PATTERN : VV1 0xBB V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 -# R/R 128 -PATTERN : VV1 0xBB V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 +###FILE: ../xed/datafiles/bdw/adox-adcx-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2018 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: -} { -ICLASS : VFMSUB231SS -EXCEPTIONS: avx-type-3 +ICLASS : ADCX CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR simd_scalar -# R/M 128 -PATTERN : VV1 0xBB V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 -# R/R 128 -PATTERN : VV1 0xBB V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 +CATEGORY : ADOX_ADCX +EXTENSION : ADOX_ADCX +ISA_SET : ADOX_ADCX + +FLAGS : MUST [ cf-tst cf-mod ] + +# reg:rw rm:r +# 32b +PATTERN : 0x0F 0x38 0xF6 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix W0 IMMUNE66() +OPERANDS : REG0=GPR32_R():rw:d REG1=GPR32_B():r:d +PATTERN : 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix W0 IMMUNE66() +OPERANDS : REG0=GPR32_R():rw:d MEM0:r:d +# 64b +PATTERN : 0x0F 0x38 0xF6 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix W1 IMMUNE66() +OPERANDS : REG0=GPR64_R():rw:q REG1=GPR64_B():r:q +PATTERN : 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix W1 IMMUNE66() +OPERANDS : REG0=GPR64_R():rw:q MEM0:r:q } -################################################### { -ICLASS : VFNMADD132PD -EXCEPTIONS: avx-type-2 +ICLASS : ADOX CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR -# R/M 128 -PATTERN : VV1 0x9C VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 -# R/R 128 -PATTERN : VV1 0x9C VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 +CATEGORY : ADOX_ADCX +EXTENSION : ADOX_ADCX +ISA_SET : ADOX_ADCX +FLAGS : MUST [ of-tst of-mod ] -# R/M 256 -PATTERN : VV1 0x9C VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 -# R/R 256 -PATTERN : VV1 0x9C VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 -} -{ -ICLASS : VFNMADD132PS -EXCEPTIONS: avx-type-2 -CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR -# R/M 128 -PATTERN : VV1 0x9C VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 -# R/R 128 -PATTERN : VV1 0x9C VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 - - -# R/M 256 -PATTERN : VV1 0x9C VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 -# R/R 256 -PATTERN : VV1 0x9C VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 -} -{ -ICLASS : VFNMADD132SD -EXCEPTIONS: avx-type-3 -CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR simd_scalar -# R/M 128 -PATTERN : VV1 0x9D V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 -# R/R 128 -PATTERN : VV1 0x9D V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 -} -{ -ICLASS : VFNMADD132SS -EXCEPTIONS: avx-type-3 -CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR simd_scalar -# R/M 128 -PATTERN : VV1 0x9D V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 -# R/R 128 -PATTERN : VV1 0x9D V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 - -} - -{ -ICLASS : VFNMADD213PD -EXCEPTIONS: avx-type-2 -CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR -# R/M 128 -PATTERN : VV1 0xAC VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 -# R/R 128 -PATTERN : VV1 0xAC VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 - - -# R/M 256 -PATTERN : VV1 0xAC VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 -# R/R 256 -PATTERN : VV1 0xAC VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 -} -{ -ICLASS : VFNMADD213PS -EXCEPTIONS: avx-type-2 -CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR -# R/M 128 -PATTERN : VV1 0xAC VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 -# R/R 128 -PATTERN : VV1 0xAC VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 - - -# R/M 256 -PATTERN : VV1 0xAC VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 -# R/R 256 -PATTERN : VV1 0xAC VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 -} -{ -ICLASS : VFNMADD213SD -EXCEPTIONS: avx-type-3 -CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR simd_scalar -# R/M 128 -PATTERN : VV1 0xAD V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 -# R/R 128 -PATTERN : VV1 0xAD V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 - -} -{ -ICLASS : VFNMADD213SS -EXCEPTIONS: avx-type-3 -CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR simd_scalar -# R/M 128 -PATTERN : VV1 0xAD V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 -# R/R 128 -PATTERN : VV1 0xAD V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 -} - -{ -ICLASS : VFNMADD231PD -EXCEPTIONS: avx-type-2 -CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR -# R/M 128 -PATTERN : VV1 0xBC VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 -# R/R 128 -PATTERN : VV1 0xBC VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 - - -# R/M 256 -PATTERN : VV1 0xBC VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 -# R/R 256 -PATTERN : VV1 0xBC VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 - -} -{ -ICLASS : VFNMADD231PS -EXCEPTIONS: avx-type-2 -CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR -# R/M 128 -PATTERN : VV1 0xBC VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 -# R/R 128 -PATTERN : VV1 0xBC VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 - -# R/M 256 -PATTERN : VV1 0xBC VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 -# R/R 256 -PATTERN : VV1 0xBC VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 - -} -{ -ICLASS : VFNMADD231SD -EXCEPTIONS: avx-type-3 -CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR simd_scalar -# R/M 128 -PATTERN : VV1 0xBD V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 -# R/R 128 -PATTERN : VV1 0xBD V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 - -} -{ -ICLASS : VFNMADD231SS -EXCEPTIONS: avx-type-3 -CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR simd_scalar -# R/M 128 -PATTERN : VV1 0xBD V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 -# R/R 128 -PATTERN : VV1 0xBD V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 - -} - -################################################### - - -{ -ICLASS : VFNMSUB132PD -EXCEPTIONS: avx-type-2 -CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR -# R/M 128 -PATTERN : VV1 0x9E VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 -# R/R 128 -PATTERN : VV1 0x9E VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 - - -# R/M 256 -PATTERN : VV1 0x9E VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 -# R/R 256 -PATTERN : VV1 0x9E VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 -} -{ -ICLASS : VFNMSUB132PS -EXCEPTIONS: avx-type-2 -CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR -# R/M 128 -PATTERN : VV1 0x9E VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 -# R/R 128 -PATTERN : VV1 0x9E VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 - - -# R/M 256 -PATTERN : VV1 0x9E VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 -# R/R 256 -PATTERN : VV1 0x9E VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 -} -{ -ICLASS : VFNMSUB132SD -EXCEPTIONS: avx-type-3 -CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR simd_scalar -# R/M 128 -PATTERN : VV1 0x9F V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 -# R/R 128 -PATTERN : VV1 0x9F V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 -} -{ -ICLASS : VFNMSUB132SS -EXCEPTIONS: avx-type-3 -CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR simd_scalar -# R/M 128 -PATTERN : VV1 0x9F V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 -# R/R 128 -PATTERN : VV1 0x9F V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 - -} - -{ -ICLASS : VFNMSUB213PD -EXCEPTIONS: avx-type-2 -CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR -# R/M 128 -PATTERN : VV1 0xAE VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 -# R/R 128 -PATTERN : VV1 0xAE VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 - - -# R/M 256 -PATTERN : VV1 0xAE VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 -# R/R 256 -PATTERN : VV1 0xAE VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 -} -{ -ICLASS : VFNMSUB213PS -EXCEPTIONS: avx-type-2 -CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR -# R/M 128 -PATTERN : VV1 0xAE VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 -# R/R 128 -PATTERN : VV1 0xAE VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 - - -# R/M 256 -PATTERN : VV1 0xAE VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 -# R/R 256 -PATTERN : VV1 0xAE VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 -} -{ -ICLASS : VFNMSUB213SD -EXCEPTIONS: avx-type-3 -CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR simd_scalar -# R/M 128 -PATTERN : VV1 0xAF V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 -# R/R 128 -PATTERN : VV1 0xAF V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 - -} -{ -ICLASS : VFNMSUB213SS -EXCEPTIONS: avx-type-3 -CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR simd_scalar -# R/M 128 -PATTERN : VV1 0xAF V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 -# R/R 128 -PATTERN : VV1 0xAF V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 -} - -{ -ICLASS : VFNMSUB231PD -EXCEPTIONS: avx-type-2 -CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR -# R/M 128 -PATTERN : VV1 0xBE VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 -# R/R 128 -PATTERN : VV1 0xBE VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 - - -# R/M 256 -PATTERN : VV1 0xBE VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 -# R/R 256 -PATTERN : VV1 0xBE VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 - -} -{ -ICLASS : VFNMSUB231PS -EXCEPTIONS: avx-type-2 -CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR -# R/M 128 -PATTERN : VV1 0xBE VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 -# R/R 128 -PATTERN : VV1 0xBE VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 - -# R/M 256 -PATTERN : VV1 0xBE VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 -# R/R 256 -PATTERN : VV1 0xBE VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 - -} -{ -ICLASS : VFNMSUB231SD -EXCEPTIONS: avx-type-3 -CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR simd_scalar -# R/M 128 -PATTERN : VV1 0xBF V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 -# R/R 128 -PATTERN : VV1 0xBF V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 - -} -{ -ICLASS : VFNMSUB231SS -EXCEPTIONS: avx-type-3 -CPL : 3 -CATEGORY : VFMA -EXTENSION : FMA -ATTRIBUTES: MXCSR simd_scalar -# R/M 128 -PATTERN : VV1 0xBF V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 -# R/R 128 -PATTERN : VV1 0xBF V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] -OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 +# reg:rw rm:r +# 32b +PATTERN : 0x0F 0x38 0xF6 MOD[0b11] MOD=3 REG[rrr] RM[nnn] refining_f3 W0 IMMUNE66() +OPERANDS : REG0=GPR32_R():rw:d REG1=GPR32_B():r:d +PATTERN : 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() refining_f3 W0 IMMUNE66() +OPERANDS : REG0=GPR32_R():rw:d MEM0:r:d +# 64b +PATTERN : 0x0F 0x38 0xF6 MOD[0b11] MOD=3 REG[rrr] RM[nnn] refining_f3 W1 IMMUNE66() +OPERANDS : REG0=GPR64_R():rw:q REG1=GPR64_B():r:q +PATTERN : 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() refining_f3 W1 IMMUNE66() +OPERANDS : REG0=GPR64_R():rw:q MEM0:r:q } -################################################### - - - - -###FILE: ../xed/datafiles/bdw/lin2.xed.txt +###FILE: ../xed/datafiles/pku/pku-isa.xed.txt #BEGIN_LEGAL # -#Copyright (c) 2016 Intel Corporation +#Copyright (c) 2018 Intel Corporation # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -26934,57 +28649,40 @@ OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 # limitations under the License. # #END_LEGAL + + INSTRUCTIONS():: { -ICLASS : ADCX -CPL : 3 -CATEGORY : BDW -EXTENSION : BDW -FLAGS : MUST [ cf-tst cf-mod ] -# reg:rw rm:r -# 32b -PATTERN : 0x0F 0x38 0xF6 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix W0 IMMUNE66() -OPERANDS : REG0=GPR32_R():rw:d REG1=GPR32_B():r:d -PATTERN : 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix W0 IMMUNE66() -OPERANDS : REG0=GPR32_R():rw:d MEM0:r:d - -# 64b -PATTERN : 0x0F 0x38 0xF6 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix W1 IMMUNE66() -OPERANDS : REG0=GPR64_R():rw:q REG1=GPR64_B():r:q -PATTERN : 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix W1 IMMUNE66() -OPERANDS : REG0=GPR64_R():rw:q MEM0:r:q +ICLASS: RDPKRU +CPL: 3 +CATEGORY: PKU +EXTENSION: PKU +ISA_SET: PKU +ATTRIBUTES: +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b110] no_refining_prefix +OPERANDS: REG0=XED_REG_EDX:w:SUPP REG1=XED_REG_EAX:w:SUPP REG2=XED_REG_ECX:r:SUPP } - { -ICLASS : ADOX -CPL : 3 -CATEGORY : BDW -EXTENSION : BDW -FLAGS : MUST [ of-tst of-mod ] -# reg:rw rm:r -# 32b -PATTERN : 0x0F 0x38 0xF6 MOD[0b11] MOD=3 REG[rrr] RM[nnn] refining_f3 W0 IMMUNE66() -OPERANDS : REG0=GPR32_R():rw:d REG1=GPR32_B():r:d -PATTERN : 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() refining_f3 W0 IMMUNE66() -OPERANDS : REG0=GPR32_R():rw:d MEM0:r:d - -# 64b -PATTERN : 0x0F 0x38 0xF6 MOD[0b11] MOD=3 REG[rrr] RM[nnn] refining_f3 W1 IMMUNE66() -OPERANDS : REG0=GPR64_R():rw:q REG1=GPR64_B():r:q -PATTERN : 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() refining_f3 W1 IMMUNE66() -OPERANDS : REG0=GPR64_R():rw:q MEM0:r:q +ICLASS: WRPKRU +CPL: 3 +CATEGORY: PKU +EXTENSION: PKU +ISA_SET: PKU +ATTRIBUTES: +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b111] no_refining_prefix +OPERANDS: REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_ECX:r:SUPP } -###FILE: ../xed/datafiles/bdw/rdseed.xed.txt +###FILE: ../xed/datafiles/clwb/clwb.xed.txt #BEGIN_LEGAL # -#Copyright (c) 2016 Intel Corporation +#Copyright (c) 2018 Intel Corporation # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -26999,26 +28697,28 @@ OPERANDS : REG0=GPR64_R():rw:q MEM0:r:q # limitations under the License. # #END_LEGAL + INSTRUCTIONS():: { -ICLASS : RDSEED -CPL : 3 -CATEGORY : RDSEED -EXTENSION : RDSEED -ISA_SET : RDSEED -FLAGS : MUST [ cf-mod zf-0 of-0 af-0 pf-0 sf-0 ] -PATTERN : 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] not_refining -OPERANDS : REG0=GPRv_B():w +ICLASS: CLWB +CPL: 3 +CATEGORY: CLWB +EXTENSION: CLWB +ISA_SET: CLWB +ATTRIBUTES: PREFETCH # check TSX-friendlyness +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] osz_refining_prefix REFINING66() MODRM() +OPERANDS : MEM0:r:mprefetch } -###FILE: ../xed/datafiles/bdw/smap.xed.txt + +###FILE: ../xed/datafiles/vnni/vnni-isa.xed.txt #BEGIN_LEGAL # -#Copyright (c) 2016 Intel Corporation +#Copyright (c) 2018 Intel Corporation # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -27033,256 +28733,383 @@ OPERANDS : REG0=GPRv_B():w # limitations under the License. # #END_LEGAL - -INSTRUCTIONS():: - -{ -ICLASS : CLAC -CPL : 0 -CATEGORY : SMAP -EXTENSION : SMAP -FLAGS : MUST [ ac-0 ] -# 0F 01 CA = 1100_1010 = 11_001_010 -PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b010] no_refining_prefix -OPERANDS : -} - -{ -ICLASS : STAC -CPL : 0 -CATEGORY : SMAP -EXTENSION : SMAP -FLAGS : MUST [ ac-1 ] -# 0F 01 CB = 1100_1011 = 11_001_011 -PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b011] no_refining_prefix -OPERANDS : -} - - - -###FILE: ../xed/datafiles/sgx/sgx-isa.xed.txt - -#BEGIN_LEGAL # -#Copyright (c) 2016 Intel Corporation # -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at # -# http://www.apache.org/licenses/LICENSE-2.0 +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** # -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. # -#END_LEGAL +# +EVEX_INSTRUCTIONS():: +# EMITTING VPDPBUSD (VPDPBUSD-128-1) +{ +ICLASS: VPDPBUSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x50 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u32 +IFORM: VPDPBUSD_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512 +} -INSTRUCTIONS():: +{ +ICLASS: VPDPBUSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x50 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPDPBUSD_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512 +} -# Both read EAX -# Both may read or write or r/w RBX, RCX, RDX -# ENCLU 0f 01 D7 -# D7 = 1101 0111 -# ENCLS 0f 01 CF -# CF = 1100_1111 +# EMITTING VPDPBUSD (VPDPBUSD-256-1) +{ +ICLASS: VPDPBUSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x50 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u32 +IFORM: VPDPBUSD_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512 +} +{ +ICLASS: VPDPBUSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x50 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPDPBUSD_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512 +} +# EMITTING VPDPBUSD (VPDPBUSD-512-1) { -ICLASS: ENCLU -CPL: 3 -CATEGORY: SGX -EXTENSION: SGX -ISA_SET: SGX -COMMENT: May set flags -PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b111] no_refining_prefix -OPERANDS: REG0=XED_REG_EAX:r:SUPP \ - REG1=XED_REG_RBX:crw:SUPP \ - REG2=XED_REG_RCX:crw:SUPP \ - REG3=XED_REG_RDX:crw:SUPP +ICLASS: VPDPBUSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x50 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu32 +IFORM: VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512 } { - -ICLASS: ENCLS -CPL: 0 -CATEGORY: SGX -EXTENSION: SGX -ISA_SET: SGX -COMMENT: May set flags -PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b111] no_refining_prefix -OPERANDS: REG0=XED_REG_EAX:r:SUPP \ - REG1=XED_REG_RBX:crw:SUPP \ - REG2=XED_REG_RCX:crw:SUPP \ - REG3=XED_REG_RDX:crw:SUPP - +ICLASS: VPDPBUSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x50 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512 } -###FILE: ../xed/datafiles/pku/pku-isa.xed.txt +# EMITTING VPDPBUSDS (VPDPBUSDS-128-1) +{ +ICLASS: VPDPBUSDS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x51 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u32 +IFORM: VPDPBUSDS_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512 +} -#BEGIN_LEGAL -# -#Copyright (c) 2016 Intel Corporation -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -#END_LEGAL +{ +ICLASS: VPDPBUSDS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x51 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPDPBUSDS_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512 +} -INSTRUCTIONS():: +# EMITTING VPDPBUSDS (VPDPBUSDS-256-1) +{ +ICLASS: VPDPBUSDS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x51 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u32 +IFORM: VPDPBUSDS_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512 +} { -ICLASS: RDPKRU +ICLASS: VPDPBUSDS CPL: 3 -CATEGORY: PKU -EXTENSION: PKU -ISA_SET: PKU -ATTRIBUTES: -PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b110] -OPERANDS: REG0=XED_REG_EDX:w:SUPP REG1=XED_REG_EAX:w:SUPP REG2=XED_REG_ECX:r:SUPP +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x51 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPDPBUSDS_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512 } +# EMITTING VPDPBUSDS (VPDPBUSDS-512-1) { -ICLASS: WRPKRU +ICLASS: VPDPBUSDS CPL: 3 -CATEGORY: PKU -EXTENSION: PKU -ISA_SET: PKU -ATTRIBUTES: -PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b111] -OPERANDS: REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_ECX:r:SUPP +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x51 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu32 +IFORM: VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512 } +{ +ICLASS: VPDPBUSDS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x51 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512 +} -###FILE: ../xed/datafiles/memory/clwb.xed.txt +# EMITTING VPDPWSSD (VPDPWSSD-128-1) +{ +ICLASS: VPDPWSSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x52 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:u32 +IFORM: VPDPWSSD_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512 +} -#BEGIN_LEGAL -# -#Copyright (c) 2016 Intel Corporation -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -#END_LEGAL +{ +ICLASS: VPDPWSSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x52 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPDPWSSD_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512 +} -INSTRUCTIONS():: +# EMITTING VPDPWSSD (VPDPWSSD-256-1) { -ICLASS: CLWB -CPL: 3 -CATEGORY: CLWB -EXTENSION: CLWB -ISA_SET: CLWB -ATTRIBUTES: PREFETCH # check TSX-friendlyness -PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] osz_refining_prefix REFINING66() MODRM() -OPERANDS : MEM0:r:mprefetch +ICLASS: VPDPWSSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x52 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:u32 +IFORM: VPDPWSSD_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512 } +{ +ICLASS: VPDPWSSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x52 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPDPWSSD_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512 +} +# EMITTING VPDPWSSD (VPDPWSSD-512-1) +{ +ICLASS: VPDPWSSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x52 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zu32 +IFORM: VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512 +} -###FILE: ../xed/datafiles/memory/clflushopt.xed.txt - -#BEGIN_LEGAL -# -#Copyright (c) 2016 Intel Corporation -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -#END_LEGAL +{ +ICLASS: VPDPWSSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x52 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 +} -INSTRUCTIONS():: +# EMITTING VPDPWSSDS (VPDPWSSDS-128-1) { -ICLASS: CLFLUSHOPT -CPL: 3 -CATEGORY: CLFLUSHOPT -EXTENSION: CLFLUSHOPT -ISA_SET: CLFLUSHOPT -ATTRIBUTES: PREFETCH # check TSX-friendlyness -PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b111] RM[nnn] osz_refining_prefix REFINING66() MODRM() -OPERANDS : MEM0:r:mprefetch +ICLASS: VPDPWSSDS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x53 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:u32 +IFORM: VPDPWSSDS_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512 } +{ +ICLASS: VPDPWSSDS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x53 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPDPWSSDS_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512 +} +# EMITTING VPDPWSSDS (VPDPWSSDS-256-1) +{ +ICLASS: VPDPWSSDS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x53 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:u32 +IFORM: VPDPWSSDS_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512 +} -###FILE: ../xed/datafiles/pt/intelpt-isa.xed.txt - -#BEGIN_LEGAL -# -#Copyright (c) 2016 Intel Corporation -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -#END_LEGAL +{ +ICLASS: VPDPWSSDS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x53 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPDPWSSDS_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512 +} -INSTRUCTIONS():: +# EMITTING VPDPWSSDS (VPDPWSSDS-512-1) { -ICLASS : PTWRITE -CPL : 3 -CATEGORY : PT -EXTENSION : PT -PATTERN : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix no66_prefix -OPERANDS : REG0=GPRy_B():r -PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b100] RM[nnn] f3_refining_prefix no66_prefix MODRM() -OPERANDS : MEM0:r:y +ICLASS: VPDPWSSDS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x53 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zu32 +IFORM: VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512 +} +{ +ICLASS: VPDPWSSDS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x53 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 } + + ###FILE: ../xed/datafiles/knl/knl-fixup.txt #BEGIN_LEGAL # -#Copyright (c) 2016 Intel Corporation +#Copyright (c) 2018 Intel Corporation # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -27306,7 +29133,7 @@ UDELETE : PREFETCH_RESERVED_0F0Dr2 #BEGIN_LEGAL # -#Copyright (c) 2016 Intel Corporation +#Copyright (c) 2018 Intel Corporation # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -27340,8960 +29167,11618 @@ EXTENSION: AVX512EVEX ISA_SET: AVX512ER_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xC8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 -IFORM: VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xC8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER +} + +{ +ICLASS: VEXP2PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xC8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER +} + +{ +ICLASS: VEXP2PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VEXP2PD_ZMMf64_MASKmskw_MEMf64_AVX512ER +} + + +# EMITTING VEXP2PS (VEXP2PS-512-1) +{ +ICLASS: VEXP2PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xC8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER +} + +{ +ICLASS: VEXP2PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xC8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER +} + +{ +ICLASS: VEXP2PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VEXP2PS_ZMMf32_MASKmskw_MEMf32_AVX512ER +} + + +# EMITTING VGATHERPF0DPD (VGATHERPF0DPD-512-1) +{ +ICLASS: VGATHERPF0DPD +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b001] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:b:f64 REG0=MASKNOT0():rw:mskw +IFORM: VGATHERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VGATHERPF0DPS (VGATHERPF0DPS-512-1) +{ +ICLASS: VGATHERPF0DPS +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b001] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:b:f32 REG0=MASKNOT0():rw:mskw +IFORM: VGATHERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VGATHERPF0QPD (VGATHERPF0QPD-512-1) +{ +ICLASS: VGATHERPF0QPD +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b001] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:b:f64 REG0=MASKNOT0():rw:mskw +IFORM: VGATHERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VGATHERPF0QPS (VGATHERPF0QPS-512-1) +{ +ICLASS: VGATHERPF0QPS +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b001] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:b:f32 REG0=MASKNOT0():rw:mskw +IFORM: VGATHERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VGATHERPF1DPD (VGATHERPF1DPD-512-1) +{ +ICLASS: VGATHERPF1DPD +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:b:f64 REG0=MASKNOT0():rw:mskw +IFORM: VGATHERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VGATHERPF1DPS (VGATHERPF1DPS-512-1) +{ +ICLASS: VGATHERPF1DPS +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:b:f32 REG0=MASKNOT0():rw:mskw +IFORM: VGATHERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VGATHERPF1QPD (VGATHERPF1QPD-512-1) +{ +ICLASS: VGATHERPF1QPD +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:b:f64 REG0=MASKNOT0():rw:mskw +IFORM: VGATHERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VGATHERPF1QPS (VGATHERPF1QPS-512-1) +{ +ICLASS: VGATHERPF1QPS +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:b:f32 REG0=MASKNOT0():rw:mskw +IFORM: VGATHERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VRCP28PD (VRCP28PD-512-1) +{ +ICLASS: VRCP28PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xCA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER +} + +{ +ICLASS: VRCP28PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xCA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER +} + +{ +ICLASS: VRCP28PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xCA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VRCP28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER +} + + +# EMITTING VRCP28PS (VRCP28PS-512-1) +{ +ICLASS: VRCP28PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xCA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER +} + +{ +ICLASS: VRCP28PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xCA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER +} + +{ +ICLASS: VRCP28PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xCA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VRCP28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER +} + + +# EMITTING VRCP28SD (VRCP28SD-128-1) +{ +ICLASS: VRCP28SD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xCB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER +} + +{ +ICLASS: VRCP28SD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xCB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER +} + +{ +ICLASS: VRCP28SD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0xCB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VRCP28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER +} + + +# EMITTING VRCP28SS (VRCP28SS-128-1) +{ +ICLASS: VRCP28SS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xCB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER +} + +{ +ICLASS: VRCP28SS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xCB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER +} + +{ +ICLASS: VRCP28SS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0xCB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VRCP28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER +} + + +# EMITTING VRSQRT28PD (VRSQRT28PD-512-1) +{ +ICLASS: VRSQRT28PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xCC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER +} + +{ +ICLASS: VRSQRT28PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xCC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER +} + +{ +ICLASS: VRSQRT28PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xCC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VRSQRT28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER +} + + +# EMITTING VRSQRT28PS (VRSQRT28PS-512-1) +{ +ICLASS: VRSQRT28PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xCC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER +} + +{ +ICLASS: VRSQRT28PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xCC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER +} + +{ +ICLASS: VRSQRT28PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xCC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VRSQRT28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER +} + + +# EMITTING VRSQRT28SD (VRSQRT28SD-128-1) +{ +ICLASS: VRSQRT28SD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xCD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER +} + +{ +ICLASS: VRSQRT28SD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xCD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER +} + +{ +ICLASS: VRSQRT28SD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0xCD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VRSQRT28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER +} + + +# EMITTING VRSQRT28SS (VRSQRT28SS-128-1) +{ +ICLASS: VRSQRT28SS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xCD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER +} + +{ +ICLASS: VRSQRT28SS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xCD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER +} + +{ +ICLASS: VRSQRT28SS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0xCD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VRSQRT28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER +} + + +# EMITTING VSCATTERPF0DPD (VSCATTERPF0DPD-512-1) +{ +ICLASS: VSCATTERPF0DPD +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b101] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:b:f64 REG0=MASKNOT0():rw:mskw +IFORM: VSCATTERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VSCATTERPF0DPS (VSCATTERPF0DPS-512-1) +{ +ICLASS: VSCATTERPF0DPS +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b101] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:b:f32 REG0=MASKNOT0():rw:mskw +IFORM: VSCATTERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VSCATTERPF0QPD (VSCATTERPF0QPD-512-1) +{ +ICLASS: VSCATTERPF0QPD +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b101] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:b:f64 REG0=MASKNOT0():rw:mskw +IFORM: VSCATTERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VSCATTERPF0QPS (VSCATTERPF0QPS-512-1) +{ +ICLASS: VSCATTERPF0QPS +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b101] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:b:f32 REG0=MASKNOT0():rw:mskw +IFORM: VSCATTERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VSCATTERPF1DPD (VSCATTERPF1DPD-512-1) +{ +ICLASS: VSCATTERPF1DPD +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:b:f64 REG0=MASKNOT0():rw:mskw +IFORM: VSCATTERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VSCATTERPF1DPS (VSCATTERPF1DPS-512-1) +{ +ICLASS: VSCATTERPF1DPS +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:b:f32 REG0=MASKNOT0():rw:mskw +IFORM: VSCATTERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VSCATTERPF1QPD (VSCATTERPF1QPD-512-1) +{ +ICLASS: VSCATTERPF1QPD +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:b:f64 REG0=MASKNOT0():rw:mskw +IFORM: VSCATTERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VSCATTERPF1QPS (VSCATTERPF1QPS-512-1) +{ +ICLASS: VSCATTERPF1QPS +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:b:f32 REG0=MASKNOT0():rw:mskw +IFORM: VSCATTERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512 +} + + +INSTRUCTIONS():: +# EMITTING PREFETCHWT1 (PREFETCHWT1-N/A-1) +{ +ICLASS: PREFETCHWT1 +CPL: 3 +CATEGORY: PREFETCHWT1 +EXTENSION: PREFETCHWT1 +ISA_SET: PREFETCHWT1 +REAL_OPCODE: Y +ATTRIBUTES: PREFETCH +PATTERN: 0x0F 0x0D MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS: MEM0:r:b:u8 +IFORM: PREFETCHWT1_MEMu8 +} + + + + +###FILE: ../xed/datafiles/4fmaps-512/4fmaps-512-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2018 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING V4FMADDPS (V4FMADDPS-512-1) +{ +ICLASS: V4FMADDPS +CPL: 3 +CATEGORY: AVX512_4FMAPS +EXTENSION: AVX512EVEX +ISA_SET: AVX512_4FMAPS_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MULTISOURCE4 DISP8_TUPLE1_4X MXCSR MASKOP_EVEX +PATTERN: EVV 0x9A VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_TUPLE1_4X() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32:MULTISOURCE4 MEM0:r:dq:f32 +IFORM: V4FMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING V4FMADDSS (V4FMADDSS-128-1) +{ +ICLASS: V4FMADDSS +CPL: 3 +CATEGORY: AVX512_4FMAPS +EXTENSION: AVX512EVEX +ISA_SET: AVX512_4FMAPS_SCALAR +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_TUPLE1_4X MXCSR MULTISOURCE4 MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SIMD_SCALAR +PATTERN: EVV 0x9B VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_TUPLE1_4X() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32:MULTISOURCE4 MEM0:r:dq:f32 +IFORM: V4FMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING V4FNMADDPS (V4FNMADDPS-512-1) +{ +ICLASS: V4FNMADDPS +CPL: 3 +CATEGORY: AVX512_4FMAPS +EXTENSION: AVX512EVEX +ISA_SET: AVX512_4FMAPS_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MULTISOURCE4 DISP8_TUPLE1_4X MXCSR MASKOP_EVEX +PATTERN: EVV 0xAA VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_TUPLE1_4X() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32:MULTISOURCE4 MEM0:r:dq:f32 +IFORM: V4FNMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING V4FNMADDSS (V4FNMADDSS-128-1) +{ +ICLASS: V4FNMADDSS +CPL: 3 +CATEGORY: AVX512_4FMAPS +EXTENSION: AVX512EVEX +ISA_SET: AVX512_4FMAPS_SCALAR +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_TUPLE1_4X MXCSR MULTISOURCE4 MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SIMD_SCALAR +PATTERN: EVV 0xAB VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_TUPLE1_4X() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32:MULTISOURCE4 MEM0:r:dq:f32 +IFORM: V4FNMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + + + +###FILE: ../xed/datafiles/4vnniw-512/4vnniw-512-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2018 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING VP4DPWSSD (VP4DPWSSD-512-1) +{ +ICLASS: VP4DPWSSD +CPL: 3 +CATEGORY: AVX512_4VNNIW +EXTENSION: AVX512EVEX +ISA_SET: AVX512_4VNNIW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MULTISOURCE4 DISP8_TUPLE1_4X MASKOP_EVEX +PATTERN: EVV 0x52 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 VL512 W0 ESIZE_32_BITS() NELEM_TUPLE1_4X() +OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16:MULTISOURCE4 MEM0:r:dq:u32 +IFORM: VP4DPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 +} + + +# EMITTING VP4DPWSSDS (VP4DPWSSDS-512-1) +{ +ICLASS: VP4DPWSSDS +CPL: 3 +CATEGORY: AVX512_4VNNIW +EXTENSION: AVX512EVEX +ISA_SET: AVX512_4VNNIW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MULTISOURCE4 DISP8_TUPLE1_4X MASKOP_EVEX +PATTERN: EVV 0x53 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 VL512 W0 ESIZE_32_BITS() NELEM_TUPLE1_4X() +OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16:MULTISOURCE4 MEM0:r:dq:u32 +IFORM: VP4DPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 +} + + + + +###FILE: ../xed/datafiles/vpopcntdq-512/vpopcntdq-512-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2018 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING VPOPCNTD (VPOPCNTD-512-1) +{ +ICLASS: VPOPCNTD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VPOPCNTDQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x55 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 +IFORM: VPOPCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512 +} + +{ +ICLASS: VPOPCNTD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VPOPCNTDQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPOPCNTD_ZMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VPOPCNTQ (VPOPCNTQ-512-1) +{ +ICLASS: VPOPCNTQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VPOPCNTDQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x55 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VPOPCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512 +} + +{ +ICLASS: VPOPCNTQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VPOPCNTDQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPOPCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512 +} + + + + +###FILE: ../xed/datafiles/avx512f/avx512-foundation-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2018 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING VADDPD (VADDPD-512-1) +{ +ICLASS: VADDPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x58 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VADDPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x58 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VADDPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x58 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VADDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VADDPS (VADDPS-512-1) +{ +ICLASS: VADDPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x58 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VADDPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x58 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VADDPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x58 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VADDSD (VADDSD-128-1) +{ +ICLASS: VADDSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x58 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VADDSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x58 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VADDSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x58 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VADDSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VADDSS (VADDSS-128-1) +{ +ICLASS: VADDSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x58 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VADDSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x58 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VADDSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x58 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VALIGND (VALIGND-512-1) +{ +ICLASS: VALIGND +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 IMM0:r:b +IFORM: VALIGND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 +} + +{ +ICLASS: VALIGND +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VALIGND_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VALIGNQ (VALIGNQ-512-1) +{ +ICLASS: VALIGNQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 IMM0:r:b +IFORM: VALIGNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 +} + +{ +ICLASS: VALIGNQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VALIGNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VBLENDMPD (VBLENDMPD-512-1) +{ +ICLASS: VBLENDMPD +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VBLENDMPD +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL +PATTERN: EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VBLENDMPS (VBLENDMPS-512-1) +{ +ICLASS: VBLENDMPS +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VBLENDMPS +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL +PATTERN: EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VBROADCASTF32X4 (VBROADCASTF32X4-512-1) +{ +ICLASS: VBROADCASTF32X4 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x1A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE4() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32 EMX_BROADCAST_4TO16_32 +IFORM: VBROADCASTF32X4_ZMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VBROADCASTF64X4 (VBROADCASTF64X4-512-1) +{ +ICLASS: VBROADCASTF64X4 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x1B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE4() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f64 EMX_BROADCAST_4TO8_64 +IFORM: VBROADCASTF64X4_ZMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VBROADCASTI32X4 (VBROADCASTI32X4-512-1) +{ +ICLASS: VBROADCASTI32X4 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x5A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE4() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u32 EMX_BROADCAST_4TO16_32 +IFORM: VBROADCASTI32X4_ZMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VBROADCASTI64X4 (VBROADCASTI64X4-512-1) +{ +ICLASS: VBROADCASTI64X4 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x5B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE4() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u64 EMX_BROADCAST_4TO8_64 +IFORM: VBROADCASTI64X4_ZMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VBROADCASTSD (VBROADCASTSD-512-1) +{ +ICLASS: VBROADCASTSD +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 +PATTERN: EVV 0x19 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE1() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f64 EMX_BROADCAST_1TO8_64 +IFORM: VBROADCASTSD_ZMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VBROADCASTSD (VBROADCASTSD-512-2) +{ +ICLASS: VBROADCASTSD +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x19 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 EMX_BROADCAST_1TO8_64 +IFORM: VBROADCASTSD_ZMMf64_MASKmskw_XMMf64_AVX512 +} + + +# EMITTING VBROADCASTSS (VBROADCASTSS-512-1) +{ +ICLASS: VBROADCASTSS +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 +PATTERN: EVV 0x18 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:f32 EMX_BROADCAST_1TO16_32 +IFORM: VBROADCASTSS_ZMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VBROADCASTSS (VBROADCASTSS-512-2) +{ +ICLASS: VBROADCASTSS +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x18 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 EMX_BROADCAST_1TO16_32 +IFORM: VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512 +} + + +# EMITTING VCMPPD (VCMPPD-512-1) +{ +ICLASS: VCMPPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xC2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 +} + +{ +ICLASS: VCMPPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xC2 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw:TXT=SAESTR REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 +} + +{ +ICLASS: VCMPPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xC2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VCMPPD_MASKmskw_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VCMPPS (VCMPPS-512-1) +{ +ICLASS: VCMPPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xC2 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 +} + +{ +ICLASS: VCMPPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xC2 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw:TXT=SAESTR REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 +} + +{ +ICLASS: VCMPPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xC2 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VCMPPS_MASKmskw_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VCMPSD (VCMPSD-128-1) +{ +ICLASS: VCMPSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xC2 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VCMPSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xC2 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw:TXT=SAESTR REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VCMPSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0xC2 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b +IFORM: VCMPSD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VCMPSS (VCMPSS-128-1) +{ +ICLASS: VCMPSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xC2 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VCMPSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xC2 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw:TXT=SAESTR REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VCMPSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0xC2 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b +IFORM: VCMPSS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VCOMISD (VCOMISD-128-1) +{ +ICLASS: VCOMISD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():r:dq:f64 REG1=XMM_B3():r:dq:f64 +IFORM: VCOMISD_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VCOMISD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2F V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():r:dq:f64:TXT=SAESTR REG1=XMM_B3():r:dq:f64 +IFORM: VCOMISD_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VCOMISD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x2F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():r:dq:f64 MEM0:r:q:f64 +IFORM: VCOMISD_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VCOMISS (VCOMISS-128-1) +{ +ICLASS: VCOMISS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2F VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():r:dq:f32 REG1=XMM_B3():r:dq:f32 +IFORM: VCOMISS_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VCOMISS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2F VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():r:dq:f32:TXT=SAESTR REG1=XMM_B3():r:dq:f32 +IFORM: VCOMISS_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VCOMISS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x2F VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():r:dq:f32 MEM0:r:d:f32 +IFORM: VCOMISS_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VCOMPRESSPD (VCOMPRESSPD-512-1) +{ +ICLASS: VCOMPRESSPD +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:zd:f64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf64 +IFORM: VCOMPRESSPD_MEMf64_MASKmskw_ZMMf64_AVX512 +} + + +# EMITTING VCOMPRESSPD (VCOMPRESSPD-512-2) +{ +ICLASS: VCOMPRESSPD +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf64 +IFORM: VCOMPRESSPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +} + + +# EMITTING VCOMPRESSPS (VCOMPRESSPS-512-1) +{ +ICLASS: VCOMPRESSPS +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:zd:f32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32 +IFORM: VCOMPRESSPS_MEMf32_MASKmskw_ZMMf32_AVX512 +} + + +# EMITTING VCOMPRESSPS (VCOMPRESSPS-512-2) +{ +ICLASS: VCOMPRESSPS +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 +IFORM: VCOMPRESSPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +} + + +# EMITTING VCVTDQ2PD (VCVTDQ2PD-512-1) +{ +ICLASS: VCVTDQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32 +IFORM: VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512 +} + +{ +ICLASS: VCVTDQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED +PATTERN: EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VCVTDQ2PD_ZMMf64_MASKmskw_MEMi32_AVX512 +} + + +# EMITTING VCVTDQ2PS (VCVTDQ2PS-512-1) +{ +ICLASS: VCVTDQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi32 +IFORM: VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512 +} + +{ +ICLASS: VCVTDQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi32 +IFORM: VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512 +} + +{ +ICLASS: VCVTDQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VCVTDQ2PS_ZMMf32_MASKmskw_MEMi32_AVX512 +} + + +# EMITTING VCVTPD2DQ (VCVTPD2DQ-512-1) +{ +ICLASS: VCVTPD2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xE6 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512 +} + +{ +ICLASS: VCVTPD2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xE6 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512 +} + +{ +ICLASS: VCVTPD2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xE6 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512 +} + + +# EMITTING VCVTPD2PS (VCVTPD2PS-512-1) +{ +ICLASS: VCVTPD2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512 +} + +{ +ICLASS: VCVTPD2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5A V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512 +} + +{ +ICLASS: VCVTPD2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512 +} + + +# EMITTING VCVTPD2UDQ (VCVTPD2UDQ-512-1) +{ +ICLASS: VCVTPD2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512 +} + +{ +ICLASS: VCVTPD2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512 +} + +{ +ICLASS: VCVTPD2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512 +} + + +# EMITTING VCVTPH2PS (VCVTPH2PS-512-1) +{ +ICLASS: VCVTPH2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E11 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 +IFORM: VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E11 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 +IFORM: VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E11 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR DISP8_HALFMEM +PATTERN: EVV 0x13 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f16 +IFORM: VCVTPH2PS_ZMMf32_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPS2DQ (VCVTPS2DQ-512-1) +{ +ICLASS: VCVTPS2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTPS2PD (VCVTPS2PD-512-1) +{ +ICLASS: VCVTPS2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5A VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5A VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5A VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2PD_ZMMf64_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTPS2PH (VCVTPS2PH-512-1) +{ +ICLASS: VCVTPS2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E11NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +OPERANDS: REG0=YMM_B3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 IMM0:r:b +IFORM: VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512 +} + +{ +ICLASS: VCVTPS2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E11NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8() +OPERANDS: REG0=YMM_B3():w:qq:f16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 IMM0:r:b +IFORM: VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512 +} + + +# EMITTING VCVTPS2PH (VCVTPS2PH-512-2) +{ +ICLASS: VCVTPS2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E11 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR DISP8_HALFMEM +PATTERN: EVV 0x1D V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:qq:f16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32 IMM0:r:b +IFORM: VCVTPS2PH_MEMf16_MASKmskw_ZMMf32_IMM8_AVX512 +} + + +# EMITTING VCVTPS2UDQ (VCVTPS2UDQ-512-1) +{ +ICLASS: VCVTPS2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTSD2SI (VCVTSD2SI-128-1) +{ +ICLASS: VCVTSD2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f64 +IFORM: VCVTSD2SI_GPR32i32_XMMf64_AVX512 +PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f64 +IFORM: VCVTSD2SI_GPR32i32_XMMf64_AVX512 +} + +{ +ICLASS: VCVTSD2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:i32:TXT=ROUNDC REG1=XMM_B3():r:dq:f64 +IFORM: VCVTSD2SI_GPR32i32_XMMf64_AVX512 +PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:i32:TXT=ROUNDC REG1=XMM_B3():r:dq:f64 +IFORM: VCVTSD2SI_GPR32i32_XMMf64_AVX512 +} + +{ +ICLASS: VCVTSD2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q +PATTERN: EVV 0x2D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() +OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:q:f64 +IFORM: VCVTSD2SI_GPR32i32_MEMf64_AVX512 +PATTERN: EVV 0x2D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:q:f64 +IFORM: VCVTSD2SI_GPR32i32_MEMf64_AVX512 +} + + +# EMITTING VCVTSD2SI (VCVTSD2SI-128-2) +{ +ICLASS: VCVTSD2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f64 +IFORM: VCVTSD2SI_GPR64i64_XMMf64_AVX512 +} + +{ +ICLASS: VCVTSD2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:i64:TXT=ROUNDC REG1=XMM_B3():r:dq:f64 +IFORM: VCVTSD2SI_GPR64i64_XMMf64_AVX512 +} + +{ +ICLASS: VCVTSD2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q +PATTERN: EVV 0x2D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:i64 MEM0:r:q:f64 +IFORM: VCVTSD2SI_GPR64i64_MEMf64_AVX512 +} + + +# EMITTING VCVTSD2SS (VCVTSD2SS-128-1) +{ +ICLASS: VCVTSD2SS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VCVTSD2SS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VCVTSD2SS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VCVTSD2USI (VCVTSD2USI-128-1) +{ +ICLASS: VCVTSD2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f64 +IFORM: VCVTSD2USI_GPR32u32_XMMf64_AVX512 +PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f64 +IFORM: VCVTSD2USI_GPR32u32_XMMf64_AVX512 +} + +{ +ICLASS: VCVTSD2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:u32:TXT=ROUNDC REG1=XMM_B3():r:dq:f64 +IFORM: VCVTSD2USI_GPR32u32_XMMf64_AVX512 +PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:u32:TXT=ROUNDC REG1=XMM_B3():r:dq:f64 +IFORM: VCVTSD2USI_GPR32u32_XMMf64_AVX512 +} + +{ +ICLASS: VCVTSD2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q +PATTERN: EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() +OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:q:f64 +IFORM: VCVTSD2USI_GPR32u32_MEMf64_AVX512 +PATTERN: EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:q:f64 +IFORM: VCVTSD2USI_GPR32u32_MEMf64_AVX512 +} + + +# EMITTING VCVTSD2USI (VCVTSD2USI-128-2) +{ +ICLASS: VCVTSD2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f64 +IFORM: VCVTSD2USI_GPR64u64_XMMf64_AVX512 +} + +{ +ICLASS: VCVTSD2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:u64:TXT=ROUNDC REG1=XMM_B3():r:dq:f64 +IFORM: VCVTSD2USI_GPR64u64_XMMf64_AVX512 +} + +{ +ICLASS: VCVTSD2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q +PATTERN: EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:u64 MEM0:r:q:f64 +IFORM: VCVTSD2USI_GPR64u64_MEMf64_AVX512 +} + + +# EMITTING VCVTSI2SD (VCVTSI2SD-128-1) +{ +ICLASS: VCVTSI2SD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E10NF +REAL_OPCODE: Y +ATTRIBUTES: SIMD_SCALAR +COMMENT: Ignores rounding controls: 32b-INT-to-FP64 does not need rounding +PATTERN: EVV 0x2A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR32_B():r:d:i32 +IFORM: VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512 +PATTERN: EVV 0x2A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR32_B():r:d:i32 +IFORM: VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512 +} + +{ +ICLASS: VCVTSI2SD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E10NF +REAL_OPCODE: Y +ATTRIBUTES: SIMD_SCALAR DISP8_GPR_READER +PATTERN: EVV 0x2A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:d:i32 +IFORM: VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512 +PATTERN: EVV 0x2A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W0 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:d:i32 +IFORM: VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512 +} + + +# EMITTING VCVTSI2SD (VCVTSI2SD-128-2) +{ +ICLASS: VCVTSI2SD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=0 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR64_B():r:q:i64 +IFORM: VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512 } { -ICLASS: VEXP2PD +ICLASS: VCVTSI2SD CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512ER_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xC8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 -IFORM: VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=1 FIX_ROUND_LEN128() AVX512_ROUND() +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=XMM_N3():r:dq:f64 REG2=GPR64_B():r:q:i64 +IFORM: VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512 } { -ICLASS: VEXP2PD +ICLASS: VCVTSI2SD CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512ER_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xC8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VEXP2PD_ZMMf64_MASKmskw_MEMf64_AVX512ER +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER +PATTERN: EVV 0x2A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W1 ZEROING=0 MASK=0 BCRC=0 ESIZE_64_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:q:i64 +IFORM: VCVTSI2SD_XMMf64_XMMf64_MEMi64_AVX512 } -# EMITTING VEXP2PS (VEXP2PS-512-1) +# EMITTING VCVTSI2SS (VCVTSI2SS-128-1) { -ICLASS: VEXP2PS +ICLASS: VCVTSI2SS CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512ER_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xC8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 -IFORM: VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:i32 +IFORM: VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512 +PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:i32 +IFORM: VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512 } { -ICLASS: VEXP2PS +ICLASS: VCVTSI2SS CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512ER_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xC8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 -IFORM: VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:i32 +IFORM: VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512 +PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:i32 +IFORM: VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512 } { -ICLASS: VEXP2PS +ICLASS: VCVTSI2SS CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512ER_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xC8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VEXP2PS_ZMMf32_MASKmskw_MEMf32_AVX512ER +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER +PATTERN: EVV 0x2A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:d:i32 +IFORM: VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512 +PATTERN: EVV 0x2A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:d:i32 +IFORM: VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512 } -# EMITTING VGATHERPF0DPD (VGATHERPF0DPD-512-1) +# EMITTING VCVTSI2SS (VCVTSI2SS-128-2) { -ICLASS: VGATHERPF0DPD +ICLASS: VCVTSI2SS CPL: 3 -CATEGORY: GATHER +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512PF_512 -EXCEPTIONS: AVX512-E12NP +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b001] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() -OPERANDS: MEM0:r:b:f64 REG0=MASKNOT0():rw:mskw -IFORM: VGATHERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512 +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR64_B():r:q:i64 +IFORM: VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512 } - -# EMITTING VGATHERPF0DPS (VGATHERPF0DPS-512-1) { -ICLASS: VGATHERPF0DPS +ICLASS: VCVTSI2SS CPL: 3 -CATEGORY: GATHER +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512PF_512 -EXCEPTIONS: AVX512-E12NP +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b001] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() -OPERANDS: MEM0:r:b:f32 REG0=MASKNOT0():rw:mskw -IFORM: VGATHERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512 +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR64_B():r:q:i64 +IFORM: VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512 } - -# EMITTING VGATHERPF0QPD (VGATHERPF0QPD-512-1) { -ICLASS: VGATHERPF0QPD +ICLASS: VCVTSI2SS CPL: 3 -CATEGORY: GATHER +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512PF_512 -EXCEPTIONS: AVX512-E12NP +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b001] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() -OPERANDS: MEM0:r:b:f64 REG0=MASKNOT0():rw:mskw -IFORM: VGATHERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512 +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER +PATTERN: EVV 0x2A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:q:i64 +IFORM: VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512 +} +# EMITTING VCVTSS2SD (VCVTSS2SD-128-1) +{ +ICLASS: VCVTSS2SD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512 } +{ +ICLASS: VCVTSS2SD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512 +} -# EMITTING VGATHERPF0QPS (VGATHERPF0QPS-512-1) { -ICLASS: VGATHERPF0QPS +ICLASS: VCVTSS2SD CPL: 3 -CATEGORY: GATHER +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512PF_512 -EXCEPTIONS: AVX512-E12NP +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b001] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() -OPERANDS: MEM0:r:b:f32 REG0=MASKNOT0():rw:mskw -IFORM: VGATHERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VCVTSS2SD_XMMf64_MASKmskw_XMMf32_MEMf32_AVX512 } -# EMITTING VGATHERPF1DPD (VGATHERPF1DPD-512-1) +# EMITTING VCVTSS2SI (VCVTSS2SI-128-1) { -ICLASS: VGATHERPF1DPD +ICLASS: VCVTSS2SI CPL: 3 -CATEGORY: GATHER +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512PF_512 -EXCEPTIONS: AVX512-E12NP +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() -OPERANDS: MEM0:r:b:f64 REG0=MASKNOT0():rw:mskw -IFORM: VGATHERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512 +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f32 +IFORM: VCVTSS2SI_GPR32i32_XMMf32_AVX512 +PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f32 +IFORM: VCVTSS2SI_GPR32i32_XMMf32_AVX512 } +{ +ICLASS: VCVTSS2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:i32:TXT=ROUNDC REG1=XMM_B3():r:dq:f32 +IFORM: VCVTSS2SI_GPR32i32_XMMf32_AVX512 +PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:i32:TXT=ROUNDC REG1=XMM_B3():r:dq:f32 +IFORM: VCVTSS2SI_GPR32i32_XMMf32_AVX512 +} -# EMITTING VGATHERPF1DPS (VGATHERPF1DPS-512-1) { -ICLASS: VGATHERPF1DPS +ICLASS: VCVTSS2SI CPL: 3 -CATEGORY: GATHER +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512PF_512 -EXCEPTIONS: AVX512-E12NP +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() -OPERANDS: MEM0:r:b:f32 REG0=MASKNOT0():rw:mskw -IFORM: VGATHERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512 +ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() +OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:d:f32 +IFORM: VCVTSS2SI_GPR32i32_MEMf32_AVX512 +PATTERN: EVV 0x2D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:d:f32 +IFORM: VCVTSS2SI_GPR32i32_MEMf32_AVX512 } -# EMITTING VGATHERPF1QPD (VGATHERPF1QPD-512-1) +# EMITTING VCVTSS2SI (VCVTSS2SI-128-2) { -ICLASS: VGATHERPF1QPD +ICLASS: VCVTSS2SI CPL: 3 -CATEGORY: GATHER +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512PF_512 -EXCEPTIONS: AVX512-E12NP +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() -OPERANDS: MEM0:r:b:f64 REG0=MASKNOT0():rw:mskw -IFORM: VGATHERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512 +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f32 +IFORM: VCVTSS2SI_GPR64i64_XMMf32_AVX512 } +{ +ICLASS: VCVTSS2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:i64:TXT=ROUNDC REG1=XMM_B3():r:dq:f32 +IFORM: VCVTSS2SI_GPR64i64_XMMf32_AVX512 +} -# EMITTING VGATHERPF1QPS (VGATHERPF1QPS-512-1) { -ICLASS: VGATHERPF1QPS +ICLASS: VCVTSS2SI CPL: 3 -CATEGORY: GATHER +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512PF_512 -EXCEPTIONS: AVX512-E12NP +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() -OPERANDS: MEM0:r:b:f32 REG0=MASKNOT0():rw:mskw -IFORM: VGATHERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512 +ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:i64 MEM0:r:d:f32 +IFORM: VCVTSS2SI_GPR64i64_MEMf32_AVX512 } -# EMITTING VRCP28PD (VRCP28PD-512-1) +# EMITTING VCVTSS2USI (VCVTSS2USI-128-1) { -ICLASS: VRCP28PD +ICLASS: VCVTSS2USI CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512ER_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xCA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 -IFORM: VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f32 +IFORM: VCVTSS2USI_GPR32u32_XMMf32_AVX512 +PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f32 +IFORM: VCVTSS2USI_GPR32u32_XMMf32_AVX512 } { -ICLASS: VRCP28PD +ICLASS: VCVTSS2USI CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512ER_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xCA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 -IFORM: VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:u32:TXT=ROUNDC REG1=XMM_B3():r:dq:f32 +IFORM: VCVTSS2USI_GPR32u32_XMMf32_AVX512 +PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:u32:TXT=ROUNDC REG1=XMM_B3():r:dq:f32 +IFORM: VCVTSS2USI_GPR32u32_XMMf32_AVX512 } { -ICLASS: VRCP28PD +ICLASS: VCVTSS2USI CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512ER_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xCA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VRCP28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER +ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() +OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:d:f32 +IFORM: VCVTSS2USI_GPR32u32_MEMf32_AVX512 +PATTERN: EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:d:f32 +IFORM: VCVTSS2USI_GPR32u32_MEMf32_AVX512 } -# EMITTING VRCP28PS (VRCP28PS-512-1) +# EMITTING VCVTSS2USI (VCVTSS2USI-128-2) { -ICLASS: VRCP28PS +ICLASS: VCVTSS2USI CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512ER_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xCA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 -IFORM: VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f32 +IFORM: VCVTSS2USI_GPR64u64_XMMf32_AVX512 } { -ICLASS: VRCP28PS +ICLASS: VCVTSS2USI CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512ER_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xCA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 -IFORM: VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:u64:TXT=ROUNDC REG1=XMM_B3():r:dq:f32 +IFORM: VCVTSS2USI_GPR64u64_XMMf32_AVX512 } { -ICLASS: VRCP28PS +ICLASS: VCVTSS2USI CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512ER_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xCA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VRCP28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER +ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:u64 MEM0:r:d:f32 +IFORM: VCVTSS2USI_GPR64u64_MEMf32_AVX512 } -# EMITTING VRCP28SD (VRCP28SD-128-1) +# EMITTING VCVTTPD2DQ (VCVTTPD2DQ-512-1) { -ICLASS: VRCP28SD +ICLASS: VCVTTPD2DQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512ER_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0xCB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xE6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512 } { -ICLASS: VRCP28SD +ICLASS: VCVTTPD2DQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512ER_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0xCB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 -OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xE6 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512 } { -ICLASS: VRCP28SD +ICLASS: VCVTTPD2DQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512ER_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0xCB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 -IFORM: VRCP28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xE6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512 } -# EMITTING VRCP28SS (VRCP28SS-128-1) +# EMITTING VCVTTPD2UDQ (VCVTTPD2UDQ-512-1) { -ICLASS: VRCP28SS +ICLASS: VCVTTPD2UDQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512ER_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0xCB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512 } { -ICLASS: VRCP28SS +ICLASS: VCVTTPD2UDQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512ER_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0xCB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 -OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512 } { -ICLASS: VRCP28SS +ICLASS: VCVTTPD2UDQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512ER_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0xCB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 -IFORM: VRCP28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512 } -# EMITTING VRSQRT28PD (VRSQRT28PD-512-1) +# EMITTING VCVTTPS2DQ (VCVTTPS2DQ-512-1) { -ICLASS: VRSQRT28PD +ICLASS: VCVTTPS2DQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512ER_512 +ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xCC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 -IFORM: VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512 } { -ICLASS: VRSQRT28PD +ICLASS: VCVTTPS2DQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512ER_512 +ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xCC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 -IFORM: VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512 } { -ICLASS: VRSQRT28PD +ICLASS: VCVTTPS2DQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512ER_512 +ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xCC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VRSQRT28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512 } -# EMITTING VRSQRT28PS (VRSQRT28PS-512-1) +# EMITTING VCVTTPS2UDQ (VCVTTPS2UDQ-512-1) { -ICLASS: VRSQRT28PS +ICLASS: VCVTTPS2UDQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512ER_512 +ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xCC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 -IFORM: VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512 } { -ICLASS: VRSQRT28PS +ICLASS: VCVTTPS2UDQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512ER_512 +ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xCC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 -IFORM: VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512 } { -ICLASS: VRSQRT28PS +ICLASS: VCVTTPS2UDQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512ER_512 +ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xCC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VRSQRT28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512 } -# EMITTING VRSQRT28SD (VRSQRT28SD-128-1) +# EMITTING VCVTTSD2SI (VCVTTSD2SI-128-1) { -ICLASS: VRSQRT28SD +ICLASS: VCVTTSD2SI CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512ER_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0xCD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f64 +IFORM: VCVTTSD2SI_GPR32i32_XMMf64_AVX512 +PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f64 +IFORM: VCVTTSD2SI_GPR32i32_XMMf64_AVX512 } { -ICLASS: VRSQRT28SD +ICLASS: VCVTTSD2SI CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512ER_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0xCD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 -OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f64 +IFORM: VCVTTSD2SI_GPR32i32_XMMf64_AVX512 +PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f64 +IFORM: VCVTTSD2SI_GPR32i32_XMMf64_AVX512 } { -ICLASS: VRSQRT28SD +ICLASS: VCVTTSD2SI CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512ER_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0xCD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 -IFORM: VRSQRT28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q +PATTERN: EVV 0x2C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() +OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:q:f64 +IFORM: VCVTTSD2SI_GPR32i32_MEMf64_AVX512 +PATTERN: EVV 0x2C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:q:f64 +IFORM: VCVTTSD2SI_GPR32i32_MEMf64_AVX512 } -# EMITTING VRSQRT28SS (VRSQRT28SS-128-1) +# EMITTING VCVTTSD2SI (VCVTTSD2SI-128-2) { -ICLASS: VRSQRT28SS +ICLASS: VCVTTSD2SI CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512ER_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0xCD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f64 +IFORM: VCVTTSD2SI_GPR64i64_XMMf64_AVX512 } { -ICLASS: VRSQRT28SS +ICLASS: VCVTTSD2SI CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512ER_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0xCD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 -OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:i64:TXT=SAESTR REG1=XMM_B3():r:dq:f64 +IFORM: VCVTTSD2SI_GPR64i64_XMMf64_AVX512 } { -ICLASS: VRSQRT28SS +ICLASS: VCVTTSD2SI CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512ER_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0xCD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 -IFORM: VRSQRT28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q +PATTERN: EVV 0x2C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:i64 MEM0:r:q:f64 +IFORM: VCVTTSD2SI_GPR64i64_MEMf64_AVX512 } -# EMITTING VSCATTERPF0DPD (VSCATTERPF0DPD-512-1) +# EMITTING VCVTTSD2USI (VCVTTSD2USI-128-1) { -ICLASS: VSCATTERPF0DPD +ICLASS: VCVTTSD2USI CPL: 3 -CATEGORY: SCATTER +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512PF_512 -EXCEPTIONS: AVX512-E12NP +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b101] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() -OPERANDS: MEM0:r:b:f64 REG0=MASKNOT0():rw:mskw -IFORM: VSCATTERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512 +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f64 +IFORM: VCVTTSD2USI_GPR32u32_XMMf64_AVX512 +PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f64 +IFORM: VCVTTSD2USI_GPR32u32_XMMf64_AVX512 } - -# EMITTING VSCATTERPF0DPS (VSCATTERPF0DPS-512-1) { -ICLASS: VSCATTERPF0DPS +ICLASS: VCVTTSD2USI CPL: 3 -CATEGORY: SCATTER +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512PF_512 -EXCEPTIONS: AVX512-E12NP +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b101] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() -OPERANDS: MEM0:r:b:f32 REG0=MASKNOT0():rw:mskw -IFORM: VSCATTERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512 +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f64 +IFORM: VCVTTSD2USI_GPR32u32_XMMf64_AVX512 +PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f64 +IFORM: VCVTTSD2USI_GPR32u32_XMMf64_AVX512 } - -# EMITTING VSCATTERPF0QPD (VSCATTERPF0QPD-512-1) { -ICLASS: VSCATTERPF0QPD +ICLASS: VCVTTSD2USI CPL: 3 -CATEGORY: SCATTER +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512PF_512 -EXCEPTIONS: AVX512-E12NP +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b101] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() -OPERANDS: MEM0:r:b:f64 REG0=MASKNOT0():rw:mskw -IFORM: VSCATTERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512 +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q +PATTERN: EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() +OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:q:f64 +IFORM: VCVTTSD2USI_GPR32u32_MEMf64_AVX512 +PATTERN: EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:q:f64 +IFORM: VCVTTSD2USI_GPR32u32_MEMf64_AVX512 } -# EMITTING VSCATTERPF0QPS (VSCATTERPF0QPS-512-1) +# EMITTING VCVTTSD2USI (VCVTTSD2USI-128-2) { -ICLASS: VSCATTERPF0QPS +ICLASS: VCVTTSD2USI CPL: 3 -CATEGORY: SCATTER +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512PF_512 -EXCEPTIONS: AVX512-E12NP +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b101] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() -OPERANDS: MEM0:r:b:f32 REG0=MASKNOT0():rw:mskw -IFORM: VSCATTERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512 +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f64 +IFORM: VCVTTSD2USI_GPR64u64_XMMf64_AVX512 } - -# EMITTING VSCATTERPF1DPD (VSCATTERPF1DPD-512-1) { -ICLASS: VSCATTERPF1DPD +ICLASS: VCVTTSD2USI CPL: 3 -CATEGORY: SCATTER +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512PF_512 -EXCEPTIONS: AVX512-E12NP +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() -OPERANDS: MEM0:r:b:f64 REG0=MASKNOT0():rw:mskw -IFORM: VSCATTERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512 +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:u64:TXT=SAESTR REG1=XMM_B3():r:dq:f64 +IFORM: VCVTTSD2USI_GPR64u64_XMMf64_AVX512 } - -# EMITTING VSCATTERPF1DPS (VSCATTERPF1DPS-512-1) { -ICLASS: VSCATTERPF1DPS +ICLASS: VCVTTSD2USI CPL: 3 -CATEGORY: SCATTER +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512PF_512 -EXCEPTIONS: AVX512-E12NP +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() -OPERANDS: MEM0:r:b:f32 REG0=MASKNOT0():rw:mskw -IFORM: VSCATTERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512 +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q +PATTERN: EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:u64 MEM0:r:q:f64 +IFORM: VCVTTSD2USI_GPR64u64_MEMf64_AVX512 } -# EMITTING VSCATTERPF1QPD (VSCATTERPF1QPD-512-1) +# EMITTING VCVTTSS2SI (VCVTTSS2SI-128-1) { -ICLASS: VSCATTERPF1QPD +ICLASS: VCVTTSS2SI CPL: 3 -CATEGORY: SCATTER +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512PF_512 -EXCEPTIONS: AVX512-E12NP +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() -OPERANDS: MEM0:r:b:f64 REG0=MASKNOT0():rw:mskw -IFORM: VSCATTERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512 +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f32 +IFORM: VCVTTSS2SI_GPR32i32_XMMf32_AVX512 +PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f32 +IFORM: VCVTTSS2SI_GPR32i32_XMMf32_AVX512 } - -# EMITTING VSCATTERPF1QPS (VSCATTERPF1QPS-512-1) { -ICLASS: VSCATTERPF1QPS +ICLASS: VCVTTSS2SI CPL: 3 -CATEGORY: SCATTER +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512PF_512 -EXCEPTIONS: AVX512-E12NP +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() -OPERANDS: MEM0:r:b:f32 REG0=MASKNOT0():rw:mskw -IFORM: VSCATTERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512 +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f32 +IFORM: VCVTTSS2SI_GPR32i32_XMMf32_AVX512 +PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f32 +IFORM: VCVTTSS2SI_GPR32i32_XMMf32_AVX512 } - -INSTRUCTIONS():: -# EMITTING PREFETCHWT1 (PREFETCHWT1-N/A-1) { -ICLASS: PREFETCHWT1 +ICLASS: VCVTTSS2SI CPL: 3 -CATEGORY: AVX512 -EXTENSION: PREFETCHWT1 -ISA_SET: PREFETCHWT1 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: PREFETCH -PATTERN: 0x0F 0x0D MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() -OPERANDS: MEM0:r:b:u8 -IFORM: PREFETCHWT1_MEMu8 +ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() +OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:d:f32 +IFORM: VCVTTSS2SI_GPR32i32_MEMf32_AVX512 +PATTERN: EVV 0x2C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:d:f32 +IFORM: VCVTTSS2SI_GPR32i32_MEMf32_AVX512 } - - -###FILE: ../xed/datafiles/4fmaps-512/4fmaps-512-isa.xed.txt - -#BEGIN_LEGAL -# -#Copyright (c) 2016 Intel Corporation -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -#END_LEGAL -# -# -# -# ***** GENERATED FILE -- DO NOT EDIT! ***** -# ***** GENERATED FILE -- DO NOT EDIT! ***** -# ***** GENERATED FILE -- DO NOT EDIT! ***** -# -# -# -EVEX_INSTRUCTIONS():: -# EMITTING V4FMADDPS (V4FMADDPS-512-1) +# EMITTING VCVTTSS2SI (VCVTTSS2SI-128-2) { -ICLASS: V4FMADDPS +ICLASS: VCVTTSS2SI CPL: 3 -CATEGORY: AVX512_4FMAPS +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512_4FMAPS_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MULTISOURCE4 DISP8_TUPLE1_4X MXCSR MASKOP_EVEX -PATTERN: EVV 0x9A VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_TUPLE1_4X() -OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32:MULTISOURCE4 MEM0:r:dq:f32 -IFORM: V4FMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f32 +IFORM: VCVTTSS2SI_GPR64i64_XMMf32_AVX512 } - -# EMITTING V4FMADDSS (V4FMADDSS-128-1) { -ICLASS: V4FMADDSS +ICLASS: VCVTTSS2SI CPL: 3 -CATEGORY: AVX512_4FMAPS +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512_4FMAPS_SCALAR -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: DISP8_TUPLE1_4X MXCSR MULTISOURCE4 MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SIMD_SCALAR -PATTERN: EVV 0x9B VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_TUPLE1_4X() -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32:MULTISOURCE4 MEM0:r:dq:f32 -IFORM: V4FMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:i64:TXT=SAESTR REG1=XMM_B3():r:dq:f32 +IFORM: VCVTTSS2SI_GPR64i64_XMMf32_AVX512 } - -# EMITTING V4FNMADDPS (V4FNMADDPS-512-1) { -ICLASS: V4FNMADDPS +ICLASS: VCVTTSS2SI CPL: 3 -CATEGORY: AVX512_4FMAPS +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512_4FMAPS_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MULTISOURCE4 DISP8_TUPLE1_4X MXCSR MASKOP_EVEX -PATTERN: EVV 0xAA VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_TUPLE1_4X() -OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32:MULTISOURCE4 MEM0:r:dq:f32 -IFORM: V4FNMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:i64 MEM0:r:d:f32 +IFORM: VCVTTSS2SI_GPR64i64_MEMf32_AVX512 } -# EMITTING V4FNMADDSS (V4FNMADDSS-128-1) +# EMITTING VCVTTSS2USI (VCVTTSS2USI-128-1) { -ICLASS: V4FNMADDSS +ICLASS: VCVTTSS2USI CPL: 3 -CATEGORY: AVX512_4FMAPS +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512_4FMAPS_SCALAR -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: DISP8_TUPLE1_4X MXCSR MULTISOURCE4 MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SIMD_SCALAR -PATTERN: EVV 0xAB VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_TUPLE1_4X() -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32:MULTISOURCE4 MEM0:r:dq:f32 -IFORM: V4FNMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f32 +IFORM: VCVTTSS2USI_GPR32u32_XMMf32_AVX512 +PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f32 +IFORM: VCVTTSS2USI_GPR32u32_XMMf32_AVX512 } - - - -###FILE: ../xed/datafiles/4vnniw-512/4vnniw-512-isa.xed.txt - -#BEGIN_LEGAL -# -#Copyright (c) 2016 Intel Corporation -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -#END_LEGAL -# -# -# -# ***** GENERATED FILE -- DO NOT EDIT! ***** -# ***** GENERATED FILE -- DO NOT EDIT! ***** -# ***** GENERATED FILE -- DO NOT EDIT! ***** -# -# -# -EVEX_INSTRUCTIONS():: -# EMITTING VP4DPWSSD (VP4DPWSSD-512-1) { -ICLASS: VP4DPWSSD +ICLASS: VCVTTSS2USI CPL: 3 -CATEGORY: AVX512_4VNNIW +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512_4VNNIW_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MULTISOURCE4 DISP8_TUPLE1_4X MASKOP_EVEX -PATTERN: EVV 0x52 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_TUPLE1_4X() -OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16:MULTISOURCE4 MEM0:r:dq:u32 -IFORM: VP4DPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f32 +IFORM: VCVTTSS2USI_GPR32u32_XMMf32_AVX512 +PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f32 +IFORM: VCVTTSS2USI_GPR32u32_XMMf32_AVX512 } - -# EMITTING VP4DPWSSDS (VP4DPWSSDS-512-1) { -ICLASS: VP4DPWSSDS +ICLASS: VCVTTSS2USI CPL: 3 -CATEGORY: AVX512_4VNNIW +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512_4VNNIW_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MULTISOURCE4 DISP8_TUPLE1_4X MASKOP_EVEX -PATTERN: EVV 0x53 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_TUPLE1_4X() -OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16:MULTISOURCE4 MEM0:r:dq:u32 -IFORM: VP4DPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 +ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() +OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:d:f32 +IFORM: VCVTTSS2USI_GPR32u32_MEMf32_AVX512 +PATTERN: EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:d:f32 +IFORM: VCVTTSS2USI_GPR32u32_MEMf32_AVX512 } - - -###FILE: ../xed/datafiles/vpopcntdq-512/vpopcntdq-512-isa.xed.txt - -#BEGIN_LEGAL -# -#Copyright (c) 2016 Intel Corporation -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -#END_LEGAL -# -# -# -# ***** GENERATED FILE -- DO NOT EDIT! ***** -# ***** GENERATED FILE -- DO NOT EDIT! ***** -# ***** GENERATED FILE -- DO NOT EDIT! ***** -# -# -# -EVEX_INSTRUCTIONS():: -# EMITTING VPOPCNTD (VPOPCNTD-512-1) +# EMITTING VCVTTSS2USI (VCVTTSS2USI-128-2) +{ +ICLASS: VCVTTSS2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f32 +IFORM: VCVTTSS2USI_GPR64u64_XMMf32_AVX512 +} + { -ICLASS: VPOPCNTD +ICLASS: VCVTTSS2USI CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512_VPOPCNTDQ_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x55 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 -IFORM: VPOPCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512 +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:u64:TXT=SAESTR REG1=XMM_B3():r:dq:f32 +IFORM: VCVTTSS2USI_GPR64u64_XMMf32_AVX512 } { -ICLASS: VPOPCNTD +ICLASS: VCVTTSS2USI CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512_VPOPCNTDQ_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPOPCNTD_ZMMu32_MASKmskw_MEMu32_AVX512 +ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:u64 MEM0:r:d:f32 +IFORM: VCVTTSS2USI_GPR64u64_MEMf32_AVX512 } -# EMITTING VPOPCNTQ (VPOPCNTQ-512-1) +# EMITTING VCVTUDQ2PD (VCVTUDQ2PD-512-1) { -ICLASS: VPOPCNTQ +ICLASS: VCVTUDQ2PD CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512_VPOPCNTDQ_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x55 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 -IFORM: VPOPCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512 +PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 +IFORM: VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512 } { -ICLASS: VPOPCNTQ +ICLASS: VCVTUDQ2PD CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512_VPOPCNTDQ_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPOPCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED +PATTERN: EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VCVTUDQ2PD_ZMMf64_MASKmskw_MEMu32_AVX512 } - - -###FILE: ../xed/datafiles/avx512f/avx512-foundation-isa.xed.txt - -#BEGIN_LEGAL -# -#Copyright (c) 2016 Intel Corporation -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -#END_LEGAL -# -# -# -# ***** GENERATED FILE -- DO NOT EDIT! ***** -# ***** GENERATED FILE -- DO NOT EDIT! ***** -# ***** GENERATED FILE -- DO NOT EDIT! ***** -# -# -# -EVEX_INSTRUCTIONS():: -# EMITTING VADDPD (VADDPD-512-1) +# EMITTING VCVTUDQ2PS (VCVTUDQ2PS-512-1) { -ICLASS: VADDPD +ICLASS: VCVTUDQ2PS CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x58 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 +IFORM: VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512 } { -ICLASS: VADDPD +ICLASS: VCVTUDQ2PS CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x58 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 -OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 +IFORM: VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512 } { -ICLASS: VADDPD +ICLASS: VCVTUDQ2PS CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x58 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VADDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VCVTUDQ2PS_ZMMf32_MASKmskw_MEMu32_AVX512 } -# EMITTING VADDPS (VADDPS-512-1) +# EMITTING VCVTUSI2SD (VCVTUSI2SD-128-1) { -ICLASS: VADDPS +ICLASS: VCVTUSI2SD CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E10NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x58 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +ATTRIBUTES: SIMD_SCALAR +PATTERN: EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR32_B():r:d:u32 +IFORM: VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512 +PATTERN: EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR32_B():r:d:u32 +IFORM: VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512 } { -ICLASS: VADDPS +ICLASS: VCVTUSI2SD CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E10NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x58 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 -OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +ATTRIBUTES: SIMD_SCALAR DISP8_GPR_READER +PATTERN: EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:d:u32 +IFORM: VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512 +PATTERN: EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W0 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:d:u32 +IFORM: VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512 } + +# EMITTING VCVTUSI2SD (VCVTUSI2SD-128-2) { -ICLASS: VADDPS +ICLASS: VCVTUSI2SD CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x58 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=0 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR64_B():r:q:u64 +IFORM: VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512 } - -# EMITTING VADDSD (VADDSD-128-1) { -ICLASS: VADDSD +ICLASS: VCVTUSI2SD CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x58 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=1 FIX_ROUND_LEN128() AVX512_ROUND() +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=XMM_N3():r:dq:f64 REG2=GPR64_B():r:q:u64 +IFORM: VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512 } { -ICLASS: VADDSD +ICLASS: VCVTUSI2SD CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x58 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 -OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER +PATTERN: EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W1 ZEROING=0 MASK=0 BCRC=0 ESIZE_64_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:q:u64 +IFORM: VCVTUSI2SD_XMMf64_XMMf64_MEMu64_AVX512 } + +# EMITTING VCVTUSI2SS (VCVTUSI2SS-128-1) { -ICLASS: VADDSD +ICLASS: VCVTUSI2SS CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0x58 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 -IFORM: VADDSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:u32 +IFORM: VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512 +PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:u32 +IFORM: VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512 } - -# EMITTING VADDSS (VADDSS-128-1) { -ICLASS: VADDSS +ICLASS: VCVTUSI2SS CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x58 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:u32 +IFORM: VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512 +PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:u32 +IFORM: VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512 } { -ICLASS: VADDSS +ICLASS: VCVTUSI2SS CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x58 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 -OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER +PATTERN: EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:d:u32 +IFORM: VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512 +PATTERN: EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:d:u32 +IFORM: VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512 } + +# EMITTING VCVTUSI2SS (VCVTUSI2SS-128-2) { -ICLASS: VADDSS +ICLASS: VCVTUSI2SS CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0x58 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 -IFORM: VADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR64_B():r:q:u64 +IFORM: VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512 } - -# EMITTING VALIGND (VALIGND-512-1) { -ICLASS: VALIGND +ICLASS: VCVTUSI2SS CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 IMM0:r:b -IFORM: VALIGND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR64_B():r:q:u64 +IFORM: VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512 } { -ICLASS: VALIGND +ICLASS: VCVTUSI2SS CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b -IFORM: VALIGND_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER +PATTERN: EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:q:u64 +IFORM: VCVTUSI2SS_XMMf32_XMMf32_MEMu64_AVX512 } -# EMITTING VALIGNQ (VALIGNQ-512-1) +# EMITTING VDIVPD (VDIVPD-512-1) { -ICLASS: VALIGNQ +ICLASS: VDIVPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 IMM0:r:b -IFORM: VALIGNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 } { -ICLASS: VALIGNQ +ICLASS: VDIVPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b -IFORM: VALIGNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5E V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 } - -# EMITTING VBLENDMPD (VBLENDMPD-512-1) { -ICLASS: VBLENDMPD +ICLASS: VDIVPD CPL: 3 -CATEGORY: BLEND +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL -PATTERN: EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VDIVPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 } + +# EMITTING VDIVPS (VDIVPS-512-1) { -ICLASS: VBLENDMPD +ICLASS: VDIVPS CPL: 3 -CATEGORY: BLEND +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5E VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 } - -# EMITTING VBLENDMPS (VBLENDMPS-512-1) { -ICLASS: VBLENDMPS +ICLASS: VDIVPS CPL: 3 -CATEGORY: BLEND +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL -PATTERN: EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5E VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 } { -ICLASS: VBLENDMPS +ICLASS: VDIVPS CPL: 3 -CATEGORY: BLEND +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5E VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +IFORM: VDIVPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 } -# EMITTING VBROADCASTF32X4 (VBROADCASTF32X4-512-1) +# EMITTING VDIVSD (VDIVSD-128-1) { -ICLASS: VBROADCASTF32X4 +ICLASS: VDIVSD CPL: 3 -CATEGORY: BROADCAST +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE4 -PATTERN: EVV 0x1A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE4() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32 EMX_BROADCAST_4TO16_32 -IFORM: VBROADCASTF32X4_ZMMf32_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5E VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } - -# EMITTING VBROADCASTF64X4 (VBROADCASTF64X4-512-1) { -ICLASS: VBROADCASTF64X4 +ICLASS: VDIVSD CPL: 3 -CATEGORY: BROADCAST +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE4 -PATTERN: EVV 0x1B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE4() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f64 EMX_BROADCAST_4TO8_64 -IFORM: VBROADCASTF64X4_ZMMf64_MASKmskw_MEMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5E VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } - -# EMITTING VBROADCASTI32X4 (VBROADCASTI32X4-512-1) { -ICLASS: VBROADCASTI32X4 +ICLASS: VDIVSD CPL: 3 -CATEGORY: BROADCAST +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE4 -PATTERN: EVV 0x5A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE4() -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u32 EMX_BROADCAST_4TO16_32 -IFORM: VBROADCASTI32X4_ZMMu32_MASKmskw_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x5E VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VDIVSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 } -# EMITTING VBROADCASTI64X4 (VBROADCASTI64X4-512-1) +# EMITTING VDIVSS (VDIVSS-128-1) { -ICLASS: VBROADCASTI64X4 +ICLASS: VDIVSS CPL: 3 -CATEGORY: BROADCAST +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE4 -PATTERN: EVV 0x5B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE4() -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u64 EMX_BROADCAST_4TO8_64 -IFORM: VBROADCASTI64X4_ZMMu64_MASKmskw_MEMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5E VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } - -# EMITTING VBROADCASTSD (VBROADCASTSD-512-1) { -ICLASS: VBROADCASTSD +ICLASS: VDIVSS CPL: 3 -CATEGORY: BROADCAST +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 -PATTERN: EVV 0x19 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE1() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f64 EMX_BROADCAST_1TO8_64 -IFORM: VBROADCASTSD_ZMMf64_MASKmskw_MEMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5E VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } - -# EMITTING VBROADCASTSD (VBROADCASTSD-512-2) { -ICLASS: VBROADCASTSD +ICLASS: VDIVSS CPL: 3 -CATEGORY: BROADCAST +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x19 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 EMX_BROADCAST_1TO8_64 -IFORM: VBROADCASTSD_ZMMf64_MASKmskw_XMMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x5E VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VDIVSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 } -# EMITTING VBROADCASTSS (VBROADCASTSS-512-1) +# EMITTING VEXPANDPD (VEXPANDPD-512-1) { -ICLASS: VBROADCASTSS +ICLASS: VEXPANDPD CPL: 3 -CATEGORY: BROADCAST +CATEGORY: EXPAND EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 -PATTERN: EVV 0x18 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:f32 EMX_BROADCAST_1TO16_32 -IFORM: VBROADCASTSS_ZMMf32_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f64 +IFORM: VEXPANDPD_ZMMf64_MASKmskw_MEMf64_AVX512 } -# EMITTING VBROADCASTSS (VBROADCASTSS-512-2) +# EMITTING VEXPANDPD (VEXPANDPD-512-2) { -ICLASS: VBROADCASTSS +ICLASS: VEXPANDPD CPL: 3 -CATEGORY: BROADCAST +CATEGORY: EXPAND EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6 -REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x18 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 EMX_BROADCAST_1TO16_32 -IFORM: VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VEXPANDPD_ZMMf64_MASKmskw_ZMMf64_AVX512 } -# EMITTING VCMPPD (VCMPPD-512-1) +# EMITTING VEXPANDPS (VEXPANDPS-512-1) { -ICLASS: VCMPPD +ICLASS: VEXPANDPS CPL: 3 -CATEGORY: AVX512 +CATEGORY: EXPAND EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xC2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 UIMM8() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b -IFORM: VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f32 +IFORM: VEXPANDPS_ZMMf32_MASKmskw_MEMf32_AVX512 } + +# EMITTING VEXPANDPS (VEXPANDPS-512-2) { -ICLASS: VCMPPD +ICLASS: VEXPANDPS CPL: 3 -CATEGORY: AVX512 +CATEGORY: EXPAND EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xC2 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 ZEROING=0 UIMM8() -OPERANDS: REG0=MASK_R():w:mskw:TXT=SAESTR REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b -IFORM: VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VEXPANDPS_ZMMf32_MASKmskw_ZMMf32_AVX512 } + +# EMITTING VEXTRACTF32X4 (VEXTRACTF32X4-512-1) { -ICLASS: VCMPPD +ICLASS: VEXTRACTF32X4 CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xC2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b -IFORM: VCMPPD_MASKmskw_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x19 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +OPERANDS: REG0=XMM_B3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 IMM0:r:b +IFORM: VEXTRACTF32X4_XMMf32_MASKmskw_ZMMf32_IMM8_AVX512 } -# EMITTING VCMPPS (VCMPPS-512-1) +# EMITTING VEXTRACTF32X4 (VEXTRACTF32X4-512-2) { -ICLASS: VCMPPS +ICLASS: VEXTRACTF32X4 CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xC2 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b -IFORM: VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x19 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() +OPERANDS: MEM0:w:dq:f32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32 IMM0:r:b +IFORM: VEXTRACTF32X4_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512 } + +# EMITTING VEXTRACTF64X4 (VEXTRACTF64X4-512-1) { -ICLASS: VCMPPS +ICLASS: VEXTRACTF64X4 CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xC2 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 ZEROING=0 UIMM8() -OPERANDS: REG0=MASK_R():w:mskw:TXT=SAESTR REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b -IFORM: VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() +OPERANDS: REG0=YMM_B3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf64 IMM0:r:b +IFORM: VEXTRACTF64X4_YMMf64_MASKmskw_ZMMf64_IMM8_AVX512 } + +# EMITTING VEXTRACTF64X4 (VEXTRACTF64X4-512-2) { -ICLASS: VCMPPS +ICLASS: VEXTRACTF64X4 CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xC2 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b -IFORM: VCMPPS_MASKmskw_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x1B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE4() +OPERANDS: MEM0:w:qq:f64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf64 IMM0:r:b +IFORM: VEXTRACTF64X4_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512 } -# EMITTING VCMPSD (VCMPSD-128-1) +# EMITTING VEXTRACTI32X4 (VEXTRACTI32X4-512-1) { -ICLASS: VCMPSD +ICLASS: VEXTRACTI32X4 CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0xC2 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 ZEROING=0 UIMM8() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b -IFORM: VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x39 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 IMM0:r:b +IFORM: VEXTRACTI32X4_XMMu32_MASKmskw_ZMMu32_IMM8_AVX512 } + +# EMITTING VEXTRACTI32X4 (VEXTRACTI32X4-512-2) { -ICLASS: VCMPSD +ICLASS: VEXTRACTI32X4 CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0xC2 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 ZEROING=0 UIMM8() -OPERANDS: REG0=MASK_R():w:mskw:TXT=SAESTR REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b -IFORM: VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x39 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() +OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 IMM0:r:b +IFORM: VEXTRACTI32X4_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512 } + +# EMITTING VEXTRACTI64X4 (VEXTRACTI64X4-512-1) { -ICLASS: VCMPSD +ICLASS: VEXTRACTI64X4 CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0xC2 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b -IFORM: VCMPSD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() +OPERANDS: REG0=YMM_B3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 IMM0:r:b +IFORM: VEXTRACTI64X4_YMMu64_MASKmskw_ZMMu64_IMM8_AVX512 } -# EMITTING VCMPSS (VCMPSS-128-1) +# EMITTING VEXTRACTI64X4 (VEXTRACTI64X4-512-2) { -ICLASS: VCMPSS +ICLASS: VEXTRACTI64X4 CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0xC2 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 ZEROING=0 UIMM8() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b -IFORM: VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x3B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE4() +OPERANDS: MEM0:w:qq:u64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 IMM0:r:b +IFORM: VEXTRACTI64X4_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512 } + +# EMITTING VEXTRACTPS (VEXTRACTPS-128-1) { -ICLASS: VCMPSS +ICLASS: VEXTRACTPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0xC2 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 ZEROING=0 UIMM8() -OPERANDS: REG0=MASK_R():w:mskw:TXT=SAESTR REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b -IFORM: VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +PATTERN: EVV 0x17 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=GPR32_B():w:d:f32 REG1=XMM_R3():r:dq:f32 IMM0:r:b +IFORM: VEXTRACTPS_GPR32f32_XMMf32_IMM8_AVX512 } { -ICLASS: VCMPSS +ICLASS: VEXTRACTPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0xC2 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b -IFORM: VCMPSS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 +ATTRIBUTES: DISP8_GPR_WRITER_STORE +PATTERN: EVV 0x17 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_WRITER_STORE() +OPERANDS: MEM0:w:d:f32 REG0=XMM_R3():r:dq:f32 IMM0:r:b +IFORM: VEXTRACTPS_MEMf32_XMMf32_IMM8_AVX512 } -# EMITTING VCOMISD (VCOMISD-128-1) +# EMITTING VFIXUPIMMPD (VFIXUPIMMPD-512-1) { -ICLASS: VCOMISD +ICLASS: VFIXUPIMMPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] -ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x2F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=XMM_R3():r:dq:f64 REG1=XMM_B3():r:dq:f64 -IFORM: VCOMISD_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 } { -ICLASS: VCOMISD +ICLASS: VFIXUPIMMPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] -ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x2F V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=XMM_R3():r:dq:f64:TXT=SAESTR REG1=XMM_B3():r:dq:f64 -IFORM: VCOMISD_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 UIMM8() +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 } { -ICLASS: VCOMISD +ICLASS: VFIXUPIMMPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] -ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_SCALAR -PATTERN: EVV 0x2F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():r:dq:f64 MEM0:r:q:f64 -IFORM: VCOMISD_XMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 } -# EMITTING VCOMISS (VCOMISS-128-1) +# EMITTING VFIXUPIMMPS (VFIXUPIMMPS-512-1) { -ICLASS: VCOMISS +ICLASS: VFIXUPIMMPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] -ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x2F VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=XMM_R3():r:dq:f32 REG1=XMM_B3():r:dq:f32 -IFORM: VCOMISS_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 } { -ICLASS: VCOMISS +ICLASS: VFIXUPIMMPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] -ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x2F VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=XMM_R3():r:dq:f32:TXT=SAESTR REG1=XMM_B3():r:dq:f32 -IFORM: VCOMISS_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 UIMM8() +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 } { -ICLASS: VCOMISS +ICLASS: VFIXUPIMMPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] -ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_SCALAR -PATTERN: EVV 0x2F VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():r:dq:f32 MEM0:r:d:f32 -IFORM: VCOMISS_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 } -# EMITTING VCOMPRESSPD (VCOMPRESSPD-512-1) +# EMITTING VFIXUPIMMSD (VFIXUPIMMSD-128-1) { -ICLASS: VCOMPRESSPD +ICLASS: VFIXUPIMMSD CPL: 3 -CATEGORY: COMPRESS +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() -OPERANDS: MEM0:w:zd:f64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf64 -IFORM: VCOMPRESSPD_MEMf64_MASKmskw_ZMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x55 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 UIMM8() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 } - -# EMITTING VCOMPRESSPD (VCOMPRESSPD-512-2) { -ICLASS: VCOMPRESSPD +ICLASS: VFIXUPIMMSD CPL: 3 -CATEGORY: COMPRESS +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR -OPERANDS: REG0=ZMM_B3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf64 -IFORM: VCOMPRESSPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x55 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 UIMM8() +OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 } - -# EMITTING VCOMPRESSPS (VCOMPRESSPS-512-1) { -ICLASS: VCOMPRESSPS +ICLASS: VFIXUPIMMSD CPL: 3 -CATEGORY: COMPRESS +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() -OPERANDS: MEM0:w:zd:f32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32 -IFORM: VCOMPRESSPS_MEMf32_MASKmskw_ZMMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x55 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b +IFORM: VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 } -# EMITTING VCOMPRESSPS (VCOMPRESSPS-512-2) +# EMITTING VFIXUPIMMSS (VFIXUPIMMSS-128-1) { -ICLASS: VCOMPRESSPS +ICLASS: VFIXUPIMMSS CPL: 3 -CATEGORY: COMPRESS +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=ZMM_B3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 -IFORM: VCOMPRESSPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x55 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 UIMM8() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 } - -# EMITTING VCVTDQ2PD (VCVTDQ2PD-512-1) { -ICLASS: VCVTDQ2PD +ICLASS: VFIXUPIMMSS CPL: 3 -CATEGORY: CONVERT +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E5 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32 -IFORM: VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x55 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8() +OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 } { -ICLASS: VCVTDQ2PD +ICLASS: VFIXUPIMMSS CPL: 3 -CATEGORY: CONVERT +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E5 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED -PATTERN: EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR -IFORM: VCVTDQ2PD_ZMMf64_MASKmskw_MEMi32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x55 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b +IFORM: VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 } -# EMITTING VCVTDQ2PS (VCVTDQ2PS-512-1) +# EMITTING VFMADD132PD (VFMADD132PD-512-1) { -ICLASS: VCVTDQ2PS +ICLASS: VFMADD132PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi32 -IFORM: VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 } { -ICLASS: VCVTDQ2PS +ICLASS: VFMADD132PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi32 -IFORM: VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 } { -ICLASS: VCVTDQ2PS +ICLASS: VFMADD132PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR -IFORM: VCVTDQ2PS_ZMMf32_MASKmskw_MEMi32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 } -# EMITTING VCVTPD2DQ (VCVTPD2DQ-512-1) +# EMITTING VFMADD132PS (VFMADD132PS-512-1) { -ICLASS: VCVTPD2DQ +ICLASS: VFMADD132PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xE6 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 -IFORM: VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 } { -ICLASS: VCVTPD2DQ +ICLASS: VFMADD132PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xE6 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:i32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 -IFORM: VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 } { -ICLASS: VCVTPD2DQ +ICLASS: VFMADD132PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xE6 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 } -# EMITTING VCVTPD2PS (VCVTPD2PS-512-1) +# EMITTING VFMADD132SD (VFMADD132SD-128-1) { -ICLASS: VCVTPD2PS +ICLASS: VFMADD132SD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 -IFORM: VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x99 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VCVTPD2PS +ICLASS: VFMADD132SD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5A V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 -IFORM: VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x99 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VCVTPD2PS +ICLASS: VFMADD132SD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x5A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x99 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VFMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 } -# EMITTING VCVTPD2UDQ (VCVTPD2UDQ-512-1) +# EMITTING VFMADD132SS (VFMADD132SS-128-1) { -ICLASS: VCVTPD2UDQ +ICLASS: VFMADD132SS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 -IFORM: VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x99 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VCVTPD2UDQ +ICLASS: VFMADD132SS CPL: 3 -CATEGORY: CONVERT -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:u32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 -IFORM: VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x99 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VCVTPD2UDQ +ICLASS: VFMADD132SS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x99 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VFMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 } -# EMITTING VCVTPH2PS (VCVTPH2PS-512-1) +# EMITTING VFMADD213PD (VFMADD213PD-512-1) { -ICLASS: VCVTPH2PS +ICLASS: VFMADD213PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E11 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 -IFORM: VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 } { -ICLASS: VCVTPH2PS +ICLASS: VFMADD213PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E11 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 -IFORM: VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 } { -ICLASS: VCVTPH2PS +ICLASS: VFMADD213PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E11 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM -PATTERN: EVV 0x13 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f16 -IFORM: VCVTPH2PS_ZMMf32_MASKmskw_MEMf16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 } -# EMITTING VCVTPS2DQ (VCVTPS2DQ-512-1) +# EMITTING VFMADD213PS (VFMADD213PS-512-1) { -ICLASS: VCVTPS2DQ +ICLASS: VFMADD213PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 -IFORM: VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 } { -ICLASS: VCVTPS2DQ +ICLASS: VFMADD213PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zi32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 -IFORM: VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 } { -ICLASS: VCVTPS2DQ +ICLASS: VFMADD213PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x5B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VCVTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 } -# EMITTING VCVTPS2PD (VCVTPS2PD-512-1) +# EMITTING VFMADD213SD (VFMADD213SD-128-1) { -ICLASS: VCVTPS2PD +ICLASS: VFMADD213SD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 +ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5A VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 -IFORM: VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xA9 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VCVTPS2PD +ICLASS: VFMADD213SD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 +ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5A VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 -IFORM: VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xA9 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VCVTPS2PD +ICLASS: VFMADD213SD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 +ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED -PATTERN: EVV 0x5A VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VCVTPS2PD_ZMMf64_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0xA9 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VFMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 } -# EMITTING VCVTPS2PH (VCVTPS2PH-512-1) +# EMITTING VFMADD213SS (VFMADD213SS-128-1) { -ICLASS: VCVTPS2PH +ICLASS: VFMADD213SS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E11NF +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() -OPERANDS: REG0=YMM_B3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 IMM0:r:b -IFORM: VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xA9 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VCVTPS2PH +ICLASS: VFMADD213SS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E11NF +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8() -OPERANDS: REG0=YMM_B3():w:qq:f16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 IMM0:r:b -IFORM: VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xA9 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } - -# EMITTING VCVTPS2PH (VCVTPS2PH-512-2) { -ICLASS: VCVTPS2PH +ICLASS: VFMADD213SS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E11NF +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM -PATTERN: EVV 0x1D V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_HALFMEM() -OPERANDS: MEM0:w:qq:f16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32 IMM0:r:b -IFORM: VCVTPS2PH_MEMf16_MASKmskw_ZMMf32_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0xA9 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VFMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 } -# EMITTING VCVTPS2UDQ (VCVTPS2UDQ-512-1) +# EMITTING VFMADD231PD (VFMADD231PD-512-1) { -ICLASS: VCVTPS2UDQ +ICLASS: VFMADD231PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 -IFORM: VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 } { -ICLASS: VCVTPS2UDQ +ICLASS: VFMADD231PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zu32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 -IFORM: VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 } { -ICLASS: VCVTPS2UDQ +ICLASS: VFMADD231PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 } -# EMITTING VCVTSD2SI (VCVTSD2SI-128-1) +# EMITTING VFMADD231PS (VFMADD231PS-512-1) { -ICLASS: VCVTSD2SI +ICLASS: VFMADD231PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f64 -IFORM: VCVTSD2SI_GPR32i32_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 } { -ICLASS: VCVTSD2SI +ICLASS: VFMADD231PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=GPR32_R():w:d:i32:TXT=ROUNDC REG1=XMM_B3():r:dq:f64 -IFORM: VCVTSD2SI_GPR32i32_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 } { -ICLASS: VCVTSD2SI +ICLASS: VFMADD231PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q -PATTERN: EVV 0x2D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() -OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:q:f64 -IFORM: VCVTSD2SI_GPR32i32_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 } -# EMITTING VCVTSD2SI (VCVTSD2SI-128-2) +# EMITTING VFMADD231SD (VFMADD231SD-128-1) { -ICLASS: VCVTSD2SI +ICLASS: VFMADD231SD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f64 -IFORM: VCVTSD2SI_GPR64i64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xB9 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VCVTSD2SI +ICLASS: VFMADD231SD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=GPR64_R():w:q:i64:TXT=ROUNDC REG1=XMM_B3():r:dq:f64 -IFORM: VCVTSD2SI_GPR64i64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xB9 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VCVTSD2SI +ICLASS: VFMADD231SD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q -PATTERN: EVV 0x2D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() -OPERANDS: REG0=GPR64_R():w:q:i64 MEM0:r:q:f64 -IFORM: VCVTSD2SI_GPR64i64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0xB9 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VFMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 } -# EMITTING VCVTSD2SS (VCVTSD2SS-128-1) +# EMITTING VFMADD231SS (VFMADD231SS-128-1) { -ICLASS: VCVTSD2SS +ICLASS: VFMADD231SS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xB9 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VCVTSD2SS +ICLASS: VFMADD231SS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 -OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xB9 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VCVTSD2SS +ICLASS: VFMADD231SS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 -IFORM: VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0xB9 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VFMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 } -# EMITTING VCVTSD2USI (VCVTSD2USI-128-1) +# EMITTING VFMADDSUB132PD (VFMADDSUB132PD-512-1) { -ICLASS: VCVTSD2USI +ICLASS: VFMADDSUB132PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f64 -IFORM: VCVTSD2USI_GPR32u32_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 } { -ICLASS: VCVTSD2USI +ICLASS: VFMADDSUB132PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=GPR32_R():w:d:u32:TXT=ROUNDC REG1=XMM_B3():r:dq:f64 -IFORM: VCVTSD2USI_GPR32u32_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 } { -ICLASS: VCVTSD2USI +ICLASS: VFMADDSUB132PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q -PATTERN: EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() -OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:q:f64 -IFORM: VCVTSD2USI_GPR32u32_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 } -# EMITTING VCVTSD2USI (VCVTSD2USI-128-2) +# EMITTING VFMADDSUB132PS (VFMADDSUB132PS-512-1) { -ICLASS: VCVTSD2USI +ICLASS: VFMADDSUB132PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f64 -IFORM: VCVTSD2USI_GPR64u64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 } { -ICLASS: VCVTSD2USI +ICLASS: VFMADDSUB132PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=GPR64_R():w:q:u64:TXT=ROUNDC REG1=XMM_B3():r:dq:f64 -IFORM: VCVTSD2USI_GPR64u64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 } { -ICLASS: VCVTSD2USI +ICLASS: VFMADDSUB132PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q -PATTERN: EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() -OPERANDS: REG0=GPR64_R():w:q:u64 MEM0:r:q:f64 -IFORM: VCVTSD2USI_GPR64u64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 } -# EMITTING VCVTSI2SD (VCVTSI2SD-128-1) +# EMITTING VFMADDSUB213PD (VFMADDSUB213PD-512-1) { -ICLASS: VCVTSI2SD +ICLASS: VFMADDSUB213PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E10NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: SIMD_SCALAR -PATTERN: EVV 0x2A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 ZEROING=0 MASK=0 -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR32_B():r:d:i32 -IFORM: VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 } { -ICLASS: VCVTSI2SD +ICLASS: VFMADDSUB213PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E10NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: SIMD_SCALAR DISP8_GPR_READER -PATTERN: EVV 0x2A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:d:i32 -IFORM: VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 } - -# EMITTING VCVTSI2SD (VCVTSI2SD-128-2) { -ICLASS: VCVTSI2SD +ICLASS: VFMADDSUB213PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x2A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 ZEROING=0 MASK=0 -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR64_B():r:q:i64 -IFORM: VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 } + +# EMITTING VFMADDSUB213PS (VFMADDSUB213PS-512-1) { -ICLASS: VCVTSI2SD +ICLASS: VFMADDSUB213PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x2A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0 -OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=XMM_N3():r:dq:f64 REG2=GPR64_B():r:q:i64 -IFORM: VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 } { -ICLASS: VCVTSI2SD +ICLASS: VFMADDSUB213PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER -PATTERN: EVV 0x2A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:q:i64 -IFORM: VCVTSI2SD_XMMf64_XMMf64_MEMi64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMADDSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 } -# EMITTING VCVTSI2SS (VCVTSI2SS-128-1) +# EMITTING VFMADDSUB231PD (VFMADDSUB231PD-512-1) { -ICLASS: VCVTSI2SS +ICLASS: VFMADDSUB231PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 ZEROING=0 MASK=0 -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:i32 -IFORM: VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 } { -ICLASS: VCVTSI2SS +ICLASS: VFMADDSUB231PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 ZEROING=0 MASK=0 -OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:i32 -IFORM: VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 } { -ICLASS: VCVTSI2SS +ICLASS: VFMADDSUB231PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER -PATTERN: EVV 0x2A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:d:i32 -IFORM: VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 } -# EMITTING VCVTSI2SS (VCVTSI2SS-128-2) +# EMITTING VFMADDSUB231PS (VFMADDSUB231PS-512-1) { -ICLASS: VCVTSI2SS +ICLASS: VFMADDSUB231PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 ZEROING=0 MASK=0 -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR64_B():r:q:i64 -IFORM: VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 } { -ICLASS: VCVTSI2SS +ICLASS: VFMADDSUB231PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0 -OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR64_B():r:q:i64 -IFORM: VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 } { -ICLASS: VCVTSI2SS +ICLASS: VFMADDSUB231PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER -PATTERN: EVV 0x2A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:q:i64 -IFORM: VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 } -# EMITTING VCVTSS2SD (VCVTSS2SD-128-1) +# EMITTING VFMSUB132PD (VFMSUB132PD-512-1) { -ICLASS: VCVTSS2SD +ICLASS: VFMSUB132PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 } { -ICLASS: VCVTSS2SD +ICLASS: VFMSUB132PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 -OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 } { -ICLASS: VCVTSS2SD +ICLASS: VFMSUB132PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 -IFORM: VCVTSS2SD_XMMf64_MASKmskw_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 } -# EMITTING VCVTSS2SI (VCVTSS2SI-128-1) +# EMITTING VFMSUB132PS (VFMSUB132PS-512-1) { -ICLASS: VCVTSS2SI +ICLASS: VFMSUB132PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f32 -IFORM: VCVTSS2SI_GPR32i32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 } { -ICLASS: VCVTSS2SI +ICLASS: VFMSUB132PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=GPR32_R():w:d:i32:TXT=ROUNDC REG1=XMM_B3():r:dq:f32 -IFORM: VCVTSS2SI_GPR32i32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 } { -ICLASS: VCVTSS2SI +ICLASS: VFMSUB132PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_D -PATTERN: EVV 0x2D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() -OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:d:f32 -IFORM: VCVTSS2SI_GPR32i32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 } -# EMITTING VCVTSS2SI (VCVTSS2SI-128-2) +# EMITTING VFMSUB132SD (VFMSUB132SD-128-1) { -ICLASS: VCVTSS2SI +ICLASS: VFMSUB132SD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f32 -IFORM: VCVTSS2SI_GPR64i64_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x9B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VCVTSS2SI +ICLASS: VFMSUB132SD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=GPR64_R():w:q:i64:TXT=ROUNDC REG1=XMM_B3():r:dq:f32 -IFORM: VCVTSS2SI_GPR64i64_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x9B V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VCVTSS2SI +ICLASS: VFMSUB132SD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_D -PATTERN: EVV 0x2D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() -OPERANDS: REG0=GPR64_R():w:q:i64 MEM0:r:d:f32 -IFORM: VCVTSS2SI_GPR64i64_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x9B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VFMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 } -# EMITTING VCVTSS2USI (VCVTSS2USI-128-1) +# EMITTING VFMSUB132SS (VFMSUB132SS-128-1) { -ICLASS: VCVTSS2USI +ICLASS: VFMSUB132SS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f32 -IFORM: VCVTSS2USI_GPR32u32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x9B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VCVTSS2USI +ICLASS: VFMSUB132SS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=GPR32_R():w:d:u32:TXT=ROUNDC REG1=XMM_B3():r:dq:f32 -IFORM: VCVTSS2USI_GPR32u32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x9B V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VCVTSS2USI +ICLASS: VFMSUB132SS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_D -PATTERN: EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() -OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:d:f32 -IFORM: VCVTSS2USI_GPR32u32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x9B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VFMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 } -# EMITTING VCVTSS2USI (VCVTSS2USI-128-2) +# EMITTING VFMSUB213PD (VFMSUB213PD-512-1) { -ICLASS: VCVTSS2USI +ICLASS: VFMSUB213PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f32 -IFORM: VCVTSS2USI_GPR64u64_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 } { -ICLASS: VCVTSS2USI +ICLASS: VFMSUB213PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=GPR64_R():w:q:u64:TXT=ROUNDC REG1=XMM_B3():r:dq:f32 -IFORM: VCVTSS2USI_GPR64u64_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 } { -ICLASS: VCVTSS2USI +ICLASS: VFMSUB213PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_D -PATTERN: EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() -OPERANDS: REG0=GPR64_R():w:q:u64 MEM0:r:d:f32 -IFORM: VCVTSS2USI_GPR64u64_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 } -# EMITTING VCVTTPD2DQ (VCVTTPD2DQ-512-1) +# EMITTING VFMSUB213PS (VFMSUB213PS-512-1) { -ICLASS: VCVTTPD2DQ +ICLASS: VFMSUB213PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xE6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 -IFORM: VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 } { -ICLASS: VCVTTPD2DQ +ICLASS: VFMSUB213PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xE6 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:i32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 -IFORM: VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 } { -ICLASS: VCVTTPD2DQ +ICLASS: VFMSUB213PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xE6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 } -# EMITTING VCVTTPD2UDQ (VCVTTPD2UDQ-512-1) +# EMITTING VFMSUB213SD (VFMSUB213SD-128-1) { -ICLASS: VCVTTPD2UDQ +ICLASS: VFMSUB213SD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 -IFORM: VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xAB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VCVTTPD2UDQ +ICLASS: VFMSUB213SD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:u32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 -IFORM: VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xAB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VCVTTPD2UDQ +ICLASS: VFMSUB213SD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0xAB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VFMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 } -# EMITTING VCVTTPS2DQ (VCVTTPS2DQ-512-1) +# EMITTING VFMSUB213SS (VFMSUB213SS-128-1) { -ICLASS: VCVTTPS2DQ +ICLASS: VFMSUB213SS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 -IFORM: VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xAB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VCVTTPS2DQ +ICLASS: VFMSUB213SS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zi32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 -IFORM: VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xAB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VCVTTPS2DQ +ICLASS: VFMSUB213SS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x5B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VCVTTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0xAB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VFMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 } -# EMITTING VCVTTPS2UDQ (VCVTTPS2UDQ-512-1) +# EMITTING VFMSUB231PD (VFMSUB231PD-512-1) { -ICLASS: VCVTTPS2UDQ +ICLASS: VFMSUB231PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 -IFORM: VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 } { -ICLASS: VCVTTPS2UDQ +ICLASS: VFMSUB231PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zu32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 -IFORM: VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 } { -ICLASS: VCVTTPS2UDQ +ICLASS: VFMSUB231PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 } -# EMITTING VCVTTSD2SI (VCVTTSD2SI-128-1) +# EMITTING VFMSUB231PS (VFMSUB231PS-512-1) { -ICLASS: VCVTTSD2SI +ICLASS: VFMSUB231PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f64 -IFORM: VCVTTSD2SI_GPR32i32_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 } { -ICLASS: VCVTTSD2SI +ICLASS: VFMSUB231PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f64 -IFORM: VCVTTSD2SI_GPR32i32_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 } { -ICLASS: VCVTTSD2SI +ICLASS: VFMSUB231PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q -PATTERN: EVV 0x2C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() -OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:q:f64 -IFORM: VCVTTSD2SI_GPR32i32_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 } -# EMITTING VCVTTSD2SI (VCVTTSD2SI-128-2) +# EMITTING VFMSUB231SD (VFMSUB231SD-128-1) { -ICLASS: VCVTTSD2SI +ICLASS: VFMSUB231SD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f64 -IFORM: VCVTTSD2SI_GPR64i64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xBB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VCVTTSD2SI +ICLASS: VFMSUB231SD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 mode64 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=GPR64_R():w:q:i64:TXT=SAESTR REG1=XMM_B3():r:dq:f64 -IFORM: VCVTTSD2SI_GPR64i64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xBB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VCVTTSD2SI +ICLASS: VFMSUB231SD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q -PATTERN: EVV 0x2C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() -OPERANDS: REG0=GPR64_R():w:q:i64 MEM0:r:q:f64 -IFORM: VCVTTSD2SI_GPR64i64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0xBB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VFMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 } -# EMITTING VCVTTSD2USI (VCVTTSD2USI-128-1) +# EMITTING VFMSUB231SS (VFMSUB231SS-128-1) { -ICLASS: VCVTTSD2USI +ICLASS: VFMSUB231SS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f64 -IFORM: VCVTTSD2USI_GPR32u32_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xBB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VCVTTSD2USI +ICLASS: VFMSUB231SS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f64 -IFORM: VCVTTSD2USI_GPR32u32_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xBB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VCVTTSD2USI +ICLASS: VFMSUB231SS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q -PATTERN: EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() -OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:q:f64 -IFORM: VCVTTSD2USI_GPR32u32_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0xBB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VFMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 } -# EMITTING VCVTTSD2USI (VCVTTSD2USI-128-2) +# EMITTING VFMSUBADD132PD (VFMSUBADD132PD-512-1) { -ICLASS: VCVTTSD2USI +ICLASS: VFMSUBADD132PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f64 -IFORM: VCVTTSD2USI_GPR64u64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 } { -ICLASS: VCVTTSD2USI +ICLASS: VFMSUBADD132PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 mode64 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=GPR64_R():w:q:u64:TXT=SAESTR REG1=XMM_B3():r:dq:f64 -IFORM: VCVTTSD2USI_GPR64u64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 } { -ICLASS: VCVTTSD2USI +ICLASS: VFMSUBADD132PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q -PATTERN: EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() -OPERANDS: REG0=GPR64_R():w:q:u64 MEM0:r:q:f64 -IFORM: VCVTTSD2USI_GPR64u64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 } -# EMITTING VCVTTSS2SI (VCVTTSS2SI-128-1) +# EMITTING VFMSUBADD132PS (VFMSUBADD132PS-512-1) { -ICLASS: VCVTTSS2SI +ICLASS: VFMSUBADD132PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f32 -IFORM: VCVTTSS2SI_GPR32i32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 } { -ICLASS: VCVTTSS2SI +ICLASS: VFMSUBADD132PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f32 -IFORM: VCVTTSS2SI_GPR32i32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 } { -ICLASS: VCVTTSS2SI +ICLASS: VFMSUBADD132PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_D -PATTERN: EVV 0x2C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() -OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:d:f32 -IFORM: VCVTTSS2SI_GPR32i32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 } -# EMITTING VCVTTSS2SI (VCVTTSS2SI-128-2) +# EMITTING VFMSUBADD213PD (VFMSUBADD213PD-512-1) { -ICLASS: VCVTTSS2SI +ICLASS: VFMSUBADD213PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f32 -IFORM: VCVTTSS2SI_GPR64i64_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 } { -ICLASS: VCVTTSS2SI +ICLASS: VFMSUBADD213PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 mode64 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=GPR64_R():w:q:i64:TXT=SAESTR REG1=XMM_B3():r:dq:f32 -IFORM: VCVTTSS2SI_GPR64i64_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 } { -ICLASS: VCVTTSS2SI +ICLASS: VFMSUBADD213PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_D -PATTERN: EVV 0x2C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() -OPERANDS: REG0=GPR64_R():w:q:i64 MEM0:r:d:f32 -IFORM: VCVTTSS2SI_GPR64i64_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 } -# EMITTING VCVTTSS2USI (VCVTTSS2USI-128-1) +# EMITTING VFMSUBADD213PS (VFMSUBADD213PS-512-1) { -ICLASS: VCVTTSS2USI +ICLASS: VFMSUBADD213PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f32 -IFORM: VCVTTSS2USI_GPR32u32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 } { -ICLASS: VCVTTSS2USI +ICLASS: VFMSUBADD213PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f32 -IFORM: VCVTTSS2USI_GPR32u32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 } { -ICLASS: VCVTTSS2USI +ICLASS: VFMSUBADD213PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_D -PATTERN: EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() -OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:d:f32 -IFORM: VCVTTSS2USI_GPR32u32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 } -# EMITTING VCVTTSS2USI (VCVTTSS2USI-128-2) +# EMITTING VFMSUBADD231PD (VFMSUBADD231PD-512-1) { -ICLASS: VCVTTSS2USI +ICLASS: VFMSUBADD231PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f32 -IFORM: VCVTTSS2USI_GPR64u64_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 } { -ICLASS: VCVTTSS2USI +ICLASS: VFMSUBADD231PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 mode64 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=GPR64_R():w:q:u64:TXT=SAESTR REG1=XMM_B3():r:dq:f32 -IFORM: VCVTTSS2USI_GPR64u64_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 } { -ICLASS: VCVTTSS2USI +ICLASS: VFMSUBADD231PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_D -PATTERN: EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() -OPERANDS: REG0=GPR64_R():w:q:u64 MEM0:r:d:f32 -IFORM: VCVTTSS2USI_GPR64u64_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 } -# EMITTING VCVTUDQ2PD (VCVTUDQ2PD-512-1) +# EMITTING VFMSUBADD231PS (VFMSUBADD231PS-512-1) { -ICLASS: VCVTUDQ2PD +ICLASS: VFMSUBADD231PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E5 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 -IFORM: VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 } { -ICLASS: VCVTUDQ2PD +ICLASS: VFMSUBADD231PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E5 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED -PATTERN: EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VCVTUDQ2PD_ZMMf64_MASKmskw_MEMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 } - -# EMITTING VCVTUDQ2PS (VCVTUDQ2PS-512-1) { -ICLASS: VCVTUDQ2PS +ICLASS: VFMSUBADD231PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 -IFORM: VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 } + +# EMITTING VFNMADD132PD (VFNMADD132PD-512-1) { -ICLASS: VCVTUDQ2PS +ICLASS: VFNMADD132PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 -IFORM: VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 } { -ICLASS: VCVTUDQ2PS +ICLASS: VFNMADD132PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VCVTUDQ2PS_ZMMf32_MASKmskw_MEMu32_AVX512 -} - - -# EMITTING VCVTUSI2SD (VCVTUSI2SD-128-1) -{ -ICLASS: VCVTUSI2SD -CPL: 3 -CATEGORY: CONVERT -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E10NF -REAL_OPCODE: Y -ATTRIBUTES: SIMD_SCALAR -PATTERN: EVV 0x7B VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 ZEROING=0 MASK=0 -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR32_B():r:d:u32 -IFORM: VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 } { -ICLASS: VCVTUSI2SD +ICLASS: VFNMADD132PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E10NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: SIMD_SCALAR DISP8_GPR_READER -PATTERN: EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:d:u32 -IFORM: VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 } -# EMITTING VCVTUSI2SD (VCVTUSI2SD-128-2) +# EMITTING VFNMADD132PS (VFNMADD132PS-512-1) { -ICLASS: VCVTUSI2SD +ICLASS: VFNMADD132PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x7B VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 ZEROING=0 MASK=0 -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR64_B():r:q:u64 -IFORM: VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 } { -ICLASS: VCVTUSI2SD +ICLASS: VFNMADD132PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x7B VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0 -OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=XMM_N3():r:dq:f64 REG2=GPR64_B():r:q:u64 -IFORM: VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 } { -ICLASS: VCVTUSI2SD +ICLASS: VFNMADD132PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER -PATTERN: EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:q:u64 -IFORM: VCVTUSI2SD_XMMf64_XMMf64_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 } -# EMITTING VCVTUSI2SS (VCVTUSI2SS-128-1) +# EMITTING VFNMADD132SD (VFNMADD132SD-128-1) { -ICLASS: VCVTUSI2SS +ICLASS: VFNMADD132SD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 ZEROING=0 MASK=0 -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:u32 -IFORM: VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x9D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VCVTUSI2SS +ICLASS: VFNMADD132SD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 ZEROING=0 MASK=0 -OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:u32 -IFORM: VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x9D V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VCVTUSI2SS +ICLASS: VFNMADD132SD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER -PATTERN: EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:d:u32 -IFORM: VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x9D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VFNMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 } -# EMITTING VCVTUSI2SS (VCVTUSI2SS-128-2) +# EMITTING VFNMADD132SS (VFNMADD132SS-128-1) { -ICLASS: VCVTUSI2SS +ICLASS: VFNMADD132SS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 ZEROING=0 MASK=0 -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR64_B():r:q:u64 -IFORM: VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x9D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VCVTUSI2SS +ICLASS: VFNMADD132SS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0 -OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR64_B():r:q:u64 -IFORM: VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x9D V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VCVTUSI2SS +ICLASS: VFNMADD132SS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER -PATTERN: EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:q:u64 -IFORM: VCVTUSI2SS_XMMf32_XMMf32_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x9D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VFNMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 } -# EMITTING VDIVPD (VDIVPD-512-1) +# EMITTING VFNMADD213PD (VFNMADD213PD-512-1) { -ICLASS: VDIVPD +ICLASS: VFNMADD213PD CPL: 3 -CATEGORY: AVX512 +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 } { -ICLASS: VDIVPD +ICLASS: VFNMADD213PD CPL: 3 -CATEGORY: AVX512 +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5E V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 -OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 } { -ICLASS: VDIVPD +ICLASS: VFNMADD213PD CPL: 3 -CATEGORY: AVX512 +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x5E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VDIVPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 } -# EMITTING VDIVPS (VDIVPS-512-1) +# EMITTING VFNMADD213PS (VFNMADD213PS-512-1) { -ICLASS: VDIVPS +ICLASS: VFNMADD213PS CPL: 3 -CATEGORY: AVX512 +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5E VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 } { -ICLASS: VDIVPS +ICLASS: VFNMADD213PS CPL: 3 -CATEGORY: AVX512 +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5E VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 -OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 } { -ICLASS: VDIVPS +ICLASS: VFNMADD213PS CPL: 3 -CATEGORY: AVX512 +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x5E VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VDIVPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 } -# EMITTING VDIVSD (VDIVSD-128-1) +# EMITTING VFNMADD213SD (VFNMADD213SD-128-1) { -ICLASS: VDIVSD +ICLASS: VFNMADD213SD CPL: 3 -CATEGORY: AVX512 +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x5E VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xAD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VDIVSD +ICLASS: VFNMADD213SD CPL: 3 -CATEGORY: AVX512 +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x5E VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 -OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xAD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VDIVSD +ICLASS: VFNMADD213SD CPL: 3 -CATEGORY: AVX512 +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0x5E VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 -IFORM: VDIVSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0xAD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VFNMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 } -# EMITTING VDIVSS (VDIVSS-128-1) +# EMITTING VFNMADD213SS (VFNMADD213SS-128-1) { -ICLASS: VDIVSS +ICLASS: VFNMADD213SS CPL: 3 -CATEGORY: AVX512 +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x5E VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xAD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VDIVSS +ICLASS: VFNMADD213SS CPL: 3 -CATEGORY: AVX512 +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x5E VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 -OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xAD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VDIVSS +ICLASS: VFNMADD213SS CPL: 3 -CATEGORY: AVX512 +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0x5E VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 -IFORM: VDIVSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 -} - - -# EMITTING VEXPANDPD (VEXPANDPD-512-1) -{ -ICLASS: VEXPANDPD -CPL: 3 -CATEGORY: EXPAND -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 -REAL_OPCODE: Y -ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f64 -IFORM: VEXPANDPD_ZMMf64_MASKmskw_MEMf64_AVX512 -} - - -# EMITTING VEXPANDPD (VEXPANDPD-512-2) -{ -ICLASS: VEXPANDPD -CPL: 3 -CATEGORY: EXPAND -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 -REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 -IFORM: VEXPANDPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0xAD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VFNMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 } -# EMITTING VEXPANDPS (VEXPANDPS-512-1) +# EMITTING VFNMADD231PD (VFNMADD231PD-512-1) { -ICLASS: VEXPANDPS +ICLASS: VFNMADD231PD CPL: 3 -CATEGORY: EXPAND +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f32 -IFORM: VEXPANDPS_ZMMf32_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 } - -# EMITTING VEXPANDPS (VEXPANDPS-512-2) { -ICLASS: VEXPANDPS +ICLASS: VFNMADD231PD CPL: 3 -CATEGORY: EXPAND +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 -IFORM: VEXPANDPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 } - -# EMITTING VEXTRACTF32X4 (VEXTRACTF32X4-512-1) { -ICLASS: VEXTRACTF32X4 +ICLASS: VFNMADD231PD CPL: 3 -CATEGORY: AVX512 +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x19 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() -OPERANDS: REG0=XMM_B3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 IMM0:r:b -IFORM: VEXTRACTF32X4_XMMf32_MASKmskw_ZMMf32_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 } -# EMITTING VEXTRACTF32X4 (VEXTRACTF32X4-512-2) +# EMITTING VFNMADD231PS (VFNMADD231PS-512-1) { -ICLASS: VEXTRACTF32X4 +ICLASS: VFNMADD231PS CPL: 3 -CATEGORY: AVX512 +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 -PATTERN: EVV 0x19 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() -OPERANDS: MEM0:w:dq:f32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32 IMM0:r:b -IFORM: VEXTRACTF32X4_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 } - -# EMITTING VEXTRACTF64X4 (VEXTRACTF64X4-512-1) { -ICLASS: VEXTRACTF64X4 +ICLASS: VFNMADD231PS CPL: 3 -CATEGORY: AVX512 +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x1B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() -OPERANDS: REG0=YMM_B3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf64 IMM0:r:b -IFORM: VEXTRACTF64X4_YMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 } - -# EMITTING VEXTRACTF64X4 (VEXTRACTF64X4-512-2) { -ICLASS: VEXTRACTF64X4 +ICLASS: VFNMADD231PS CPL: 3 -CATEGORY: AVX512 +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 -PATTERN: EVV 0x1B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE4() -OPERANDS: MEM0:w:qq:f64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf64 IMM0:r:b -IFORM: VEXTRACTF64X4_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 } -# EMITTING VEXTRACTI32X4 (VEXTRACTI32X4-512-1) +# EMITTING VFNMADD231SD (VFNMADD231SD-128-1) { -ICLASS: VEXTRACTI32X4 +ICLASS: VFNMADD231SD CPL: 3 -CATEGORY: AVX512 +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x39 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() -OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 IMM0:r:b -IFORM: VEXTRACTI32X4_XMMu32_MASKmskw_ZMMu32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xBD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } - -# EMITTING VEXTRACTI32X4 (VEXTRACTI32X4-512-2) { -ICLASS: VEXTRACTI32X4 +ICLASS: VFNMADD231SD CPL: 3 -CATEGORY: AVX512 +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 -PATTERN: EVV 0x39 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() -OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 IMM0:r:b -IFORM: VEXTRACTI32X4_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xBD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } - -# EMITTING VEXTRACTI64X4 (VEXTRACTI64X4-512-1) { -ICLASS: VEXTRACTI64X4 +ICLASS: VFNMADD231SD CPL: 3 -CATEGORY: AVX512 +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x3B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() -OPERANDS: REG0=YMM_B3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 IMM0:r:b -IFORM: VEXTRACTI64X4_YMMu64_MASKmskw_ZMMu64_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0xBD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VFNMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 } -# EMITTING VEXTRACTI64X4 (VEXTRACTI64X4-512-2) +# EMITTING VFNMADD231SS (VFNMADD231SS-128-1) { -ICLASS: VEXTRACTI64X4 +ICLASS: VFNMADD231SS CPL: 3 -CATEGORY: AVX512 +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 -PATTERN: EVV 0x3B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE4() -OPERANDS: MEM0:w:qq:u64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 IMM0:r:b -IFORM: VEXTRACTI64X4_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xBD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } - -# EMITTING VEXTRACTPS (VEXTRACTPS-128-1) { -ICLASS: VEXTRACTPS +ICLASS: VFNMADD231SS CPL: 3 -CATEGORY: AVX512 +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128N -EXCEPTIONS: AVX512-E9NF +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -PATTERN: EVV 0x17 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() -OPERANDS: REG0=GPR32_B():w:d:f32 REG1=XMM_R3():r:dq:f32 IMM0:r:b -IFORM: VEXTRACTPS_GPR32f32_XMMf32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xBD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VEXTRACTPS +ICLASS: VFNMADD231SS CPL: 3 -CATEGORY: AVX512 +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128N -EXCEPTIONS: AVX512-E9NF +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: DISP8_GPR_WRITER_STORE -PATTERN: EVV 0x17 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_WRITER_STORE() -OPERANDS: MEM0:w:d:f32 REG0=XMM_R3():r:dq:f32 IMM0:r:b -IFORM: VEXTRACTPS_MEMf32_XMMf32_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0xBD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VFNMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 } -# EMITTING VFIXUPIMMPD (VFIXUPIMMPD-512-1) +# EMITTING VFNMSUB132PD (VFNMSUB132PD-512-1) { -ICLASS: VFIXUPIMMPD +ICLASS: VFNMSUB132PD CPL: 3 -CATEGORY: AVX512 +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() -OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b -IFORM: VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 } { -ICLASS: VFIXUPIMMPD +ICLASS: VFNMSUB132PD CPL: 3 -CATEGORY: AVX512 +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 UIMM8() -OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b -IFORM: VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 } { -ICLASS: VFIXUPIMMPD +ICLASS: VFNMSUB132PD CPL: 3 -CATEGORY: AVX512 +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b -IFORM: VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 } -# EMITTING VFIXUPIMMPS (VFIXUPIMMPS-512-1) +# EMITTING VFNMSUB132PS (VFNMSUB132PS-512-1) { -ICLASS: VFIXUPIMMPS +ICLASS: VFNMSUB132PS CPL: 3 -CATEGORY: AVX512 +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() -OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b -IFORM: VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 } { -ICLASS: VFIXUPIMMPS +ICLASS: VFNMSUB132PS CPL: 3 -CATEGORY: AVX512 +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 UIMM8() -OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b -IFORM: VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 } { -ICLASS: VFIXUPIMMPS +ICLASS: VFNMSUB132PS CPL: 3 -CATEGORY: AVX512 +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b -IFORM: VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 } -# EMITTING VFIXUPIMMSD (VFIXUPIMMSD-128-1) +# EMITTING VFNMSUB132SD (VFNMSUB132SD-128-1) { -ICLASS: VFIXUPIMMSD +ICLASS: VFNMSUB132SD CPL: 3 -CATEGORY: AVX512 +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x55 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 UIMM8() -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b -IFORM: VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x9F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VFIXUPIMMSD +ICLASS: VFNMSUB132SD CPL: 3 -CATEGORY: AVX512 +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x55 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 UIMM8() -OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b -IFORM: VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x9F V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VFIXUPIMMSD +ICLASS: VFNMSUB132SD CPL: 3 -CATEGORY: AVX512 +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0x55 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b -IFORM: VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x9F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 } -# EMITTING VFIXUPIMMSS (VFIXUPIMMSS-128-1) +# EMITTING VFNMSUB132SS (VFNMSUB132SS-128-1) { -ICLASS: VFIXUPIMMSS +ICLASS: VFNMSUB132SS CPL: 3 -CATEGORY: AVX512 +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x55 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 UIMM8() -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b -IFORM: VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x9F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VFIXUPIMMSS +ICLASS: VFNMSUB132SS CPL: 3 -CATEGORY: AVX512 +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x55 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8() -OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b -IFORM: VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x9F V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VFIXUPIMMSS +ICLASS: VFNMSUB132SS CPL: 3 -CATEGORY: AVX512 +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0x55 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b -IFORM: VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x9F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 } -# EMITTING VFMADD132PD (VFMADD132PD-512-1) +# EMITTING VFNMSUB213PD (VFNMSUB213PD-512-1) { -ICLASS: VFMADD132PD +ICLASS: VFNMSUB213PD CPL: 3 CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +IFORM: VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 } { -ICLASS: VFMADD132PD +ICLASS: VFNMSUB213PD CPL: 3 CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +IFORM: VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 } { -ICLASS: VFMADD132PD +ICLASS: VFNMSUB213PD CPL: 3 CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +IFORM: VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 } -# EMITTING VFMADD132PS (VFMADD132PS-512-1) +# EMITTING VFNMSUB213PS (VFNMSUB213PS-512-1) { -ICLASS: VFMADD132PS +ICLASS: VFNMSUB213PS CPL: 3 CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +IFORM: VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 } { -ICLASS: VFMADD132PS +ICLASS: VFNMSUB213PS CPL: 3 CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +IFORM: VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 } { -ICLASS: VFMADD132PS +ICLASS: VFNMSUB213PS CPL: 3 CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +IFORM: VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 } -# EMITTING VFMADD132SD (VFMADD132SD-128-1) +# EMITTING VFNMSUB213SD (VFNMSUB213SD-128-1) { -ICLASS: VFMADD132SD +ICLASS: VFNMSUB213SD CPL: 3 CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x99 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xAF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +IFORM: VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VFMADD132SD +ICLASS: VFNMSUB213SD CPL: 3 CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x99 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xAF V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +IFORM: VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VFMADD132SD +ICLASS: VFNMSUB213SD CPL: 3 CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0x99 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0xAF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 -IFORM: VFMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +IFORM: VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 } -# EMITTING VFMADD132SS (VFMADD132SS-128-1) +# EMITTING VFNMSUB213SS (VFNMSUB213SS-128-1) { -ICLASS: VFMADD132SS +ICLASS: VFNMSUB213SS CPL: 3 CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x99 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xAF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +IFORM: VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VFMADD132SS +ICLASS: VFNMSUB213SS CPL: 3 CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x99 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xAF V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +IFORM: VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VFMADD132SS +ICLASS: VFNMSUB213SS CPL: 3 CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0x99 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0xAF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 -IFORM: VFMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +IFORM: VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 } -# EMITTING VFMADD213PD (VFMADD213PD-512-1) +# EMITTING VFNMSUB231PD (VFNMSUB231PD-512-1) { -ICLASS: VFMADD213PD +ICLASS: VFNMSUB231PD CPL: 3 CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +IFORM: VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 } { -ICLASS: VFMADD213PD +ICLASS: VFNMSUB231PD CPL: 3 CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +IFORM: VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 } { -ICLASS: VFMADD213PD +ICLASS: VFNMSUB231PD CPL: 3 CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +IFORM: VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 } -# EMITTING VFMADD213PS (VFMADD213PS-512-1) +# EMITTING VFNMSUB231PS (VFNMSUB231PS-512-1) { -ICLASS: VFMADD213PS +ICLASS: VFNMSUB231PS CPL: 3 CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +IFORM: VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 } { -ICLASS: VFMADD213PS +ICLASS: VFNMSUB231PS CPL: 3 CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +IFORM: VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 } { -ICLASS: VFMADD213PS +ICLASS: VFNMSUB231PS CPL: 3 CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +IFORM: VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 } -# EMITTING VFMADD213SD (VFMADD213SD-128-1) +# EMITTING VFNMSUB231SD (VFNMSUB231SD-128-1) { -ICLASS: VFMADD213SD +ICLASS: VFNMSUB231SD CPL: 3 CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0xA9 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xBF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +IFORM: VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VFMADD213SD +ICLASS: VFNMSUB231SD CPL: 3 CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0xA9 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xBF V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +IFORM: VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VFMADD213SD +ICLASS: VFNMSUB231SD CPL: 3 CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0xA9 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0xBF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 -IFORM: VFMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +IFORM: VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 } -# EMITTING VFMADD213SS (VFMADD213SS-128-1) +# EMITTING VFNMSUB231SS (VFNMSUB231SS-128-1) { -ICLASS: VFMADD213SS +ICLASS: VFNMSUB231SS CPL: 3 CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0xA9 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xBF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +IFORM: VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VFMADD213SS +ICLASS: VFNMSUB231SS CPL: 3 CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0xA9 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xBF V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +IFORM: VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VFMADD213SS +ICLASS: VFNMSUB231SS CPL: 3 CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0xA9 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0xBF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 -IFORM: VFMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +IFORM: VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 } -# EMITTING VFMADD231PD (VFMADD231PD-512-1) +# EMITTING VGATHERDPD (VGATHERDPD-512-1) { -ICLASS: VFMADD231PD +ICLASS: VGATHERDPD CPL: 3 -CATEGORY: VFMA +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASKNOT0():rw:mskw MEM0:r:q:f64 +IFORM: VGATHERDPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512 +} + + +# EMITTING VGATHERDPS (VGATHERDPS-512-1) +{ +ICLASS: VGATHERDPS +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASKNOT0():rw:mskw MEM0:r:d:f32 +IFORM: VGATHERDPS_ZMMf32_MASKmskw_MEMf32_AVX512_VL512 +} + + +# EMITTING VGATHERQPD (VGATHERQPD-512-1) +{ +ICLASS: VGATHERQPD +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASKNOT0():rw:mskw MEM0:r:q:f64 +IFORM: VGATHERQPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512 +} + + +# EMITTING VGATHERQPS (VGATHERQPS-512-1) +{ +ICLASS: VGATHERQPS +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASKNOT0():rw:mskw MEM0:r:d:f32 +IFORM: VGATHERQPS_YMMf32_MASKmskw_MEMf32_AVX512_VL512 +} + + +# EMITTING VGETEXPPD (VGETEXPPD-512-1) +{ +ICLASS: VGETEXPPD +CPL: 3 +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512 } { -ICLASS: VFMADD231PD +ICLASS: VGETEXPPD CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 -OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512 } { -ICLASS: VFMADD231PD +ICLASS: VGETEXPPD CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VGETEXPPD_ZMMf64_MASKmskw_MEMf64_AVX512 } -# EMITTING VFMADD231PS (VFMADD231PS-512-1) +# EMITTING VGETEXPPS (VGETEXPPS-512-1) { -ICLASS: VFMADD231PS +ICLASS: VGETEXPPS CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512 } { -ICLASS: VFMADD231PS +ICLASS: VGETEXPPS CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 -OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512 } { -ICLASS: VFMADD231PS +ICLASS: VGETEXPPS CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VGETEXPPS_ZMMf32_MASKmskw_MEMf32_AVX512 } -# EMITTING VFMADD231SD (VFMADD231SD-128-1) +# EMITTING VGETEXPSD (VGETEXPSD-128-1) { -ICLASS: VFMADD231SD +ICLASS: VGETEXPSD CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0xB9 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x43 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VFMADD231SD +ICLASS: VGETEXPSD CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0xB9 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 -OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x43 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VFMADD231SD +ICLASS: VGETEXPSD CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0xB9 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 -IFORM: VFMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x43 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VGETEXPSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 } -# EMITTING VFMADD231SS (VFMADD231SS-128-1) +# EMITTING VGETEXPSS (VGETEXPSS-128-1) { -ICLASS: VFMADD231SS +ICLASS: VGETEXPSS CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0xB9 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x43 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VFMADD231SS +ICLASS: VGETEXPSS CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0xB9 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 -OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x43 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VFMADD231SS +ICLASS: VGETEXPSS CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0xB9 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 -IFORM: VFMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x43 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VGETEXPSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 } -# EMITTING VFMADDSUB132PD (VFMADDSUB132PD-512-1) +# EMITTING VGETMANTPD (VGETMANTPD-512-1) { -ICLASS: VFMADDSUB132PD +ICLASS: VGETMANTPD CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 } { -ICLASS: VFMADDSUB132PD +ICLASS: VGETMANTPD CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 -OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 } { -ICLASS: VFMADDSUB132PD +ICLASS: VGETMANTPD CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VGETMANTPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 } -# EMITTING VFMADDSUB132PS (VFMADDSUB132PS-512-1) +# EMITTING VGETMANTPS (VGETMANTPS-512-1) { -ICLASS: VFMADDSUB132PS +ICLASS: VGETMANTPS CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 } { -ICLASS: VFMADDSUB132PS +ICLASS: VGETMANTPS CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 -OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 } { -ICLASS: VFMADDSUB132PS +ICLASS: VGETMANTPS CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VGETMANTPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 } -# EMITTING VFMADDSUB213PD (VFMADDSUB213PD-512-1) +# EMITTING VGETMANTSD (VGETMANTSD-128-1) { -ICLASS: VFMADDSUB213PD +ICLASS: VGETMANTSD CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x27 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 } { -ICLASS: VFMADDSUB213PD +ICLASS: VGETMANTSD CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 -OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x27 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 } { -ICLASS: VFMADDSUB213PD +ICLASS: VGETMANTSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x27 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b +IFORM: VGETMANTSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VGETMANTSS (VGETMANTSS-128-1) +{ +ICLASS: VGETMANTSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x27 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VGETMANTSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x27 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VGETMANTSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x27 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b +IFORM: VGETMANTSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VINSERTF32X4 (VINSERTF32X4-512-1) +{ +ICLASS: VINSERTF32X4 CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x18 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_XMMf32_IMM8_AVX512 } - -# EMITTING VFMADDSUB213PS (VFMADDSUB213PS-512-1) { -ICLASS: VFMADDSUB213PS +ICLASS: VINSERTF32X4 CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x18 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:dq:f32 IMM0:r:b +IFORM: VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 } + +# EMITTING VINSERTF64X4 (VINSERTF64X4-512-1) { -ICLASS: VFMADDSUB213PS +ICLASS: VINSERTF64X4 CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 -OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=YMM_B3():r:qq:f64 IMM0:r:b +IFORM: VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_YMMf64_IMM8_AVX512 } { -ICLASS: VFMADDSUB213PS +ICLASS: VINSERTF64X4 CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x1A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE4() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:qq:f64 IMM0:r:b +IFORM: VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 } -# EMITTING VFMADDSUB231PD (VFMADDSUB231PD-512-1) +# EMITTING VINSERTI32X4 (VINSERTI32X4-512-1) { -ICLASS: VFMADDSUB231PD +ICLASS: VINSERTI32X4 CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x38 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=XMM_B3():r:dq:u32 IMM0:r:b +IFORM: VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_XMMu32_IMM8_AVX512 } { -ICLASS: VFMADDSUB231PD +ICLASS: VINSERTI32X4 CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 -OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x38 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:dq:u32 IMM0:r:b +IFORM: VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 } + +# EMITTING VINSERTI64X4 (VINSERTI64X4-512-1) { -ICLASS: VFMADDSUB231PD +ICLASS: VINSERTI64X4 CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_YMMu64_IMM8_AVX512 } - -# EMITTING VFMADDSUB231PS (VFMADDSUB231PS-512-1) { -ICLASS: VFMADDSUB231PS +ICLASS: VINSERTI64X4 CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x3A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE4() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:qq:u64 IMM0:r:b +IFORM: VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 } + +# EMITTING VINSERTPS (VINSERTPS-128-1) { -ICLASS: VFMADDSUB231PS +ICLASS: VINSERTPS CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 -OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +PATTERN: EVV 0x21 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VINSERTPS_XMMf32_XMMf32_XMMf32_IMM8_AVX512 } { -ICLASS: VFMADDSUB231PS +ICLASS: VINSERTPS CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +ATTRIBUTES: DISP8_TUPLE1 +PATTERN: EVV 0x21 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE1() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b +IFORM: VINSERTPS_XMMf32_XMMf32_MEMf32_IMM8_AVX512 } -# EMITTING VFMSUB132PD (VFMSUB132PD-512-1) +# EMITTING VMAXPD (VMAXPD-512-1) { -ICLASS: VFMSUB132PD +ICLASS: VMAXPD CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 } { -ICLASS: VFMSUB132PD +ICLASS: VMAXPD CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 -OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5F V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 } { -ICLASS: VFMSUB132PD +ICLASS: VMAXPD CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 } -# EMITTING VFMSUB132PS (VFMSUB132PS-512-1) +# EMITTING VMAXPS (VMAXPS-512-1) { -ICLASS: VFMSUB132PS +ICLASS: VMAXPS CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5F VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 } { -ICLASS: VFMSUB132PS +ICLASS: VMAXPS CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 -OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5F VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 } { -ICLASS: VFMSUB132PS +ICLASS: VMAXPS CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5F VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 } -# EMITTING VFMSUB132SD (VFMSUB132SD-128-1) +# EMITTING VMAXSD (VMAXSD-128-1) { -ICLASS: VFMSUB132SD +ICLASS: VMAXSD CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x9B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VFMSUB132SD +ICLASS: VMAXSD CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x9B V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 -OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5F VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VFMSUB132SD +ICLASS: VMAXSD CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0x9B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 -IFORM: VFMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x5F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 } -# EMITTING VFMSUB132SS (VFMSUB132SS-128-1) +# EMITTING VMAXSS (VMAXSS-128-1) { -ICLASS: VFMSUB132SS +ICLASS: VMAXSS CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x9B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VFMSUB132SS +ICLASS: VMAXSS CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x9B V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 -OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5F VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VFMSUB132SS +ICLASS: VMAXSS CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0x9B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 -IFORM: VFMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x5F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 } -# EMITTING VFMSUB213PD (VFMSUB213PD-512-1) +# EMITTING VMINPD (VMINPD-512-1) { -ICLASS: VFMSUB213PD +ICLASS: VMINPD CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 } { -ICLASS: VFMSUB213PD +ICLASS: VMINPD CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 -OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5D V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 } { -ICLASS: VFMSUB213PD +ICLASS: VMINPD CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VMINPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 } -# EMITTING VFMSUB213PS (VFMSUB213PS-512-1) +# EMITTING VMINPS (VMINPS-512-1) { -ICLASS: VFMSUB213PS +ICLASS: VMINPS CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5D VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 } { -ICLASS: VFMSUB213PS +ICLASS: VMINPS CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 -OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5D VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 } { -ICLASS: VFMSUB213PS +ICLASS: VMINPS CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5D VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VMINPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 } -# EMITTING VFMSUB213SD (VFMSUB213SD-128-1) +# EMITTING VMINSD (VMINSD-128-1) { -ICLASS: VFMSUB213SD +ICLASS: VMINSD CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0xAB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VFMSUB213SD +ICLASS: VMINSD CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0xAB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 -OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VFMSUB213SD +ICLASS: VMINSD CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0xAB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 -IFORM: VFMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x5D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VMINSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 } -# EMITTING VFMSUB213SS (VFMSUB213SS-128-1) +# EMITTING VMINSS (VMINSS-128-1) { -ICLASS: VFMSUB213SS +ICLASS: VMINSS CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0xAB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VMINSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VMINSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x5D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VMINSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VMOVAPD (VMOVAPD-512-1) +{ +ICLASS: VMOVAPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x28 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VMOVAPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x28 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f64 +IFORM: VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VMOVAPD (VMOVAPD-512-2) +{ +ICLASS: VMOVAPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x29 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf64 +IFORM: VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +} + + +# EMITTING VMOVAPD (VMOVAPD-512-3) +{ +ICLASS: VMOVAPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x29 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:zd:f64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf64 +IFORM: VMOVAPD_MEMf64_MASKmskw_ZMMf64_AVX512 +} + + +# EMITTING VMOVAPS (VMOVAPS-512-1) +{ +ICLASS: VMOVAPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x28 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512 } { -ICLASS: VFMSUB213SS +ICLASS: VMOVAPS CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0xAB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 -OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x28 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f32 +IFORM: VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512 } + +# EMITTING VMOVAPS (VMOVAPS-512-2) { -ICLASS: VFMSUB213SS +ICLASS: VMOVAPS CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0xAB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 -IFORM: VFMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x29 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 +IFORM: VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512 } -# EMITTING VFMSUB231PD (VFMSUB231PD-512-1) +# EMITTING VMOVAPS (VMOVAPS-512-3) { -ICLASS: VFMSUB231PD +ICLASS: VMOVAPS CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E1 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x29 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:zd:f32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32 +IFORM: VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512 } + +# EMITTING VMOVD (VMOVD-128-1) { -ICLASS: VFMSUB231PD +ICLASS: VMOVD CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 -OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +PATTERN: EVV 0x6E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=GPR32_B():r:d:u32 +IFORM: VMOVD_XMMu32_GPR32u32_AVX512 +PATTERN: EVV 0x6E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=GPR32_B():r:d:u32 +IFORM: VMOVD_XMMu32_GPR32u32_AVX512 } { -ICLASS: VFMSUB231PD +ICLASS: VMOVD CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +ATTRIBUTES: DISP8_GPR_READER +PATTERN: EVV 0x6E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:u32 MEM0:r:d:u32 +IFORM: VMOVD_XMMu32_MEMu32_AVX512 +PATTERN: EVV 0x6E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:u32 MEM0:r:d:u32 +IFORM: VMOVD_XMMu32_MEMu32_AVX512 } -# EMITTING VFMSUB231PS (VFMSUB231PS-512-1) +# EMITTING VMOVD (VMOVD-128-2) { -ICLASS: VFMSUB231PS +ICLASS: VMOVD CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +PATTERN: EVV 0x7E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_B():w:d:u32 REG1=XMM_R3():r:dq:u32 +IFORM: VMOVD_GPR32u32_XMMu32_AVX512 +PATTERN: EVV 0x7E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_B():w:d:u32 REG1=XMM_R3():r:dq:u32 +IFORM: VMOVD_GPR32u32_XMMu32_AVX512 } { -ICLASS: VFMSUB231PS +ICLASS: VMOVD CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 -OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +ATTRIBUTES: DISP8_GPR_WRITER_STORE +PATTERN: EVV 0x7E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_STORE() +OPERANDS: MEM0:w:d:u32 REG0=XMM_R3():r:dq:u32 +IFORM: VMOVD_MEMu32_XMMu32_AVX512 +PATTERN: EVV 0x7E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_STORE() +OPERANDS: MEM0:w:d:u32 REG0=XMM_R3():r:dq:u32 +IFORM: VMOVD_MEMu32_XMMu32_AVX512 } + +# EMITTING VMOVDDUP (VMOVDDUP-512-1) { -ICLASS: VFMSUB231PS +ICLASS: VMOVDDUP CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E5NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x12 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VMOVDDUP_ZMMf64_MASKmskw_ZMMf64_AVX512 } - -# EMITTING VFMSUB231SD (VFMSUB231SD-128-1) { -ICLASS: VFMSUB231SD +ICLASS: VMOVDDUP CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0xBB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_MOVDDUP +PATTERN: EVV 0x12 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_MOVDDUP() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f64 +IFORM: VMOVDDUP_ZMMf64_MASKmskw_MEMf64_AVX512 } + +# EMITTING VMOVDQA32 (VMOVDQA32-512-1) { -ICLASS: VFMSUB231SD +ICLASS: VMOVDQA32 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0xBB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 -OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 +IFORM: VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512 } { -ICLASS: VFMSUB231SD +ICLASS: VMOVDQA32 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0xBB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 -IFORM: VFMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u32 +IFORM: VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512 } -# EMITTING VFMSUB231SS (VFMSUB231SS-128-1) +# EMITTING VMOVDQA32 (VMOVDQA32-512-2) { -ICLASS: VFMSUB231SS +ICLASS: VMOVDQA32 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0xBB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 +IFORM: VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512 } + +# EMITTING VMOVDQA32 (VMOVDQA32-512-3) { -ICLASS: VFMSUB231SS +ICLASS: VMOVDQA32 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0xBB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 -OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:zd:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 +IFORM: VMOVDQA32_MEMu32_MASKmskw_ZMMu32_AVX512 } + +# EMITTING VMOVDQA64 (VMOVDQA64-512-1) { -ICLASS: VFMSUB231SS +ICLASS: VMOVDQA64 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0xBB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 -IFORM: VFMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512 } - -# EMITTING VFMSUBADD132PD (VFMSUBADD132PD-512-1) { -ICLASS: VFMSUBADD132PD +ICLASS: VMOVDQA64 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E1 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u64 +IFORM: VMOVDQA64_ZMMu64_MASKmskw_MEMu64_AVX512 } + +# EMITTING VMOVDQA64 (VMOVDQA64-512-2) { -ICLASS: VFMSUBADD132PD +ICLASS: VMOVDQA64 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E1 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 -OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 +IFORM: VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512 } + +# EMITTING VMOVDQA64 (VMOVDQA64-512-3) { -ICLASS: VFMSUBADD132PD +ICLASS: VMOVDQA64 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E1 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:zd:u64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 +IFORM: VMOVDQA64_MEMu64_MASKmskw_ZMMu64_AVX512 } -# EMITTING VFMSUBADD132PS (VFMSUBADD132PS-512-1) +# EMITTING VMOVDQU32 (VMOVDQU32-512-1) { -ICLASS: VFMSUBADD132PS +ICLASS: VMOVDQU32 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 +IFORM: VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512 } { -ICLASS: VFMSUBADD132PS +ICLASS: VMOVDQU32 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 -OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u32 +IFORM: VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512 } + +# EMITTING VMOVDQU32 (VMOVDQU32-512-2) { -ICLASS: VFMSUBADD132PS +ICLASS: VMOVDQU32 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 +IFORM: VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512 } -# EMITTING VFMSUBADD213PD (VFMSUBADD213PD-512-1) +# EMITTING VMOVDQU32 (VMOVDQU32-512-3) { -ICLASS: VFMSUBADD213PD +ICLASS: VMOVDQU32 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:zd:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 +IFORM: VMOVDQU32_MEMu32_MASKmskw_ZMMu32_AVX512 } + +# EMITTING VMOVDQU64 (VMOVDQU64-512-1) { -ICLASS: VFMSUBADD213PD +ICLASS: VMOVDQU64 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 -OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512 } { -ICLASS: VFMSUBADD213PD +ICLASS: VMOVDQU64 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u64 +IFORM: VMOVDQU64_ZMMu64_MASKmskw_MEMu64_AVX512 } -# EMITTING VFMSUBADD213PS (VFMSUBADD213PS-512-1) +# EMITTING VMOVDQU64 (VMOVDQU64-512-2) { -ICLASS: VFMSUBADD213PS +ICLASS: VMOVDQU64 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 +IFORM: VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512 } + +# EMITTING VMOVDQU64 (VMOVDQU64-512-3) { -ICLASS: VFMSUBADD213PS +ICLASS: VMOVDQU64 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 -OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:zd:u64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 +IFORM: VMOVDQU64_MEMu64_MASKmskw_ZMMu64_AVX512 } + +# EMITTING VMOVHLPS (VMOVHLPS-128-1) { -ICLASS: VFMSUBADD213PS +ICLASS: VMOVHLPS CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E7NM128 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +PATTERN: EVV 0x12 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=XMM_B3():r:dq:f32 +IFORM: VMOVHLPS_XMMf32_XMMf32_XMMf32_AVX512 } -# EMITTING VFMSUBADD231PD (VFMSUBADD231PD-512-1) +# EMITTING VMOVHPD (VMOVHPD-128-1) { -ICLASS: VFMSUBADD231PD +ICLASS: VMOVHPD CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +ATTRIBUTES: DISP8_SCALAR +PATTERN: EVV 0x16 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:q:f64 MEM0:r:q:f64 +IFORM: VMOVHPD_XMMf64_XMMf64_MEMf64_AVX512 } + +# EMITTING VMOVHPD (VMOVHPD-128-2) { -ICLASS: VFMSUBADD231PD +ICLASS: VMOVHPD CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 -OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +ATTRIBUTES: DISP8_SCALAR +PATTERN: EVV 0x17 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: MEM0:w:q:f64 REG0=XMM_R3():r:dq:f64 +IFORM: VMOVHPD_MEMf64_XMMf64_AVX512 } + +# EMITTING VMOVHPS (VMOVHPS-128-1) { -ICLASS: VFMSUBADD231PD +ICLASS: VMOVHPS CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +ATTRIBUTES: DISP8_TUPLE2 +PATTERN: EVV 0x16 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_TUPLE2() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:q:f32 MEM0:r:q:f32 +IFORM: VMOVHPS_XMMf32_XMMf32_MEMf32_AVX512 } -# EMITTING VFMSUBADD231PS (VFMSUBADD231PS-512-1) +# EMITTING VMOVHPS (VMOVHPS-128-2) { -ICLASS: VFMSUBADD231PS +ICLASS: VMOVHPS CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +ATTRIBUTES: DISP8_TUPLE2 +PATTERN: EVV 0x17 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_TUPLE2() +OPERANDS: MEM0:w:q:f32 REG0=XMM_R3():r:dq:f32 +IFORM: VMOVHPS_MEMf32_XMMf32_AVX512 } + +# EMITTING VMOVLHPS (VMOVLHPS-128-1) { -ICLASS: VFMSUBADD231PS +ICLASS: VMOVLHPS CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 -REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 -OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E7NM128 +REAL_OPCODE: Y +PATTERN: EVV 0x16 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:q:f32 REG2=XMM_B3():r:q:f32 +IFORM: VMOVLHPS_XMMf32_XMMf32_XMMf32_AVX512 } + +# EMITTING VMOVLPD (VMOVLPD-128-1) { -ICLASS: VFMSUBADD231PS +ICLASS: VMOVLPD CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +ATTRIBUTES: DISP8_SCALAR +PATTERN: EVV 0x12 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VMOVLPD_XMMf64_XMMf64_MEMf64_AVX512 } -# EMITTING VFNMADD132PD (VFNMADD132PD-512-1) +# EMITTING VMOVLPD (VMOVLPD-128-2) { -ICLASS: VFNMADD132PD +ICLASS: VMOVLPD CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +ATTRIBUTES: DISP8_SCALAR +PATTERN: EVV 0x13 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: MEM0:w:q:f64 REG0=XMM_R3():r:q:f64 +IFORM: VMOVLPD_MEMf64_XMMf64_AVX512 } + +# EMITTING VMOVLPS (VMOVLPS-128-1) { -ICLASS: VFNMADD132PD +ICLASS: VMOVLPS CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 -OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +ATTRIBUTES: DISP8_TUPLE2 +PATTERN: EVV 0x12 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_TUPLE2() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:q:f32 +IFORM: VMOVLPS_XMMf32_XMMf32_MEMf32_AVX512 } + +# EMITTING VMOVLPS (VMOVLPS-128-2) { -ICLASS: VFNMADD132PD +ICLASS: VMOVLPS CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +ATTRIBUTES: DISP8_TUPLE2 +PATTERN: EVV 0x13 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_TUPLE2() +OPERANDS: MEM0:w:q:f32 REG0=XMM_R3():r:q:f32 +IFORM: VMOVLPS_MEMf32_XMMf32_AVX512 } -# EMITTING VFNMADD132PS (VFNMADD132PS-512-1) +# EMITTING VMOVNTDQ (VMOVNTDQ-512-1) { -ICLASS: VFNMADD132PS +ICLASS: VMOVNTDQ CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E1NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0xE7 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:zd:u32 REG0=ZMM_R3():r:zu32 +IFORM: VMOVNTDQ_MEMu32_ZMMu32_AVX512 } + +# EMITTING VMOVNTDQA (VMOVNTDQA-512-1) { -ICLASS: VFNMADD132PS +ICLASS: VMOVNTDQA CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E1NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 -OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x2A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu32 MEM0:r:zd:u32 +IFORM: VMOVNTDQA_ZMMu32_MEMu32_AVX512 } + +# EMITTING VMOVNTPD (VMOVNTPD-512-1) { -ICLASS: VFNMADD132PS +ICLASS: VMOVNTPD CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E1NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x2B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:zd:f64 REG0=ZMM_R3():r:zf64 +IFORM: VMOVNTPD_MEMf64_ZMMf64_AVX512 } -# EMITTING VFNMADD132SD (VFNMADD132SD-128-1) +# EMITTING VMOVNTPS (VMOVNTPS-512-1) { -ICLASS: VFNMADD132SD +ICLASS: VMOVNTPS CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x9D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x2B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:zd:f32 REG0=ZMM_R3():r:zf32 +IFORM: VMOVNTPS_MEMf32_ZMMf32_AVX512 } + +# EMITTING VMOVQ (VMOVQ-128-1) { -ICLASS: VFNMADD132SD +ICLASS: VMOVQ CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x9D V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 -OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +PATTERN: EVV 0x6E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=GPR64_B():r:q:u64 +IFORM: VMOVQ_XMMu64_GPR64u64_AVX512 } { -ICLASS: VFNMADD132SD +ICLASS: VMOVQ CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0x9D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 -IFORM: VFNMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +ATTRIBUTES: DISP8_GPR_READER +PATTERN: EVV 0x6E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:u64 MEM0:r:q:u64 +IFORM: VMOVQ_XMMu64_MEMu64_AVX512 } -# EMITTING VFNMADD132SS (VFNMADD132SS-128-1) +# EMITTING VMOVQ (VMOVQ-128-2) { -ICLASS: VFNMADD132SS +ICLASS: VMOVQ CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x9D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +PATTERN: EVV 0x7E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR64_B():w:q:u64 REG1=XMM_R3():r:dq:u64 +IFORM: VMOVQ_GPR64u64_XMMu64_AVX512 } { -ICLASS: VFNMADD132SS +ICLASS: VMOVQ CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x9D V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 -OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: DISP8_GPR_WRITER_STORE +PATTERN: EVV 0x7E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_STORE() +OPERANDS: MEM0:w:q:u64 REG0=XMM_R3():r:dq:u64 +IFORM: VMOVQ_MEMu64_XMMu64_AVX512 } + +# EMITTING VMOVQ (VMOVQ-128-3) { -ICLASS: VFNMADD132SS +ICLASS: VMOVQ CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0x9D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 -IFORM: VFNMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +PATTERN: EVV 0x7E VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=XMM_B3():r:dq:u64 +IFORM: VMOVQ_XMMu64_XMMu64_AVX512 } - -# EMITTING VFNMADD213PD (VFNMADD213PD-512-1) { -ICLASS: VFNMADD213PD +ICLASS: VMOVQ CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +ATTRIBUTES: DISP8_SCALAR +PATTERN: EVV 0x7E VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:u64 MEM0:r:q:u64 +IFORM: VMOVQ_XMMu64_MEMu64_AVX512 } + +# EMITTING VMOVQ (VMOVQ-128-4) { -ICLASS: VFNMADD213PD +ICLASS: VMOVQ CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 -OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +PATTERN: EVV 0xD6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_B3():w:dq:u64 REG1=XMM_R3():r:dq:u64 +IFORM: VMOVQ_XMMu64_XMMu64_AVX512 } { -ICLASS: VFNMADD213PD +ICLASS: VMOVQ CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +ATTRIBUTES: DISP8_SCALAR +PATTERN: EVV 0xD6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: MEM0:w:q:u64 REG0=XMM_R3():r:dq:u64 +IFORM: VMOVQ_MEMu64_XMMu64_AVX512 } -# EMITTING VFNMADD213PS (VFNMADD213PS-512-1) +# EMITTING VMOVSD (VMOVSD-128-1) { -ICLASS: VFNMADD213PS +ICLASS: VMOVSD CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x10 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f64 +IFORM: VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512 } + +# EMITTING VMOVSD (VMOVSD-128-2) { -ICLASS: VFNMADD213PS +ICLASS: VMOVSD CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 -OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x11 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: MEM0:w:q:f64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f64 +IFORM: VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512 } + +# EMITTING VMOVSD (VMOVSD-128-3) { -ICLASS: VFNMADD213PS +ICLASS: VMOVSD CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX SIMD_SCALAR +PATTERN: EVV 0x10 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } -# EMITTING VFNMADD213SD (VFNMADD213SD-128-1) +# EMITTING VMOVSD (VMOVSD-128-4) { -ICLASS: VFNMADD213SD +ICLASS: VMOVSD CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0xAD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX SIMD_SCALAR +PATTERN: EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_R3():r:dq:f64 +IFORM: VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } + +# EMITTING VMOVSHDUP (VMOVSHDUP-512-1) { -ICLASS: VFNMADD213SD +ICLASS: VMOVSHDUP CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0xAD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 -OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x16 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VMOVSHDUP_ZMMf32_MASKmskw_ZMMf32_AVX512 } { -ICLASS: VFNMADD213SD +ICLASS: VMOVSHDUP CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0xAD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 -IFORM: VFNMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x16 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f32 +IFORM: VMOVSHDUP_ZMMf32_MASKmskw_MEMf32_AVX512 } -# EMITTING VFNMADD213SS (VFNMADD213SS-128-1) +# EMITTING VMOVSLDUP (VMOVSLDUP-512-1) { -ICLASS: VFNMADD213SS +ICLASS: VMOVSLDUP CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0xAD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x12 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VMOVSLDUP_ZMMf32_MASKmskw_ZMMf32_AVX512 } { -ICLASS: VFNMADD213SS +ICLASS: VMOVSLDUP CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0xAD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 -OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x12 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f32 +IFORM: VMOVSLDUP_ZMMf32_MASKmskw_MEMf32_AVX512 } + +# EMITTING VMOVSS (VMOVSS-128-1) { -ICLASS: VFNMADD213SS +ICLASS: VMOVSS CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0xAD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 -IFORM: VFNMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x10 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:f32 +IFORM: VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512 } -# EMITTING VFNMADD231PD (VFNMADD231PD-512-1) +# EMITTING VMOVSS (VMOVSS-128-2) { -ICLASS: VFNMADD231PD +ICLASS: VMOVSS CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x11 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: MEM0:w:d:f32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f32 +IFORM: VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512 } + +# EMITTING VMOVSS (VMOVSS-128-3) { -ICLASS: VFNMADD231PD +ICLASS: VMOVSS CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 -OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX SIMD_SCALAR +PATTERN: EVV 0x10 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } + +# EMITTING VMOVSS (VMOVSS-128-4) { -ICLASS: VFNMADD231PD +ICLASS: VMOVSS CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX SIMD_SCALAR +PATTERN: EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_B3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_R3():r:dq:f32 +IFORM: VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } -# EMITTING VFNMADD231PS (VFNMADD231PS-512-1) +# EMITTING VMOVUPD (VMOVUPD-512-1) { -ICLASS: VFNMADD231PS +ICLASS: VMOVUPD CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x10 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512 } { -ICLASS: VFNMADD231PS +ICLASS: VMOVUPD CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 -OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x10 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f64 +IFORM: VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512 } + +# EMITTING VMOVUPD (VMOVUPD-512-2) { -ICLASS: VFNMADD231PS +ICLASS: VMOVUPD CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x11 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf64 +IFORM: VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512 } -# EMITTING VFNMADD231SD (VFNMADD231SD-128-1) +# EMITTING VMOVUPD (VMOVUPD-512-3) { -ICLASS: VFNMADD231SD +ICLASS: VMOVUPD CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0xBD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x11 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:zd:f64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf64 +IFORM: VMOVUPD_MEMf64_MASKmskw_ZMMf64_AVX512 } + +# EMITTING VMOVUPS (VMOVUPS-512-1) { -ICLASS: VFNMADD231SD +ICLASS: VMOVUPS CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0xBD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 -OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x10 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512 } { -ICLASS: VFNMADD231SD +ICLASS: VMOVUPS CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0xBD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 -IFORM: VFNMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x10 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f32 +IFORM: VMOVUPS_ZMMf32_MASKmskw_MEMf32_AVX512 } -# EMITTING VFNMADD231SS (VFNMADD231SS-128-1) +# EMITTING VMOVUPS (VMOVUPS-512-2) { -ICLASS: VFNMADD231SS +ICLASS: VMOVUPS CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0xBD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x11 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 +IFORM: VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512 } -{ -ICLASS: VFNMADD231SS -CPL: 3 -CATEGORY: VFMA -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 -REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0xBD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 -OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 -} +# EMITTING VMOVUPS (VMOVUPS-512-3) { -ICLASS: VFNMADD231SS +ICLASS: VMOVUPS CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0xBD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 -IFORM: VFNMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x11 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:zd:f32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32 +IFORM: VMOVUPS_MEMf32_MASKmskw_ZMMf32_AVX512 } -# EMITTING VFNMSUB132PD (VFNMSUB132PD-512-1) +# EMITTING VMULPD (VMULPD-512-1) { -ICLASS: VFNMSUB132PD +ICLASS: VMULPD CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x59 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 } { -ICLASS: VFNMSUB132PD +ICLASS: VMULPD CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 -OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x59 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 } { -ICLASS: VFNMSUB132PD +ICLASS: VMULPD CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x59 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VMULPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 } -# EMITTING VFNMSUB132PS (VFNMSUB132PS-512-1) +# EMITTING VMULPS (VMULPS-512-1) { -ICLASS: VFNMSUB132PS +ICLASS: VMULPS CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x59 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 } { -ICLASS: VFNMSUB132PS +ICLASS: VMULPS CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 -OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x59 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 } { -ICLASS: VFNMSUB132PS +ICLASS: VMULPS CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x59 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VMULPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 } -# EMITTING VFNMSUB132SD (VFNMSUB132SD-128-1) +# EMITTING VMULSD (VMULSD-128-1) { -ICLASS: VFNMSUB132SD +ICLASS: VMULSD CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x9F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x59 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VFNMSUB132SD +ICLASS: VMULSD CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x9F V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 -OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x59 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VFNMSUB132SD +ICLASS: VMULSD CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0x9F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 -IFORM: VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x59 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VMULSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 } -# EMITTING VFNMSUB132SS (VFNMSUB132SS-128-1) +# EMITTING VMULSS (VMULSS-128-1) { -ICLASS: VFNMSUB132SS +ICLASS: VMULSS CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x9F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x59 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VFNMSUB132SS +ICLASS: VMULSS CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x9F V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 -OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x59 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VFNMSUB132SS +ICLASS: VMULSS CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0x9F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 -IFORM: VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x59 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VMULSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 } -# EMITTING VFNMSUB213PD (VFNMSUB213PD-512-1) -{ -ICLASS: VFNMSUB213PD -CPL: 3 -CATEGORY: VFMA -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 -REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 -} - +# EMITTING VPABSD (VPABSD-512-1) { -ICLASS: VFNMSUB213PD +ICLASS: VPABSD CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 -OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi32 +IFORM: VPABSD_ZMMi32_MASKmskw_ZMMi32_AVX512 } { -ICLASS: VFNMSUB213PD +ICLASS: VPABSD CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPABSD_ZMMi32_MASKmskw_MEMi32_AVX512 } -# EMITTING VFNMSUB213PS (VFNMSUB213PS-512-1) -{ -ICLASS: VFNMSUB213PS -CPL: 3 -CATEGORY: VFMA -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 -REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 -} - +# EMITTING VPABSQ (VPABSQ-512-1) { -ICLASS: VFNMSUB213PS +ICLASS: VPABSQ CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 -OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi64 +IFORM: VPABSQ_ZMMi64_MASKmskw_ZMMi64_AVX512 } { -ICLASS: VFNMSUB213PS +ICLASS: VPABSQ CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i64:TXT=BCASTSTR +IFORM: VPABSQ_ZMMi64_MASKmskw_MEMi64_AVX512 } -# EMITTING VFNMSUB213SD (VFNMSUB213SD-128-1) -{ -ICLASS: VFNMSUB213SD -CPL: 3 -CATEGORY: VFMA -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 -REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0xAF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 -} - +# EMITTING VPADDD (VPADDD-512-1) { -ICLASS: VFNMSUB213SD +ICLASS: VPADDD CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0xAF V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 -OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xFE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPADDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 } { -ICLASS: VFNMSUB213SD +ICLASS: VPADDD CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0xAF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 -IFORM: VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xFE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPADDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 } -# EMITTING VFNMSUB213SS (VFNMSUB213SS-128-1) -{ -ICLASS: VFNMSUB213SS -CPL: 3 -CATEGORY: VFMA -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 -REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0xAF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 -} - +# EMITTING VPADDQ (VPADDQ-512-1) { -ICLASS: VFNMSUB213SS +ICLASS: VPADDQ CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0xAF V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 -OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPADDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 } { -ICLASS: VFNMSUB213SS +ICLASS: VPADDQ CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0xAF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 -IFORM: VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xD4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPADDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 } -# EMITTING VFNMSUB231PD (VFNMSUB231PD-512-1) +# EMITTING VPANDD (VPANDD-512-1) { -ICLASS: VFNMSUB231PD +ICLASS: VPANDD CPL: 3 -CATEGORY: VFMA +CATEGORY: LOGICAL EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPANDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 } { -ICLASS: VFNMSUB231PD +ICLASS: VPANDD CPL: 3 -CATEGORY: VFMA +CATEGORY: LOGICAL EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 -OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPANDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 } + +# EMITTING VPANDND (VPANDND-512-1) { -ICLASS: VFNMSUB231PD +ICLASS: VPANDND CPL: 3 -CATEGORY: VFMA +CATEGORY: LOGICAL EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPANDND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 } - -# EMITTING VFNMSUB231PS (VFNMSUB231PS-512-1) { -ICLASS: VFNMSUB231PS +ICLASS: VPANDND CPL: 3 -CATEGORY: VFMA +CATEGORY: LOGICAL EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPANDND_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 } + +# EMITTING VPANDNQ (VPANDNQ-512-1) { -ICLASS: VFNMSUB231PS +ICLASS: VPANDNQ CPL: 3 -CATEGORY: VFMA +CATEGORY: LOGICAL EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 -OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPANDNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 } { -ICLASS: VFNMSUB231PS +ICLASS: VPANDNQ CPL: 3 -CATEGORY: VFMA +CATEGORY: LOGICAL EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPANDNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 } -# EMITTING VFNMSUB231SD (VFNMSUB231SD-128-1) +# EMITTING VPANDQ (VPANDQ-512-1) { -ICLASS: VFNMSUB231SD +ICLASS: VPANDQ CPL: 3 -CATEGORY: VFMA +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0xBF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPANDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 } { -ICLASS: VFNMSUB231SD +ICLASS: VPANDQ CPL: 3 -CATEGORY: VFMA +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0xBF V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 -OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPANDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 } + +# EMITTING VPBLENDMD (VPBLENDMD-512-1) { -ICLASS: VFNMSUB231SD +ICLASS: VPBLENDMD CPL: 3 -CATEGORY: VFMA +CATEGORY: BLEND EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0xBF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 -IFORM: VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 } - -# EMITTING VFNMSUB231SS (VFNMSUB231SS-128-1) { -ICLASS: VFNMSUB231SS +ICLASS: VPBLENDMD CPL: 3 -CATEGORY: VFMA +CATEGORY: BLEND EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0xBF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL +PATTERN: EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 } + +# EMITTING VPBLENDMQ (VPBLENDMQ-512-1) { -ICLASS: VFNMSUB231SS +ICLASS: VPBLENDMQ CPL: 3 -CATEGORY: VFMA +CATEGORY: BLEND EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0xBF V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 -OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 } { -ICLASS: VFNMSUB231SS +ICLASS: VPBLENDMQ CPL: 3 -CATEGORY: VFMA +CATEGORY: BLEND EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0xBF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 -IFORM: VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL +PATTERN: EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 } -# EMITTING VGATHERDPD (VGATHERDPD-512-1) +# EMITTING VPBROADCASTD (VPBROADCASTD-512-1) { -ICLASS: VGATHERDPD +ICLASS: VPBROADCASTD CPL: 3 -CATEGORY: GATHER +CATEGORY: BROADCAST EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E12 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASKNOT0():rw:mskw MEM0:r:zd:f64 -IFORM: VGATHERDPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 +PATTERN: EVV 0x58 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:u32 EMX_BROADCAST_1TO16_32 +IFORM: VPBROADCASTD_ZMMu32_MASKmskw_MEMu32_AVX512 } -# EMITTING VGATHERDPS (VGATHERDPS-512-1) +# EMITTING VPBROADCASTD (VPBROADCASTD-512-2) { -ICLASS: VGATHERDPS +ICLASS: VPBROADCASTD CPL: 3 -CATEGORY: GATHER +CATEGORY: BROADCAST EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E12 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASKNOT0():rw:mskw MEM0:r:zd:f32 -IFORM: VGATHERDPS_ZMMf32_MASKmskw_MEMf32_AVX512_VL512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x58 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_1TO16_32 +IFORM: VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512 } -# EMITTING VGATHERQPD (VGATHERQPD-512-1) +# EMITTING VPBROADCASTD (VPBROADCASTD-512-3) { -ICLASS: VGATHERQPD +ICLASS: VPBROADCASTD CPL: 3 -CATEGORY: GATHER +CATEGORY: BROADCAST EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E12 +EXCEPTIONS: AVX512-E7NM REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASKNOT0():rw:mskw MEM0:r:zd:f64 -IFORM: VGATHERQPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 not64 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO16_32 +IFORM: VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512 +PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 mode64 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO16_32 +IFORM: VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512 } -# EMITTING VGATHERQPS (VGATHERQPS-512-1) +# EMITTING VPBROADCASTQ (VPBROADCASTQ-512-1) { -ICLASS: VGATHERQPS +ICLASS: VPBROADCASTQ CPL: 3 -CATEGORY: GATHER +CATEGORY: BROADCAST EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E12 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASKNOT0():rw:mskw MEM0:r:qq:f32 -IFORM: VGATHERQPS_YMMf32_MASKmskw_MEMf32_AVX512_VL512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 +PATTERN: EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE1() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u64 EMX_BROADCAST_1TO8_64 +IFORM: VPBROADCASTQ_ZMMu64_MASKmskw_MEMu64_AVX512 } -# EMITTING VGETEXPPD (VGETEXPPD-512-1) +# EMITTING VPBROADCASTQ (VPBROADCASTQ-512-2) { -ICLASS: VGETEXPPD +ICLASS: VPBROADCASTQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: BROADCAST EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 -IFORM: VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 EMX_BROADCAST_1TO8_64 +IFORM: VPBROADCASTQ_ZMMu64_MASKmskw_XMMu64_AVX512 } + +# EMITTING VPBROADCASTQ (VPBROADCASTQ-512-3) { -ICLASS: VGETEXPPD +ICLASS: VPBROADCASTQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: BROADCAST EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E7NM REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 -IFORM: VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 mode64 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR64_B():r:q:u64 EMX_BROADCAST_1TO8_64 +IFORM: VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512 } + +# EMITTING VPCMPD (VPCMPD-512-1) { -ICLASS: VGETEXPPD +ICLASS: VPCMPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VGETEXPPD_ZMMf64_MASKmskw_MEMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi32 REG3=ZMM_B3():r:zi32 IMM0:r:b +IFORM: VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512 } - -# EMITTING VGETEXPPS (VGETEXPPS-512-1) { -ICLASS: VGETEXPPS +ICLASS: VPCMPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 -IFORM: VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi32 MEM0:r:vv:i32:TXT=BCASTSTR IMM0:r:b +IFORM: VPCMPD_MASKmskw_MASKmskw_ZMMi32_MEMi32_IMM8_AVX512 } + +# EMITTING VPCMPEQD (VPCMPEQD-512-1) { -ICLASS: VGETEXPPS +ICLASS: VPCMPEQD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 -IFORM: VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x76 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 } { -ICLASS: VGETEXPPS +ICLASS: VPCMPEQD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VGETEXPPS_ZMMf32_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x76 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512 } -# EMITTING VGETEXPSD (VGETEXPSD-128-1) +# EMITTING VPCMPEQQ (VPCMPEQQ-512-1) { -ICLASS: VGETEXPSD +ICLASS: VPCMPEQQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x43 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512 } { -ICLASS: VGETEXPSD +ICLASS: VPCMPEQQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x43 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 -OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512 } + +# EMITTING VPCMPGTD (VPCMPGTD-512-1) { -ICLASS: VGETEXPSD +ICLASS: VPCMPGTD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0x43 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 -IFORM: VGETEXPSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x66 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi32 REG3=ZMM_B3():r:zi32 +IFORM: VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_AVX512 } - -# EMITTING VGETEXPSS (VGETEXPSS-128-1) { -ICLASS: VGETEXPSS +ICLASS: VPCMPGTD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x43 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x66 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi32 MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_MEMi32_AVX512 } + +# EMITTING VPCMPGTQ (VPCMPGTQ-512-1) { -ICLASS: VGETEXPSS +ICLASS: VPCMPGTQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x43 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 -OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x37 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi64 REG3=ZMM_B3():r:zi64 +IFORM: VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_AVX512 } { -ICLASS: VGETEXPSS +ICLASS: VPCMPGTQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0x43 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 -IFORM: VGETEXPSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x37 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi64 MEM0:r:vv:i64:TXT=BCASTSTR +IFORM: VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_AVX512 } -# EMITTING VGETMANTPD (VGETMANTPD-512-1) +# EMITTING VPCMPQ (VPCMPQ-512-1) { -ICLASS: VGETMANTPD +ICLASS: VPCMPQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b -IFORM: VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi64 REG3=ZMM_B3():r:zi64 IMM0:r:b +IFORM: VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512 } { -ICLASS: VGETMANTPD +ICLASS: VPCMPQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR UIMM8() -OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b -IFORM: VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi64 MEM0:r:vv:i64:TXT=BCASTSTR IMM0:r:b +IFORM: VPCMPQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_IMM8_AVX512 } + +# EMITTING VPCMPUD (VPCMPUD-512-1) { -ICLASS: VGETMANTPD +ICLASS: VPCMPUD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b -IFORM: VGETMANTPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 IMM0:r:b +IFORM: VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 } - -# EMITTING VGETMANTPS (VGETMANTPS-512-1) { -ICLASS: VGETMANTPS +ICLASS: VPCMPUD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b -IFORM: VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPCMPUD_MASKmskw_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 } + +# EMITTING VPCMPUQ (VPCMPUQ-512-1) { -ICLASS: VGETMANTPS +ICLASS: VPCMPUQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8() -OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b -IFORM: VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 IMM0:r:b +IFORM: VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 } { -ICLASS: VGETMANTPS +ICLASS: VPCMPUQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b -IFORM: VGETMANTPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 } -# EMITTING VGETMANTSD (VGETMANTSD-128-1) +# EMITTING VPCOMPRESSD (VPCOMPRESSD-512-1) { -ICLASS: VGETMANTSD +ICLASS: VPCOMPRESSD CPL: 3 -CATEGORY: AVX512 +CATEGORY: COMPRESS EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x27 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 UIMM8() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b -IFORM: VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:zd:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 +IFORM: VPCOMPRESSD_MEMu32_MASKmskw_ZMMu32_AVX512 } + +# EMITTING VPCOMPRESSD (VPCOMPRESSD-512-2) { -ICLASS: VGETMANTSD +ICLASS: VPCOMPRESSD CPL: 3 -CATEGORY: AVX512 +CATEGORY: COMPRESS EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x27 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 UIMM8() -OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b -IFORM: VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 +IFORM: VPCOMPRESSD_ZMMu32_MASKmskw_ZMMu32_AVX512 } + +# EMITTING VPCOMPRESSQ (VPCOMPRESSQ-512-1) { -ICLASS: VGETMANTSD +ICLASS: VPCOMPRESSQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: COMPRESS EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0x27 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b -IFORM: VGETMANTSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:zd:u64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 +IFORM: VPCOMPRESSQ_MEMu64_MASKmskw_ZMMu64_AVX512 } -# EMITTING VGETMANTSS (VGETMANTSS-128-1) +# EMITTING VPCOMPRESSQ (VPCOMPRESSQ-512-2) { -ICLASS: VGETMANTSS +ICLASS: VPCOMPRESSQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: COMPRESS EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x27 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 UIMM8() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b -IFORM: VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 +IFORM: VPCOMPRESSQ_ZMMu64_MASKmskw_ZMMu64_AVX512 } + +# EMITTING VPERMD (VPERMD-512-1) { -ICLASS: VGETMANTSS +ICLASS: VPERMD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x27 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8() -OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b -IFORM: VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x36 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 } { -ICLASS: VGETMANTSS +ICLASS: VPERMD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0x27 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b -IFORM: VGETMANTSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x36 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPERMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 } -# EMITTING VINSERTF32X4 (VINSERTF32X4-512-1) +# EMITTING VPERMI2D (VPERMI2D-512-1) { -ICLASS: VINSERTF32X4 +ICLASS: VPERMI2D CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x18 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=XMM_B3():r:dq:f32 IMM0:r:b -IFORM: VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_XMMf32_IMM8_AVX512 +PATTERN: EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPERMI2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 } { -ICLASS: VINSERTF32X4 +ICLASS: VPERMI2D CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 -PATTERN: EVV 0x18 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:dq:f32 IMM0:r:b -IFORM: VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPERMI2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 } -# EMITTING VINSERTF64X4 (VINSERTF64X4-512-1) +# EMITTING VPERMI2PD (VPERMI2PD-512-1) { -ICLASS: VINSERTF64X4 +ICLASS: VPERMI2PD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x1A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=YMM_B3():r:qq:f64 IMM0:r:b -IFORM: VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_YMMf64_IMM8_AVX512 +PATTERN: EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 } { -ICLASS: VINSERTF64X4 +ICLASS: VPERMI2PD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 -PATTERN: EVV 0x1A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE4() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:qq:f64 IMM0:r:b -IFORM: VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 } -# EMITTING VINSERTI32X4 (VINSERTI32X4-512-1) +# EMITTING VPERMI2PS (VPERMI2PS-512-1) { -ICLASS: VINSERTI32X4 +ICLASS: VPERMI2PS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x38 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=XMM_B3():r:dq:u32 IMM0:r:b -IFORM: VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_XMMu32_IMM8_AVX512 +PATTERN: EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 } { -ICLASS: VINSERTI32X4 +ICLASS: VPERMI2PS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 -PATTERN: EVV 0x38 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:dq:u32 IMM0:r:b -IFORM: VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 } -# EMITTING VINSERTI64X4 (VINSERTI64X4-512-1) +# EMITTING VPERMI2Q (VPERMI2Q-512-1) { -ICLASS: VINSERTI64X4 +ICLASS: VPERMI2Q CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x3A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=YMM_B3():r:qq:u64 IMM0:r:b -IFORM: VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_YMMu64_IMM8_AVX512 +PATTERN: EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 } { -ICLASS: VINSERTI64X4 +ICLASS: VPERMI2Q CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 -PATTERN: EVV 0x3A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE4() -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:qq:u64 IMM0:r:b -IFORM: VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 } -# EMITTING VINSERTPS (VINSERTPS-128-1) +# EMITTING VPERMILPD (VPERMILPD-512-1) { -ICLASS: VINSERTPS +ICLASS: VPERMILPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128N -EXCEPTIONS: AVX512-E9NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -PATTERN: EVV 0x21 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 MASK=0 UIMM8() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=XMM_B3():r:dq:f32 IMM0:r:b -IFORM: VINSERTPS_XMMf32_XMMf32_XMMf32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x05 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VPERMILPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 } { -ICLASS: VINSERTPS +ICLASS: VPERMILPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128N -EXCEPTIONS: AVX512-E9NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: DISP8_TUPLE1 -PATTERN: EVV 0x21 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE1() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b -IFORM: VINSERTPS_XMMf32_XMMf32_MEMf32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x05 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VPERMILPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 } -# EMITTING VMAXPD (VMAXPD-512-1) +# EMITTING VPERMILPD (VPERMILPD-512-2) { -ICLASS: VMAXPD +ICLASS: VPERMILPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x0D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +IFORM: VPERMILPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 } { -ICLASS: VMAXPD +ICLASS: VPERMILPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5F V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 -OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x0D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VPERMILPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 } + +# EMITTING VPERMILPS (VPERMILPS-512-1) { -ICLASS: VMAXPD +ICLASS: VPERMILPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x5F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x04 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VPERMILPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 } - -# EMITTING VMAXPS (VMAXPS-512-1) { -ICLASS: VMAXPS +ICLASS: VPERMILPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5F VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x04 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VPERMILPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 } + +# EMITTING VPERMILPS (VPERMILPS-512-2) { -ICLASS: VMAXPS +ICLASS: VPERMILPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5F VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 -OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x0C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VPERMILPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 } { -ICLASS: VMAXPS +ICLASS: VPERMILPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x5F VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x0C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +IFORM: VPERMILPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 } -# EMITTING VMAXSD (VMAXSD-128-1) +# EMITTING VPERMPD (VPERMPD-512-1) { -ICLASS: VMAXSD +ICLASS: VPERMPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x5F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x01 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VPERMPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 } { -ICLASS: VMAXSD +ICLASS: VPERMPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x5F VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 -OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x01 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VPERMPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 } + +# EMITTING VPERMPD (VPERMPD-512-2) { -ICLASS: VMAXSD +ICLASS: VPERMPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0x5F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 -IFORM: VMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x16 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VPERMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 } - -# EMITTING VMAXSS (VMAXSS-128-1) { -ICLASS: VMAXSS +ICLASS: VPERMPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x5F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x16 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VPERMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 } + +# EMITTING VPERMPS (VPERMPS-512-1) { -ICLASS: VMAXSS +ICLASS: VPERMPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x5F VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 -OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x16 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 } { -ICLASS: VMAXSS +ICLASS: VPERMPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0x5F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 -IFORM: VMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x16 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VPERMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 } -# EMITTING VMINPD (VMINPD-512-1) +# EMITTING VPERMQ (VPERMQ-512-1) { -ICLASS: VMINPD +ICLASS: VPERMQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x00 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b +IFORM: VPERMQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 } { -ICLASS: VMINPD +ICLASS: VPERMQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5D V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 -OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x00 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPERMQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 } + +# EMITTING VPERMQ (VPERMQ-512-2) { -ICLASS: VMINPD +ICLASS: VPERMQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x5D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VMINPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x36 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPERMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 } - -# EMITTING VMINPS (VMINPS-512-1) { -ICLASS: VMINPS +ICLASS: VPERMQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5D VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x36 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPERMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 } + +# EMITTING VPERMT2D (VPERMT2D-512-1) { -ICLASS: VMINPS +ICLASS: VPERMT2D CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5D VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 -OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPERMT2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 } { -ICLASS: VMINPS +ICLASS: VPERMT2D CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x5D VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VMINPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPERMT2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 } -# EMITTING VMINSD (VMINSD-128-1) +# EMITTING VPERMT2PD (VPERMT2PD-512-1) { -ICLASS: VMINSD +ICLASS: VPERMT2PD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x5D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 } { -ICLASS: VMINSD +ICLASS: VPERMT2PD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x5D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 -OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 } + +# EMITTING VPERMT2PS (VPERMT2PS-512-1) { -ICLASS: VMINSD +ICLASS: VPERMT2PS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0x5D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 -IFORM: VMINSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 } - -# EMITTING VMINSS (VMINSS-128-1) { -ICLASS: VMINSS +ICLASS: VPERMT2PS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x5D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 } + +# EMITTING VPERMT2Q (VPERMT2Q-512-1) { -ICLASS: VMINSS +ICLASS: VPERMT2Q CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x5D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 -OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 } { -ICLASS: VMINSS +ICLASS: VPERMT2Q CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0x5D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 -IFORM: VMINSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 } -# EMITTING VMOVAPD (VMOVAPD-512-1) +# EMITTING VPEXPANDD (VPEXPANDD-512-1) { -ICLASS: VMOVAPD +ICLASS: VPEXPANDD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: EXPAND EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E1 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x28 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 -IFORM: VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u32 +IFORM: VPEXPANDD_ZMMu32_MASKmskw_MEMu32_AVX512 } + +# EMITTING VPEXPANDD (VPEXPANDD-512-2) { -ICLASS: VMOVAPD +ICLASS: VPEXPANDD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: EXPAND EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E1 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x28 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f64 -IFORM: VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 +IFORM: VPEXPANDD_ZMMu32_MASKmskw_ZMMu32_AVX512 } -# EMITTING VMOVAPD (VMOVAPD-512-2) +# EMITTING VPEXPANDQ (VPEXPANDQ-512-1) { -ICLASS: VMOVAPD +ICLASS: VPEXPANDQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: EXPAND EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E1 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x29 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR -OPERANDS: REG0=ZMM_B3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf64 -IFORM: VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u64 +IFORM: VPEXPANDQ_ZMMu64_MASKmskw_MEMu64_AVX512 } -# EMITTING VMOVAPD (VMOVAPD-512-3) +# EMITTING VPEXPANDQ (VPEXPANDQ-512-2) { -ICLASS: VMOVAPD +ICLASS: VPEXPANDQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: EXPAND EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E1 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x29 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() -OPERANDS: MEM0:w:zd:f64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf64 -IFORM: VMOVAPD_MEMf64_MASKmskw_ZMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VPEXPANDQ_ZMMu64_MASKmskw_ZMMu64_AVX512 } -# EMITTING VMOVAPS (VMOVAPS-512-1) +# EMITTING VPGATHERDD (VPGATHERDD-512-1) { -ICLASS: VMOVAPS +ICLASS: VPGATHERDD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: GATHER EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E1 +EXCEPTIONS: AVX512-E12 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x28 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 -IFORM: VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASKNOT0():rw:mskw MEM0:r:d:u32 +IFORM: VPGATHERDD_ZMMu32_MASKmskw_MEMu32_AVX512_VL512 } + +# EMITTING VPGATHERDQ (VPGATHERDQ-512-1) { -ICLASS: VMOVAPS +ICLASS: VPGATHERDQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: GATHER EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E1 +EXCEPTIONS: AVX512-E12 REAL_OPCODE: Y -ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x28 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f32 -IFORM: VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASKNOT0():rw:mskw MEM0:r:q:u64 +IFORM: VPGATHERDQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512 } -# EMITTING VMOVAPS (VMOVAPS-512-2) +# EMITTING VPGATHERQD (VPGATHERQD-512-1) { -ICLASS: VMOVAPS +ICLASS: VPGATHERQD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: GATHER EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E1 +EXCEPTIONS: AVX512-E12 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x29 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=ZMM_B3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 -IFORM: VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASKNOT0():rw:mskw MEM0:r:d:u32 +IFORM: VPGATHERQD_YMMu32_MASKmskw_MEMu32_AVX512_VL512 } -# EMITTING VMOVAPS (VMOVAPS-512-3) +# EMITTING VPGATHERQQ (VPGATHERQQ-512-1) { -ICLASS: VMOVAPS +ICLASS: VPGATHERQQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: GATHER EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E1 +EXCEPTIONS: AVX512-E12 REAL_OPCODE: Y -ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x29 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() -OPERANDS: MEM0:w:zd:f32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32 -IFORM: VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512 +ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASKNOT0():rw:mskw MEM0:r:q:u64 +IFORM: VPGATHERQQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512 } -# EMITTING VMOVD (VMOVD-128-1) +# EMITTING VPMAXSD (VPMAXSD-512-1) { -ICLASS: VMOVD +ICLASS: VPMAXSD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128N -EXCEPTIONS: AVX512-E9NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -PATTERN: EVV 0x6E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=GPR32_B():r:d:u32 -IFORM: VMOVD_XMMu32_GPR32u32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 REG3=ZMM_B3():r:zi32 +IFORM: VPMAXSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512 } { -ICLASS: VMOVD +ICLASS: VPMAXSD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128N -EXCEPTIONS: AVX512-E9NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: DISP8_GPR_READER -PATTERN: EVV 0x6E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() -OPERANDS: REG0=XMM_R3():w:dq:u32 MEM0:r:d:u32 -IFORM: VMOVD_XMMu32_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPMAXSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512 } -# EMITTING VMOVD (VMOVD-128-2) +# EMITTING VPMAXSQ (VPMAXSQ-512-1) { -ICLASS: VMOVD +ICLASS: VPMAXSQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128N -EXCEPTIONS: AVX512-E9NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -PATTERN: EVV 0x7E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=GPR32_B():w:d:u32 REG1=XMM_R3():r:dq:u32 -IFORM: VMOVD_GPR32u32_XMMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi64 REG3=ZMM_B3():r:zi64 +IFORM: VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512 } { -ICLASS: VMOVD +ICLASS: VPMAXSQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128N -EXCEPTIONS: AVX512-E9NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: DISP8_GPR_WRITER_STORE -PATTERN: EVV 0x7E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_STORE() -OPERANDS: MEM0:w:d:u32 REG0=XMM_R3():r:dq:u32 -IFORM: VMOVD_MEMu32_XMMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi64 MEM0:r:vv:i64:TXT=BCASTSTR +IFORM: VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512 } -# EMITTING VMOVDDUP (VMOVDDUP-512-1) +# EMITTING VPMAXUD (VPMAXUD-512-1) { -ICLASS: VMOVDDUP +ICLASS: VPMAXUD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E5NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x12 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 -IFORM: VMOVDDUP_ZMMf64_MASKmskw_ZMMf64_AVX512 +PATTERN: EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPMAXUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 } { -ICLASS: VMOVDDUP +ICLASS: VPMAXUD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E5NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_MOVDDUP -PATTERN: EVV 0x12 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_MOVDDUP() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f64 -IFORM: VMOVDDUP_ZMMf64_MASKmskw_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPMAXUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 } -# EMITTING VMOVDQA32 (VMOVDQA32-512-1) +# EMITTING VPMAXUQ (VPMAXUQ-512-1) { -ICLASS: VMOVDQA32 +ICLASS: VPMAXUQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E1 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 -IFORM: VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512 +PATTERN: EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 } { -ICLASS: VMOVDQA32 +ICLASS: VPMAXUQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E1 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u32 -IFORM: VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 } -# EMITTING VMOVDQA32 (VMOVDQA32-512-2) +# EMITTING VPMINSD (VPMINSD-512-1) { -ICLASS: VMOVDQA32 +ICLASS: VPMINSD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E1 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=ZMM_B3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 -IFORM: VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512 +PATTERN: EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 REG3=ZMM_B3():r:zi32 +IFORM: VPMINSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512 } - -# EMITTING VMOVDQA32 (VMOVDQA32-512-3) { -ICLASS: VMOVDQA32 +ICLASS: VPMINSD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E1 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() -OPERANDS: MEM0:w:zd:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 -IFORM: VMOVDQA32_MEMu32_MASKmskw_ZMMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPMINSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512 } -# EMITTING VMOVDQA64 (VMOVDQA64-512-1) +# EMITTING VPMINSQ (VPMINSQ-512-1) { -ICLASS: VMOVDQA64 +ICLASS: VPMINSQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E1 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 -IFORM: VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512 +PATTERN: EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi64 REG3=ZMM_B3():r:zi64 +IFORM: VPMINSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512 } { -ICLASS: VMOVDQA64 +ICLASS: VPMINSQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E1 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u64 -IFORM: VMOVDQA64_ZMMu64_MASKmskw_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi64 MEM0:r:vv:i64:TXT=BCASTSTR +IFORM: VPMINSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512 } -# EMITTING VMOVDQA64 (VMOVDQA64-512-2) +# EMITTING VPMINUD (VPMINUD-512-1) { -ICLASS: VMOVDQA64 +ICLASS: VPMINUD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E1 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR -OPERANDS: REG0=ZMM_B3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 -IFORM: VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512 +PATTERN: EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPMINUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 } - -# EMITTING VMOVDQA64 (VMOVDQA64-512-3) { -ICLASS: VMOVDQA64 +ICLASS: VPMINUD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E1 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() -OPERANDS: MEM0:w:zd:u64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 -IFORM: VMOVDQA64_MEMu64_MASKmskw_ZMMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPMINUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 } -# EMITTING VMOVDQU32 (VMOVDQU32-512-1) +# EMITTING VPMINUQ (VPMINUQ-512-1) { -ICLASS: VMOVDQU32 +ICLASS: VPMINUQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 -IFORM: VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512 +PATTERN: EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPMINUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 } { -ICLASS: VMOVDQU32 +ICLASS: VPMINUQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u32 -IFORM: VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMINUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 } -# EMITTING VMOVDQU32 (VMOVDQU32-512-2) +# EMITTING VPMOVDB (VPMOVDB-512-1) { -ICLASS: VMOVDQU32 +ICLASS: VPMOVDB CPL: 3 CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=ZMM_B3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 -IFORM: VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512 +PATTERN: EVV 0x31 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 +IFORM: VPMOVDB_XMMu8_MASKmskw_ZMMu32_AVX512 } -# EMITTING VMOVDQU32 (VMOVDQU32-512-3) +# EMITTING VPMOVDB (VPMOVDB-512-2) { -ICLASS: VMOVDQU32 +ICLASS: VPMOVDB CPL: 3 CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() -OPERANDS: MEM0:w:zd:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 -IFORM: VMOVDQU32_MEMu32_MASKmskw_ZMMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x31 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:dq:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 +IFORM: VPMOVDB_MEMu8_MASKmskw_ZMMu32_AVX512 } -# EMITTING VMOVDQU64 (VMOVDQU64-512-1) +# EMITTING VPMOVDW (VPMOVDW-512-1) { -ICLASS: VMOVDQU64 +ICLASS: VPMOVDW CPL: 3 CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 -IFORM: VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512 +PATTERN: EVV 0x33 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 +IFORM: VPMOVDW_YMMu16_MASKmskw_ZMMu32_AVX512 } + +# EMITTING VPMOVDW (VPMOVDW-512-2) { -ICLASS: VMOVDQU64 +ICLASS: VPMOVDW CPL: 3 CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u64 -IFORM: VMOVDQU64_ZMMu64_MASKmskw_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x33 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:qq:u16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 +IFORM: VPMOVDW_MEMu16_MASKmskw_ZMMu32_AVX512 } -# EMITTING VMOVDQU64 (VMOVDQU64-512-2) +# EMITTING VPMOVQB (VPMOVQB-512-1) { -ICLASS: VMOVDQU64 +ICLASS: VPMOVQB CPL: 3 CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR -OPERANDS: REG0=ZMM_B3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 -IFORM: VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512 +PATTERN: EVV 0x32 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 +IFORM: VPMOVQB_XMMu8_MASKmskw_ZMMu64_AVX512 } -# EMITTING VMOVDQU64 (VMOVDQU64-512-3) +# EMITTING VPMOVQB (VPMOVQB-512-2) { -ICLASS: VMOVDQU64 +ICLASS: VPMOVQB CPL: 3 CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() -OPERANDS: MEM0:w:zd:u64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 -IFORM: VMOVDQU64_MEMu64_MASKmskw_ZMMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x32 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 +IFORM: VPMOVQB_MEMu8_MASKmskw_ZMMu64_AVX512 } -# EMITTING VMOVHLPS (VMOVHLPS-128-1) +# EMITTING VPMOVQD (VPMOVQD-512-1) { -ICLASS: VMOVHLPS +ICLASS: VPMOVQD CPL: 3 CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128N -EXCEPTIONS: AVX512-E7NM128 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -PATTERN: EVV 0x12 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 MASK=0 -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=XMM_B3():r:dq:f32 -IFORM: VMOVHLPS_XMMf32_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x35 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 +IFORM: VPMOVQD_YMMu32_MASKmskw_ZMMu64_AVX512 } -# EMITTING VMOVHPD (VMOVHPD-128-1) +# EMITTING VPMOVQD (VPMOVQD-512-2) { -ICLASS: VMOVHPD +ICLASS: VPMOVQD CPL: 3 CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128N -EXCEPTIONS: AVX512-E9NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: DISP8_SCALAR -PATTERN: EVV 0x16 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:q:f64 MEM0:r:q:f64 -IFORM: VMOVHPD_XMMf64_XMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x35 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 +IFORM: VPMOVQD_MEMu32_MASKmskw_ZMMu64_AVX512 } -# EMITTING VMOVHPD (VMOVHPD-128-2) +# EMITTING VPMOVQW (VPMOVQW-512-1) { -ICLASS: VMOVHPD +ICLASS: VPMOVQW CPL: 3 CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128N -EXCEPTIONS: AVX512-E9NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: DISP8_SCALAR -PATTERN: EVV 0x17 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() -OPERANDS: MEM0:w:q:f64 REG0=XMM_R3():r:dq:f64 -IFORM: VMOVHPD_MEMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x34 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 +IFORM: VPMOVQW_XMMu16_MASKmskw_ZMMu64_AVX512 } -# EMITTING VMOVHPS (VMOVHPS-128-1) +# EMITTING VPMOVQW (VPMOVQW-512-2) { -ICLASS: VMOVHPS +ICLASS: VPMOVQW CPL: 3 CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128N -EXCEPTIONS: AVX512-E9NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: DISP8_TUPLE2 -PATTERN: EVV 0x16 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_TUPLE2() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:q:f32 MEM0:r:q:f32 -IFORM: VMOVHPS_XMMf32_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x34 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:dq:u16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 +IFORM: VPMOVQW_MEMu16_MASKmskw_ZMMu64_AVX512 } -# EMITTING VMOVHPS (VMOVHPS-128-2) +# EMITTING VPMOVSDB (VPMOVSDB-512-1) { -ICLASS: VMOVHPS +ICLASS: VPMOVSDB CPL: 3 CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128N -EXCEPTIONS: AVX512-E9NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: DISP8_TUPLE2 -PATTERN: EVV 0x17 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_TUPLE2() -OPERANDS: MEM0:w:q:f32 REG0=XMM_R3():r:dq:f32 -IFORM: VMOVHPS_MEMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x21 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zi32 +IFORM: VPMOVSDB_XMMi8_MASKmskw_ZMMi32_AVX512 } -# EMITTING VMOVLHPS (VMOVLHPS-128-1) +# EMITTING VPMOVSDB (VPMOVSDB-512-2) { -ICLASS: VMOVLHPS +ICLASS: VPMOVSDB CPL: 3 CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128N -EXCEPTIONS: AVX512-E7NM128 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -PATTERN: EVV 0x16 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 MASK=0 -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:q:f32 REG2=XMM_B3():r:q:f32 -IFORM: VMOVLHPS_XMMf32_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x21 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:dq:i8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zi32 +IFORM: VPMOVSDB_MEMi8_MASKmskw_ZMMi32_AVX512 } -# EMITTING VMOVLPD (VMOVLPD-128-1) +# EMITTING VPMOVSDW (VPMOVSDW-512-1) { -ICLASS: VMOVLPD +ICLASS: VPMOVSDW CPL: 3 CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128N -EXCEPTIONS: AVX512-E9NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: DISP8_SCALAR -PATTERN: EVV 0x12 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:q:f64 -IFORM: VMOVLPD_XMMf64_XMMf64_MEMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x23 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zi32 +IFORM: VPMOVSDW_YMMi16_MASKmskw_ZMMi32_AVX512 } -# EMITTING VMOVLPD (VMOVLPD-128-2) +# EMITTING VPMOVSDW (VPMOVSDW-512-2) { -ICLASS: VMOVLPD +ICLASS: VPMOVSDW CPL: 3 CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128N -EXCEPTIONS: AVX512-E9NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: DISP8_SCALAR -PATTERN: EVV 0x13 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() -OPERANDS: MEM0:w:q:f64 REG0=XMM_R3():r:q:f64 -IFORM: VMOVLPD_MEMf64_XMMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x23 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:qq:i16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zi32 +IFORM: VPMOVSDW_MEMi16_MASKmskw_ZMMi32_AVX512 } -# EMITTING VMOVLPS (VMOVLPS-128-1) +# EMITTING VPMOVSQB (VPMOVSQB-512-1) { -ICLASS: VMOVLPS +ICLASS: VPMOVSQB CPL: 3 CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128N -EXCEPTIONS: AVX512-E9NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: DISP8_TUPLE2 -PATTERN: EVV 0x12 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_TUPLE2() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:q:f32 -IFORM: VMOVLPS_XMMf32_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x22 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zi64 +IFORM: VPMOVSQB_XMMi8_MASKmskw_ZMMi64_AVX512 } -# EMITTING VMOVLPS (VMOVLPS-128-2) +# EMITTING VPMOVSQB (VPMOVSQB-512-2) { -ICLASS: VMOVLPS +ICLASS: VPMOVSQB CPL: 3 CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128N -EXCEPTIONS: AVX512-E9NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: DISP8_TUPLE2 -PATTERN: EVV 0x13 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_TUPLE2() -OPERANDS: MEM0:w:q:f32 REG0=XMM_R3():r:q:f32 -IFORM: VMOVLPS_MEMf32_XMMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x22 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: MEM0:w:q:i8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zi64 +IFORM: VPMOVSQB_MEMi8_MASKmskw_ZMMi64_AVX512 } -# EMITTING VMOVNTDQ (VMOVNTDQ-512-1) +# EMITTING VPMOVSQD (VPMOVSQD-512-1) { -ICLASS: VMOVNTDQ +ICLASS: VPMOVSQD CPL: 3 CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E1NF +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM -PATTERN: EVV 0xE7 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() -OPERANDS: MEM0:w:zd:u32 REG0=ZMM_R3():r:zu32 -IFORM: VMOVNTDQ_MEMu32_ZMMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x25 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zi64 +IFORM: VPMOVSQD_YMMi32_MASKmskw_ZMMi64_AVX512 } -# EMITTING VMOVNTDQA (VMOVNTDQA-512-1) +# EMITTING VPMOVSQD (VPMOVSQD-512-2) { -ICLASS: VMOVNTDQA +ICLASS: VPMOVSQD CPL: 3 CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E1NF +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM -PATTERN: EVV 0x2A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zu32 MEM0:r:zd:u32 -IFORM: VMOVNTDQA_ZMMu32_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x25 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:qq:i32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zi64 +IFORM: VPMOVSQD_MEMi32_MASKmskw_ZMMi64_AVX512 } -# EMITTING VMOVNTPD (VMOVNTPD-512-1) +# EMITTING VPMOVSQW (VPMOVSQW-512-1) { -ICLASS: VMOVNTPD +ICLASS: VPMOVSQW CPL: 3 CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E1NF +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM -PATTERN: EVV 0x2B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_FULLMEM() -OPERANDS: MEM0:w:zd:f64 REG0=ZMM_R3():r:zf64 -IFORM: VMOVNTPD_MEMf64_ZMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x24 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zi64 +IFORM: VPMOVSQW_XMMi16_MASKmskw_ZMMi64_AVX512 } -# EMITTING VMOVNTPS (VMOVNTPS-512-1) +# EMITTING VPMOVSQW (VPMOVSQW-512-2) { -ICLASS: VMOVNTPS +ICLASS: VPMOVSQW CPL: 3 CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E1NF +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM -PATTERN: EVV 0x2B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() -OPERANDS: MEM0:w:zd:f32 REG0=ZMM_R3():r:zf32 -IFORM: VMOVNTPS_MEMf32_ZMMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x24 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:dq:i16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zi64 +IFORM: VPMOVSQW_MEMi16_MASKmskw_ZMMi64_AVX512 } -# EMITTING VMOVQ (VMOVQ-128-1) +# EMITTING VPMOVSXBD (VPMOVSXBD-512-1) { -ICLASS: VMOVQ +ICLASS: VPMOVSXBD CPL: 3 CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128N -EXCEPTIONS: AVX512-E9NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -PATTERN: EVV 0x6E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=GPR64_B():r:q:u64 -IFORM: VMOVQ_XMMu64_GPR64u64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x21 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVSXBD_ZMMi32_MASKmskw_XMMi8_AVX512 } { -ICLASS: VMOVQ +ICLASS: VPMOVSXBD CPL: 3 CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128N -EXCEPTIONS: AVX512-E9NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: DISP8_GPR_READER -PATTERN: EVV 0x6E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() -OPERANDS: REG0=XMM_R3():w:dq:u64 MEM0:r:q:u64 -IFORM: VMOVQ_XMMu64_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x21 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i8 +IFORM: VPMOVSXBD_ZMMi32_MASKmskw_MEMi8_AVX512 } -# EMITTING VMOVQ (VMOVQ-128-2) +# EMITTING VPMOVSXBQ (VPMOVSXBQ-512-1) { -ICLASS: VMOVQ +ICLASS: VPMOVSXBQ CPL: 3 CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128N -EXCEPTIONS: AVX512-E9NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -PATTERN: EVV 0x7E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=GPR64_B():w:q:u64 REG1=XMM_R3():r:dq:u64 -IFORM: VMOVQ_GPR64u64_XMMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x22 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVSXBQ_ZMMi64_MASKmskw_XMMi8_AVX512 } { -ICLASS: VMOVQ +ICLASS: VPMOVSXBQ CPL: 3 CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128N -EXCEPTIONS: AVX512-E9NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: DISP8_GPR_WRITER_STORE -PATTERN: EVV 0x7E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_STORE() -OPERANDS: MEM0:w:q:u64 REG0=XMM_R3():r:dq:u64 -IFORM: VMOVQ_MEMu64_XMMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x22 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8 +IFORM: VPMOVSXBQ_ZMMi64_MASKmskw_MEMi8_AVX512 } -# EMITTING VMOVQ (VMOVQ-128-3) +# EMITTING VPMOVSXDQ (VPMOVSXDQ-512-1) { -ICLASS: VMOVQ +ICLASS: VPMOVSXDQ CPL: 3 CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128N -EXCEPTIONS: AVX512-E9NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -PATTERN: EVV 0x7E VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=XMM_B3():r:dq:u64 -IFORM: VMOVQ_XMMu64_XMMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x25 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32 +IFORM: VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512 } { -ICLASS: VMOVQ +ICLASS: VPMOVSXDQ CPL: 3 CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128N -EXCEPTIONS: AVX512-E9NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: DISP8_SCALAR -PATTERN: EVV 0x7E VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():w:dq:u64 MEM0:r:q:u64 -IFORM: VMOVQ_XMMu64_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x25 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i32 +IFORM: VPMOVSXDQ_ZMMi64_MASKmskw_MEMi32_AVX512 } -# EMITTING VMOVQ (VMOVQ-128-4) +# EMITTING VPMOVSXWD (VPMOVSXWD-512-1) { -ICLASS: VMOVQ +ICLASS: VPMOVSXWD CPL: 3 CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128N -EXCEPTIONS: AVX512-E9NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -PATTERN: EVV 0xD6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=XMM_B3():w:dq:u64 REG1=XMM_R3():r:dq:u64 -IFORM: VMOVQ_XMMu64_XMMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x23 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i16 +IFORM: VPMOVSXWD_ZMMi32_MASKmskw_YMMi16_AVX512 } { -ICLASS: VMOVQ +ICLASS: VPMOVSXWD CPL: 3 CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128N -EXCEPTIONS: AVX512-E9NF +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: DISP8_SCALAR -PATTERN: EVV 0xD6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() -OPERANDS: MEM0:w:q:u64 REG0=XMM_R3():r:dq:u64 -IFORM: VMOVQ_MEMu64_XMMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x23 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i16 +IFORM: VPMOVSXWD_ZMMi32_MASKmskw_MEMi16_AVX512 } -# EMITTING VMOVSD (VMOVSD-128-1) +# EMITTING VPMOVSXWQ (VPMOVSXWQ-512-1) { -ICLASS: VMOVSD +ICLASS: VPMOVSXWQ CPL: 3 CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR +ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0x10 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ESIZE_64_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f64 -IFORM: VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x24 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 +IFORM: VPMOVSXWQ_ZMMi64_MASKmskw_XMMi16_AVX512 } - -# EMITTING VMOVSD (VMOVSD-128-2) { -ICLASS: VMOVSD +ICLASS: VPMOVSXWQ CPL: 3 CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR +ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0x11 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_SCALAR() -OPERANDS: MEM0:w:q:f64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f64 -IFORM: VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x24 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i16 +IFORM: VPMOVSXWQ_ZMMi64_MASKmskw_MEMi16_AVX512 } -# EMITTING VMOVSD (VMOVSD-128-3) +# EMITTING VPMOVUSDB (VPMOVUSDB-512-1) { -ICLASS: VMOVSD +ICLASS: VPMOVUSDB CPL: 3 CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E5 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x10 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x11 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 +IFORM: VPMOVUSDB_XMMu8_MASKmskw_ZMMu32_AVX512 } -# EMITTING VMOVSD (VMOVSD-128-4) +# EMITTING VPMOVUSDB (VPMOVUSDB-512-2) { -ICLASS: VMOVSD +ICLASS: VPMOVUSDB CPL: 3 CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E5 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 -OPERANDS: REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_R3():r:dq:f64 -IFORM: VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x11 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:dq:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 +IFORM: VPMOVUSDB_MEMu8_MASKmskw_ZMMu32_AVX512 } -# EMITTING VMOVSHDUP (VMOVSHDUP-512-1) +# EMITTING VPMOVUSDW (VPMOVUSDW-512-1) { -ICLASS: VMOVSHDUP +ICLASS: VPMOVUSDW CPL: 3 CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x16 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 -IFORM: VMOVSHDUP_ZMMf32_MASKmskw_ZMMf32_AVX512 +PATTERN: EVV 0x13 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 +IFORM: VPMOVUSDW_YMMu16_MASKmskw_ZMMu32_AVX512 } + +# EMITTING VPMOVUSDW (VPMOVUSDW-512-2) { -ICLASS: VMOVSHDUP +ICLASS: VPMOVUSDW CPL: 3 CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x16 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f32 -IFORM: VMOVSHDUP_ZMMf32_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x13 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:qq:u16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 +IFORM: VPMOVUSDW_MEMu16_MASKmskw_ZMMu32_AVX512 } -# EMITTING VMOVSLDUP (VMOVSLDUP-512-1) +# EMITTING VPMOVUSQB (VPMOVUSQB-512-1) { -ICLASS: VMOVSLDUP +ICLASS: VPMOVUSQB CPL: 3 CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x12 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 -IFORM: VMOVSLDUP_ZMMf32_MASKmskw_ZMMf32_AVX512 +PATTERN: EVV 0x12 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 +IFORM: VPMOVUSQB_XMMu8_MASKmskw_ZMMu64_AVX512 } + +# EMITTING VPMOVUSQB (VPMOVUSQB-512-2) { -ICLASS: VMOVSLDUP +ICLASS: VPMOVUSQB CPL: 3 CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x12 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f32 -IFORM: VMOVSLDUP_ZMMf32_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x12 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 +IFORM: VPMOVUSQB_MEMu8_MASKmskw_ZMMu64_AVX512 } -# EMITTING VMOVSS (VMOVSS-128-1) +# EMITTING VPMOVUSQD (VPMOVUSQD-512-1) { -ICLASS: VMOVSS +ICLASS: VPMOVUSQD CPL: 3 CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E5 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0x10 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ESIZE_32_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:f32 -IFORM: VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x15 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 +IFORM: VPMOVUSQD_YMMu32_MASKmskw_ZMMu64_AVX512 } -# EMITTING VMOVSS (VMOVSS-128-2) +# EMITTING VPMOVUSQD (VPMOVUSQD-512-2) { -ICLASS: VMOVSS +ICLASS: VPMOVUSQD CPL: 3 CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E5 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0x11 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_SCALAR() -OPERANDS: MEM0:w:d:f32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f32 -IFORM: VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x15 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 +IFORM: VPMOVUSQD_MEMu32_MASKmskw_ZMMu64_AVX512 } -# EMITTING VMOVSS (VMOVSS-128-3) +# EMITTING VPMOVUSQW (VPMOVUSQW-512-1) { -ICLASS: VMOVSS +ICLASS: VPMOVUSQW CPL: 3 CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E5 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x10 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x14 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 +IFORM: VPMOVUSQW_XMMu16_MASKmskw_ZMMu64_AVX512 } -# EMITTING VMOVSS (VMOVSS-128-4) +# EMITTING VPMOVUSQW (VPMOVUSQW-512-2) { -ICLASS: VMOVSS +ICLASS: VPMOVUSQW CPL: 3 CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E5 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 -OPERANDS: REG0=XMM_B3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_R3():r:dq:f32 -IFORM: VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x14 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:dq:u16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 +IFORM: VPMOVUSQW_MEMu16_MASKmskw_ZMMu64_AVX512 } -# EMITTING VMOVUPD (VMOVUPD-512-1) +# EMITTING VPMOVZXBD (VPMOVZXBD-512-1) { -ICLASS: VMOVUPD +ICLASS: VPMOVZXBD CPL: 3 CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x10 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 -IFORM: VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +PATTERN: EVV 0x31 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVZXBD_ZMMi32_MASKmskw_XMMi8_AVX512 } { -ICLASS: VMOVUPD +ICLASS: VPMOVZXBD CPL: 3 CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x10 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f64 -IFORM: VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x31 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i8 +IFORM: VPMOVZXBD_ZMMi32_MASKmskw_MEMi8_AVX512 } -# EMITTING VMOVUPD (VMOVUPD-512-2) +# EMITTING VPMOVZXBQ (VPMOVZXBQ-512-1) { -ICLASS: VMOVUPD +ICLASS: VPMOVZXBQ CPL: 3 CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x11 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR -OPERANDS: REG0=ZMM_B3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf64 -IFORM: VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +PATTERN: EVV 0x32 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVZXBQ_ZMMi64_MASKmskw_XMMi8_AVX512 } - -# EMITTING VMOVUPD (VMOVUPD-512-3) { -ICLASS: VMOVUPD +ICLASS: VPMOVZXBQ CPL: 3 CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x11 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() -OPERANDS: MEM0:w:zd:f64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf64 -IFORM: VMOVUPD_MEMf64_MASKmskw_ZMMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x32 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8 +IFORM: VPMOVZXBQ_ZMMi64_MASKmskw_MEMi8_AVX512 } -# EMITTING VMOVUPS (VMOVUPS-512-1) +# EMITTING VPMOVZXDQ (VPMOVZXDQ-512-1) { -ICLASS: VMOVUPS +ICLASS: VPMOVZXDQ CPL: 3 CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x10 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 -IFORM: VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +PATTERN: EVV 0x35 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32 +IFORM: VPMOVZXDQ_ZMMi64_MASKmskw_YMMi32_AVX512 } { -ICLASS: VMOVUPS +ICLASS: VPMOVZXDQ CPL: 3 CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x10 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f32 -IFORM: VMOVUPS_ZMMf32_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x35 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i32 +IFORM: VPMOVZXDQ_ZMMi64_MASKmskw_MEMi32_AVX512 } -# EMITTING VMOVUPS (VMOVUPS-512-2) +# EMITTING VPMOVZXWD (VPMOVZXWD-512-1) { -ICLASS: VMOVUPS +ICLASS: VPMOVZXWD CPL: 3 CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x11 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=ZMM_B3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 -IFORM: VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +PATTERN: EVV 0x33 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i16 +IFORM: VPMOVZXWD_ZMMi32_MASKmskw_YMMi16_AVX512 } - -# EMITTING VMOVUPS (VMOVUPS-512-3) { -ICLASS: VMOVUPS +ICLASS: VPMOVZXWD CPL: 3 CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x11 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() -OPERANDS: MEM0:w:zd:f32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32 -IFORM: VMOVUPS_MEMf32_MASKmskw_ZMMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x33 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i16 +IFORM: VPMOVZXWD_ZMMi32_MASKmskw_MEMi16_AVX512 } -# EMITTING VMULPD (VMULPD-512-1) +# EMITTING VPMOVZXWQ (VPMOVZXWQ-512-1) { -ICLASS: VMULPD +ICLASS: VPMOVZXWQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x59 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x34 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 +IFORM: VPMOVZXWQ_ZMMi64_MASKmskw_XMMi16_AVX512 } { -ICLASS: VMULPD +ICLASS: VPMOVZXWQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x59 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 -OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x34 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i16 +IFORM: VPMOVZXWQ_ZMMi64_MASKmskw_MEMi16_AVX512 } + +# EMITTING VPMULDQ (VPMULDQ-512-1) { -ICLASS: VMULPD +ICLASS: VPMULDQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x59 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VMULPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +COMMENT: Strange instruction that uses 32b of each 64b input element +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi64 REG3=ZMM_B3():r:zi64 +IFORM: VPMULDQ_ZMMi64_MASKmskw_ZMMi32_ZMMi32_AVX512 } - -# EMITTING VMULPS (VMULPS-512-1) { -ICLASS: VMULPS +ICLASS: VPMULDQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x59 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +COMMENT: Strange instruction that uses 32b of each 64b input element +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP DISP8_FULL BROADCAST_ENABLED MASKOP_EVEX +PATTERN: EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi64 MEM0:r:vv:i64:TXT=BCASTSTR +IFORM: VPMULDQ_ZMMi64_MASKmskw_ZMMi32_MEMi32_AVX512 } + +# EMITTING VPMULLD (VPMULLD-512-1) { -ICLASS: VMULPS +ICLASS: VPMULLD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x59 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 -OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPMULLD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 } { -ICLASS: VMULPS +ICLASS: VPMULLD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x59 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VMULPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPMULLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 } -# EMITTING VMULSD (VMULSD-128-1) +# EMITTING VPMULUDQ (VPMULUDQ-512-1) { -ICLASS: VMULSD +ICLASS: VPMULUDQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x59 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +COMMENT: Strange instruction that uses 32b of each 64b input element +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_ZMMu32_AVX512 } { -ICLASS: VMULSD +ICLASS: VPMULUDQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x59 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 -OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +COMMENT: Strange instruction that uses 32b of each 64b input element +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP DISP8_FULL BROADCAST_ENABLED MASKOP_EVEX +PATTERN: EVV 0xF4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_MEMu32_AVX512 } + +# EMITTING VPORD (VPORD-512-1) { -ICLASS: VMULSD +ICLASS: VPORD CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0x59 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 -IFORM: VMULSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 } - -# EMITTING VMULSS (VMULSS-128-1) { -ICLASS: VMULSS +ICLASS: VPORD CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x59 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 } + +# EMITTING VPORQ (VPORQ-512-1) { -ICLASS: VMULSS +ICLASS: VPORQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x59 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 -OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 } { -ICLASS: VMULSS +ICLASS: VPORQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0x59 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 -IFORM: VMULSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 } -# EMITTING VPABSD (VPABSD-512-1) +# EMITTING VPROLD (VPROLD-512-1) { -ICLASS: VPABSD +ICLASS: VPROLD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -36301,13 +40786,13 @@ ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x1E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi32 -IFORM: VPABSD_ZMMi32_MASKmskw_ZMMi32_AVX512 +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b +IFORM: VPROLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 } { -ICLASS: VPABSD +ICLASS: VPROLD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -36315,15 +40800,15 @@ ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x1E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR -IFORM: VPABSD_ZMMi32_MASKmskw_MEMi32_AVX512 +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPROLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 } -# EMITTING VPABSQ (VPABSQ-512-1) +# EMITTING VPROLQ (VPROLQ-512-1) { -ICLASS: VPABSQ +ICLASS: VPROLQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -36331,13 +40816,13 @@ ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x1F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi64 -IFORM: VPABSQ_ZMMi64_MASKmskw_ZMMi64_AVX512 +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b +IFORM: VPROLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 } { -ICLASS: VPABSQ +ICLASS: VPROLQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -36345,15 +40830,15 @@ ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x1F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i64:TXT=BCASTSTR -IFORM: VPABSQ_ZMMi64_MASKmskw_MEMi64_AVX512 +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPROLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 } -# EMITTING VPADDD (VPADDD-512-1) +# EMITTING VPROLVD (VPROLVD-512-1) { -ICLASS: VPADDD +ICLASS: VPROLVD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -36361,13 +40846,13 @@ ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xFE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +PATTERN: EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 -IFORM: VPADDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +IFORM: VPROLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 } { -ICLASS: VPADDD +ICLASS: VPROLVD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -36375,15 +40860,15 @@ ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xFE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +PATTERN: EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPADDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +IFORM: VPROLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 } -# EMITTING VPADDQ (VPADDQ-512-1) +# EMITTING VPROLVQ (VPROLVQ-512-1) { -ICLASS: VPADDQ +ICLASS: VPROLVQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -36391,13 +40876,13 @@ ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xD4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +PATTERN: EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 -IFORM: VPADDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +IFORM: VPROLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 } { -ICLASS: VPADDQ +ICLASS: VPROLVQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -36405,291 +40890,319 @@ ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xD4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +PATTERN: EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPADDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +IFORM: VPROLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 } -# EMITTING VPANDD (VPANDD-512-1) +# EMITTING VPRORD (VPRORD-512-1) { -ICLASS: VPANDD +ICLASS: VPRORD CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 -IFORM: VPANDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b +IFORM: VPRORD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 } { -ICLASS: VPANDD +ICLASS: VPRORD CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPANDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPRORD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 } -# EMITTING VPANDND (VPANDND-512-1) +# EMITTING VPRORQ (VPRORQ-512-1) { -ICLASS: VPANDND +ICLASS: VPRORQ CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 -IFORM: VPANDND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b +IFORM: VPRORQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 } { -ICLASS: VPANDND +ICLASS: VPRORQ CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPANDND_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPRORQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 } -# EMITTING VPANDNQ (VPANDNQ-512-1) +# EMITTING VPRORVD (VPRORVD-512-1) { -ICLASS: VPANDNQ +ICLASS: VPRORVD CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 -IFORM: VPANDNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +PATTERN: EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPRORVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 } { -ICLASS: VPANDNQ +ICLASS: VPRORVD CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPANDNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +PATTERN: EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPRORVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 } -# EMITTING VPANDQ (VPANDQ-512-1) +# EMITTING VPRORVQ (VPRORVQ-512-1) { -ICLASS: VPANDQ +ICLASS: VPRORVQ CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +PATTERN: EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 -IFORM: VPANDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +IFORM: VPRORVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 } { -ICLASS: VPANDQ +ICLASS: VPRORVQ CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +PATTERN: EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPANDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +IFORM: VPRORVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 } -# EMITTING VPBLENDMD (VPBLENDMD-512-1) +# EMITTING VPSCATTERDD (VPSCATTERDD-512-1) { -ICLASS: VPBLENDMD +ICLASS: VPSCATTERDD CPL: 3 -CATEGORY: BLEND +CATEGORY: SCATTER EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E12 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL -PATTERN: EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 -IFORM: VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:d:u32 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zu32 +IFORM: VPSCATTERDD_MEMu32_MASKmskw_ZMMu32_AVX512_VL512 } + +# EMITTING VPSCATTERDQ (VPSCATTERDQ-512-1) { -ICLASS: VPBLENDMD +ICLASS: VPSCATTERDQ CPL: 3 -CATEGORY: BLEND +CATEGORY: SCATTER EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E12 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:q:u64 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zu64 +IFORM: VPSCATTERDQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512 } -# EMITTING VPBLENDMQ (VPBLENDMQ-512-1) +# EMITTING VPSCATTERQD (VPSCATTERQD-512-1) { -ICLASS: VPBLENDMQ +ICLASS: VPSCATTERQD CPL: 3 -CATEGORY: BLEND +CATEGORY: SCATTER EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E12 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL -PATTERN: EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 -IFORM: VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:d:u32 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:u32 +IFORM: VPSCATTERQD_MEMu32_MASKmskw_YMMu32_AVX512_VL512 } + +# EMITTING VPSCATTERQQ (VPSCATTERQQ-512-1) { -ICLASS: VPBLENDMQ +ICLASS: VPSCATTERQQ CPL: 3 -CATEGORY: BLEND +CATEGORY: SCATTER EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E12 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:q:u64 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zu64 +IFORM: VPSCATTERQQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512 } -# EMITTING VPBROADCASTD (VPBROADCASTD-512-1) +# EMITTING VPSHUFD (VPSHUFD-512-1) { -ICLASS: VPBROADCASTD +ICLASS: VPSHUFD CPL: 3 -CATEGORY: BROADCAST +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 -PATTERN: EVV 0x58 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1() -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:u32 EMX_BROADCAST_1TO16_32 -IFORM: VPBROADCASTD_ZMMu32_MASKmskw_MEMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x70 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b +IFORM: VPSHUFD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 } - -# EMITTING VPBROADCASTD (VPBROADCASTD-512-2) { -ICLASS: VPBROADCASTD +ICLASS: VPSHUFD CPL: 3 -CATEGORY: BROADCAST +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x58 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_1TO16_32 -IFORM: VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x70 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSHUFD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 } -# EMITTING VPBROADCASTD (VPBROADCASTD-512-3) +# EMITTING VPSLLD (VPSLLD-512-1) { -ICLASS: VPBROADCASTD +ICLASS: VPSLLD CPL: 3 -CATEGORY: BROADCAST +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E7NM +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO16_32 -IFORM: VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512 +PATTERN: EVV 0xF2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSLLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512 } - -# EMITTING VPBROADCASTQ (VPBROADCASTQ-512-1) { -ICLASS: VPBROADCASTQ +ICLASS: VPSLLD CPL: 3 -CATEGORY: BROADCAST +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 -PATTERN: EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE1() -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u64 EMX_BROADCAST_1TO8_64 -IFORM: VPBROADCASTQ_ZMMu64_MASKmskw_MEMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xF2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_MEM128() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:dq:u32 +IFORM: VPSLLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 } -# EMITTING VPBROADCASTQ (VPBROADCASTQ-512-2) +# EMITTING VPSLLD (VPSLLD-512-2) { -ICLASS: VPBROADCASTQ +ICLASS: VPSLLD CPL: 3 -CATEGORY: BROADCAST +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 EMX_BROADCAST_1TO8_64 -IFORM: VPBROADCASTQ_ZMMu64_MASKmskw_XMMu64_AVX512 +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b +IFORM: VPSLLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPSLLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSLLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 } -# EMITTING VPBROADCASTQ (VPBROADCASTQ-512-3) +# EMITTING VPSLLQ (VPSLLQ-512-1) { -ICLASS: VPBROADCASTQ +ICLASS: VPSLLQ CPL: 3 -CATEGORY: BROADCAST +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E7NM +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 mode64 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR64_B():r:q:u64 EMX_BROADCAST_1TO8_64 -IFORM: VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512 +PATTERN: EVV 0xF3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSLLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPSLLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xF3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_64_BITS() NELEM_MEM128() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:dq:u64 +IFORM: VPSLLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 } -# EMITTING VPCMPD (VPCMPD-512-1) +# EMITTING VPSLLQ (VPSLLQ-512-2) { -ICLASS: VPCMPD +ICLASS: VPSLLQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -36697,13 +41210,13 @@ ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi32 REG3=ZMM_B3():r:zi32 IMM0:r:b -IFORM: VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512 +PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b +IFORM: VPSLLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 } { -ICLASS: VPCMPD +ICLASS: VPSLLQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -36711,15 +41224,15 @@ ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi32 MEM0:r:vv:i32:TXT=BCASTSTR IMM0:r:b -IFORM: VPCMPD_MASKmskw_MASKmskw_ZMMi32_MEMi32_IMM8_AVX512 +PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPSLLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 } -# EMITTING VPCMPEQD (VPCMPEQD-512-1) +# EMITTING VPSLLVD (VPSLLVD-512-1) { -ICLASS: VPCMPEQD +ICLASS: VPSLLVD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -36727,13 +41240,13 @@ ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x76 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 -IFORM: VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 +PATTERN: EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPSLLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 } { -ICLASS: VPCMPEQD +ICLASS: VPSLLVD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -36741,15 +41254,15 @@ ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x76 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512 +PATTERN: EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSLLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 } -# EMITTING VPCMPEQQ (VPCMPEQQ-512-1) +# EMITTING VPSLLVQ (VPSLLVQ-512-1) { -ICLASS: VPCMPEQQ +ICLASS: VPSLLVQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -36757,13 +41270,13 @@ ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 -IFORM: VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512 +PATTERN: EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 } { -ICLASS: VPCMPEQQ +ICLASS: VPSLLVQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -36771,15 +41284,45 @@ ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512 +PATTERN: EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSRAD (VPSRAD-512-1) +{ +ICLASS: VPSRAD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSRAD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPSRAD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_MEM128() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:dq:u32 +IFORM: VPSRAD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 } -# EMITTING VPCMPGTD (VPCMPGTD-512-1) +# EMITTING VPSRAD (VPSRAD-512-2) { -ICLASS: VPCMPGTD +ICLASS: VPSRAD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -36787,13 +41330,13 @@ ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x66 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi32 REG3=ZMM_B3():r:zi32 -IFORM: VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_AVX512 +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b +IFORM: VPSRAD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 } { -ICLASS: VPCMPGTD +ICLASS: VPSRAD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -36801,45 +41344,45 @@ ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x66 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi32 MEM0:r:vv:i32:TXT=BCASTSTR -IFORM: VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_MEMi32_AVX512 +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSRAD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 } -# EMITTING VPCMPGTQ (VPCMPGTQ-512-1) +# EMITTING VPSRAQ (VPSRAQ-512-1) { -ICLASS: VPCMPGTQ +ICLASS: VPSRAQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x37 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi64 REG3=ZMM_B3():r:zi64 -IFORM: VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_AVX512 +PATTERN: EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 } { -ICLASS: VPCMPGTQ +ICLASS: VPSRAQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x37 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi64 MEM0:r:vv:i64:TXT=BCASTSTR -IFORM: VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_64_BITS() NELEM_MEM128() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:dq:u64 +IFORM: VPSRAQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 } -# EMITTING VPCMPQ (VPCMPQ-512-1) +# EMITTING VPSRAQ (VPSRAQ-512-2) { -ICLASS: VPCMPQ +ICLASS: VPSRAQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -36847,13 +41390,13 @@ ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 UIMM8() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi64 REG3=ZMM_B3():r:zi64 IMM0:r:b -IFORM: VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512 +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b +IFORM: VPSRAQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 } { -ICLASS: VPCMPQ +ICLASS: VPSRAQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -36861,15 +41404,15 @@ ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi64 MEM0:r:vv:i64:TXT=BCASTSTR IMM0:r:b -IFORM: VPCMPQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_IMM8_AVX512 +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPSRAQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 } -# EMITTING VPCMPUD (VPCMPUD-512-1) +# EMITTING VPSRAVD (VPSRAVD-512-1) { -ICLASS: VPCMPUD +ICLASS: VPSRAVD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -36877,13 +41420,13 @@ ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 IMM0:r:b -IFORM: VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 +PATTERN: EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPSRAVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 } { -ICLASS: VPCMPUD +ICLASS: VPSRAVD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -36891,15 +41434,15 @@ ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b -IFORM: VPCMPUD_MASKmskw_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 +PATTERN: EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSRAVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 } -# EMITTING VPCMPUQ (VPCMPUQ-512-1) +# EMITTING VPSRAVQ (VPSRAVQ-512-1) { -ICLASS: VPCMPUQ +ICLASS: VPSRAVQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -36907,13 +41450,13 @@ ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 UIMM8() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 IMM0:r:b -IFORM: VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 +PATTERN: EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 } { -ICLASS: VPCMPUQ +ICLASS: VPSRAVQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -36921,79 +41464,75 @@ ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b -IFORM: VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 +PATTERN: EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 } -# EMITTING VPCOMPRESSD (VPCOMPRESSD-512-1) +# EMITTING VPSRLD (VPSRLD-512-1) { -ICLASS: VPCOMPRESSD +ICLASS: VPSRLD CPL: 3 -CATEGORY: COMPRESS +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() -OPERANDS: MEM0:w:zd:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 -IFORM: VPCOMPRESSD_MEMu32_MASKmskw_ZMMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSRLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512 } - -# EMITTING VPCOMPRESSD (VPCOMPRESSD-512-2) { -ICLASS: VPCOMPRESSD +ICLASS: VPSRLD CPL: 3 -CATEGORY: COMPRESS +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=ZMM_B3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 -IFORM: VPCOMPRESSD_ZMMu32_MASKmskw_ZMMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xD2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_MEM128() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:dq:u32 +IFORM: VPSRLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 } -# EMITTING VPCOMPRESSQ (VPCOMPRESSQ-512-1) +# EMITTING VPSRLD (VPSRLD-512-2) { -ICLASS: VPCOMPRESSQ +ICLASS: VPSRLD CPL: 3 -CATEGORY: COMPRESS +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() -OPERANDS: MEM0:w:zd:u64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 -IFORM: VPCOMPRESSQ_MEMu64_MASKmskw_ZMMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b +IFORM: VPSRLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 } - -# EMITTING VPCOMPRESSQ (VPCOMPRESSQ-512-2) { -ICLASS: VPCOMPRESSQ +ICLASS: VPSRLD CPL: 3 -CATEGORY: COMPRESS +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR -OPERANDS: REG0=ZMM_B3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 -IFORM: VPCOMPRESSQ_ZMMu64_MASKmskw_ZMMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSRLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 } -# EMITTING VPERMD (VPERMD-512-1) +# EMITTING VPSRLQ (VPSRLQ-512-1) { -ICLASS: VPERMD +ICLASS: VPSRLQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -37001,359 +41540,359 @@ ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x36 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 -IFORM: VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +PATTERN: EVV 0xD3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 } { -ICLASS: VPERMD +ICLASS: VPSRLQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x36 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPERMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xD3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_64_BITS() NELEM_MEM128() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:dq:u64 +IFORM: VPSRLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 } -# EMITTING VPERMI2D (VPERMI2D-512-1) +# EMITTING VPSRLQ (VPSRLQ-512-2) { -ICLASS: VPERMI2D +ICLASS: VPSRLQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 -IFORM: VPERMI2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b +IFORM: VPSRLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 } { -ICLASS: VPERMI2D +ICLASS: VPSRLQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPERMI2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPSRLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 } -# EMITTING VPERMI2PD (VPERMI2PD-512-1) +# EMITTING VPSRLVD (VPSRLVD-512-1) { -ICLASS: VPERMI2PD +ICLASS: VPSRLVD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +PATTERN: EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPSRLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 } { -ICLASS: VPERMI2PD +ICLASS: VPSRLVD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSRLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 } -# EMITTING VPERMI2PS (VPERMI2PS-512-1) +# EMITTING VPSRLVQ (VPSRLVQ-512-1) { -ICLASS: VPERMI2PS +ICLASS: VPSRLVQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +PATTERN: EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 } { -ICLASS: VPERMI2PS +ICLASS: VPSRLVQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 } -# EMITTING VPERMI2Q (VPERMI2Q-512-1) +# EMITTING VPSUBD (VPSUBD-512-1) { -ICLASS: VPERMI2Q +ICLASS: VPSUBD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 -IFORM: VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +PATTERN: EVV 0xFA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPSUBD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 } { -ICLASS: VPERMI2Q +ICLASS: VPSUBD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xFA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSUBD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 } -# EMITTING VPERMILPD (VPERMILPD-512-1) +# EMITTING VPSUBQ (VPSUBQ-512-1) { -ICLASS: VPERMILPD +ICLASS: VPSUBQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x05 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b -IFORM: VPERMILPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +PATTERN: EVV 0xFB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPSUBQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 } { -ICLASS: VPERMILPD +ICLASS: VPSUBQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x05 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b -IFORM: VPERMILPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xFB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSUBQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 } -# EMITTING VPERMILPD (VPERMILPD-512-2) +# EMITTING VPTERNLOGD (VPTERNLOGD-512-1) { -ICLASS: VPERMILPD +ICLASS: VPTERNLOGD CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x0D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VPERMILPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +PATTERN: EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 IMM0:r:b +IFORM: VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 } { -ICLASS: VPERMILPD +ICLASS: VPTERNLOGD CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x0D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VPERMILPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 } -# EMITTING VPERMILPS (VPERMILPS-512-1) +# EMITTING VPTERNLOGQ (VPTERNLOGQ-512-1) { -ICLASS: VPERMILPS +ICLASS: VPTERNLOGQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x04 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b -IFORM: VPERMILPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 +PATTERN: EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 IMM0:r:b +IFORM: VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 } { -ICLASS: VPERMILPS +ICLASS: VPTERNLOGQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x04 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b -IFORM: VPERMILPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 } -# EMITTING VPERMILPS (VPERMILPS-512-2) +# EMITTING VPTESTMD (VPTESTMD-512-1) { -ICLASS: VPERMILPS +ICLASS: VPTESTMD CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x0C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VPERMILPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +PATTERN: EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPTESTMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 } { -ICLASS: VPERMILPS +ICLASS: VPTESTMD CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x0C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VPERMILPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPTESTMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512 } -# EMITTING VPERMPD (VPERMPD-512-1) +# EMITTING VPTESTMQ (VPTESTMQ-512-1) { -ICLASS: VPERMPD +ICLASS: VPTESTMQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x01 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b -IFORM: VPERMPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +PATTERN: EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512 } { -ICLASS: VPERMPD +ICLASS: VPTESTMQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x01 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b -IFORM: VPERMPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512 } -# EMITTING VPERMPD (VPERMPD-512-2) +# EMITTING VPTESTNMD (VPTESTNMD-512-1) { -ICLASS: VPERMPD +ICLASS: VPTESTNMD CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x16 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VPERMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +PATTERN: EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 } { -ICLASS: VPERMPD +ICLASS: VPTESTNMD CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x16 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VPERMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512 } -# EMITTING VPERMPS (VPERMPS-512-1) +# EMITTING VPTESTNMQ (VPTESTNMQ-512-1) { -ICLASS: VPERMPS +ICLASS: VPTESTNMQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x16 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +PATTERN: EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512 } { -ICLASS: VPERMPS +ICLASS: VPTESTNMQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x16 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VPERMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512 } -# EMITTING VPERMQ (VPERMQ-512-1) +# EMITTING VPUNPCKHDQ (VPUNPCKHDQ-512-1) { -ICLASS: VPERMQ +ICLASS: VPUNPCKHDQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -37361,13 +41900,13 @@ ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x00 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b -IFORM: VPERMQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 +PATTERN: EVV 0x6A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 } { -ICLASS: VPERMQ +ICLASS: VPUNPCKHDQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -37375,15 +41914,15 @@ ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x00 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b -IFORM: VPERMQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 +PATTERN: EVV 0x6A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 } -# EMITTING VPERMQ (VPERMQ-512-2) +# EMITTING VPUNPCKHQDQ (VPUNPCKHQDQ-512-1) { -ICLASS: VPERMQ +ICLASS: VPUNPCKHQDQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -37391,13 +41930,13 @@ ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x36 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +PATTERN: EVV 0x6D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 -IFORM: VPERMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +IFORM: VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 } { -ICLASS: VPERMQ +ICLASS: VPUNPCKHQDQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -37405,15 +41944,15 @@ ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x36 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +PATTERN: EVV 0x6D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPERMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +IFORM: VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 } -# EMITTING VPERMT2D (VPERMT2D-512-1) +# EMITTING VPUNPCKLDQ (VPUNPCKLDQ-512-1) { -ICLASS: VPERMT2D +ICLASS: VPUNPCKLDQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -37421,13 +41960,13 @@ ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 -IFORM: VPERMT2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +PATTERN: EVV 0x62 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 } { -ICLASS: VPERMT2D +ICLASS: VPUNPCKLDQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -37435,15 +41974,15 @@ ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPERMT2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +PATTERN: EVV 0x62 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 } -# EMITTING VPERMT2PD (VPERMT2PD-512-1) +# EMITTING VPUNPCKLQDQ (VPUNPCKLQDQ-512-1) { -ICLASS: VPERMT2PD +ICLASS: VPUNPCKLQDQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -37451,13 +41990,13 @@ ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +PATTERN: EVV 0x6C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 } { -ICLASS: VPERMT2PD +ICLASS: VPUNPCKLQDQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -37465,15149 +42004,15101 @@ ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +PATTERN: EVV 0x6C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 } -# EMITTING VPERMT2PS (VPERMT2PS-512-1) +# EMITTING VPXORD (VPXORD-512-1) { -ICLASS: VPERMT2PS +ICLASS: VPXORD CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +PATTERN: EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 } { -ICLASS: VPERMT2PS +ICLASS: VPXORD CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPXORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 } -# EMITTING VPERMT2Q (VPERMT2Q-512-1) +# EMITTING VPXORQ (VPXORQ-512-1) { -ICLASS: VPERMT2Q +ICLASS: VPXORQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 -IFORM: VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +PATTERN: EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 } { -ICLASS: VPERMT2Q +ICLASS: VPXORQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPXORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 } -# EMITTING VPEXPANDD (VPEXPANDD-512-1) +# EMITTING VRCP14PD (VRCP14PD-512-1) { -ICLASS: VPEXPANDD +ICLASS: VRCP14PD CPL: 3 -CATEGORY: EXPAND +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT() -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u32 -IFORM: VPEXPANDD_ZMMu32_MASKmskw_MEMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VRCP14PD_ZMMf64_MASKmskw_ZMMf64_AVX512 } - -# EMITTING VPEXPANDD (VPEXPANDD-512-2) { -ICLASS: VPEXPANDD +ICLASS: VRCP14PD CPL: 3 -CATEGORY: EXPAND +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 -IFORM: VPEXPANDD_ZMMu32_MASKmskw_ZMMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VRCP14PD_ZMMf64_MASKmskw_MEMf64_AVX512 } -# EMITTING VPEXPANDQ (VPEXPANDQ-512-1) +# EMITTING VRCP14PS (VRCP14PS-512-1) { -ICLASS: VPEXPANDQ +ICLASS: VRCP14PS CPL: 3 -CATEGORY: EXPAND +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT() -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u64 -IFORM: VPEXPANDQ_ZMMu64_MASKmskw_MEMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VRCP14PS_ZMMf32_MASKmskw_ZMMf32_AVX512 } - -# EMITTING VPEXPANDQ (VPEXPANDQ-512-2) { -ICLASS: VPEXPANDQ +ICLASS: VRCP14PS CPL: 3 -CATEGORY: EXPAND +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 -IFORM: VPEXPANDQ_ZMMu64_MASKmskw_ZMMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VRCP14PS_ZMMf32_MASKmskw_MEMf32_AVX512 } -# EMITTING VPGATHERDD (VPGATHERDD-512-1) +# EMITTING VRCP14SD (VRCP14SD-128-1) { -ICLASS: VPGATHERDD +ICLASS: VRCP14SD CPL: 3 -CATEGORY: GATHER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E12 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E10 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASKNOT0():rw:mskw MEM0:r:zd:u32 -IFORM: VPGATHERDD_ZMMu32_MASKmskw_MEMu32_AVX512_VL512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x4D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VRCP14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } - -# EMITTING VPGATHERDQ (VPGATHERDQ-512-1) { -ICLASS: VPGATHERDQ +ICLASS: VRCP14SD CPL: 3 -CATEGORY: GATHER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E12 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E10 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASKNOT0():rw:mskw MEM0:r:zd:u64 -IFORM: VPGATHERDQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x4D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VRCP14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 } -# EMITTING VPGATHERQD (VPGATHERQD-512-1) +# EMITTING VRCP14SS (VRCP14SS-128-1) { -ICLASS: VPGATHERQD +ICLASS: VRCP14SS CPL: 3 -CATEGORY: GATHER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E12 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E10 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASKNOT0():rw:mskw MEM0:r:qq:u32 -IFORM: VPGATHERQD_YMMu32_MASKmskw_MEMu32_AVX512_VL512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x4D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } - -# EMITTING VPGATHERQQ (VPGATHERQQ-512-1) { -ICLASS: VPGATHERQQ +ICLASS: VRCP14SS CPL: 3 -CATEGORY: GATHER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E12 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E10 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASKNOT0():rw:mskw MEM0:r:zd:u64 -IFORM: VPGATHERQQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x4D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VRCP14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 } -# EMITTING VPMAXSD (VPMAXSD-512-1) +# EMITTING VRNDSCALEPD (VRNDSCALEPD-512-1) { -ICLASS: VPMAXSD +ICLASS: VRNDSCALEPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 REG3=ZMM_B3():r:zi32 -IFORM: VPMAXSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x09 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 } { -ICLASS: VPMAXSD +ICLASS: VRNDSCALEPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 MEM0:r:vv:i32:TXT=BCASTSTR -IFORM: VPMAXSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x09 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 } - -# EMITTING VPMAXSQ (VPMAXSQ-512-1) { -ICLASS: VPMAXSQ +ICLASS: VRNDSCALEPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi64 REG3=ZMM_B3():r:zi64 -IFORM: VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x09 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VRNDSCALEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 } + +# EMITTING VRNDSCALEPS (VRNDSCALEPS-512-1) { -ICLASS: VPMAXSQ +ICLASS: VRNDSCALEPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi64 MEM0:r:vv:i64:TXT=BCASTSTR -IFORM: VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x08 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 } - -# EMITTING VPMAXUD (VPMAXUD-512-1) { -ICLASS: VPMAXUD +ICLASS: VRNDSCALEPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 -IFORM: VPMAXUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x08 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 } { -ICLASS: VPMAXUD +ICLASS: VRNDSCALEPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPMAXUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x08 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VRNDSCALEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 } -# EMITTING VPMAXUQ (VPMAXUQ-512-1) +# EMITTING VRNDSCALESD (VRNDSCALESD-128-1) { -ICLASS: VPMAXUQ +ICLASS: VRNDSCALESD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 -IFORM: VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x0B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 } { -ICLASS: VPMAXUQ +ICLASS: VRNDSCALESD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x0B V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VRNDSCALESD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x0B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b +IFORM: VRNDSCALESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 } -# EMITTING VPMINSD (VPMINSD-512-1) +# EMITTING VRNDSCALESS (VRNDSCALESS-128-1) { -ICLASS: VPMINSD +ICLASS: VRNDSCALESS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 REG3=ZMM_B3():r:zi32 -IFORM: VPMINSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x0A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 } { -ICLASS: VPMINSD +ICLASS: VRNDSCALESS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 MEM0:r:vv:i32:TXT=BCASTSTR -IFORM: VPMINSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x0A V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VRNDSCALESS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x0A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b +IFORM: VRNDSCALESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 } -# EMITTING VPMINSQ (VPMINSQ-512-1) +# EMITTING VRSQRT14PD (VRSQRT14PD-512-1) { -ICLASS: VPMINSQ +ICLASS: VRSQRT14PD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi64 REG3=ZMM_B3():r:zi64 -IFORM: VPMINSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VRSQRT14PD_ZMMf64_MASKmskw_ZMMf64_AVX512 } { -ICLASS: VPMINSQ +ICLASS: VRSQRT14PD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi64 MEM0:r:vv:i64:TXT=BCASTSTR -IFORM: VPMINSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VRSQRT14PD_ZMMf64_MASKmskw_MEMf64_AVX512 } -# EMITTING VPMINUD (VPMINUD-512-1) +# EMITTING VRSQRT14PS (VRSQRT14PS-512-1) { -ICLASS: VPMINUD +ICLASS: VRSQRT14PS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 -IFORM: VPMINUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VRSQRT14PS_ZMMf32_MASKmskw_ZMMf32_AVX512 } { -ICLASS: VPMINUD +ICLASS: VRSQRT14PS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPMINUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VRSQRT14PS_ZMMf32_MASKmskw_MEMf32_AVX512 } -# EMITTING VPMINUQ (VPMINUQ-512-1) +# EMITTING VRSQRT14SD (VRSQRT14SD-128-1) { -ICLASS: VPMINUQ +ICLASS: VRSQRT14SD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E10 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 -IFORM: VPMINUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x4F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VRSQRT14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VPMINUQ +ICLASS: VRSQRT14SD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E10 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPMINUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x4F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VRSQRT14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 } -# EMITTING VPMOVDB (VPMOVDB-512-1) +# EMITTING VRSQRT14SS (VRSQRT14SS-128-1) { -ICLASS: VPMOVDB +ICLASS: VRSQRT14SS CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E10 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x31 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 -IFORM: VPMOVDB_XMMu8_MASKmskw_ZMMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x4F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } - -# EMITTING VPMOVDB (VPMOVDB-512-2) { -ICLASS: VPMOVDB +ICLASS: VRSQRT14SS CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E10 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM -PATTERN: EVV 0x31 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() -OPERANDS: MEM0:w:dq:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 -IFORM: VPMOVDB_MEMu8_MASKmskw_ZMMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x4F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VRSQRT14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 } -# EMITTING VPMOVDW (VPMOVDW-512-1) +# EMITTING VSCALEFPD (VSCALEFPD-512-1) { -ICLASS: VPMOVDW +ICLASS: VSCALEFPD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x33 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=YMM_B3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 -IFORM: VPMOVDW_YMMu16_MASKmskw_ZMMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 } - -# EMITTING VPMOVDW (VPMOVDW-512-2) { -ICLASS: VPMOVDW +ICLASS: VSCALEFPD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM -PATTERN: EVV 0x33 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() -OPERANDS: MEM0:w:qq:u16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 -IFORM: VPMOVDW_MEMu16_MASKmskw_ZMMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 } - -# EMITTING VPMOVQB (VPMOVQB-512-1) { -ICLASS: VPMOVQB +ICLASS: VSCALEFPD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x32 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 -IFORM: VPMOVQB_XMMu8_MASKmskw_ZMMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 } -# EMITTING VPMOVQB (VPMOVQB-512-2) +# EMITTING VSCALEFPS (VSCALEFPS-512-1) { -ICLASS: VPMOVQB +ICLASS: VSCALEFPS CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM -PATTERN: EVV 0x32 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() -OPERANDS: MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 -IFORM: VPMOVQB_MEMu8_MASKmskw_ZMMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 } - -# EMITTING VPMOVQD (VPMOVQD-512-1) { -ICLASS: VPMOVQD +ICLASS: VSCALEFPS CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x35 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=YMM_B3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 -IFORM: VPMOVQD_YMMu32_MASKmskw_ZMMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 } - -# EMITTING VPMOVQD (VPMOVQD-512-2) { -ICLASS: VPMOVQD +ICLASS: VSCALEFPS CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM -PATTERN: EVV 0x35 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() -OPERANDS: MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 -IFORM: VPMOVQD_MEMu32_MASKmskw_ZMMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 } -# EMITTING VPMOVQW (VPMOVQW-512-1) +# EMITTING VSCALEFSD (VSCALEFSD-128-1) { -ICLASS: VPMOVQW +ICLASS: VSCALEFSD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x34 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 -IFORM: VPMOVQW_XMMu16_MASKmskw_ZMMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } - -# EMITTING VPMOVQW (VPMOVQW-512-2) { -ICLASS: VPMOVQW +ICLASS: VSCALEFSD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM -PATTERN: EVV 0x34 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() -OPERANDS: MEM0:w:dq:u16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 -IFORM: VPMOVQW_MEMu16_MASKmskw_ZMMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } - -# EMITTING VPMOVSDB (VPMOVSDB-512-1) { -ICLASS: VPMOVSDB +ICLASS: VSCALEFSD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x21 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zi32 -IFORM: VPMOVSDB_XMMi8_MASKmskw_ZMMi32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x2D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VSCALEFSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 } -# EMITTING VPMOVSDB (VPMOVSDB-512-2) +# EMITTING VSCALEFSS (VSCALEFSS-128-1) { -ICLASS: VPMOVSDB +ICLASS: VSCALEFSS CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM -PATTERN: EVV 0x21 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() -OPERANDS: MEM0:w:dq:i8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zi32 -IFORM: VPMOVSDB_MEMi8_MASKmskw_ZMMi32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } - -# EMITTING VPMOVSDW (VPMOVSDW-512-1) { -ICLASS: VPMOVSDW +ICLASS: VSCALEFSS CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x23 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=YMM_B3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zi32 -IFORM: VPMOVSDW_YMMi16_MASKmskw_ZMMi32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } - -# EMITTING VPMOVSDW (VPMOVSDW-512-2) { -ICLASS: VPMOVSDW +ICLASS: VSCALEFSS CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM -PATTERN: EVV 0x23 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() -OPERANDS: MEM0:w:qq:i16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zi32 -IFORM: VPMOVSDW_MEMi16_MASKmskw_ZMMi32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x2D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VSCALEFSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 } -# EMITTING VPMOVSQB (VPMOVSQB-512-1) +# EMITTING VSCATTERDPD (VSCATTERDPD-512-1) { -ICLASS: VPMOVSQB +ICLASS: VSCATTERDPD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: SCATTER EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E12 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x22 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zi64 -IFORM: VPMOVSQB_XMMi8_MASKmskw_ZMMi64_AVX512 +ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:q:f64 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zf64 +IFORM: VSCATTERDPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512 } -# EMITTING VPMOVSQB (VPMOVSQB-512-2) +# EMITTING VSCATTERDPS (VSCATTERDPS-512-1) { -ICLASS: VPMOVSQB +ICLASS: VSCATTERDPS CPL: 3 -CATEGORY: DATAXFER +CATEGORY: SCATTER EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E12 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM -PATTERN: EVV 0x22 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() -OPERANDS: MEM0:w:q:i8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zi64 -IFORM: VPMOVSQB_MEMi8_MASKmskw_ZMMi64_AVX512 +ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:d:f32 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zf32 +IFORM: VSCATTERDPS_MEMf32_MASKmskw_ZMMf32_AVX512_VL512 } -# EMITTING VPMOVSQD (VPMOVSQD-512-1) +# EMITTING VSCATTERQPD (VSCATTERQPD-512-1) { -ICLASS: VPMOVSQD +ICLASS: VSCATTERQPD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: SCATTER EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E12 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x25 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=YMM_B3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zi64 -IFORM: VPMOVSQD_YMMi32_MASKmskw_ZMMi64_AVX512 +ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:q:f64 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zf64 +IFORM: VSCATTERQPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512 } -# EMITTING VPMOVSQD (VPMOVSQD-512-2) +# EMITTING VSCATTERQPS (VSCATTERQPS-512-1) { -ICLASS: VPMOVSQD +ICLASS: VSCATTERQPS CPL: 3 -CATEGORY: DATAXFER +CATEGORY: SCATTER EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E12 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM -PATTERN: EVV 0x25 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() -OPERANDS: MEM0:w:qq:i32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zi64 -IFORM: VPMOVSQD_MEMi32_MASKmskw_ZMMi64_AVX512 +ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:d:f32 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:f32 +IFORM: VSCATTERQPS_MEMf32_MASKmskw_YMMf32_AVX512_VL512 } -# EMITTING VPMOVSQW (VPMOVSQW-512-1) +# EMITTING VSHUFF32X4 (VSHUFF32X4-512-1) { -ICLASS: VPMOVSQW +ICLASS: VSHUFF32X4 CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x24 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zi64 -IFORM: VPMOVSQW_XMMi16_MASKmskw_ZMMi64_AVX512 +PATTERN: EVV 0x23 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 } - -# EMITTING VPMOVSQW (VPMOVSQW-512-2) { -ICLASS: VPMOVSQW +ICLASS: VSHUFF32X4 CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM -PATTERN: EVV 0x24 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() -OPERANDS: MEM0:w:dq:i16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zi64 -IFORM: VPMOVSQW_MEMi16_MASKmskw_ZMMi64_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x23 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 } -# EMITTING VPMOVSXBD (VPMOVSXBD-512-1) +# EMITTING VSHUFF64X2 (VSHUFF64X2-512-1) { -ICLASS: VPMOVSXBD +ICLASS: VSHUFF64X2 CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E5 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x21 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 -IFORM: VPMOVSXBD_ZMMi32_MASKmskw_XMMi8_AVX512 +PATTERN: EVV 0x23 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 } { -ICLASS: VPMOVSXBD +ICLASS: VSHUFF64X2 CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E5 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM -PATTERN: EVV 0x21 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM() -OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i8 -IFORM: VPMOVSXBD_ZMMi32_MASKmskw_MEMi8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x23 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 } -# EMITTING VPMOVSXBQ (VPMOVSXBQ-512-1) +# EMITTING VSHUFI32X4 (VSHUFI32X4-512-1) { -ICLASS: VPMOVSXBQ +ICLASS: VSHUFI32X4 CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E5 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x22 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 -IFORM: VPMOVSXBQ_ZMMi64_MASKmskw_XMMi8_AVX512 +PATTERN: EVV 0x43 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 IMM0:r:b +IFORM: VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 } { -ICLASS: VPMOVSXBQ +ICLASS: VSHUFI32X4 CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E5 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM -PATTERN: EVV 0x22 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM() -OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8 -IFORM: VPMOVSXBQ_ZMMi64_MASKmskw_MEMi8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x43 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 } -# EMITTING VPMOVSXDQ (VPMOVSXDQ-512-1) +# EMITTING VSHUFI64X2 (VSHUFI64X2-512-1) { -ICLASS: VPMOVSXDQ +ICLASS: VSHUFI64X2 CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E5 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x25 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32 -IFORM: VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512 +PATTERN: EVV 0x43 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 IMM0:r:b +IFORM: VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 } { -ICLASS: VPMOVSXDQ +ICLASS: VSHUFI64X2 CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E5 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM -PATTERN: EVV 0x25 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM() -OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i32 -IFORM: VPMOVSXDQ_ZMMi64_MASKmskw_MEMi32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x43 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 } -# EMITTING VPMOVSXWD (VPMOVSXWD-512-1) +# EMITTING VSHUFPD (VSHUFPD-512-1) { -ICLASS: VPMOVSXWD +ICLASS: VSHUFPD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E5 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x23 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i16 -IFORM: VPMOVSXWD_ZMMi32_MASKmskw_YMMi16_AVX512 +PATTERN: EVV 0xC6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VSHUFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 } { -ICLASS: VPMOVSXWD +ICLASS: VSHUFPD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E5 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM -PATTERN: EVV 0x23 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() -OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i16 -IFORM: VPMOVSXWD_ZMMi32_MASKmskw_MEMi16_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 } -# EMITTING VPMOVSXWQ (VPMOVSXWQ-512-1) +# EMITTING VSHUFPS (VSHUFPS-512-1) { -ICLASS: VPMOVSXWQ +ICLASS: VSHUFPS CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E5 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x24 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 -IFORM: VPMOVSXWQ_ZMMi64_MASKmskw_XMMi16_AVX512 +PATTERN: EVV 0xC6 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VSHUFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 } { -ICLASS: VPMOVSXWQ +ICLASS: VSHUFPS CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E5 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM -PATTERN: EVV 0x24 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM() -OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i16 -IFORM: VPMOVSXWQ_ZMMi64_MASKmskw_MEMi16_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC6 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 } -# EMITTING VPMOVUSDB (VPMOVUSDB-512-1) +# EMITTING VSQRTPD (VSQRTPD-512-1) { -ICLASS: VPMOVUSDB +ICLASS: VSQRTPD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x11 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 -IFORM: VPMOVUSDB_XMMu8_MASKmskw_ZMMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x51 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512 } - -# EMITTING VPMOVUSDB (VPMOVUSDB-512-2) { -ICLASS: VPMOVUSDB +ICLASS: VSQRTPD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM -PATTERN: EVV 0x11 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() -OPERANDS: MEM0:w:dq:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 -IFORM: VPMOVUSDB_MEMu8_MASKmskw_ZMMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x51 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512 } - -# EMITTING VPMOVUSDW (VPMOVUSDW-512-1) { -ICLASS: VPMOVUSDW +ICLASS: VSQRTPD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x13 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=YMM_B3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 -IFORM: VPMOVUSDW_YMMu16_MASKmskw_ZMMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x51 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VSQRTPD_ZMMf64_MASKmskw_MEMf64_AVX512 } -# EMITTING VPMOVUSDW (VPMOVUSDW-512-2) +# EMITTING VSQRTPS (VSQRTPS-512-1) { -ICLASS: VPMOVUSDW +ICLASS: VSQRTPS CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM -PATTERN: EVV 0x13 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() -OPERANDS: MEM0:w:qq:u16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 -IFORM: VPMOVUSDW_MEMu16_MASKmskw_ZMMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x51 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512 } - -# EMITTING VPMOVUSQB (VPMOVUSQB-512-1) { -ICLASS: VPMOVUSQB +ICLASS: VSQRTPS CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x12 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 -IFORM: VPMOVUSQB_XMMu8_MASKmskw_ZMMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x51 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512 } - -# EMITTING VPMOVUSQB (VPMOVUSQB-512-2) { -ICLASS: VPMOVUSQB +ICLASS: VSQRTPS CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM -PATTERN: EVV 0x12 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() -OPERANDS: MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 -IFORM: VPMOVUSQB_MEMu8_MASKmskw_ZMMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x51 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VSQRTPS_ZMMf32_MASKmskw_MEMf32_AVX512 } -# EMITTING VPMOVUSQD (VPMOVUSQD-512-1) +# EMITTING VSQRTSD (VSQRTSD-128-1) { -ICLASS: VPMOVUSQD +ICLASS: VSQRTSD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x15 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=YMM_B3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 -IFORM: VPMOVUSQD_YMMu32_MASKmskw_ZMMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } - -# EMITTING VPMOVUSQD (VPMOVUSQD-512-2) { -ICLASS: VPMOVUSQD +ICLASS: VSQRTSD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM -PATTERN: EVV 0x15 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() -OPERANDS: MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 -IFORM: VPMOVUSQD_MEMu32_MASKmskw_ZMMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } - -# EMITTING VPMOVUSQW (VPMOVUSQW-512-1) { -ICLASS: VPMOVUSQW +ICLASS: VSQRTSD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x14 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 -IFORM: VPMOVUSQW_XMMu16_MASKmskw_ZMMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VSQRTSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 } -# EMITTING VPMOVUSQW (VPMOVUSQW-512-2) +# EMITTING VSQRTSS (VSQRTSS-128-1) { -ICLASS: VPMOVUSQW +ICLASS: VSQRTSS CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM -PATTERN: EVV 0x14 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() -OPERANDS: MEM0:w:dq:u16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 -IFORM: VPMOVUSQW_MEMu16_MASKmskw_ZMMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } - -# EMITTING VPMOVZXBD (VPMOVZXBD-512-1) { -ICLASS: VPMOVZXBD +ICLASS: VSQRTSS CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E5 -REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x31 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 -IFORM: VPMOVZXBD_ZMMi32_MASKmskw_XMMi8_AVX512 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VPMOVZXBD +ICLASS: VSQRTSS CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E5 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM -PATTERN: EVV 0x31 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM() -OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i8 -IFORM: VPMOVZXBD_ZMMi32_MASKmskw_MEMi8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VSQRTSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 } -# EMITTING VPMOVZXBQ (VPMOVZXBQ-512-1) +# EMITTING VSUBPD (VSUBPD-512-1) { -ICLASS: VPMOVZXBQ +ICLASS: VSUBPD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E5 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x32 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 -IFORM: VPMOVZXBQ_ZMMi64_MASKmskw_XMMi8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 } { -ICLASS: VPMOVZXBQ +ICLASS: VSUBPD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E5 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM -PATTERN: EVV 0x32 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM() -OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8 -IFORM: VPMOVZXBQ_ZMMi64_MASKmskw_MEMi8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5C V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 } - -# EMITTING VPMOVZXDQ (VPMOVZXDQ-512-1) { -ICLASS: VPMOVZXDQ +ICLASS: VSUBPD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E5 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x35 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32 -IFORM: VPMOVZXDQ_ZMMi64_MASKmskw_YMMi32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VSUBPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 } + +# EMITTING VSUBPS (VSUBPS-512-1) { -ICLASS: VPMOVZXDQ +ICLASS: VSUBPS CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E5 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM -PATTERN: EVV 0x35 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM() -OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i32 -IFORM: VPMOVZXDQ_ZMMi64_MASKmskw_MEMi32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5C VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 } - -# EMITTING VPMOVZXWD (VPMOVZXWD-512-1) { -ICLASS: VPMOVZXWD +ICLASS: VSUBPS CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E5 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x33 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i16 -IFORM: VPMOVZXWD_ZMMi32_MASKmskw_YMMi16_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5C VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 } { -ICLASS: VPMOVZXWD +ICLASS: VSUBPS CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E5 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM -PATTERN: EVV 0x33 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() -OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i16 -IFORM: VPMOVZXWD_ZMMi32_MASKmskw_MEMi16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5C VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VSUBPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 } -# EMITTING VPMOVZXWQ (VPMOVZXWQ-512-1) +# EMITTING VSUBSD (VSUBSD-128-1) { -ICLASS: VPMOVZXWQ +ICLASS: VSUBSD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E5 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x34 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 -IFORM: VPMOVZXWQ_ZMMi64_MASKmskw_XMMi16_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VPMOVZXWQ +ICLASS: VSUBSD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E5 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM -PATTERN: EVV 0x34 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM() -OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i16 -IFORM: VPMOVZXWQ_ZMMi64_MASKmskw_MEMi16_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } - -# EMITTING VPMULDQ (VPMULDQ-512-1) { -ICLASS: VPMULDQ +ICLASS: VSUBSD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 REG3=ZMM_B3():r:zi32 -IFORM: VPMULDQ_ZMMi64_MASKmskw_ZMMi32_ZMMi32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x5C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VSUBSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 } + +# EMITTING VSUBSS (VSUBSS-128-1) { -ICLASS: VPMULDQ +ICLASS: VSUBSS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 MEM0:r:vv:i32:TXT=BCASTSTR -IFORM: VPMULDQ_ZMMi64_MASKmskw_ZMMi32_MEMi32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } - -# EMITTING VPMULLD (VPMULLD-512-1) { -ICLASS: VPMULLD +ICLASS: VSUBSS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 -IFORM: VPMULLD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VPMULLD +ICLASS: VSUBSS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPMULLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x5C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VSUBSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 } -# EMITTING VPMULUDQ (VPMULUDQ-512-1) +# EMITTING VUCOMISD (VUCOMISD-128-1) { -ICLASS: VPMULUDQ +ICLASS: VUCOMISD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xF4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 -IFORM: VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_ZMMu32_AVX512 +FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():r:dq:f64 REG1=XMM_B3():r:dq:f64 +IFORM: VUCOMISD_XMMf64_XMMf64_AVX512 } { -ICLASS: VPMULUDQ +ICLASS: VUCOMISD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xF4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_MEMu32_AVX512 +FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2E V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():r:dq:f64:TXT=SAESTR REG1=XMM_B3():r:dq:f64 +IFORM: VUCOMISD_XMMf64_XMMf64_AVX512 } - -# EMITTING VPORD (VPORD-512-1) { -ICLASS: VPORD +ICLASS: VUCOMISD CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 -IFORM: VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x2E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():r:dq:f64 MEM0:r:q:f64 +IFORM: VUCOMISD_XMMf64_MEMf64_AVX512 } + +# EMITTING VUCOMISS (VUCOMISS-128-1) { -ICLASS: VPORD +ICLASS: VUCOMISS CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2E VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():r:dq:f32 REG1=XMM_B3():r:dq:f32 +IFORM: VUCOMISS_XMMf32_XMMf32_AVX512 } - -# EMITTING VPORQ (VPORQ-512-1) { -ICLASS: VPORQ +ICLASS: VUCOMISS CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 -IFORM: VPORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2E VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():r:dq:f32:TXT=SAESTR REG1=XMM_B3():r:dq:f32 +IFORM: VUCOMISS_XMMf32_XMMf32_AVX512 } { -ICLASS: VPORQ +ICLASS: VUCOMISS CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x2E VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():r:dq:f32 MEM0:r:d:f32 +IFORM: VUCOMISS_XMMf32_MEMf32_AVX512 } -# EMITTING VPROLD (VPROLD-512-1) +# EMITTING VUNPCKHPD (VUNPCKHPD-512-1) { -ICLASS: VPROLD +ICLASS: VUNPCKHPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL512 W0 UIMM8() -OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b -IFORM: VPROLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 +PATTERN: EVV 0x15 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 } { -ICLASS: VPROLD +ICLASS: VUNPCKHPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b -IFORM: VPROLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x15 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 } -# EMITTING VPROLQ (VPROLQ-512-1) +# EMITTING VUNPCKHPS (VUNPCKHPS-512-1) { -ICLASS: VPROLQ +ICLASS: VUNPCKHPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL512 W1 UIMM8() -OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b -IFORM: VPROLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 +PATTERN: EVV 0x15 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 } { -ICLASS: VPROLQ +ICLASS: VUNPCKHPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b -IFORM: VPROLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x15 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 } -# EMITTING VPROLVD (VPROLVD-512-1) +# EMITTING VUNPCKLPD (VUNPCKLPD-512-1) { -ICLASS: VPROLVD +ICLASS: VUNPCKLPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 -IFORM: VPROLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +PATTERN: EVV 0x14 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 } { -ICLASS: VPROLVD +ICLASS: VUNPCKLPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPROLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x14 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 } -# EMITTING VPROLVQ (VPROLVQ-512-1) +# EMITTING VUNPCKLPS (VUNPCKLPS-512-1) { -ICLASS: VPROLVQ +ICLASS: VUNPCKLPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 -IFORM: VPROLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +PATTERN: EVV 0x14 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 } { -ICLASS: VPROLVQ +ICLASS: VUNPCKLPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPROLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x14 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 } -# EMITTING VPRORD (VPRORD-512-1) +AVX_INSTRUCTIONS():: +# EMITTING KANDNW (KANDNW-256-1) { -ICLASS: VPRORD +ICLASS: KANDNW CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K20 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL512 W0 UIMM8() -OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b -IFORM: VPRORD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 +ATTRIBUTES: KMASK +PATTERN: VV1 0x42 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KANDNW_MASKmskw_MASKmskw_MASKmskw_AVX512 } + +# EMITTING KANDW (KANDW-256-1) { -ICLASS: VPRORD +ICLASS: KANDW CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K20 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b -IFORM: VPRORD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 +ATTRIBUTES: KMASK +PATTERN: VV1 0x41 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KANDW_MASKmskw_MASKmskw_MASKmskw_AVX512 } -# EMITTING VPRORQ (VPRORQ-512-1) +# EMITTING KMOVW (KMOVW-128-1) { -ICLASS: VPRORQ +ICLASS: KMOVW CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K21 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL512 W1 UIMM8() -OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b -IFORM: VPRORQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 +ATTRIBUTES: KMASK +PATTERN: VV1 0x90 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw:u16 +IFORM: KMOVW_MASKmskw_MASKu16_AVX512 } { -ICLASS: VPRORQ +ICLASS: KMOVW CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K21 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b -IFORM: VPRORQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 +ATTRIBUTES: KMASK +PATTERN: VV1 0x90 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL=0 W0 NOVSR +OPERANDS: REG0=MASK_R():w:mskw MEM0:r:wrd:u16 +IFORM: KMOVW_MASKmskw_MEMu16_AVX512 } -# EMITTING VPRORVD (VPRORVD-512-1) +# EMITTING KMOVW (KMOVW-128-2) { -ICLASS: VPRORVD +ICLASS: KMOVW CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K21 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 -IFORM: VPRORVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +ATTRIBUTES: KMASK +PATTERN: VV1 0x91 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL=0 W0 NOVSR +OPERANDS: MEM0:w:wrd:u16 REG0=MASK_R():r:mskw +IFORM: KMOVW_MEMu16_MASKmskw_AVX512 } + +# EMITTING KMOVW (KMOVW-128-3) { -ICLASS: VPRORVD +ICLASS: KMOVW +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K21 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x92 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR +OPERANDS: REG0=MASK_R():w:mskw REG1=GPR32_B():r:d:u32 +IFORM: KMOVW_MASKmskw_GPR32u32_AVX512 +} + + +# EMITTING KMOVW (KMOVW-128-4) +{ +ICLASS: KMOVW CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K20 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPRORVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +ATTRIBUTES: KMASK +PATTERN: VV1 0x93 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR +OPERANDS: REG0=GPR32_R():w:d:u32 REG1=MASK_B():r:mskw +IFORM: KMOVW_GPR32u32_MASKmskw_AVX512 } -# EMITTING VPRORVQ (VPRORVQ-512-1) +# EMITTING KNOTW (KNOTW-128-1) { -ICLASS: VPRORVQ +ICLASS: KNOTW CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K20 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 -IFORM: VPRORVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +ATTRIBUTES: KMASK +PATTERN: VV1 0x44 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw +IFORM: KNOTW_MASKmskw_MASKmskw_AVX512 } + +# EMITTING KORTESTW (KORTESTW-128-1) { -ICLASS: VPRORVQ +ICLASS: KORTESTW CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K20 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPRORVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] +ATTRIBUTES: KMASK +PATTERN: VV1 0x98 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR +OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw +IFORM: KORTESTW_MASKmskw_MASKmskw_AVX512 } -# EMITTING VPSCATTERDD (VPSCATTERDD-512-1) +# EMITTING KORW (KORW-256-1) { -ICLASS: VPSCATTERDD +ICLASS: KORW CPL: 3 -CATEGORY: SCATTER -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E12 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K20 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() -OPERANDS: MEM0:w:zd:u32 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zu32 -IFORM: VPSCATTERDD_MEMu32_MASKmskw_ZMMu32_AVX512_VL512 +ATTRIBUTES: KMASK +PATTERN: VV1 0x45 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KORW_MASKmskw_MASKmskw_MASKmskw_AVX512 } -# EMITTING VPSCATTERDQ (VPSCATTERDQ-512-1) +# EMITTING KSHIFTLW (KSHIFTLW-128-1) { -ICLASS: VPSCATTERDQ +ICLASS: KSHIFTLW CPL: 3 -CATEGORY: SCATTER -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E12 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K20 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() -OPERANDS: MEM0:w:zd:u64 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zu64 -IFORM: VPSCATTERDQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512 +ATTRIBUTES: KMASK +PATTERN: VV1 0x32 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b +IFORM: KSHIFTLW_MASKmskw_MASKmskw_IMM8_AVX512 } -# EMITTING VPSCATTERQD (VPSCATTERQD-512-1) +# EMITTING KSHIFTRW (KSHIFTRW-128-1) { -ICLASS: VPSCATTERQD +ICLASS: KSHIFTRW CPL: 3 -CATEGORY: SCATTER -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E12 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K20 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() -OPERANDS: MEM0:w:qq:u32 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:u32 -IFORM: VPSCATTERQD_MEMu32_MASKmskw_YMMu32_AVX512_VL512 +ATTRIBUTES: KMASK +PATTERN: VV1 0x30 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b +IFORM: KSHIFTRW_MASKmskw_MASKmskw_IMM8_AVX512 } -# EMITTING VPSCATTERQQ (VPSCATTERQQ-512-1) +# EMITTING KUNPCKBW (KUNPCKBW-256-1) { -ICLASS: VPSCATTERQQ +ICLASS: KUNPCKBW CPL: 3 -CATEGORY: SCATTER -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E12 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K20 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() -OPERANDS: MEM0:w:zd:u64 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zu64 -IFORM: VPSCATTERQQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512 +ATTRIBUTES: KMASK +PATTERN: VV1 0x4B V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KUNPCKBW_MASKmskw_MASKmskw_MASKmskw_AVX512 } -# EMITTING VPSHUFD (VPSHUFD-512-1) +# EMITTING KXNORW (KXNORW-256-1) { -ICLASS: VPSHUFD +ICLASS: KXNORW CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K20 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x70 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b -IFORM: VPSHUFD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 +ATTRIBUTES: KMASK +PATTERN: VV1 0x46 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KXNORW_MASKmskw_MASKmskw_MASKmskw_AVX512 } + +# EMITTING KXORW (KXORW-256-1) { -ICLASS: VPSHUFD +ICLASS: KXORW CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K20 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x70 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b -IFORM: VPSHUFD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 +ATTRIBUTES: KMASK +PATTERN: VV1 0x47 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KXORW_MASKmskw_MASKmskw_MASKmskw_AVX512 } -# EMITTING VPSLLD (VPSLLD-512-1) + + +###FILE: ../xed/datafiles/avx512cd/vconflict-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2018 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING VPBROADCASTMB2Q (VPBROADCASTMB2Q-512-1) { -ICLASS: VPSLLD +ICLASS: VPBROADCASTMB2Q CPL: 3 -CATEGORY: AVX512 +CATEGORY: BROADCAST EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512CD_512 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xF2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=XMM_B3():r:dq:u32 -IFORM: VPSLLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512 +PATTERN: EVV 0x2A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK_B():r:mskw:u64 EMX_BROADCAST_1TO8_8 +IFORM: VPBROADCASTMB2Q_ZMMu64_MASKu64_AVX512CD } + +# EMITTING VPBROADCASTMW2D (VPBROADCASTMW2D-512-1) { -ICLASS: VPSLLD +ICLASS: VPBROADCASTMW2D CPL: 3 -CATEGORY: AVX512 +CATEGORY: BROADCAST EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512CD_512 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 -PATTERN: EVV 0xF2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_MEM128() -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:dq:u32 -IFORM: VPSLLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +PATTERN: EVV 0x3A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK_B():r:mskw:u32 EMX_BROADCAST_1TO16_16 +IFORM: VPBROADCASTMW2D_ZMMu32_MASKu32_AVX512CD } -# EMITTING VPSLLD (VPSLLD-512-2) +# EMITTING VPCONFLICTD (VPCONFLICTD-512-1) { -ICLASS: VPSLLD +ICLASS: VPCONFLICTD CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONFLICT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512CD_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL512 W0 UIMM8() -OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b -IFORM: VPSLLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 +PATTERN: EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 +IFORM: VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD } { -ICLASS: VPSLLD +ICLASS: VPCONFLICTD CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONFLICT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512CD_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b -IFORM: VPSLLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPCONFLICTD_ZMMu32_MASKmskw_MEMu32_AVX512CD } -# EMITTING VPSLLQ (VPSLLQ-512-1) +# EMITTING VPCONFLICTQ (VPCONFLICTQ-512-1) { -ICLASS: VPSLLQ +ICLASS: VPCONFLICTQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONFLICT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 +ISA_SET: AVX512CD_512 EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xF3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=XMM_B3():r:dq:u64 -IFORM: VPSLLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 +PATTERN: EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD } { -ICLASS: VPSLLQ +ICLASS: VPCONFLICTQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONFLICT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 +ISA_SET: AVX512CD_512 EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 -PATTERN: EVV 0xF3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_64_BITS() NELEM_MEM128() -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:dq:u64 -IFORM: VPSLLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPCONFLICTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD } -# EMITTING VPSLLQ (VPSLLQ-512-2) +# EMITTING VPLZCNTD (VPLZCNTD-512-1) { -ICLASS: VPSLLQ +ICLASS: VPLZCNTD CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONFLICT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 +ISA_SET: AVX512CD_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL512 W1 UIMM8() -OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b -IFORM: VPSLLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 +PATTERN: EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 +IFORM: VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD } { -ICLASS: VPSLLQ +ICLASS: VPLZCNTD CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONFLICT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 +ISA_SET: AVX512CD_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b -IFORM: VPSLLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 +PATTERN: EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPLZCNTD_ZMMu32_MASKmskw_MEMu32_AVX512CD } -# EMITTING VPSLLVD (VPSLLVD-512-1) +# EMITTING VPLZCNTQ (VPLZCNTQ-512-1) { -ICLASS: VPSLLVD +ICLASS: VPLZCNTQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONFLICT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 +ISA_SET: AVX512CD_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 -IFORM: VPSLLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +PATTERN: EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD } { -ICLASS: VPSLLVD +ICLASS: VPLZCNTQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONFLICT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 +ISA_SET: AVX512CD_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPSLLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +PATTERN: EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPLZCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD } -# EMITTING VPSLLVQ (VPSLLVQ-512-1) + + +###FILE: ../xed/datafiles/avx512-skx/skx-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2018 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING VADDPD (VADDPD-128-1) { -ICLASS: VPSLLVQ +ICLASS: VADDPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 -IFORM: VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x58 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VPSLLVQ +ICLASS: VADDPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x58 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VADDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 } -# EMITTING VPSRAD (VPSRAD-512-1) +# EMITTING VADDPD (VADDPD-256-1) { -ICLASS: VPSRAD +ICLASS: VADDPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=XMM_B3():r:dq:u32 -IFORM: VPSRAD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x58 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 } { -ICLASS: VPSRAD +ICLASS: VADDPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 -PATTERN: EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_MEM128() -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:dq:u32 -IFORM: VPSRAD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x58 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VADDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 } -# EMITTING VPSRAD (VPSRAD-512-2) +# EMITTING VADDPS (VADDPS-128-1) { -ICLASS: VPSRAD +ICLASS: VADDPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL512 W0 UIMM8() -OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b -IFORM: VPSRAD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x58 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VPSRAD +ICLASS: VADDPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b -IFORM: VPSRAD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x58 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VADDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 } -# EMITTING VPSRAQ (VPSRAQ-512-1) +# EMITTING VADDPS (VADDPS-256-1) { -ICLASS: VPSRAQ +ICLASS: VADDPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=XMM_B3():r:dq:u64 -IFORM: VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x58 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 } { -ICLASS: VPSRAQ +ICLASS: VADDPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 -PATTERN: EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_64_BITS() NELEM_MEM128() -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:dq:u64 -IFORM: VPSRAQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x58 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VADDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 } -# EMITTING VPSRAQ (VPSRAQ-512-2) +# EMITTING VALIGND (VALIGND-128-1) { -ICLASS: VPSRAQ +ICLASS: VALIGND CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL512 W1 UIMM8() -OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b -IFORM: VPSRAQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 +PATTERN: EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 IMM0:r:b +IFORM: VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 } { -ICLASS: VPSRAQ +ICLASS: VALIGND CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b -IFORM: VPSRAQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VALIGND_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 } -# EMITTING VPSRAVD (VPSRAVD-512-1) +# EMITTING VALIGND (VALIGND-256-1) { -ICLASS: VPSRAVD +ICLASS: VALIGND CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 -IFORM: VPSRAVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +PATTERN: EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 IMM0:r:b +IFORM: VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 } { -ICLASS: VPSRAVD +ICLASS: VALIGND CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPSRAVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VALIGND_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 } -# EMITTING VPSRAVQ (VPSRAVQ-512-1) +# EMITTING VALIGNQ (VALIGNQ-128-1) { -ICLASS: VPSRAVQ +ICLASS: VALIGNQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 -IFORM: VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +PATTERN: EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 IMM0:r:b +IFORM: VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 } { -ICLASS: VPSRAVQ +ICLASS: VALIGNQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VALIGNQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 } -# EMITTING VPSRLD (VPSRLD-512-1) +# EMITTING VALIGNQ (VALIGNQ-256-1) { -ICLASS: VPSRLD +ICLASS: VALIGNQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xD2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=XMM_B3():r:dq:u32 -IFORM: VPSRLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512 +PATTERN: EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 } { -ICLASS: VPSRLD +ICLASS: VALIGNQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 -PATTERN: EVV 0xD2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_MEM128() -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:dq:u32 -IFORM: VPSRLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VALIGNQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 } -# EMITTING VPSRLD (VPSRLD-512-2) +# EMITTING VANDNPD (VANDNPD-128-1) { -ICLASS: VPSRLD +ICLASS: VANDNPD CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL_FP EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 +ISA_SET: AVX512DQ_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL512 W0 UIMM8() -OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b -IFORM: VPSRLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 +PATTERN: EVV 0x55 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VANDNPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 } { -ICLASS: VPSRLD +ICLASS: VANDNPD CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL_FP EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 +ISA_SET: AVX512DQ_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b -IFORM: VPSRLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 +PATTERN: EVV 0x55 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VANDNPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 } -# EMITTING VPSRLQ (VPSRLQ-512-1) +# EMITTING VANDNPD (VANDNPD-256-1) { -ICLASS: VPSRLQ +ICLASS: VANDNPD CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL_FP EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xD3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=XMM_B3():r:dq:u64 -IFORM: VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 +PATTERN: EVV 0x55 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VANDNPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 } { -ICLASS: VPSRLQ +ICLASS: VANDNPD CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL_FP EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 -PATTERN: EVV 0xD3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_64_BITS() NELEM_MEM128() -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:dq:u64 -IFORM: VPSRLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x55 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VANDNPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 } -# EMITTING VPSRLQ (VPSRLQ-512-2) +# EMITTING VANDNPD (VANDNPD-512-1) { -ICLASS: VPSRLQ +ICLASS: VANDNPD CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL_FP EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 +ISA_SET: AVX512DQ_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL512 W1 UIMM8() -OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b -IFORM: VPSRLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 +PATTERN: EVV 0x55 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 } { -ICLASS: VPSRLQ +ICLASS: VANDNPD CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL_FP EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 +ISA_SET: AVX512DQ_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b -IFORM: VPSRLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 +PATTERN: EVV 0x55 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VANDNPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 } -# EMITTING VPSRLVD (VPSRLVD-512-1) +# EMITTING VANDNPS (VANDNPS-128-1) { -ICLASS: VPSRLVD +ICLASS: VANDNPS CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL_FP EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 +ISA_SET: AVX512DQ_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 -IFORM: VPSRLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +PATTERN: EVV 0x55 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VANDNPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 } { -ICLASS: VPSRLVD +ICLASS: VANDNPS CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL_FP EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 +ISA_SET: AVX512DQ_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPSRLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +PATTERN: EVV 0x55 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VANDNPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 } -# EMITTING VPSRLVQ (VPSRLVQ-512-1) +# EMITTING VANDNPS (VANDNPS-256-1) { -ICLASS: VPSRLVQ +ICLASS: VANDNPS CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL_FP EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 +ISA_SET: AVX512DQ_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 -IFORM: VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +PATTERN: EVV 0x55 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VANDNPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 } { -ICLASS: VPSRLVQ +ICLASS: VANDNPS CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL_FP EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 +ISA_SET: AVX512DQ_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +PATTERN: EVV 0x55 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VANDNPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 } -# EMITTING VPSUBD (VPSUBD-512-1) +# EMITTING VANDNPS (VANDNPS-512-1) { -ICLASS: VPSUBD +ICLASS: VANDNPS CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL_FP EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 +ISA_SET: AVX512DQ_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xFA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +PATTERN: EVV 0x55 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 -IFORM: VPSUBD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +IFORM: VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 } { -ICLASS: VPSUBD +ICLASS: VANDNPS CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL_FP EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 +ISA_SET: AVX512DQ_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xFA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +PATTERN: EVV 0x55 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPSUBD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +IFORM: VANDNPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 } -# EMITTING VPSUBQ (VPSUBQ-512-1) +# EMITTING VANDPD (VANDPD-128-1) { -ICLASS: VPSUBQ +ICLASS: VANDPD CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL_FP EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 +ISA_SET: AVX512DQ_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xFB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 -IFORM: VPSUBQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +PATTERN: EVV 0x54 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VANDPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 } { -ICLASS: VPSUBQ +ICLASS: VANDPD CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL_FP EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 +ISA_SET: AVX512DQ_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xFB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPSUBQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +PATTERN: EVV 0x54 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VANDPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 } -# EMITTING VPTERNLOGD (VPTERNLOGD-512-1) +# EMITTING VANDPD (VANDPD-256-1) { -ICLASS: VPTERNLOGD +ICLASS: VANDPD CPL: 3 -CATEGORY: LOGICAL +CATEGORY: LOGICAL_FP EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 +ISA_SET: AVX512DQ_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() -OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 IMM0:r:b -IFORM: VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 +PATTERN: EVV 0x54 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VANDPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 } { -ICLASS: VPTERNLOGD +ICLASS: VANDPD CPL: 3 -CATEGORY: LOGICAL +CATEGORY: LOGICAL_FP EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 +ISA_SET: AVX512DQ_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b -IFORM: VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 +PATTERN: EVV 0x54 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VANDPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 } -# EMITTING VPTERNLOGQ (VPTERNLOGQ-512-1) +# EMITTING VANDPD (VANDPD-512-1) { -ICLASS: VPTERNLOGQ +ICLASS: VANDPD CPL: 3 -CATEGORY: LOGICAL +CATEGORY: LOGICAL_FP EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 +ISA_SET: AVX512DQ_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() -OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 IMM0:r:b -IFORM: VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 +PATTERN: EVV 0x54 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 } { -ICLASS: VPTERNLOGQ +ICLASS: VANDPD CPL: 3 -CATEGORY: LOGICAL +CATEGORY: LOGICAL_FP EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 +ISA_SET: AVX512DQ_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b -IFORM: VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 +PATTERN: EVV 0x54 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VANDPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 } -# EMITTING VPTESTMD (VPTESTMD-512-1) +# EMITTING VANDPS (VANDPS-128-1) { -ICLASS: VPTESTMD +ICLASS: VANDPS CPL: 3 -CATEGORY: LOGICAL +CATEGORY: LOGICAL_FP EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 +ISA_SET: AVX512DQ_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 -IFORM: VPTESTMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 +PATTERN: EVV 0x54 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VANDPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 } { -ICLASS: VPTESTMD +ICLASS: VANDPS CPL: 3 -CATEGORY: LOGICAL +CATEGORY: LOGICAL_FP EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 +ISA_SET: AVX512DQ_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPTESTMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512 +PATTERN: EVV 0x54 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VANDPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 } -# EMITTING VPTESTMQ (VPTESTMQ-512-1) +# EMITTING VANDPS (VANDPS-256-1) { -ICLASS: VPTESTMQ +ICLASS: VANDPS CPL: 3 -CATEGORY: LOGICAL +CATEGORY: LOGICAL_FP EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 +ISA_SET: AVX512DQ_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 -IFORM: VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512 +PATTERN: EVV 0x54 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VANDPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 } { -ICLASS: VPTESTMQ +ICLASS: VANDPS CPL: 3 -CATEGORY: LOGICAL +CATEGORY: LOGICAL_FP EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 +ISA_SET: AVX512DQ_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512 +PATTERN: EVV 0x54 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VANDPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 } -# EMITTING VPTESTNMD (VPTESTNMD-512-1) +# EMITTING VANDPS (VANDPS-512-1) { -ICLASS: VPTESTNMD +ICLASS: VANDPS CPL: 3 -CATEGORY: LOGICAL +CATEGORY: LOGICAL_FP EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 +ISA_SET: AVX512DQ_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 -IFORM: VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 +PATTERN: EVV 0x54 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 } { -ICLASS: VPTESTNMD +ICLASS: VANDPS CPL: 3 -CATEGORY: LOGICAL +CATEGORY: LOGICAL_FP EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 +ISA_SET: AVX512DQ_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512 +PATTERN: EVV 0x54 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VANDPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 } -# EMITTING VPTESTNMQ (VPTESTNMQ-512-1) +# EMITTING VBLENDMPD (VBLENDMPD-128-1) { -ICLASS: VPTESTNMQ +ICLASS: VBLENDMPD CPL: 3 -CATEGORY: LOGICAL +CATEGORY: BLEND EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 -IFORM: VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VBLENDMPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VPTESTNMQ +ICLASS: VBLENDMPD CPL: 3 -CATEGORY: LOGICAL +CATEGORY: BLEND EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL +PATTERN: EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VBLENDMPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 } -# EMITTING VPUNPCKHDQ (VPUNPCKHDQ-512-1) +# EMITTING VBLENDMPD (VBLENDMPD-256-1) { -ICLASS: VPUNPCKHDQ +ICLASS: VBLENDMPD CPL: 3 -CATEGORY: AVX512 +CATEGORY: BLEND EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x6A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 -IFORM: VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VBLENDMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 } { -ICLASS: VPUNPCKHDQ +ICLASS: VBLENDMPD CPL: 3 -CATEGORY: AVX512 +CATEGORY: BLEND EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x6A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL +PATTERN: EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VBLENDMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 } -# EMITTING VPUNPCKHQDQ (VPUNPCKHQDQ-512-1) +# EMITTING VBLENDMPS (VBLENDMPS-128-1) { -ICLASS: VPUNPCKHQDQ +ICLASS: VBLENDMPS CPL: 3 -CATEGORY: AVX512 +CATEGORY: BLEND EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x6D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 -IFORM: VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VBLENDMPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VPUNPCKHQDQ +ICLASS: VBLENDMPS CPL: 3 -CATEGORY: AVX512 +CATEGORY: BLEND EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x6D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL +PATTERN: EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VBLENDMPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 } -# EMITTING VPUNPCKLDQ (VPUNPCKLDQ-512-1) +# EMITTING VBLENDMPS (VBLENDMPS-256-1) { -ICLASS: VPUNPCKLDQ +ICLASS: VBLENDMPS CPL: 3 -CATEGORY: AVX512 +CATEGORY: BLEND EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x62 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 -IFORM: VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VBLENDMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 } { -ICLASS: VPUNPCKLDQ +ICLASS: VBLENDMPS CPL: 3 -CATEGORY: AVX512 +CATEGORY: BLEND EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x62 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL +PATTERN: EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VBLENDMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 } -# EMITTING VPUNPCKLQDQ (VPUNPCKLQDQ-512-1) +# EMITTING VBROADCASTF32X2 (VBROADCASTF32X2-256-1) { -ICLASS: VPUNPCKLQDQ +ICLASS: VBROADCASTF32X2 CPL: 3 -CATEGORY: AVX512 +CATEGORY: BROADCAST EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x6C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 -IFORM: VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +PATTERN: EVV 0x19 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 EMX_BROADCAST_2TO8_32 +IFORM: VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512 } { -ICLASS: VPUNPCKLQDQ +ICLASS: VBROADCASTF32X2 CPL: 3 -CATEGORY: AVX512 +CATEGORY: BROADCAST EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x6C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x19 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE2() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f32 EMX_BROADCAST_2TO8_32 +IFORM: VBROADCASTF32X2_YMMf32_MASKmskw_MEMf32_AVX512 } -# EMITTING VPXORD (VPXORD-512-1) +# EMITTING VBROADCASTF32X2 (VBROADCASTF32X2-512-1) { -ICLASS: VPXORD +ICLASS: VBROADCASTF32X2 CPL: 3 -CATEGORY: LOGICAL +CATEGORY: BROADCAST EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 -IFORM: VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +PATTERN: EVV 0x19 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 EMX_BROADCAST_2TO16_32 +IFORM: VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512 } { -ICLASS: VPXORD +ICLASS: VBROADCASTF32X2 CPL: 3 -CATEGORY: LOGICAL +CATEGORY: BROADCAST EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPXORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x19 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE2() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f32 EMX_BROADCAST_2TO16_32 +IFORM: VBROADCASTF32X2_ZMMf32_MASKmskw_MEMf32_AVX512 } -# EMITTING VPXORQ (VPXORQ-512-1) +# EMITTING VBROADCASTF32X4 (VBROADCASTF32X4-256-1) { -ICLASS: VPXORQ +ICLASS: VBROADCASTF32X4 CPL: 3 -CATEGORY: LOGICAL +CATEGORY: BROADCAST EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 -IFORM: VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x1A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE4() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32 EMX_BROADCAST_4TO8_32 +IFORM: VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512 } + +# EMITTING VBROADCASTF32X8 (VBROADCASTF32X8-512-1) { -ICLASS: VPXORQ +ICLASS: VBROADCASTF32X8 CPL: 3 -CATEGORY: LOGICAL +CATEGORY: BROADCAST EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPXORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE8 +PATTERN: EVV 0x1B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE8() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32 EMX_BROADCAST_8TO16_32 +IFORM: VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512 } -# EMITTING VRCP14PD (VRCP14PD-512-1) +# EMITTING VBROADCASTF64X2 (VBROADCASTF64X2-256-1) { -ICLASS: VRCP14PD +ICLASS: VBROADCASTF64X2 CPL: 3 -CATEGORY: AVX512 +CATEGORY: BROADCAST EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 -IFORM: VRCP14PD_ZMMf64_MASKmskw_ZMMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x1A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE2() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f64 EMX_BROADCAST_2TO4_64 +IFORM: VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512 } + +# EMITTING VBROADCASTF64X2 (VBROADCASTF64X2-512-1) { -ICLASS: VRCP14PD +ICLASS: VBROADCASTF64X2 CPL: 3 -CATEGORY: AVX512 +CATEGORY: BROADCAST EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VRCP14PD_ZMMf64_MASKmskw_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x1A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE2() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f64 EMX_BROADCAST_2TO8_64 +IFORM: VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512 } -# EMITTING VRCP14PS (VRCP14PS-512-1) +# EMITTING VBROADCASTI32X2 (VBROADCASTI32X2-128-1) { -ICLASS: VRCP14PS +ICLASS: VBROADCASTI32X2 CPL: 3 -CATEGORY: AVX512 +CATEGORY: BROADCAST EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 -IFORM: VRCP14PS_ZMMf32_MASKmskw_ZMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_2TO4_32 +IFORM: VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512 } { -ICLASS: VRCP14PS +ICLASS: VBROADCASTI32X2 CPL: 3 -CATEGORY: AVX512 +CATEGORY: BROADCAST EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VRCP14PS_ZMMf32_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE2() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u32 EMX_BROADCAST_2TO4_32 +IFORM: VBROADCASTI32X2_XMMu32_MASKmskw_MEMu32_AVX512 } -# EMITTING VRCP14SD (VRCP14SD-128-1) +# EMITTING VBROADCASTI32X2 (VBROADCASTI32X2-256-1) { -ICLASS: VRCP14SD +ICLASS: VBROADCASTI32X2 CPL: 3 -CATEGORY: AVX512 +CATEGORY: BROADCAST EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E10 +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x4D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VRCP14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_2TO8_32 +IFORM: VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512 } { -ICLASS: VRCP14SD +ICLASS: VBROADCASTI32X2 CPL: 3 -CATEGORY: AVX512 +CATEGORY: BROADCAST EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E10 +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0x4D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 -IFORM: VRCP14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE2() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u32 EMX_BROADCAST_2TO8_32 +IFORM: VBROADCASTI32X2_YMMu32_MASKmskw_MEMu32_AVX512 } -# EMITTING VRCP14SS (VRCP14SS-128-1) +# EMITTING VBROADCASTI32X2 (VBROADCASTI32X2-512-1) { -ICLASS: VRCP14SS +ICLASS: VBROADCASTI32X2 CPL: 3 -CATEGORY: AVX512 +CATEGORY: BROADCAST EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E10 +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x4D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_2TO16_32 +IFORM: VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512 } { -ICLASS: VRCP14SS +ICLASS: VBROADCASTI32X2 CPL: 3 -CATEGORY: AVX512 +CATEGORY: BROADCAST EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E10 +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0x4D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 -IFORM: VRCP14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE2() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u32 EMX_BROADCAST_2TO16_32 +IFORM: VBROADCASTI32X2_ZMMu32_MASKmskw_MEMu32_AVX512 } -# EMITTING VRNDSCALEPD (VRNDSCALEPD-512-1) +# EMITTING VBROADCASTI32X4 (VBROADCASTI32X4-256-1) { -ICLASS: VRNDSCALEPD +ICLASS: VBROADCASTI32X4 CPL: 3 -CATEGORY: AVX512 +CATEGORY: BROADCAST EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x09 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b -IFORM: VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x5A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE4() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u32 EMX_BROADCAST_4TO8_32 +IFORM: VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512 } + +# EMITTING VBROADCASTI32X8 (VBROADCASTI32X8-512-1) { -ICLASS: VRNDSCALEPD +ICLASS: VBROADCASTI32X8 CPL: 3 -CATEGORY: AVX512 +CATEGORY: BROADCAST EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x09 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR UIMM8() -OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b -IFORM: VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE8 +PATTERN: EVV 0x5B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE8() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u32 EMX_BROADCAST_8TO16_32 +IFORM: VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512 } + +# EMITTING VBROADCASTI64X2 (VBROADCASTI64X2-256-1) { -ICLASS: VRNDSCALEPD +ICLASS: VBROADCASTI64X2 CPL: 3 -CATEGORY: AVX512 +CATEGORY: BROADCAST EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x09 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b -IFORM: VRNDSCALEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x5A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE2() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u64 EMX_BROADCAST_2TO4_64 +IFORM: VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512 } -# EMITTING VRNDSCALEPS (VRNDSCALEPS-512-1) +# EMITTING VBROADCASTI64X2 (VBROADCASTI64X2-512-1) { -ICLASS: VRNDSCALEPS +ICLASS: VBROADCASTI64X2 CPL: 3 -CATEGORY: AVX512 +CATEGORY: BROADCAST EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x08 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b -IFORM: VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x5A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE2() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u64 EMX_BROADCAST_2TO8_64 +IFORM: VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512 } + +# EMITTING VBROADCASTSD (VBROADCASTSD-256-1) { -ICLASS: VRNDSCALEPS +ICLASS: VBROADCASTSD CPL: 3 -CATEGORY: AVX512 +CATEGORY: BROADCAST EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x08 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8() -OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b -IFORM: VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 +PATTERN: EVV 0x19 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE1() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f64 EMX_BROADCAST_1TO4_64 +IFORM: VBROADCASTSD_YMMf64_MASKmskw_MEMf64_AVX512 } + +# EMITTING VBROADCASTSD (VBROADCASTSD-256-2) { -ICLASS: VRNDSCALEPS +ICLASS: VBROADCASTSD CPL: 3 -CATEGORY: AVX512 +CATEGORY: BROADCAST EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x08 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b -IFORM: VRNDSCALEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x19 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 EMX_BROADCAST_1TO4_64 +IFORM: VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512 } -# EMITTING VRNDSCALESD (VRNDSCALESD-128-1) +# EMITTING VBROADCASTSS (VBROADCASTSS-128-1) { -ICLASS: VRNDSCALESD +ICLASS: VBROADCASTSS CPL: 3 -CATEGORY: AVX512 +CATEGORY: BROADCAST EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x0B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 UIMM8() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b -IFORM: VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 +PATTERN: EVV 0x18 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:f32 EMX_BROADCAST_1TO4_32 +IFORM: VBROADCASTSS_XMMf32_MASKmskw_MEMf32_AVX512 } + +# EMITTING VBROADCASTSS (VBROADCASTSS-128-2) { -ICLASS: VRNDSCALESD +ICLASS: VBROADCASTSS CPL: 3 -CATEGORY: AVX512 +CATEGORY: BROADCAST EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x0B V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 UIMM8() -OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b -IFORM: VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x18 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 EMX_BROADCAST_1TO4_32 +IFORM: VBROADCASTSS_XMMf32_MASKmskw_XMMf32_AVX512 } + +# EMITTING VBROADCASTSS (VBROADCASTSS-256-1) { -ICLASS: VRNDSCALESD +ICLASS: VBROADCASTSS CPL: 3 -CATEGORY: AVX512 +CATEGORY: BROADCAST EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0x0B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b -IFORM: VRNDSCALESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 +PATTERN: EVV 0x18 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:f32 EMX_BROADCAST_1TO8_32 +IFORM: VBROADCASTSS_YMMf32_MASKmskw_MEMf32_AVX512 } -# EMITTING VRNDSCALESS (VRNDSCALESS-128-1) +# EMITTING VBROADCASTSS (VBROADCASTSS-256-2) { -ICLASS: VRNDSCALESS +ICLASS: VBROADCASTSS CPL: 3 -CATEGORY: AVX512 +CATEGORY: BROADCAST EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x0A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 UIMM8() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b -IFORM: VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x18 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 EMX_BROADCAST_1TO8_32 +IFORM: VBROADCASTSS_YMMf32_MASKmskw_XMMf32_AVX512 } + +# EMITTING VCMPPD (VCMPPD-128-1) { -ICLASS: VRNDSCALESS +ICLASS: VCMPPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x0A V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8() -OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b -IFORM: VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xC2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 } { -ICLASS: VRNDSCALESS +ICLASS: VCMPPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0x0A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b -IFORM: VRNDSCALESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xC2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VCMPPD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 } -# EMITTING VRSQRT14PD (VRSQRT14PD-512-1) +# EMITTING VCMPPD (VCMPPD-256-1) { -ICLASS: VRSQRT14PD +ICLASS: VCMPPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 -IFORM: VRSQRT14PD_ZMMf64_MASKmskw_ZMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xC2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 IMM0:r:b +IFORM: VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 } { -ICLASS: VRSQRT14PD +ICLASS: VCMPPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VRSQRT14PD_ZMMf64_MASKmskw_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xC2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 } -# EMITTING VRSQRT14PS (VRSQRT14PS-512-1) +# EMITTING VCMPPS (VCMPPS-128-1) { -ICLASS: VRSQRT14PS +ICLASS: VCMPPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 -IFORM: VRSQRT14PS_ZMMf32_MASKmskw_ZMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xC2 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 } { -ICLASS: VRSQRT14PS +ICLASS: VCMPPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VRSQRT14PS_ZMMf32_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xC2 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VCMPPS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 } -# EMITTING VRSQRT14SD (VRSQRT14SD-128-1) +# EMITTING VCMPPS (VCMPPS-256-1) { -ICLASS: VRSQRT14SD +ICLASS: VCMPPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E10 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x4F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VRSQRT14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xC2 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 IMM0:r:b +IFORM: VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 } { -ICLASS: VRSQRT14SD +ICLASS: VCMPPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E10 -REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0x4F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 -IFORM: VRSQRT14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xC2 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 } -# EMITTING VRSQRT14SS (VRSQRT14SS-128-1) +# EMITTING VCOMPRESSPD (VCOMPRESSPD-128-1) { -ICLASS: VRSQRT14SS +ICLASS: VCOMPRESSPD CPL: 3 -CATEGORY: AVX512 +CATEGORY: COMPRESS EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E10 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x4F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:dq:f64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f64 +IFORM: VCOMPRESSPD_MEMf64_MASKmskw_XMMf64_AVX512 } + +# EMITTING VCOMPRESSPD (VCOMPRESSPD-128-2) { -ICLASS: VRSQRT14SS +ICLASS: VCOMPRESSPD CPL: 3 -CATEGORY: AVX512 +CATEGORY: COMPRESS EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E10 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0x4F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 -IFORM: VRSQRT14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f64 +IFORM: VCOMPRESSPD_XMMf64_MASKmskw_XMMf64_AVX512 } -# EMITTING VSCALEFPD (VSCALEFPD-512-1) +# EMITTING VCOMPRESSPD (VCOMPRESSPD-256-1) { -ICLASS: VSCALEFPD +ICLASS: VCOMPRESSPD CPL: 3 -CATEGORY: AVX512 +CATEGORY: COMPRESS EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:qq:f64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f64 +IFORM: VCOMPRESSPD_MEMf64_MASKmskw_YMMf64_AVX512 } + +# EMITTING VCOMPRESSPD (VCOMPRESSPD-256-2) { -ICLASS: VSCALEFPD +ICLASS: VCOMPRESSPD CPL: 3 -CATEGORY: AVX512 +CATEGORY: COMPRESS EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 -OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f64 +IFORM: VCOMPRESSPD_YMMf64_MASKmskw_YMMf64_AVX512 } + +# EMITTING VCOMPRESSPS (VCOMPRESSPS-128-1) { -ICLASS: VSCALEFPD +ICLASS: VCOMPRESSPS CPL: 3 -CATEGORY: AVX512 +CATEGORY: COMPRESS EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:dq:f32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f32 +IFORM: VCOMPRESSPS_MEMf32_MASKmskw_XMMf32_AVX512 } -# EMITTING VSCALEFPS (VSCALEFPS-512-1) +# EMITTING VCOMPRESSPS (VCOMPRESSPS-128-2) { -ICLASS: VSCALEFPS +ICLASS: VCOMPRESSPS CPL: 3 -CATEGORY: AVX512 +CATEGORY: COMPRESS EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f32 +IFORM: VCOMPRESSPS_XMMf32_MASKmskw_XMMf32_AVX512 } + +# EMITTING VCOMPRESSPS (VCOMPRESSPS-256-1) { -ICLASS: VSCALEFPS +ICLASS: VCOMPRESSPS CPL: 3 -CATEGORY: AVX512 +CATEGORY: COMPRESS EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 -OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:qq:f32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f32 +IFORM: VCOMPRESSPS_MEMf32_MASKmskw_YMMf32_AVX512 } + +# EMITTING VCOMPRESSPS (VCOMPRESSPS-256-2) { -ICLASS: VSCALEFPS +ICLASS: VCOMPRESSPS CPL: 3 -CATEGORY: AVX512 +CATEGORY: COMPRESS EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f32 +IFORM: VCOMPRESSPS_YMMf32_MASKmskw_YMMf32_AVX512 } -# EMITTING VSCALEFSD (VSCALEFSD-128-1) +# EMITTING VCVTDQ2PD (VCVTDQ2PD-128-1) { -ICLASS: VSCALEFSD +ICLASS: VCVTDQ2PD CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x2D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 +IFORM: VCVTDQ2PD_XMMf64_MASKmskw_XMMi32_AVX512 } { -ICLASS: VSCALEFSD +ICLASS: VCVTDQ2PD CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x2D V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 -OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED +PATTERN: EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VCVTDQ2PD_XMMf64_MASKmskw_MEMi32_AVX512 } + +# EMITTING VCVTDQ2PD (VCVTDQ2PD-256-1) { -ICLASS: VSCALEFSD +ICLASS: VCVTDQ2PD CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0x2D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 -IFORM: VSCALEFSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 +IFORM: VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512 } - -# EMITTING VSCALEFSS (VSCALEFSS-128-1) { -ICLASS: VSCALEFSS +ICLASS: VCVTDQ2PD CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x2D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED +PATTERN: EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VCVTDQ2PD_YMMf64_MASKmskw_MEMi32_AVX512 } + +# EMITTING VCVTDQ2PS (VCVTDQ2PS-128-1) { -ICLASS: VSCALEFSS +ICLASS: VCVTDQ2PS CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x2D V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 -OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 +IFORM: VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512 } { -ICLASS: VSCALEFSS +ICLASS: VCVTDQ2PS CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0x2D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 -IFORM: VSCALEFSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VCVTDQ2PS_XMMf32_MASKmskw_MEMi32_AVX512 } -# EMITTING VSCATTERDPD (VSCATTERDPD-512-1) +# EMITTING VCVTDQ2PS (VCVTDQ2PS-256-1) { -ICLASS: VSCATTERDPD +ICLASS: VCVTDQ2PS CPL: 3 -CATEGORY: SCATTER +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E12 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() -OPERANDS: MEM0:w:zd:f64 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zf64 -IFORM: VSCATTERDPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32 +IFORM: VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512 } - -# EMITTING VSCATTERDPS (VSCATTERDPS-512-1) { -ICLASS: VSCATTERDPS +ICLASS: VCVTDQ2PS CPL: 3 -CATEGORY: SCATTER +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E12 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() -OPERANDS: MEM0:w:zd:f32 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zf32 -IFORM: VSCATTERDPS_MEMf32_MASKmskw_ZMMf32_AVX512_VL512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VCVTDQ2PS_YMMf32_MASKmskw_MEMi32_AVX512 } -# EMITTING VSCATTERQPD (VSCATTERQPD-512-1) +# EMITTING VCVTPD2DQ (VCVTPD2DQ-128-1) { -ICLASS: VSCATTERQPD +ICLASS: VCVTPD2DQ CPL: 3 -CATEGORY: SCATTER +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E12 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() -OPERANDS: MEM0:w:zd:f64 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zf64 -IFORM: VSCATTERQPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xE6 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128 } - -# EMITTING VSCATTERQPS (VSCATTERQPS-512-1) { -ICLASS: VSCATTERQPS +ICLASS: VCVTPD2DQ CPL: 3 -CATEGORY: SCATTER +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E12 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() -OPERANDS: MEM0:w:qq:f32 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:f32 -IFORM: VSCATTERQPS_MEMf32_MASKmskw_YMMf32_AVX512_VL512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xE6 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128 } -# EMITTING VSHUFF32X4 (VSHUFF32X4-512-1) +# EMITTING VCVTPD2DQ (VCVTPD2DQ-256-1) { -ICLASS: VSHUFF32X4 +ICLASS: VCVTPD2DQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x23 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b -IFORM: VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xE6 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256 } { -ICLASS: VSHUFF32X4 +ICLASS: VCVTPD2DQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x23 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b -IFORM: VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xE6 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256 } -# EMITTING VSHUFF64X2 (VSHUFF64X2-512-1) +# EMITTING VCVTPD2PS (VCVTPD2PS-128-1) { -ICLASS: VSHUFF64X2 +ICLASS: VCVTPD2PS CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x23 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b -IFORM: VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128 } { -ICLASS: VSHUFF64X2 +ICLASS: VCVTPD2PS CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x23 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b -IFORM: VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128 } -# EMITTING VSHUFI32X4 (VSHUFI32X4-512-1) +# EMITTING VCVTPD2PS (VCVTPD2PS-256-1) { -ICLASS: VSHUFI32X4 +ICLASS: VCVTPD2PS CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x43 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 IMM0:r:b -IFORM: VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256 } { -ICLASS: VSHUFI32X4 +ICLASS: VCVTPD2PS CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x43 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b -IFORM: VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256 } -# EMITTING VSHUFI64X2 (VSHUFI64X2-512-1) +# EMITTING VCVTPD2QQ (VCVTPD2QQ-128-1) { -ICLASS: VSHUFI64X2 +ICLASS: VCVTPD2QQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x43 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 IMM0:r:b -IFORM: VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512 } { -ICLASS: VSHUFI64X2 +ICLASS: VCVTPD2QQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x43 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b -IFORM: VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512 } -# EMITTING VSHUFPD (VSHUFPD-512-1) +# EMITTING VCVTPD2QQ (VCVTPD2QQ-256-1) { -ICLASS: VSHUFPD +ICLASS: VCVTPD2QQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xC6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b -IFORM: VSHUFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512 } { -ICLASS: VSHUFPD +ICLASS: VCVTPD2QQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xC6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b -IFORM: VSHUFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512 } -# EMITTING VSHUFPS (VSHUFPS-512-1) +# EMITTING VCVTPD2QQ (VCVTPD2QQ-512-1) { -ICLASS: VSHUFPS +ICLASS: VCVTPD2QQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xC6 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b -IFORM: VSHUFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512 } { -ICLASS: VSHUFPS +ICLASS: VCVTPD2QQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xC6 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b -IFORM: VSHUFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512 } - -# EMITTING VSQRTPD (VSQRTPD-512-1) { -ICLASS: VSQRTPD +ICLASS: VCVTPD2QQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 +ISA_SET: AVX512DQ_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x51 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 -IFORM: VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512 } + +# EMITTING VCVTPD2UDQ (VCVTPD2UDQ-128-1) { -ICLASS: VSQRTPD +ICLASS: VCVTPD2UDQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x51 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 -IFORM: VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128 } { -ICLASS: VSQRTPD +ICLASS: VCVTPD2UDQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x51 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VSQRTPD_ZMMf64_MASKmskw_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128 } -# EMITTING VSQRTPS (VSQRTPS-512-1) +# EMITTING VCVTPD2UDQ (VCVTPD2UDQ-256-1) { -ICLASS: VSQRTPS +ICLASS: VCVTPD2UDQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x51 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 -IFORM: VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256 } { -ICLASS: VSQRTPS +ICLASS: VCVTPD2UDQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x51 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 -IFORM: VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256 } + +# EMITTING VCVTPD2UQQ (VCVTPD2UQQ-128-1) { -ICLASS: VSQRTPS +ICLASS: VCVTPD2UQQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 +ISA_SET: AVX512DQ_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x51 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VSQRTPS_ZMMf32_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512 } - -# EMITTING VSQRTSD (VSQRTSD-128-1) { -ICLASS: VSQRTSD +ICLASS: VCVTPD2UQQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512 } + +# EMITTING VCVTPD2UQQ (VCVTPD2UQQ-256-1) { -ICLASS: VSQRTSD +ICLASS: VCVTPD2UQQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 -OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512 } { -ICLASS: VSQRTSD +ICLASS: VCVTPD2UQQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 -IFORM: VSQRTSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512 } -# EMITTING VSQRTSS (VSQRTSS-128-1) +# EMITTING VCVTPD2UQQ (VCVTPD2UQQ-512-1) { -ICLASS: VSQRTSS +ICLASS: VCVTPD2UQQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512 } { -ICLASS: VSQRTSS +ICLASS: VCVTPD2UQQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 -OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512 } { -ICLASS: VSQRTSS +ICLASS: VCVTPD2UQQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 -IFORM: VSQRTSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512 } -# EMITTING VSUBPD (VSUBPD-512-1) +# EMITTING VCVTPH2PS (VCVTPH2PS-128-2) { -ICLASS: VSUBPD +ICLASS: VCVTPH2PS CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E11 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512 } { -ICLASS: VSUBPD +ICLASS: VCVTPH2PS CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E11 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5C V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 -OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR DISP8_HALFMEM +PATTERN: EVV 0x13 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f16 +IFORM: VCVTPH2PS_XMMf32_MASKmskw_MEMf16_AVX512 } + +# EMITTING VCVTPH2PS (VCVTPH2PS-256-2) { -ICLASS: VSUBPD +ICLASS: VCVTPH2PS CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E11 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x5C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VSUBPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512 } - -# EMITTING VSUBPS (VSUBPS-512-1) { -ICLASS: VSUBPS +ICLASS: VCVTPH2PS CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E11 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5C VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR DISP8_HALFMEM +PATTERN: EVV 0x13 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f16 +IFORM: VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512 } + +# EMITTING VCVTPS2DQ (VCVTPS2DQ-128-1) { -ICLASS: VSUBPS +ICLASS: VCVTPS2DQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5C VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 -OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512 } { -ICLASS: VSUBPS +ICLASS: VCVTPS2DQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x5C VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VSUBPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512 } -# EMITTING VSUBSD (VSUBSD-128-1) +# EMITTING VCVTPS2DQ (VCVTPS2DQ-256-1) { -ICLASS: VSUBSD +ICLASS: VCVTPS2DQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x5C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512 } { -ICLASS: VSUBSD +ICLASS: VCVTPS2DQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x5C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 -OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512 } + +# EMITTING VCVTPS2PD (VCVTPS2PD-128-1) { -ICLASS: VSUBSD +ICLASS: VCVTPS2PD CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0x5C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 -IFORM: VSUBSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5A VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTPS2PD_XMMf64_MASKmskw_XMMf32_AVX512 } - -# EMITTING VSUBSS (VSUBSS-128-1) { -ICLASS: VSUBSS +ICLASS: VCVTPS2PD CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x5C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5A VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512 } + +# EMITTING VCVTPS2PD (VCVTPS2PD-256-1) { -ICLASS: VSUBSS +ICLASS: VCVTPS2PD CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x5C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 -OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5A VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512 } { -ICLASS: VSUBSS +ICLASS: VCVTPS2PD CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0x5C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 -IFORM: VSUBSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5A VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512 } -# EMITTING VUCOMISD (VUCOMISD-128-1) +# EMITTING VCVTPS2PH (VCVTPS2PH-128-2) { -ICLASS: VUCOMISD +ICLASS: VCVTPS2PH CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E11NF REAL_OPCODE: Y -FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] -ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x2E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=XMM_R3():r:dq:f64 REG1=XMM_B3():r:dq:f64 -IFORM: VUCOMISD_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() +OPERANDS: REG0=XMM_B3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f32 IMM0:r:b +IFORM: VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512 } + +# EMITTING VCVTPS2PH (VCVTPS2PH-128-3) { -ICLASS: VUCOMISD +ICLASS: VCVTPS2PH CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E11 REAL_OPCODE: Y -FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] -ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x2E V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=XMM_R3():r:dq:f64:TXT=SAESTR REG1=XMM_B3():r:dq:f64 -IFORM: VUCOMISD_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR DISP8_HALFMEM +PATTERN: EVV 0x1D V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:q:f16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f32 IMM0:r:b +IFORM: VCVTPS2PH_MEMf16_MASKmskw_XMMf32_IMM8_AVX512 } + +# EMITTING VCVTPS2PH (VCVTPS2PH-256-2) { -ICLASS: VUCOMISD +ICLASS: VCVTPS2PH CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E11NF REAL_OPCODE: Y -FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] -ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_SCALAR -PATTERN: EVV 0x2E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():r:dq:f64 MEM0:r:q:f64 -IFORM: VUCOMISD_XMMf64_MEMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() +OPERANDS: REG0=XMM_B3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f32 IMM0:r:b +IFORM: VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512 } -# EMITTING VUCOMISS (VUCOMISS-128-1) +# EMITTING VCVTPS2PH (VCVTPS2PH-256-3) { -ICLASS: VUCOMISS +ICLASS: VCVTPS2PH CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E11 REAL_OPCODE: Y -FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] -ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x2E VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=XMM_R3():r:dq:f32 REG1=XMM_B3():r:dq:f32 -IFORM: VUCOMISS_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR DISP8_HALFMEM +PATTERN: EVV 0x1D V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:dq:f16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f32 IMM0:r:b +IFORM: VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512 } + +# EMITTING VCVTPS2QQ (VCVTPS2QQ-128-1) { -ICLASS: VUCOMISS +ICLASS: VCVTPS2QQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] -ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x2E VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=XMM_R3():r:dq:f32:TXT=SAESTR REG1=XMM_B3():r:dq:f32 -IFORM: VUCOMISS_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512 } { -ICLASS: VUCOMISS +ICLASS: VCVTPS2QQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_SCALAR -EXCEPTIONS: AVX512-E3NF +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] -ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_SCALAR -PATTERN: EVV 0x2E VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():r:dq:f32 MEM0:r:d:f32 -IFORM: VUCOMISS_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512 } -# EMITTING VUNPCKHPD (VUNPCKHPD-512-1) +# EMITTING VCVTPS2QQ (VCVTPS2QQ-256-1) { -ICLASS: VUNPCKHPD +ICLASS: VCVTPS2QQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x15 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512 } { -ICLASS: VUNPCKHPD +ICLASS: VCVTPS2QQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x15 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512 } -# EMITTING VUNPCKHPS (VUNPCKHPS-512-1) -{ -ICLASS: VUNPCKHPS -CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF -REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x15 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 -} - +# EMITTING VCVTPS2QQ (VCVTPS2QQ-512-1) { -ICLASS: VUNPCKHPS +ICLASS: VCVTPS2QQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x15 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512 } - -# EMITTING VUNPCKLPD (VUNPCKLPD-512-1) { -ICLASS: VUNPCKLPD +ICLASS: VCVTPS2QQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x14 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512 } { -ICLASS: VUNPCKLPD +ICLASS: VCVTPS2QQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x14 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512 } -# EMITTING VUNPCKLPS (VUNPCKLPS-512-1) +# EMITTING VCVTPS2UDQ (VCVTPS2UDQ-128-1) { -ICLASS: VUNPCKLPS +ICLASS: VCVTPS2UDQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x14 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512 } { -ICLASS: VUNPCKLPS +ICLASS: VCVTPS2UDQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x14 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512 } -AVX_INSTRUCTIONS():: -# EMITTING KANDNW (KANDNW-256-1) +# EMITTING VCVTPS2UDQ (VCVTPS2UDQ-256-1) { -ICLASS: KANDNW +ICLASS: VCVTPS2UDQ CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512F_KOP -EXCEPTIONS: AVX512-K20 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x42 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw -IFORM: KANDNW_MASKmskw_MASKmskw_MASKmskw_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512 } - -# EMITTING KANDW (KANDW-256-1) { -ICLASS: KANDW +ICLASS: VCVTPS2UDQ CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512F_KOP -EXCEPTIONS: AVX512-K20 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x41 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw -IFORM: KANDW_MASKmskw_MASKmskw_MASKmskw_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512 } -# EMITTING KMOVW (KMOVW-128-1) +# EMITTING VCVTPS2UQQ (VCVTPS2UQQ-128-1) { -ICLASS: KMOVW +ICLASS: VCVTPS2UQQ CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512F_KOP -EXCEPTIONS: AVX512-K21 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x90 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw:u16 -IFORM: KMOVW_MASKmskw_MASKu16_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512 } { -ICLASS: KMOVW +ICLASS: VCVTPS2UQQ CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512F_KOP -EXCEPTIONS: AVX512-K21 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x90 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL=0 W0 NOVSR -OPERANDS: REG0=MASK_R():w:mskw MEM0:r:wrd:u16 -IFORM: KMOVW_MASKmskw_MEMu16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512 } -# EMITTING KMOVW (KMOVW-128-2) +# EMITTING VCVTPS2UQQ (VCVTPS2UQQ-256-1) { -ICLASS: KMOVW +ICLASS: VCVTPS2UQQ CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512F_KOP -EXCEPTIONS: AVX512-K21 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x91 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL=0 W0 NOVSR -OPERANDS: MEM0:w:wrd:u16 REG0=MASK_R():r:mskw -IFORM: KMOVW_MEMu16_MASKmskw_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512 } - -# EMITTING KMOVW (KMOVW-128-3) { -ICLASS: KMOVW +ICLASS: VCVTPS2UQQ CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512F_KOP -EXCEPTIONS: AVX512-K21 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x92 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR -OPERANDS: REG0=MASK_R():w:mskw REG1=GPR32_B():r:d:u32 -IFORM: KMOVW_MASKmskw_GPR32u32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512 } -# EMITTING KMOVW (KMOVW-128-4) +# EMITTING VCVTPS2UQQ (VCVTPS2UQQ-512-1) { -ICLASS: KMOVW +ICLASS: VCVTPS2UQQ CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512F_KOP -EXCEPTIONS: AVX512-K20 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x93 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR -OPERANDS: REG0=GPR32_R():w:d:u32 REG1=MASK_B():r:mskw -IFORM: KMOVW_GPR32u32_MASKmskw_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512 } - -# EMITTING KNOTW (KNOTW-128-1) { -ICLASS: KNOTW +ICLASS: VCVTPS2UQQ CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512F_KOP -EXCEPTIONS: AVX512-K20 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x44 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw -IFORM: KNOTW_MASKmskw_MASKmskw_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512 } - -# EMITTING KORTESTW (KORTESTW-128-1) { -ICLASS: KORTESTW +ICLASS: VCVTPS2UQQ CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512F_KOP -EXCEPTIONS: AVX512-K20 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] -ATTRIBUTES: KMASK -PATTERN: VV1 0x98 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR -OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw -IFORM: KORTESTW_MASKmskw_MASKmskw_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512 } -# EMITTING KORW (KORW-256-1) +# EMITTING VCVTQQ2PD (VCVTQQ2PD-128-1) { -ICLASS: KORW +ICLASS: VCVTQQ2PD CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512F_KOP -EXCEPTIONS: AVX512-K20 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x45 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw -IFORM: KORW_MASKmskw_MASKmskw_MASKmskw_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512 } - -# EMITTING KSHIFTLW (KSHIFTLW-128-1) { -ICLASS: KSHIFTLW +ICLASS: VCVTQQ2PD CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512F_KOP -EXCEPTIONS: AVX512-K20 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x32 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR UIMM8() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b -IFORM: KSHIFTLW_MASKmskw_MASKmskw_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTQQ2PD_XMMi64_MASKmskw_MEMf64_AVX512 } -# EMITTING KSHIFTRW (KSHIFTRW-128-1) +# EMITTING VCVTQQ2PD (VCVTQQ2PD-256-1) { -ICLASS: KSHIFTRW +ICLASS: VCVTQQ2PD CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512F_KOP -EXCEPTIONS: AVX512-K20 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x30 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR UIMM8() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b -IFORM: KSHIFTRW_MASKmskw_MASKmskw_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512 } - -# EMITTING KUNPCKBW (KUNPCKBW-256-1) { -ICLASS: KUNPCKBW +ICLASS: VCVTQQ2PD CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512F_KOP -EXCEPTIONS: AVX512-K20 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x4B V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw -IFORM: KUNPCKBW_MASKmskw_MASKmskw_MASKmskw_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTQQ2PD_YMMi64_MASKmskw_MEMf64_AVX512 } -# EMITTING KXNORW (KXNORW-256-1) +# EMITTING VCVTQQ2PD (VCVTQQ2PD-512-1) { -ICLASS: KXNORW +ICLASS: VCVTQQ2PD CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512F_KOP -EXCEPTIONS: AVX512-K20 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x46 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw -IFORM: KXNORW_MASKmskw_MASKmskw_MASKmskw_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512 } - -# EMITTING KXORW (KXORW-256-1) { -ICLASS: KXORW +ICLASS: VCVTQQ2PD CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512F_KOP -EXCEPTIONS: AVX512-K20 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x47 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw -IFORM: KXORW_MASKmskw_MASKmskw_MASKmskw_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512 } - - - -###FILE: ../xed/datafiles/avx512cd/vconflict-isa.xed.txt - -#BEGIN_LEGAL -# -#Copyright (c) 2016 Intel Corporation -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -#END_LEGAL -# -# -# -# ***** GENERATED FILE -- DO NOT EDIT! ***** -# ***** GENERATED FILE -- DO NOT EDIT! ***** -# ***** GENERATED FILE -- DO NOT EDIT! ***** -# -# -# -EVEX_INSTRUCTIONS():: -# EMITTING VPBROADCASTMB2Q (VPBROADCASTMB2Q-512-1) { -ICLASS: VPBROADCASTMB2Q +ICLASS: VCVTQQ2PD CPL: 3 -CATEGORY: BROADCAST +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512CD_512 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -PATTERN: EVV 0x2A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK_B():r:mskw:u64 EMX_BROADCAST_1TO8_8 -IFORM: VPBROADCASTMB2Q_ZMMu64_MASKu64_AVX512CD +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTQQ2PD_ZMMi64_MASKmskw_MEMf64_AVX512 } -# EMITTING VPBROADCASTMW2D (VPBROADCASTMW2D-512-1) +# EMITTING VCVTQQ2PS (VCVTQQ2PS-128-1) { -ICLASS: VPBROADCASTMW2D +ICLASS: VCVTQQ2PS CPL: 3 -CATEGORY: BROADCAST +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512CD_512 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -PATTERN: EVV 0x3A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK_B():r:mskw:u32 EMX_BROADCAST_1TO16_16 -IFORM: VPBROADCASTMW2D_ZMMu32_MASKu32_AVX512CD +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 +IFORM: VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128 } - -# EMITTING VPCONFLICTD (VPCONFLICTD-512-1) { -ICLASS: VPCONFLICTD +ICLASS: VCVTQQ2PS CPL: 3 -CATEGORY: CONFLICT +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512CD_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 -IFORM: VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128 } + +# EMITTING VCVTQQ2PS (VCVTQQ2PS-256-1) { -ICLASS: VPCONFLICTD +ICLASS: VCVTQQ2PS CPL: 3 -CATEGORY: CONFLICT +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512CD_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPCONFLICTD_ZMMu32_MASKmskw_MEMu32_AVX512CD +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 +IFORM: VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256 } - -# EMITTING VPCONFLICTQ (VPCONFLICTQ-512-1) { -ICLASS: VPCONFLICTQ +ICLASS: VCVTQQ2PS CPL: 3 -CATEGORY: CONFLICT +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512CD_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 -IFORM: VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256 } + +# EMITTING VCVTQQ2PS (VCVTQQ2PS-512-1) { -ICLASS: VPCONFLICTQ +ICLASS: VCVTQQ2PS CPL: 3 -CATEGORY: CONFLICT +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512CD_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPCONFLICTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512 } - -# EMITTING VPLZCNTD (VPLZCNTD-512-1) { -ICLASS: VPLZCNTD +ICLASS: VCVTQQ2PS CPL: 3 -CATEGORY: CONFLICT +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512CD_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 -IFORM: VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512 } { -ICLASS: VPLZCNTD +ICLASS: VCVTQQ2PS CPL: 3 -CATEGORY: CONFLICT +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512CD_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPLZCNTD_ZMMu32_MASKmskw_MEMu32_AVX512CD +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512 } -# EMITTING VPLZCNTQ (VPLZCNTQ-512-1) +# EMITTING VCVTTPD2DQ (VCVTTPD2DQ-128-1) { -ICLASS: VPLZCNTQ +ICLASS: VCVTTPD2DQ CPL: 3 -CATEGORY: CONFLICT +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512CD_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 -IFORM: VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xE6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128 } { -ICLASS: VPLZCNTQ +ICLASS: VCVTTPD2DQ CPL: 3 -CATEGORY: CONFLICT +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512CD_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPLZCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xE6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128 } - - -###FILE: ../xed/datafiles/avx512-skx/skx-isa.xed.txt - -#BEGIN_LEGAL -# -#Copyright (c) 2016 Intel Corporation -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -#END_LEGAL -# -# -# -# ***** GENERATED FILE -- DO NOT EDIT! ***** -# ***** GENERATED FILE -- DO NOT EDIT! ***** -# ***** GENERATED FILE -- DO NOT EDIT! ***** -# -# -# -EVEX_INSTRUCTIONS():: -# EMITTING VADDPD (VADDPD-128-1) +# EMITTING VCVTTPD2DQ (VCVTTPD2DQ-256-1) { -ICLASS: VADDPD +ICLASS: VCVTTPD2DQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x58 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xE6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256 } { -ICLASS: VADDPD +ICLASS: VCVTTPD2DQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x58 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VADDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xE6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256 } -# EMITTING VADDPD (VADDPD-256-1) +# EMITTING VCVTTPD2QQ (VCVTTPD2QQ-128-1) { -ICLASS: VADDPD +ICLASS: VCVTTPD2QQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 +ISA_SET: AVX512DQ_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x58 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 -IFORM: VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512 } { -ICLASS: VADDPD +ICLASS: VCVTTPD2QQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 +ISA_SET: AVX512DQ_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x58 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VADDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512 } -# EMITTING VADDPS (VADDPS-128-1) +# EMITTING VCVTTPD2QQ (VCVTTPD2QQ-256-1) { -ICLASS: VADDPS +ICLASS: VCVTTPD2QQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512DQ_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x58 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512 } { -ICLASS: VADDPS +ICLASS: VCVTTPD2QQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512DQ_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x58 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VADDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512 } -# EMITTING VADDPS (VADDPS-256-1) +# EMITTING VCVTTPD2QQ (VCVTTPD2QQ-512-1) { -ICLASS: VADDPS +ICLASS: VCVTTPD2QQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 +ISA_SET: AVX512DQ_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x58 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 -IFORM: VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512 } { -ICLASS: VADDPS +ICLASS: VCVTTPD2QQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 +ISA_SET: AVX512DQ_512 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x58 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VADDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VCVTTPD2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512 } -# EMITTING VALIGND (VALIGND-128-1) +# EMITTING VCVTTPD2UDQ (VCVTTPD2UDQ-128-1) { -ICLASS: VALIGND +ICLASS: VCVTTPD2UDQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 IMM0:r:b -IFORM: VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128 } { -ICLASS: VALIGND +ICLASS: VCVTTPD2UDQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b -IFORM: VALIGND_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128 } -# EMITTING VALIGND (VALIGND-256-1) +# EMITTING VCVTTPD2UDQ (VCVTTPD2UDQ-256-1) { -ICLASS: VALIGND +ICLASS: VCVTTPD2UDQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 IMM0:r:b -IFORM: VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256 } { -ICLASS: VALIGND +ICLASS: VCVTTPD2UDQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b -IFORM: VALIGND_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256 } -# EMITTING VALIGNQ (VALIGNQ-128-1) +# EMITTING VCVTTPD2UQQ (VCVTTPD2UQQ-128-1) { -ICLASS: VALIGNQ +ICLASS: VCVTTPD2UQQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 IMM0:r:b -IFORM: VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512 } { -ICLASS: VALIGNQ +ICLASS: VCVTTPD2UQQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b -IFORM: VALIGNQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512 } -# EMITTING VALIGNQ (VALIGNQ-256-1) +# EMITTING VCVTTPD2UQQ (VCVTTPD2UQQ-256-1) { -ICLASS: VALIGNQ +ICLASS: VCVTTPD2UQQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 IMM0:r:b -IFORM: VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512 } { -ICLASS: VALIGNQ +ICLASS: VCVTTPD2UQQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b -IFORM: VALIGNQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512 } -# EMITTING VANDNPD (VANDNPD-128-1) +# EMITTING VCVTTPD2UQQ (VCVTTPD2UQQ-512-1) { -ICLASS: VANDNPD +ICLASS: VCVTTPD2UQQ CPL: 3 -CATEGORY: LOGICAL_FP +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x55 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VANDNPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512 } { -ICLASS: VANDNPD +ICLASS: VCVTTPD2UQQ CPL: 3 -CATEGORY: LOGICAL_FP +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x55 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VANDNPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VCVTTPD2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512 } -# EMITTING VANDNPD (VANDNPD-256-1) +# EMITTING VCVTTPS2DQ (VCVTTPS2DQ-128-1) { -ICLASS: VANDNPD +ICLASS: VCVTTPS2DQ CPL: 3 -CATEGORY: LOGICAL_FP +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x55 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 -IFORM: VANDNPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512 } { -ICLASS: VANDNPD +ICLASS: VCVTTPS2DQ CPL: 3 -CATEGORY: LOGICAL_FP +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x55 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VANDNPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512 } -# EMITTING VANDNPD (VANDNPD-512-1) +# EMITTING VCVTTPS2DQ (VCVTTPS2DQ-256-1) { -ICLASS: VANDNPD +ICLASS: VCVTTPS2DQ CPL: 3 -CATEGORY: LOGICAL_FP +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x55 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VANDNPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512 } { -ICLASS: VANDNPD +ICLASS: VCVTTPS2DQ CPL: 3 -CATEGORY: LOGICAL_FP +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x55 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VANDNPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512 } -# EMITTING VANDNPS (VANDNPS-128-1) +# EMITTING VCVTTPS2QQ (VCVTTPS2QQ-128-1) { -ICLASS: VANDNPS +ICLASS: VCVTTPS2QQ CPL: 3 -CATEGORY: LOGICAL_FP +CATEGORY: CONVERT EXTENSION: AVX512EVEX ISA_SET: AVX512DQ_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x55 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VANDNPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512 } { -ICLASS: VANDNPS +ICLASS: VCVTTPS2QQ CPL: 3 -CATEGORY: LOGICAL_FP +CATEGORY: CONVERT EXTENSION: AVX512EVEX ISA_SET: AVX512DQ_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x55 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VANDNPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512 } -# EMITTING VANDNPS (VANDNPS-256-1) +# EMITTING VCVTTPS2QQ (VCVTTPS2QQ-256-1) { -ICLASS: VANDNPS +ICLASS: VCVTTPS2QQ CPL: 3 -CATEGORY: LOGICAL_FP +CATEGORY: CONVERT EXTENSION: AVX512EVEX ISA_SET: AVX512DQ_256 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x55 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 -IFORM: VANDNPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512 } { -ICLASS: VANDNPS +ICLASS: VCVTTPS2QQ CPL: 3 -CATEGORY: LOGICAL_FP +CATEGORY: CONVERT EXTENSION: AVX512EVEX ISA_SET: AVX512DQ_256 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x55 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VANDNPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512 } -# EMITTING VANDNPS (VANDNPS-512-1) +# EMITTING VCVTTPS2QQ (VCVTTPS2QQ-512-1) { -ICLASS: VANDNPS +ICLASS: VCVTTPS2QQ CPL: 3 -CATEGORY: LOGICAL_FP +CATEGORY: CONVERT EXTENSION: AVX512EVEX ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x55 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VANDNPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512 } { -ICLASS: VANDNPS +ICLASS: VCVTTPS2QQ CPL: 3 -CATEGORY: LOGICAL_FP +CATEGORY: CONVERT EXTENSION: AVX512EVEX ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E4 -REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x55 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VANDNPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 -} - - -# EMITTING VANDPD (VANDPD-128-1) -{ -ICLASS: VANDPD -CPL: 3 -CATEGORY: LOGICAL_FP -EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x54 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VANDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512 } { -ICLASS: VANDPD +ICLASS: VCVTTPS2QQ CPL: 3 -CATEGORY: LOGICAL_FP +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x54 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VANDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512 } -# EMITTING VANDPD (VANDPD-256-1) +# EMITTING VCVTTPS2UDQ (VCVTTPS2UDQ-128-1) { -ICLASS: VANDPD +ICLASS: VCVTTPS2UDQ CPL: 3 -CATEGORY: LOGICAL_FP +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x54 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 -IFORM: VANDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512 } { -ICLASS: VANDPD +ICLASS: VCVTTPS2UDQ CPL: 3 -CATEGORY: LOGICAL_FP +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x54 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VANDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512 } -# EMITTING VANDPD (VANDPD-512-1) +# EMITTING VCVTTPS2UDQ (VCVTTPS2UDQ-256-1) { -ICLASS: VANDPD +ICLASS: VCVTTPS2UDQ CPL: 3 -CATEGORY: LOGICAL_FP +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x54 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VANDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512 } { -ICLASS: VANDPD +ICLASS: VCVTTPS2UDQ CPL: 3 -CATEGORY: LOGICAL_FP +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x54 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VANDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512 } -# EMITTING VANDPS (VANDPS-128-1) +# EMITTING VCVTTPS2UQQ (VCVTTPS2UQQ-128-1) { -ICLASS: VANDPS +ICLASS: VCVTTPS2UQQ CPL: 3 -CATEGORY: LOGICAL_FP +CATEGORY: CONVERT EXTENSION: AVX512EVEX ISA_SET: AVX512DQ_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x54 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VANDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512 } { -ICLASS: VANDPS +ICLASS: VCVTTPS2UQQ CPL: 3 -CATEGORY: LOGICAL_FP +CATEGORY: CONVERT EXTENSION: AVX512EVEX ISA_SET: AVX512DQ_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x54 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VANDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512 } -# EMITTING VANDPS (VANDPS-256-1) +# EMITTING VCVTTPS2UQQ (VCVTTPS2UQQ-256-1) { -ICLASS: VANDPS +ICLASS: VCVTTPS2UQQ CPL: 3 -CATEGORY: LOGICAL_FP +CATEGORY: CONVERT EXTENSION: AVX512EVEX ISA_SET: AVX512DQ_256 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x54 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 -IFORM: VANDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512 } { -ICLASS: VANDPS +ICLASS: VCVTTPS2UQQ CPL: 3 -CATEGORY: LOGICAL_FP +CATEGORY: CONVERT EXTENSION: AVX512EVEX ISA_SET: AVX512DQ_256 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x54 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VANDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512 } -# EMITTING VANDPS (VANDPS-512-1) +# EMITTING VCVTTPS2UQQ (VCVTTPS2UQQ-512-1) { -ICLASS: VANDPS +ICLASS: VCVTTPS2UQQ CPL: 3 -CATEGORY: LOGICAL_FP +CATEGORY: CONVERT EXTENSION: AVX512EVEX ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x54 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VANDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512 } { -ICLASS: VANDPS +ICLASS: VCVTTPS2UQQ CPL: 3 -CATEGORY: LOGICAL_FP +CATEGORY: CONVERT EXTENSION: AVX512EVEX ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x54 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VANDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512 } +{ +ICLASS: VCVTTPS2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512 +} -# EMITTING VBLENDMPD (VBLENDMPD-128-1) + +# EMITTING VCVTUDQ2PD (VCVTUDQ2PD-128-1) { -ICLASS: VBLENDMPD +ICLASS: VCVTUDQ2PD CPL: 3 -CATEGORY: BLEND +CATEGORY: CONVERT EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL -PATTERN: EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VBLENDMPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 +IFORM: VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512 } { -ICLASS: VBLENDMPD +ICLASS: VCVTUDQ2PD CPL: 3 -CATEGORY: BLEND +CATEGORY: CONVERT EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VBLENDMPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED +PATTERN: EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VCVTUDQ2PD_XMMf64_MASKmskw_MEMu32_AVX512 } -# EMITTING VBLENDMPD (VBLENDMPD-256-1) +# EMITTING VCVTUDQ2PD (VCVTUDQ2PD-256-1) { -ICLASS: VBLENDMPD +ICLASS: VCVTUDQ2PD CPL: 3 -CATEGORY: BLEND +CATEGORY: CONVERT EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL -PATTERN: EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 -IFORM: VBLENDMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 +IFORM: VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512 } { -ICLASS: VBLENDMPD +ICLASS: VCVTUDQ2PD CPL: 3 -CATEGORY: BLEND +CATEGORY: CONVERT EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VBLENDMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED +PATTERN: EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VCVTUDQ2PD_YMMf64_MASKmskw_MEMu32_AVX512 } -# EMITTING VBLENDMPS (VBLENDMPS-128-1) +# EMITTING VCVTUDQ2PS (VCVTUDQ2PS-128-1) { -ICLASS: VBLENDMPS +ICLASS: VCVTUDQ2PS CPL: 3 -CATEGORY: BLEND +CATEGORY: CONVERT EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL -PATTERN: EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VBLENDMPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 +IFORM: VCVTUDQ2PS_XMMf32_MASKmskw_XMMu32_AVX512 } { -ICLASS: VBLENDMPS +ICLASS: VCVTUDQ2PS CPL: 3 -CATEGORY: BLEND +CATEGORY: CONVERT EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VBLENDMPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VCVTUDQ2PS_XMMf32_MASKmskw_MEMu32_AVX512 } -# EMITTING VBLENDMPS (VBLENDMPS-256-1) +# EMITTING VCVTUDQ2PS (VCVTUDQ2PS-256-1) { -ICLASS: VBLENDMPS +ICLASS: VCVTUDQ2PS CPL: 3 -CATEGORY: BLEND +CATEGORY: CONVERT EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL -PATTERN: EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 -IFORM: VBLENDMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 +IFORM: VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512 } { -ICLASS: VBLENDMPS +ICLASS: VCVTUDQ2PS CPL: 3 -CATEGORY: BLEND +CATEGORY: CONVERT EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VBLENDMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VCVTUDQ2PS_YMMf32_MASKmskw_MEMu32_AVX512 } -# EMITTING VBROADCASTF32X2 (VBROADCASTF32X2-256-1) +# EMITTING VCVTUQQ2PD (VCVTUQQ2PD-128-1) { -ICLASS: VBROADCASTF32X2 +ICLASS: VCVTUQQ2PD CPL: 3 -CATEGORY: BROADCAST +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 -EXCEPTIONS: AVX512-E6 +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x19 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 EMX_BROADCAST_2TO8_32 -IFORM: VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 +IFORM: VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512 } { -ICLASS: VBROADCASTF32X2 +ICLASS: VCVTUQQ2PD CPL: 3 -CATEGORY: BROADCAST +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 -EXCEPTIONS: AVX512-E6 +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 -PATTERN: EVV 0x19 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE2() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f32 EMX_BROADCAST_2TO8_32 -IFORM: VBROADCASTF32X2_YMMf32_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VCVTUQQ2PD_XMMf64_MASKmskw_MEMu64_AVX512 } -# EMITTING VBROADCASTF32X2 (VBROADCASTF32X2-512-1) -{ -ICLASS: VBROADCASTF32X2 -CPL: 3 -CATEGORY: BROADCAST -EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E6 -REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x19 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 EMX_BROADCAST_2TO16_32 -IFORM: VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512 -} - +# EMITTING VCVTUQQ2PD (VCVTUQQ2PD-256-1) { -ICLASS: VBROADCASTF32X2 +ICLASS: VCVTUQQ2PD CPL: 3 -CATEGORY: BROADCAST +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E6 +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 -PATTERN: EVV 0x19 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE2() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f32 EMX_BROADCAST_2TO16_32 -IFORM: VBROADCASTF32X2_ZMMf32_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 +IFORM: VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512 } - -# EMITTING VBROADCASTF32X4 (VBROADCASTF32X4-256-1) { -ICLASS: VBROADCASTF32X4 +ICLASS: VCVTUQQ2PD CPL: 3 -CATEGORY: BROADCAST +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E6 +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE4 -PATTERN: EVV 0x1A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE4() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32 EMX_BROADCAST_4TO8_32 -IFORM: VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VCVTUQQ2PD_YMMf64_MASKmskw_MEMu64_AVX512 } -# EMITTING VBROADCASTF32X8 (VBROADCASTF32X8-512-1) +# EMITTING VCVTUQQ2PD (VCVTUQQ2PD-512-1) { -ICLASS: VBROADCASTF32X8 +ICLASS: VCVTUQQ2PD CPL: 3 -CATEGORY: BROADCAST +CATEGORY: CONVERT EXTENSION: AVX512EVEX ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E6 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE8 -PATTERN: EVV 0x1B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE8() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32 EMX_BROADCAST_8TO16_32 -IFORM: VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512 } - -# EMITTING VBROADCASTF64X2 (VBROADCASTF64X2-256-1) { -ICLASS: VBROADCASTF64X2 +ICLASS: VCVTUQQ2PD CPL: 3 -CATEGORY: BROADCAST +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 -EXCEPTIONS: AVX512-E6 +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 -PATTERN: EVV 0x1A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE2() -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f64 EMX_BROADCAST_2TO4_64 -IFORM: VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512 } - -# EMITTING VBROADCASTF64X2 (VBROADCASTF64X2-512-1) { -ICLASS: VBROADCASTF64X2 +ICLASS: VCVTUQQ2PD CPL: 3 -CATEGORY: BROADCAST +CATEGORY: CONVERT EXTENSION: AVX512EVEX ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E6 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 -PATTERN: EVV 0x1A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE2() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f64 EMX_BROADCAST_2TO8_64 -IFORM: VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VCVTUQQ2PD_ZMMf64_MASKmskw_MEMu64_AVX512 } -# EMITTING VBROADCASTI32X2 (VBROADCASTI32X2-128-1) +# EMITTING VCVTUQQ2PS (VCVTUQQ2PS-128-1) { -ICLASS: VBROADCASTI32X2 +ICLASS: VCVTUQQ2PS CPL: 3 -CATEGORY: BROADCAST +CATEGORY: CONVERT EXTENSION: AVX512EVEX ISA_SET: AVX512DQ_128 -EXCEPTIONS: AVX512-E6 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_2TO4_32 -IFORM: VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 +IFORM: VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128 } { -ICLASS: VBROADCASTI32X2 +ICLASS: VCVTUQQ2PS CPL: 3 -CATEGORY: BROADCAST +CATEGORY: CONVERT EXTENSION: AVX512EVEX ISA_SET: AVX512DQ_128 -EXCEPTIONS: AVX512-E6 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 -PATTERN: EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE2() -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u32 EMX_BROADCAST_2TO4_32 -IFORM: VBROADCASTI32X2_XMMu32_MASKmskw_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128 } -# EMITTING VBROADCASTI32X2 (VBROADCASTI32X2-256-1) +# EMITTING VCVTUQQ2PS (VCVTUQQ2PS-256-1) { -ICLASS: VBROADCASTI32X2 +ICLASS: VCVTUQQ2PS CPL: 3 -CATEGORY: BROADCAST +CATEGORY: CONVERT EXTENSION: AVX512EVEX ISA_SET: AVX512DQ_256 -EXCEPTIONS: AVX512-E6 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_2TO8_32 -IFORM: VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 +IFORM: VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256 } { -ICLASS: VBROADCASTI32X2 +ICLASS: VCVTUQQ2PS CPL: 3 -CATEGORY: BROADCAST +CATEGORY: CONVERT EXTENSION: AVX512EVEX ISA_SET: AVX512DQ_256 -EXCEPTIONS: AVX512-E6 -REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 -PATTERN: EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE2() -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u32 EMX_BROADCAST_2TO8_32 -IFORM: VBROADCASTI32X2_YMMu32_MASKmskw_MEMu32_AVX512 -} - - -# EMITTING VBROADCASTI32X2 (VBROADCASTI32X2-512-1) -{ -ICLASS: VBROADCASTI32X2 -CPL: 3 -CATEGORY: BROADCAST -EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E6 -REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_2TO16_32 -IFORM: VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512 -} - -{ -ICLASS: VBROADCASTI32X2 -CPL: 3 -CATEGORY: BROADCAST -EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E6 -REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 -PATTERN: EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE2() -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u32 EMX_BROADCAST_2TO16_32 -IFORM: VBROADCASTI32X2_ZMMu32_MASKmskw_MEMu32_AVX512 -} - - -# EMITTING VBROADCASTI32X4 (VBROADCASTI32X4-256-1) -{ -ICLASS: VBROADCASTI32X4 -CPL: 3 -CATEGORY: BROADCAST -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E6 -REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE4 -PATTERN: EVV 0x5A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE4() -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u32 EMX_BROADCAST_4TO8_32 -IFORM: VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512 -} - - -# EMITTING VBROADCASTI32X8 (VBROADCASTI32X8-512-1) -{ -ICLASS: VBROADCASTI32X8 -CPL: 3 -CATEGORY: BROADCAST -EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E6 -REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE8 -PATTERN: EVV 0x5B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE8() -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u32 EMX_BROADCAST_8TO16_32 -IFORM: VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256 } -# EMITTING VBROADCASTI64X2 (VBROADCASTI64X2-256-1) +# EMITTING VCVTUQQ2PS (VCVTUQQ2PS-512-1) { -ICLASS: VBROADCASTI64X2 +ICLASS: VCVTUQQ2PS CPL: 3 -CATEGORY: BROADCAST +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 -EXCEPTIONS: AVX512-E6 +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 -PATTERN: EVV 0x5A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE2() -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u64 EMX_BROADCAST_2TO4_64 -IFORM: VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512 } - -# EMITTING VBROADCASTI64X2 (VBROADCASTI64X2-512-1) { -ICLASS: VBROADCASTI64X2 +ICLASS: VCVTUQQ2PS CPL: 3 -CATEGORY: BROADCAST +CATEGORY: CONVERT EXTENSION: AVX512EVEX ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E6 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 -PATTERN: EVV 0x5A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE2() -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u64 EMX_BROADCAST_2TO8_64 -IFORM: VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512 } - -# EMITTING VBROADCASTSD (VBROADCASTSD-256-1) { -ICLASS: VBROADCASTSD +ICLASS: VCVTUQQ2PS CPL: 3 -CATEGORY: BROADCAST +CATEGORY: CONVERT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E6 +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 -PATTERN: EVV 0x19 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE1() -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f64 EMX_BROADCAST_1TO4_64 -IFORM: VBROADCASTSD_YMMf64_MASKmskw_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VCVTUQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512 } -# EMITTING VBROADCASTSD (VBROADCASTSD-256-2) +# EMITTING VDBPSADBW (VDBPSADBW-128-1) { -ICLASS: VBROADCASTSD +ICLASS: VDBPSADBW CPL: 3 -CATEGORY: BROADCAST +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E6 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x19 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 EMX_BROADCAST_1TO4_64 -IFORM: VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512 +PATTERN: EVV 0x42 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 IMM0:r:b +IFORM: VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 } - -# EMITTING VBROADCASTSS (VBROADCASTSS-128-1) { -ICLASS: VBROADCASTSS +ICLASS: VDBPSADBW CPL: 3 -CATEGORY: BROADCAST +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E6 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 -PATTERN: EVV 0x18 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:f32 EMX_BROADCAST_1TO4_32 -IFORM: VBROADCASTSS_XMMf32_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x42 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 IMM0:r:b +IFORM: VDBPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 } -# EMITTING VBROADCASTSS (VBROADCASTSS-128-2) +# EMITTING VDBPSADBW (VDBPSADBW-256-1) { -ICLASS: VBROADCASTSS +ICLASS: VDBPSADBW CPL: 3 -CATEGORY: BROADCAST +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E6 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x18 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 EMX_BROADCAST_1TO4_32 -IFORM: VBROADCASTSS_XMMf32_MASKmskw_XMMf32_AVX512 +PATTERN: EVV 0x42 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 IMM0:r:b +IFORM: VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 } - -# EMITTING VBROADCASTSS (VBROADCASTSS-256-1) { -ICLASS: VBROADCASTSS +ICLASS: VDBPSADBW CPL: 3 -CATEGORY: BROADCAST +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E6 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 -PATTERN: EVV 0x18 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:f32 EMX_BROADCAST_1TO8_32 -IFORM: VBROADCASTSS_YMMf32_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x42 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 IMM0:r:b +IFORM: VDBPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 } -# EMITTING VBROADCASTSS (VBROADCASTSS-256-2) +# EMITTING VDBPSADBW (VDBPSADBW-512-1) { -ICLASS: VBROADCASTSS +ICLASS: VDBPSADBW CPL: 3 -CATEGORY: BROADCAST +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E6 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x18 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 EMX_BROADCAST_1TO8_32 -IFORM: VBROADCASTSS_YMMf32_MASKmskw_XMMf32_AVX512 +PATTERN: EVV 0x42 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 IMM0:r:b +IFORM: VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 +} + +{ +ICLASS: VDBPSADBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x42 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 IMM0:r:b +IFORM: VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 } -# EMITTING VCMPPD (VCMPPD-128-1) +# EMITTING VDIVPD (VDIVPD-128-1) { -ICLASS: VCMPPD +ICLASS: VDIVPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xC2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 UIMM8() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b -IFORM: VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VCMPPD +ICLASS: VDIVPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xC2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b -IFORM: VCMPPD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VDIVPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 } -# EMITTING VCMPPD (VCMPPD-256-1) +# EMITTING VDIVPD (VDIVPD-256-1) { -ICLASS: VCMPPD +ICLASS: VDIVPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xC2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 UIMM8() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 IMM0:r:b -IFORM: VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 } { -ICLASS: VCMPPD +ICLASS: VDIVPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xC2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b -IFORM: VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VDIVPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 } -# EMITTING VCMPPS (VCMPPS-128-1) +# EMITTING VDIVPS (VDIVPS-128-1) { -ICLASS: VCMPPS +ICLASS: VDIVPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xC2 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b -IFORM: VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5E VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VCMPPS +ICLASS: VDIVPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xC2 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b -IFORM: VCMPPS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5E VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VDIVPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 } -# EMITTING VCMPPS (VCMPPS-256-1) +# EMITTING VDIVPS (VDIVPS-256-1) { -ICLASS: VCMPPS +ICLASS: VDIVPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xC2 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 IMM0:r:b -IFORM: VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5E VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 } { -ICLASS: VCMPPS +ICLASS: VDIVPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xC2 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b -IFORM: VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5E VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VDIVPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 } -# EMITTING VCOMPRESSPD (VCOMPRESSPD-128-1) +# EMITTING VEXPANDPD (VEXPANDPD-128-1) { -ICLASS: VCOMPRESSPD +ICLASS: VEXPANDPD CPL: 3 -CATEGORY: COMPRESS +CATEGORY: EXPAND EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() -OPERANDS: MEM0:w:dq:f64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f64 -IFORM: VCOMPRESSPD_MEMf64_MASKmskw_XMMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f64 +IFORM: VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512 } -# EMITTING VCOMPRESSPD (VCOMPRESSPD-128-2) +# EMITTING VEXPANDPD (VEXPANDPD-128-2) { -ICLASS: VCOMPRESSPD +ICLASS: VEXPANDPD CPL: 3 -CATEGORY: COMPRESS +CATEGORY: EXPAND EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f64 -IFORM: VCOMPRESSPD_XMMf64_MASKmskw_XMMf64_AVX512 +PATTERN: EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512 } -# EMITTING VCOMPRESSPD (VCOMPRESSPD-256-1) +# EMITTING VEXPANDPD (VEXPANDPD-256-1) { -ICLASS: VCOMPRESSPD +ICLASS: VEXPANDPD CPL: 3 -CATEGORY: COMPRESS +CATEGORY: EXPAND EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() -OPERANDS: MEM0:w:qq:f64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f64 -IFORM: VCOMPRESSPD_MEMf64_MASKmskw_YMMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f64 +IFORM: VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512 } -# EMITTING VCOMPRESSPD (VCOMPRESSPD-256-2) +# EMITTING VEXPANDPD (VEXPANDPD-256-2) { -ICLASS: VCOMPRESSPD +ICLASS: VEXPANDPD CPL: 3 -CATEGORY: COMPRESS +CATEGORY: EXPAND EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR -OPERANDS: REG0=YMM_B3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f64 -IFORM: VCOMPRESSPD_YMMf64_MASKmskw_YMMf64_AVX512 +PATTERN: EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512 } -# EMITTING VCOMPRESSPS (VCOMPRESSPS-128-1) +# EMITTING VEXPANDPS (VEXPANDPS-128-1) { -ICLASS: VCOMPRESSPS +ICLASS: VEXPANDPS CPL: 3 -CATEGORY: COMPRESS +CATEGORY: EXPAND EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() -OPERANDS: MEM0:w:dq:f32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f32 -IFORM: VCOMPRESSPS_MEMf32_MASKmskw_XMMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32 +IFORM: VEXPANDPS_XMMf32_MASKmskw_MEMf32_AVX512 } -# EMITTING VCOMPRESSPS (VCOMPRESSPS-128-2) +# EMITTING VEXPANDPS (VEXPANDPS-128-2) { -ICLASS: VCOMPRESSPS +ICLASS: VEXPANDPS CPL: 3 -CATEGORY: COMPRESS +CATEGORY: EXPAND EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f32 -IFORM: VCOMPRESSPS_XMMf32_MASKmskw_XMMf32_AVX512 +PATTERN: EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VEXPANDPS_XMMf32_MASKmskw_XMMf32_AVX512 } -# EMITTING VCOMPRESSPS (VCOMPRESSPS-256-1) +# EMITTING VEXPANDPS (VEXPANDPS-256-1) { -ICLASS: VCOMPRESSPS +ICLASS: VEXPANDPS CPL: 3 -CATEGORY: COMPRESS +CATEGORY: EXPAND EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() -OPERANDS: MEM0:w:qq:f32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f32 -IFORM: VCOMPRESSPS_MEMf32_MASKmskw_YMMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32 +IFORM: VEXPANDPS_YMMf32_MASKmskw_MEMf32_AVX512 } -# EMITTING VCOMPRESSPS (VCOMPRESSPS-256-2) +# EMITTING VEXPANDPS (VEXPANDPS-256-2) { -ICLASS: VCOMPRESSPS +ICLASS: VEXPANDPS CPL: 3 -CATEGORY: COMPRESS +CATEGORY: EXPAND EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=YMM_B3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f32 -IFORM: VCOMPRESSPS_YMMf32_MASKmskw_YMMf32_AVX512 -} - - -# EMITTING VCVTDQ2PD (VCVTDQ2PD-128-1) -{ -ICLASS: VCVTDQ2PD -CPL: 3 -CATEGORY: CONVERT -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E5 -REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 -IFORM: VCVTDQ2PD_XMMf64_MASKmskw_XMMi32_AVX512 -} - -{ -ICLASS: VCVTDQ2PD -CPL: 3 -CATEGORY: CONVERT -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E5 -REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED -PATTERN: EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR -IFORM: VCVTDQ2PD_XMMf64_MASKmskw_MEMi32_AVX512 +PATTERN: EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VEXPANDPS_YMMf32_MASKmskw_YMMf32_AVX512 } -# EMITTING VCVTDQ2PD (VCVTDQ2PD-256-1) +# EMITTING VEXTRACTF32X4 (VEXTRACTF32X4-256-1) { -ICLASS: VCVTDQ2PD +ICLASS: VEXTRACTF32X4 CPL: 3 -CATEGORY: CONVERT +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E5 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 -IFORM: VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512 +PATTERN: EVV 0x19 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() +OPERANDS: REG0=XMM_B3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f32 IMM0:r:b +IFORM: VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512 } + +# EMITTING VEXTRACTF32X4 (VEXTRACTF32X4-256-2) { -ICLASS: VCVTDQ2PD +ICLASS: VEXTRACTF32X4 CPL: 3 -CATEGORY: CONVERT +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E5 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED -PATTERN: EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR -IFORM: VCVTDQ2PD_YMMf64_MASKmskw_MEMi32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x19 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() +OPERANDS: MEM0:w:dq:f32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f32 IMM0:r:b +IFORM: VEXTRACTF32X4_MEMf32_MASKmskw_YMMf32_IMM8_AVX512 } -# EMITTING VCVTDQ2PS (VCVTDQ2PS-128-1) -{ -ICLASS: VCVTDQ2PS -CPL: 3 -CATEGORY: CONVERT -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 -REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 -IFORM: VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512 -} - +# EMITTING VEXTRACTF32X8 (VEXTRACTF32X8-512-1) { -ICLASS: VCVTDQ2PS +ICLASS: VEXTRACTF32X8 CPL: 3 -CATEGORY: CONVERT +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR -IFORM: VCVTDQ2PS_XMMf32_MASKmskw_MEMi32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +OPERANDS: REG0=YMM_B3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 IMM0:r:b +IFORM: VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512 } -# EMITTING VCVTDQ2PS (VCVTDQ2PS-256-1) -{ -ICLASS: VCVTDQ2PS -CPL: 3 -CATEGORY: CONVERT -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 -REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32 -IFORM: VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512 -} - +# EMITTING VEXTRACTF32X8 (VEXTRACTF32X8-512-2) { -ICLASS: VCVTDQ2PS +ICLASS: VEXTRACTF32X8 CPL: 3 -CATEGORY: CONVERT +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR -IFORM: VCVTDQ2PS_YMMf32_MASKmskw_MEMi32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE8 +PATTERN: EVV 0x1B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE8() +OPERANDS: MEM0:w:qq:f32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32 IMM0:r:b +IFORM: VEXTRACTF32X8_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512 } -# EMITTING VCVTPD2DQ (VCVTPD2DQ-128-1) -{ -ICLASS: VCVTPD2DQ -CPL: 3 -CATEGORY: CONVERT -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 -REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xE6 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 -IFORM: VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128 -} - +# EMITTING VEXTRACTF64X2 (VEXTRACTF64X2-256-1) { -ICLASS: VCVTPD2DQ +ICLASS: VEXTRACTF64X2 CPL: 3 -CATEGORY: CONVERT +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xE6 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x19 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() +OPERANDS: REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f64 IMM0:r:b +IFORM: VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512 } -# EMITTING VCVTPD2DQ (VCVTPD2DQ-256-1) -{ -ICLASS: VCVTPD2DQ -CPL: 3 -CATEGORY: CONVERT -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 -REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xE6 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 -IFORM: VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256 -} - +# EMITTING VEXTRACTF64X2 (VEXTRACTF64X2-256-2) { -ICLASS: VCVTPD2DQ +ICLASS: VEXTRACTF64X2 CPL: 3 -CATEGORY: CONVERT +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xE6 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256 +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x19 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() +OPERANDS: MEM0:w:dq:f64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f64 IMM0:r:b +IFORM: VEXTRACTF64X2_MEMf64_MASKmskw_YMMf64_IMM8_AVX512 } -# EMITTING VCVTPD2PS (VCVTPD2PS-128-1) +# EMITTING VEXTRACTF64X2 (VEXTRACTF64X2-512-1) { -ICLASS: VCVTPD2PS +ICLASS: VEXTRACTF64X2 CPL: 3 -CATEGORY: CONVERT +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 -IFORM: VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x19 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() +OPERANDS: REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf64 IMM0:r:b +IFORM: VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512 } + +# EMITTING VEXTRACTF64X2 (VEXTRACTF64X2-512-2) { -ICLASS: VCVTPD2PS +ICLASS: VEXTRACTF64X2 CPL: 3 -CATEGORY: CONVERT +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x5A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128 +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x19 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() +OPERANDS: MEM0:w:dq:f64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf64 IMM0:r:b +IFORM: VEXTRACTF64X2_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512 } -# EMITTING VCVTPD2PS (VCVTPD2PS-256-1) +# EMITTING VEXTRACTI32X4 (VEXTRACTI32X4-256-1) { -ICLASS: VCVTPD2PS +ICLASS: VEXTRACTI32X4 CPL: 3 -CATEGORY: CONVERT +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 -IFORM: VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x39 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() +OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 IMM0:r:b +IFORM: VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512 } + +# EMITTING VEXTRACTI32X4 (VEXTRACTI32X4-256-2) { -ICLASS: VCVTPD2PS +ICLASS: VEXTRACTI32X4 CPL: 3 -CATEGORY: CONVERT +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x5A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256 +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x39 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() +OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 IMM0:r:b +IFORM: VEXTRACTI32X4_MEMu32_MASKmskw_YMMu32_IMM8_AVX512 } -# EMITTING VCVTPD2QQ (VCVTPD2QQ-128-1) +# EMITTING VEXTRACTI32X8 (VEXTRACTI32X8-512-1) { -ICLASS: VCVTPD2QQ +ICLASS: VEXTRACTI32X8 CPL: 3 -CATEGORY: CONVERT +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 -IFORM: VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +OPERANDS: REG0=YMM_B3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 IMM0:r:b +IFORM: VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512 } + +# EMITTING VEXTRACTI32X8 (VEXTRACTI32X8-512-2) { -ICLASS: VCVTPD2QQ +ICLASS: VEXTRACTI32X8 CPL: 3 -CATEGORY: CONVERT +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE8 +PATTERN: EVV 0x3B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE8() +OPERANDS: MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 IMM0:r:b +IFORM: VEXTRACTI32X8_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512 } -# EMITTING VCVTPD2QQ (VCVTPD2QQ-256-1) +# EMITTING VEXTRACTI64X2 (VEXTRACTI64X2-256-1) { -ICLASS: VCVTPD2QQ +ICLASS: VEXTRACTI64X2 CPL: 3 -CATEGORY: CONVERT +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512DQ_256 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 -IFORM: VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x39 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() +OPERANDS: REG0=XMM_B3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 IMM0:r:b +IFORM: VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512 } + +# EMITTING VEXTRACTI64X2 (VEXTRACTI64X2-256-2) { -ICLASS: VCVTPD2QQ +ICLASS: VEXTRACTI64X2 CPL: 3 -CATEGORY: CONVERT +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512DQ_256 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x39 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() +OPERANDS: MEM0:w:dq:u64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 IMM0:r:b +IFORM: VEXTRACTI64X2_MEMu64_MASKmskw_YMMu64_IMM8_AVX512 } -# EMITTING VCVTPD2QQ (VCVTPD2QQ-512-1) +# EMITTING VEXTRACTI64X2 (VEXTRACTI64X2-512-1) { -ICLASS: VCVTPD2QQ +ICLASS: VEXTRACTI64X2 CPL: 3 -CATEGORY: CONVERT +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 -IFORM: VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x39 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() +OPERANDS: REG0=XMM_B3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 IMM0:r:b +IFORM: VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512 } -{ -ICLASS: VCVTPD2QQ -CPL: 3 -CATEGORY: CONVERT -EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E2 -REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zi64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 -IFORM: VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512 -} +# EMITTING VEXTRACTI64X2 (VEXTRACTI64X2-512-2) { -ICLASS: VCVTPD2QQ +ICLASS: VEXTRACTI64X2 CPL: 3 -CATEGORY: CONVERT +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x39 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() +OPERANDS: MEM0:w:dq:u64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 IMM0:r:b +IFORM: VEXTRACTI64X2_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512 } -# EMITTING VCVTPD2UDQ (VCVTPD2UDQ-128-1) +# EMITTING VFIXUPIMMPD (VFIXUPIMMPD-128-1) { -ICLASS: VCVTPD2UDQ +ICLASS: VFIXUPIMMPD CPL: 3 -CATEGORY: CONVERT +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 -IFORM: VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 } { -ICLASS: VCVTPD2UDQ +ICLASS: VFIXUPIMMPD CPL: 3 -CATEGORY: CONVERT +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 } -# EMITTING VCVTPD2UDQ (VCVTPD2UDQ-256-1) +# EMITTING VFIXUPIMMPD (VFIXUPIMMPD-256-1) { -ICLASS: VCVTPD2UDQ +ICLASS: VFIXUPIMMPD CPL: 3 -CATEGORY: CONVERT +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 -IFORM: VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 IMM0:r:b +IFORM: VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 } { -ICLASS: VCVTPD2UDQ +ICLASS: VFIXUPIMMPD CPL: 3 -CATEGORY: CONVERT +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 } -# EMITTING VCVTPD2UQQ (VCVTPD2UQQ-128-1) +# EMITTING VFIXUPIMMPS (VFIXUPIMMPS-128-1) { -ICLASS: VCVTPD2UQQ +ICLASS: VFIXUPIMMPS CPL: 3 -CATEGORY: CONVERT +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 -IFORM: VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 } { -ICLASS: VCVTPD2UQQ +ICLASS: VFIXUPIMMPS CPL: 3 -CATEGORY: CONVERT +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 } -# EMITTING VCVTPD2UQQ (VCVTPD2UQQ-256-1) +# EMITTING VFIXUPIMMPS (VFIXUPIMMPS-256-1) { -ICLASS: VCVTPD2UQQ +ICLASS: VFIXUPIMMPS CPL: 3 -CATEGORY: CONVERT +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 -IFORM: VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 IMM0:r:b +IFORM: VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 } { -ICLASS: VCVTPD2UQQ +ICLASS: VFIXUPIMMPS CPL: 3 -CATEGORY: CONVERT +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 } -# EMITTING VCVTPD2UQQ (VCVTPD2UQQ-512-1) +# EMITTING VFMADD132PD (VFMADD132PD-128-1) { -ICLASS: VCVTPD2UQQ +ICLASS: VFMADD132PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 -IFORM: VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VCVTPD2UQQ +ICLASS: VFMADD132PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zu64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 -IFORM: VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 } + +# EMITTING VFMADD132PD (VFMADD132PD-256-1) { -ICLASS: VCVTPD2UQQ +ICLASS: VFMADD132PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFMADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 } -# EMITTING VCVTPH2PS (VCVTPH2PS-128-1) +# EMITTING VFMADD132PS (VFMADD132PS-128-1) { -ICLASS: VCVTPH2PS +ICLASS: VFMADD132PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E11 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 -IFORM: VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VCVTPH2PS +ICLASS: VFMADD132PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E11 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM -PATTERN: EVV 0x13 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f16 -IFORM: VCVTPH2PS_XMMf32_MASKmskw_MEMf16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 } -# EMITTING VCVTPH2PS (VCVTPH2PS-256-1) +# EMITTING VFMADD132PS (VFMADD132PS-256-1) { -ICLASS: VCVTPH2PS +ICLASS: VFMADD132PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E11 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 -IFORM: VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 } { -ICLASS: VCVTPH2PS +ICLASS: VFMADD132PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E11 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM -PATTERN: EVV 0x13 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f16 -IFORM: VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 } -# EMITTING VCVTPS2DQ (VCVTPS2DQ-128-1) +# EMITTING VFMADD213PD (VFMADD213PD-128-1) { -ICLASS: VCVTPS2DQ +ICLASS: VFMADD213PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 -IFORM: VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VCVTPS2DQ +ICLASS: VFMADD213PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x5B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VCVTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 } -# EMITTING VCVTPS2DQ (VCVTPS2DQ-256-1) +# EMITTING VFMADD213PD (VFMADD213PD-256-1) { -ICLASS: VCVTPS2DQ +ICLASS: VFMADD213PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 -IFORM: VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 } { -ICLASS: VCVTPS2DQ +ICLASS: VFMADD213PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x5B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 } -# EMITTING VCVTPS2PD (VCVTPS2PD-128-1) +# EMITTING VFMADD213PS (VFMADD213PS-128-1) { -ICLASS: VCVTPS2PD +ICLASS: VFMADD213PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E3 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5A VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 -IFORM: VCVTPS2PD_XMMf64_MASKmskw_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VCVTPS2PD +ICLASS: VFMADD213PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E3 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED -PATTERN: EVV 0x5A VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 } -# EMITTING VCVTPS2PD (VCVTPS2PD-256-1) +# EMITTING VFMADD213PS (VFMADD213PS-256-1) { -ICLASS: VCVTPS2PD +ICLASS: VFMADD213PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E3 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5A VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 -IFORM: VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 } { -ICLASS: VCVTPS2PD +ICLASS: VFMADD213PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E3 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED -PATTERN: EVV 0x5A VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 } -# EMITTING VCVTPS2PH (VCVTPS2PH-128-1) +# EMITTING VFMADD231PD (VFMADD231PD-128-1) { -ICLASS: VCVTPS2PH +ICLASS: VFMADD231PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E11NF +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() -OPERANDS: REG0=XMM_B3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f32 IMM0:r:b -IFORM: VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } - -# EMITTING VCVTPS2PH (VCVTPS2PH-128-2) { -ICLASS: VCVTPS2PH +ICLASS: VFMADD231PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E11NF +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM -PATTERN: EVV 0x1D V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_HALFMEM() -OPERANDS: MEM0:w:q:f16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f32 IMM0:r:b -IFORM: VCVTPS2PH_MEMf16_MASKmskw_XMMf32_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 } -# EMITTING VCVTPS2PH (VCVTPS2PH-256-1) +# EMITTING VFMADD231PD (VFMADD231PD-256-1) { -ICLASS: VCVTPS2PH +ICLASS: VFMADD231PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E11NF +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() -OPERANDS: REG0=XMM_B3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f32 IMM0:r:b -IFORM: VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 } - -# EMITTING VCVTPS2PH (VCVTPS2PH-256-2) { -ICLASS: VCVTPS2PH +ICLASS: VFMADD231PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E11NF +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM -PATTERN: EVV 0x1D V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_HALFMEM() -OPERANDS: MEM0:w:dq:f16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f32 IMM0:r:b -IFORM: VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 } -# EMITTING VCVTPS2QQ (VCVTPS2QQ-128-1) +# EMITTING VFMADD231PS (VFMADD231PS-128-1) { -ICLASS: VCVTPS2QQ +ICLASS: VFMADD231PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128 -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 -IFORM: VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VCVTPS2QQ +ICLASS: VFMADD231PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128 -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED -PATTERN: EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() -OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 } -# EMITTING VCVTPS2QQ (VCVTPS2QQ-256-1) +# EMITTING VFMADD231PS (VFMADD231PS-256-1) { -ICLASS: VCVTPS2QQ +ICLASS: VFMADD231PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 -IFORM: VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 } { -ICLASS: VCVTPS2QQ +ICLASS: VFMADD231PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED -PATTERN: EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() -OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 } -# EMITTING VCVTPS2QQ (VCVTPS2QQ-512-1) +# EMITTING VFMADDSUB132PD (VFMADDSUB132PD-128-1) { -ICLASS: VCVTPS2QQ +ICLASS: VFMADDSUB132PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 -IFORM: VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VCVTPS2QQ +ICLASS: VFMADDSUB132PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zi64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 -IFORM: VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 } + +# EMITTING VFMADDSUB132PD (VFMADDSUB132PD-256-1) { -ICLASS: VCVTPS2QQ +ICLASS: VFMADDSUB132PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED -PATTERN: EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() -OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFMADDSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 } -# EMITTING VCVTPS2UDQ (VCVTPS2UDQ-128-1) +# EMITTING VFMADDSUB132PS (VFMADDSUB132PS-128-1) { -ICLASS: VCVTPS2UDQ +ICLASS: VFMADDSUB132PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 -IFORM: VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VCVTPS2UDQ +ICLASS: VFMADDSUB132PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 } -# EMITTING VCVTPS2UDQ (VCVTPS2UDQ-256-1) +# EMITTING VFMADDSUB132PS (VFMADDSUB132PS-256-1) { -ICLASS: VCVTPS2UDQ +ICLASS: VFMADDSUB132PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 -IFORM: VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 } { -ICLASS: VCVTPS2UDQ +ICLASS: VFMADDSUB132PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 } -# EMITTING VCVTPS2UQQ (VCVTPS2UQQ-128-1) +# EMITTING VFMADDSUB213PD (VFMADDSUB213PD-128-1) { -ICLASS: VCVTPS2UQQ +ICLASS: VFMADDSUB213PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128 -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 -IFORM: VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VCVTPS2UQQ +ICLASS: VFMADDSUB213PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128 -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED -PATTERN: EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 } -# EMITTING VCVTPS2UQQ (VCVTPS2UQQ-256-1) +# EMITTING VFMADDSUB213PD (VFMADDSUB213PD-256-1) { -ICLASS: VCVTPS2UQQ +ICLASS: VFMADDSUB213PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 -IFORM: VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 } { -ICLASS: VCVTPS2UQQ +ICLASS: VFMADDSUB213PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED -PATTERN: EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 } -# EMITTING VCVTPS2UQQ (VCVTPS2UQQ-512-1) -{ -ICLASS: VCVTPS2UQQ -CPL: 3 -CATEGORY: CONVERT -EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E3 -REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 -IFORM: VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512 -} - +# EMITTING VFMADDSUB213PS (VFMADDSUB213PS-128-1) { -ICLASS: VCVTPS2UQQ +ICLASS: VFMADDSUB213PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zu64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 -IFORM: VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VCVTPS2UQQ +ICLASS: VFMADDSUB213PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED -PATTERN: EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 } -# EMITTING VCVTQQ2PD (VCVTQQ2PD-128-1) +# EMITTING VFMADDSUB213PS (VFMADDSUB213PS-256-1) { -ICLASS: VCVTQQ2PD +ICLASS: VFMADDSUB213PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 -IFORM: VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 } { -ICLASS: VCVTQQ2PD +ICLASS: VFMADDSUB213PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VCVTQQ2PD_XMMi64_MASKmskw_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 } -# EMITTING VCVTQQ2PD (VCVTQQ2PD-256-1) +# EMITTING VFMADDSUB231PD (VFMADDSUB231PD-128-1) { -ICLASS: VCVTQQ2PD +ICLASS: VFMADDSUB231PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 -IFORM: VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VCVTQQ2PD +ICLASS: VFMADDSUB231PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VCVTQQ2PD_YMMi64_MASKmskw_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 } -# EMITTING VCVTQQ2PD (VCVTQQ2PD-512-1) +# EMITTING VFMADDSUB231PD (VFMADDSUB231PD-256-1) { -ICLASS: VCVTQQ2PD +ICLASS: VFMADDSUB231PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 -IFORM: VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 } { -ICLASS: VCVTQQ2PD +ICLASS: VFMADDSUB231PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zi64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 -IFORM: VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 } + +# EMITTING VFMADDSUB231PS (VFMADDSUB231PS-128-1) { -ICLASS: VCVTQQ2PD +ICLASS: VFMADDSUB231PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VCVTQQ2PD_ZMMi64_MASKmskw_MEMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } - -# EMITTING VCVTQQ2PS (VCVTQQ2PS-128-1) { -ICLASS: VCVTQQ2PS +ICLASS: VFMADDSUB231PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 -IFORM: VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 } + +# EMITTING VFMADDSUB231PS (VFMADDSUB231PS-256-1) { -ICLASS: VCVTQQ2PS +ICLASS: VFMADDSUB231PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 } - -# EMITTING VCVTQQ2PS (VCVTQQ2PS-256-1) { -ICLASS: VCVTQQ2PS +ICLASS: VFMADDSUB231PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 -IFORM: VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 } + +# EMITTING VFMSUB132PD (VFMSUB132PD-128-1) { -ICLASS: VCVTQQ2PS +ICLASS: VFMSUB132PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } - -# EMITTING VCVTQQ2PS (VCVTQQ2PS-512-1) { -ICLASS: VCVTQQ2PS +ICLASS: VFMSUB132PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 -IFORM: VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 } + +# EMITTING VFMSUB132PD (VFMSUB132PD-256-1) { -ICLASS: VCVTQQ2PS +ICLASS: VFMSUB132PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 -IFORM: VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 } { -ICLASS: VCVTQQ2PS +ICLASS: VFMSUB132PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 } -# EMITTING VCVTTPD2DQ (VCVTTPD2DQ-128-1) +# EMITTING VFMSUB132PS (VFMSUB132PS-128-1) { -ICLASS: VCVTTPD2DQ +ICLASS: VFMSUB132PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xE6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 -IFORM: VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VCVTTPD2DQ +ICLASS: VFMSUB132PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xE6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 } -# EMITTING VCVTTPD2DQ (VCVTTPD2DQ-256-1) +# EMITTING VFMSUB132PS (VFMSUB132PS-256-1) { -ICLASS: VCVTTPD2DQ +ICLASS: VFMSUB132PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xE6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 -IFORM: VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 } { -ICLASS: VCVTTPD2DQ +ICLASS: VFMSUB132PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xE6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 } -# EMITTING VCVTTPD2QQ (VCVTTPD2QQ-128-1) +# EMITTING VFMSUB213PD (VFMSUB213PD-128-1) { -ICLASS: VCVTTPD2QQ +ICLASS: VFMSUB213PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 -IFORM: VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VCVTTPD2QQ +ICLASS: VFMSUB213PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 } -# EMITTING VCVTTPD2QQ (VCVTTPD2QQ-256-1) +# EMITTING VFMSUB213PD (VFMSUB213PD-256-1) { -ICLASS: VCVTTPD2QQ +ICLASS: VFMSUB213PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 -IFORM: VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 } { -ICLASS: VCVTTPD2QQ +ICLASS: VFMSUB213PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 } -# EMITTING VCVTTPD2QQ (VCVTTPD2QQ-512-1) +# EMITTING VFMSUB213PS (VFMSUB213PS-128-1) { -ICLASS: VCVTTPD2QQ +ICLASS: VFMSUB213PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 -IFORM: VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VCVTTPD2QQ +ICLASS: VFMSUB213PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zi64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 -IFORM: VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 } + +# EMITTING VFMSUB213PS (VFMSUB213PS-256-1) { -ICLASS: VCVTTPD2QQ +ICLASS: VFMSUB213PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFMSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 } -# EMITTING VCVTTPD2UDQ (VCVTTPD2UDQ-128-1) +# EMITTING VFMSUB231PD (VFMSUB231PD-128-1) { -ICLASS: VCVTTPD2UDQ +ICLASS: VFMSUB231PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 -IFORM: VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VCVTTPD2UDQ +ICLASS: VFMSUB231PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 } -# EMITTING VCVTTPD2UDQ (VCVTTPD2UDQ-256-1) +# EMITTING VFMSUB231PD (VFMSUB231PD-256-1) { -ICLASS: VCVTTPD2UDQ +ICLASS: VFMSUB231PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 -IFORM: VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 } { -ICLASS: VCVTTPD2UDQ +ICLASS: VFMSUB231PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 } -# EMITTING VCVTTPD2UQQ (VCVTTPD2UQQ-128-1) +# EMITTING VFMSUB231PS (VFMSUB231PS-128-1) { -ICLASS: VCVTTPD2UQQ +ICLASS: VFMSUB231PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 -IFORM: VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VCVTTPD2UQQ +ICLASS: VFMSUB231PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 } -# EMITTING VCVTTPD2UQQ (VCVTTPD2UQQ-256-1) +# EMITTING VFMSUB231PS (VFMSUB231PS-256-1) { -ICLASS: VCVTTPD2UQQ +ICLASS: VFMSUB231PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 -IFORM: VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 } { -ICLASS: VCVTTPD2UQQ +ICLASS: VFMSUB231PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 } -# EMITTING VCVTTPD2UQQ (VCVTTPD2UQQ-512-1) +# EMITTING VFMSUBADD132PD (VFMSUBADD132PD-128-1) { -ICLASS: VCVTTPD2UQQ +ICLASS: VFMSUBADD132PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 -IFORM: VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VCVTTPD2UQQ +ICLASS: VFMSUBADD132PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zu64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 -IFORM: VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 } + +# EMITTING VFMSUBADD132PD (VFMSUBADD132PD-256-1) { -ICLASS: VCVTTPD2UQQ +ICLASS: VFMSUBADD132PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFMSUBADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 } -# EMITTING VCVTTPS2DQ (VCVTTPS2DQ-128-1) +# EMITTING VFMSUBADD132PS (VFMSUBADD132PS-128-1) { -ICLASS: VCVTTPS2DQ +ICLASS: VFMSUBADD132PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 -IFORM: VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VCVTTPS2DQ +ICLASS: VFMSUBADD132PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x5B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VCVTTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 } -# EMITTING VCVTTPS2DQ (VCVTTPS2DQ-256-1) +# EMITTING VFMSUBADD132PS (VFMSUBADD132PS-256-1) { -ICLASS: VCVTTPS2DQ +ICLASS: VFMSUBADD132PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 -IFORM: VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 } { -ICLASS: VCVTTPS2DQ +ICLASS: VFMSUBADD132PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x5B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 } -# EMITTING VCVTTPS2QQ (VCVTTPS2QQ-128-1) +# EMITTING VFMSUBADD213PD (VFMSUBADD213PD-128-1) { -ICLASS: VCVTTPS2QQ +ICLASS: VFMSUBADD213PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128 -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 -IFORM: VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VCVTTPS2QQ +ICLASS: VFMSUBADD213PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128 -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED -PATTERN: EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() -OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 } -# EMITTING VCVTTPS2QQ (VCVTTPS2QQ-256-1) +# EMITTING VFMSUBADD213PD (VFMSUBADD213PD-256-1) { -ICLASS: VCVTTPS2QQ +ICLASS: VFMSUBADD213PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 -IFORM: VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 } { -ICLASS: VCVTTPS2QQ +ICLASS: VFMSUBADD213PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED -PATTERN: EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() -OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 } -# EMITTING VCVTTPS2QQ (VCVTTPS2QQ-512-1) +# EMITTING VFMSUBADD213PS (VFMSUBADD213PS-128-1) { -ICLASS: VCVTTPS2QQ +ICLASS: VFMSUBADD213PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 -IFORM: VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VCVTTPS2QQ +ICLASS: VFMSUBADD213PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zi64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 -IFORM: VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 } + +# EMITTING VFMSUBADD213PS (VFMSUBADD213PS-256-1) { -ICLASS: VCVTTPS2QQ +ICLASS: VFMSUBADD213PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED -PATTERN: EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() -OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFMSUBADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 } -# EMITTING VCVTTPS2UDQ (VCVTTPS2UDQ-128-1) +# EMITTING VFMSUBADD231PD (VFMSUBADD231PD-128-1) { -ICLASS: VCVTTPS2UDQ +ICLASS: VFMSUBADD231PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 -IFORM: VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VCVTTPS2UDQ +ICLASS: VFMSUBADD231PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 } -# EMITTING VCVTTPS2UDQ (VCVTTPS2UDQ-256-1) +# EMITTING VFMSUBADD231PD (VFMSUBADD231PD-256-1) { -ICLASS: VCVTTPS2UDQ +ICLASS: VFMSUBADD231PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 -IFORM: VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 } { -ICLASS: VCVTTPS2UDQ +ICLASS: VFMSUBADD231PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 } -# EMITTING VCVTTPS2UQQ (VCVTTPS2UQQ-128-1) +# EMITTING VFMSUBADD231PS (VFMSUBADD231PS-128-1) { -ICLASS: VCVTTPS2UQQ +ICLASS: VFMSUBADD231PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128 -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 -IFORM: VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VCVTTPS2UQQ +ICLASS: VFMSUBADD231PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128 -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED -PATTERN: EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VCVTTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 } -# EMITTING VCVTTPS2UQQ (VCVTTPS2UQQ-256-1) +# EMITTING VFMSUBADD231PS (VFMSUBADD231PS-256-1) { -ICLASS: VCVTTPS2UQQ +ICLASS: VFMSUBADD231PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 -IFORM: VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 } { -ICLASS: VCVTTPS2UQQ +ICLASS: VFMSUBADD231PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED -PATTERN: EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VCVTTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 } -# EMITTING VCVTTPS2UQQ (VCVTTPS2UQQ-512-1) +# EMITTING VFNMADD132PD (VFNMADD132PD-128-1) { -ICLASS: VCVTTPS2UQQ +ICLASS: VFNMADD132PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 -IFORM: VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VCVTTPS2UQQ +ICLASS: VFNMADD132PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zu64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 -IFORM: VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 } + +# EMITTING VFNMADD132PD (VFNMADD132PD-256-1) { -ICLASS: VCVTTPS2UQQ +ICLASS: VFNMADD132PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED -PATTERN: EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VCVTTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFNMADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 } -# EMITTING VCVTUDQ2PD (VCVTUDQ2PD-128-1) +# EMITTING VFNMADD132PS (VFNMADD132PS-128-1) { -ICLASS: VCVTUDQ2PD +ICLASS: VFNMADD132PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E5 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 -IFORM: VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VCVTUDQ2PD +ICLASS: VFNMADD132PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E5 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED -PATTERN: EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VCVTUDQ2PD_XMMf64_MASKmskw_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 } -# EMITTING VCVTUDQ2PD (VCVTUDQ2PD-256-1) +# EMITTING VFNMADD132PS (VFNMADD132PS-256-1) { -ICLASS: VCVTUDQ2PD +ICLASS: VFNMADD132PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E5 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 -IFORM: VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 } { -ICLASS: VCVTUDQ2PD +ICLASS: VFNMADD132PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E5 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED -PATTERN: EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VCVTUDQ2PD_YMMf64_MASKmskw_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 } -# EMITTING VCVTUDQ2PS (VCVTUDQ2PS-128-1) +# EMITTING VFNMADD213PD (VFNMADD213PD-128-1) { -ICLASS: VCVTUDQ2PS +ICLASS: VFNMADD213PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 -IFORM: VCVTUDQ2PS_XMMf32_MASKmskw_XMMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VCVTUDQ2PS +ICLASS: VFNMADD213PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VCVTUDQ2PS_XMMf32_MASKmskw_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 } -# EMITTING VCVTUDQ2PS (VCVTUDQ2PS-256-1) +# EMITTING VFNMADD213PD (VFNMADD213PD-256-1) { -ICLASS: VCVTUDQ2PS +ICLASS: VFNMADD213PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 -IFORM: VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 } { -ICLASS: VCVTUDQ2PS +ICLASS: VFNMADD213PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VCVTUDQ2PS_YMMf32_MASKmskw_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 } -# EMITTING VCVTUQQ2PD (VCVTUQQ2PD-128-1) +# EMITTING VFNMADD213PS (VFNMADD213PS-128-1) { -ICLASS: VCVTUQQ2PD +ICLASS: VFNMADD213PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 -IFORM: VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VCVTUQQ2PD +ICLASS: VFNMADD213PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VCVTUQQ2PD_XMMf64_MASKmskw_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 } -# EMITTING VCVTUQQ2PD (VCVTUQQ2PD-256-1) +# EMITTING VFNMADD213PS (VFNMADD213PS-256-1) { -ICLASS: VCVTUQQ2PD +ICLASS: VFNMADD213PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 -IFORM: VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 } { -ICLASS: VCVTUQQ2PD +ICLASS: VFNMADD213PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VCVTUQQ2PD_YMMf64_MASKmskw_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 } -# EMITTING VCVTUQQ2PD (VCVTUQQ2PD-512-1) +# EMITTING VFNMADD231PD (VFNMADD231PD-128-1) { -ICLASS: VCVTUQQ2PD +ICLASS: VFNMADD231PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 -IFORM: VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VCVTUQQ2PD +ICLASS: VFNMADD231PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 -IFORM: VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 } + +# EMITTING VFNMADD231PD (VFNMADD231PD-256-1) { -ICLASS: VCVTUQQ2PD +ICLASS: VFNMADD231PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VCVTUQQ2PD_ZMMf64_MASKmskw_MEMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 } - -# EMITTING VCVTUQQ2PS (VCVTUQQ2PS-128-1) { -ICLASS: VCVTUQQ2PS +ICLASS: VFNMADD231PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 -IFORM: VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 } + +# EMITTING VFNMADD231PS (VFNMADD231PS-128-1) { -ICLASS: VCVTUQQ2PS +ICLASS: VFNMADD231PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } - -# EMITTING VCVTUQQ2PS (VCVTUQQ2PS-256-1) { -ICLASS: VCVTUQQ2PS +ICLASS: VFNMADD231PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 -IFORM: VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 } + +# EMITTING VFNMADD231PS (VFNMADD231PS-256-1) { -ICLASS: VCVTUQQ2PS +ICLASS: VFNMADD231PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 } - -# EMITTING VCVTUQQ2PS (VCVTUQQ2PS-512-1) { -ICLASS: VCVTUQQ2PS +ICLASS: VFNMADD231PS CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 -IFORM: VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 } + +# EMITTING VFNMSUB132PD (VFNMSUB132PD-128-1) { -ICLASS: VCVTUQQ2PS +ICLASS: VFNMSUB132PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 -IFORM: VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VCVTUQQ2PS +ICLASS: VFNMSUB132PD CPL: 3 -CATEGORY: CONVERT +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VCVTUQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 } -# EMITTING VDBPSADBW (VDBPSADBW-128-1) +# EMITTING VFNMSUB132PD (VFNMSUB132PD-256-1) { -ICLASS: VDBPSADBW +ICLASS: VFNMSUB132PD CPL: 3 -CATEGORY: AVX512 +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x42 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() -OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 IMM0:r:b -IFORM: VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 } { -ICLASS: VDBPSADBW +ICLASS: VFNMSUB132PD CPL: 3 -CATEGORY: AVX512 +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x42 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 IMM0:r:b -IFORM: VDBPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 } -# EMITTING VDBPSADBW (VDBPSADBW-256-1) +# EMITTING VFNMSUB132PS (VFNMSUB132PS-128-1) { -ICLASS: VDBPSADBW +ICLASS: VFNMSUB132PS CPL: 3 -CATEGORY: AVX512 +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4 -REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x42 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() -OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 IMM0:r:b -IFORM: VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VDBPSADBW +ICLASS: VFNMSUB132PS CPL: 3 -CATEGORY: AVX512 +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x42 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 IMM0:r:b -IFORM: VDBPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 } -# EMITTING VDBPSADBW (VDBPSADBW-512-1) +# EMITTING VFNMSUB132PS (VFNMSUB132PS-256-1) { -ICLASS: VDBPSADBW +ICLASS: VFNMSUB132PS CPL: 3 -CATEGORY: AVX512 +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x42 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() -OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 IMM0:r:b -IFORM: VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 } { -ICLASS: VDBPSADBW +ICLASS: VFNMSUB132PS CPL: 3 -CATEGORY: AVX512 +CATEGORY: VFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x42 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 IMM0:r:b -IFORM: VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 } -# EMITTING VDIVPD (VDIVPD-128-1) +# EMITTING VFNMSUB213PD (VFNMSUB213PD-128-1) { -ICLASS: VDIVPD +ICLASS: VFNMSUB213PD CPL: 3 -CATEGORY: AVX512 +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VDIVPD +ICLASS: VFNMSUB213PD CPL: 3 -CATEGORY: AVX512 +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x5E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VDIVPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 } -# EMITTING VDIVPD (VDIVPD-256-1) +# EMITTING VFNMSUB213PD (VFNMSUB213PD-256-1) { -ICLASS: VDIVPD +ICLASS: VFNMSUB213PD CPL: 3 -CATEGORY: AVX512 +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 -IFORM: VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 } { -ICLASS: VDIVPD +ICLASS: VFNMSUB213PD CPL: 3 -CATEGORY: AVX512 +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x5E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VDIVPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 } -# EMITTING VDIVPS (VDIVPS-128-1) +# EMITTING VFNMSUB213PS (VFNMSUB213PS-128-1) { -ICLASS: VDIVPS +ICLASS: VFNMSUB213PS CPL: 3 -CATEGORY: AVX512 +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5E VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VDIVPS +ICLASS: VFNMSUB213PS CPL: 3 -CATEGORY: AVX512 +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x5E VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VDIVPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 } -# EMITTING VDIVPS (VDIVPS-256-1) +# EMITTING VFNMSUB213PS (VFNMSUB213PS-256-1) { -ICLASS: VDIVPS +ICLASS: VFNMSUB213PS CPL: 3 -CATEGORY: AVX512 +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5E VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 -IFORM: VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 } { -ICLASS: VDIVPS +ICLASS: VFNMSUB213PS CPL: 3 -CATEGORY: AVX512 +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x5E VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VDIVPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 } -# EMITTING VEXPANDPD (VEXPANDPD-128-1) +# EMITTING VFNMSUB231PD (VFNMSUB231PD-128-1) { -ICLASS: VEXPANDPD +ICLASS: VFNMSUB231PD CPL: 3 -CATEGORY: EXPAND +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f64 -IFORM: VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } - -# EMITTING VEXPANDPD (VEXPANDPD-128-2) { -ICLASS: VEXPANDPD +ICLASS: VFNMSUB231PD CPL: 3 -CATEGORY: EXPAND +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 -IFORM: VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 } -# EMITTING VEXPANDPD (VEXPANDPD-256-1) +# EMITTING VFNMSUB231PD (VFNMSUB231PD-256-1) { -ICLASS: VEXPANDPD +ICLASS: VFNMSUB231PD CPL: 3 -CATEGORY: EXPAND +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT() -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f64 -IFORM: VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 } - -# EMITTING VEXPANDPD (VEXPANDPD-256-2) { -ICLASS: VEXPANDPD +ICLASS: VFNMSUB231PD CPL: 3 -CATEGORY: EXPAND +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 -IFORM: VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 } -# EMITTING VEXPANDPS (VEXPANDPS-128-1) +# EMITTING VFNMSUB231PS (VFNMSUB231PS-128-1) { -ICLASS: VEXPANDPS +ICLASS: VFNMSUB231PS CPL: 3 -CATEGORY: EXPAND +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32 -IFORM: VEXPANDPS_XMMf32_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } - -# EMITTING VEXPANDPS (VEXPANDPS-128-2) { -ICLASS: VEXPANDPS +ICLASS: VFNMSUB231PS CPL: 3 -CATEGORY: EXPAND +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 -IFORM: VEXPANDPS_XMMf32_MASKmskw_XMMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 } -# EMITTING VEXPANDPS (VEXPANDPS-256-1) +# EMITTING VFNMSUB231PS (VFNMSUB231PS-256-1) { -ICLASS: VEXPANDPS +ICLASS: VFNMSUB231PS CPL: 3 -CATEGORY: EXPAND +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32 -IFORM: VEXPANDPS_YMMf32_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 } - -# EMITTING VEXPANDPS (VEXPANDPS-256-2) { -ICLASS: VEXPANDPS +ICLASS: VFNMSUB231PS CPL: 3 -CATEGORY: EXPAND +CATEGORY: VFMA EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 -IFORM: VEXPANDPS_YMMf32_MASKmskw_YMMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 } -# EMITTING VEXTRACTF32X4 (VEXTRACTF32X4-256-1) +# EMITTING VFPCLASSPD (VFPCLASSPD-128-1) { -ICLASS: VEXTRACTF32X4 +ICLASS: VFPCLASSPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x19 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() -OPERANDS: REG0=XMM_B3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f32 IMM0:r:b -IFORM: VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512 } - -# EMITTING VEXTRACTF32X4 (VEXTRACTF32X4-256-2) { -ICLASS: VEXTRACTF32X4 +ICLASS: VFPCLASSPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 -PATTERN: EVV 0x19 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() -OPERANDS: MEM0:w:dq:f32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f32 IMM0:r:b -IFORM: VEXTRACTF32X4_MEMf32_MASKmskw_YMMf32_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL128 } -# EMITTING VEXTRACTF32X8 (VEXTRACTF32X8-512-1) +# EMITTING VFPCLASSPD (VFPCLASSPD-256-1) { -ICLASS: VEXTRACTF32X8 +ICLASS: VFPCLASSPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x1B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() -OPERANDS: REG0=YMM_B3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 IMM0:r:b -IFORM: VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_B3():r:qq:f64 IMM0:r:b +IFORM: VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512 } - -# EMITTING VEXTRACTF32X8 (VEXTRACTF32X8-512-2) { -ICLASS: VEXTRACTF32X8 +ICLASS: VFPCLASSPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE8 -PATTERN: EVV 0x1B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE8() -OPERANDS: MEM0:w:qq:f32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32 IMM0:r:b -IFORM: VEXTRACTF32X8_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256 } -# EMITTING VEXTRACTF64X2 (VEXTRACTF64X2-256-1) +# EMITTING VFPCLASSPD (VFPCLASSPD-512-1) { -ICLASS: VEXTRACTF64X2 +ICLASS: VFPCLASSPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x19 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() -OPERANDS: REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f64 IMM0:r:b -IFORM: VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512 } - -# EMITTING VEXTRACTF64X2 (VEXTRACTF64X2-256-2) { -ICLASS: VEXTRACTF64X2 +ICLASS: VFPCLASSPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 -PATTERN: EVV 0x19 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() -OPERANDS: MEM0:w:dq:f64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f64 IMM0:r:b -IFORM: VEXTRACTF64X2_MEMf64_MASKmskw_YMMf64_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL512 } -# EMITTING VEXTRACTF64X2 (VEXTRACTF64X2-512-1) +# EMITTING VFPCLASSPS (VFPCLASSPS-128-1) { -ICLASS: VEXTRACTF64X2 +ICLASS: VFPCLASSPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x19 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() -OPERANDS: REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf64 IMM0:r:b -IFORM: VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VFPCLASSPS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512 } - -# EMITTING VEXTRACTF64X2 (VEXTRACTF64X2-512-2) { -ICLASS: VEXTRACTF64X2 +ICLASS: VFPCLASSPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 -PATTERN: EVV 0x19 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() -OPERANDS: MEM0:w:dq:f64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf64 IMM0:r:b -IFORM: VEXTRACTF64X2_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL128 } -# EMITTING VEXTRACTI32X4 (VEXTRACTI32X4-256-1) +# EMITTING VFPCLASSPS (VFPCLASSPS-256-1) { -ICLASS: VEXTRACTI32X4 +ICLASS: VFPCLASSPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x39 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() -OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 IMM0:r:b -IFORM: VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_B3():r:qq:f32 IMM0:r:b +IFORM: VFPCLASSPS_MASKmskw_MASKmskw_YMMf32_IMM8_AVX512 } - -# EMITTING VEXTRACTI32X4 (VEXTRACTI32X4-256-2) { -ICLASS: VEXTRACTI32X4 +ICLASS: VFPCLASSPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 -PATTERN: EVV 0x39 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() -OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 IMM0:r:b -IFORM: VEXTRACTI32X4_MEMu32_MASKmskw_YMMu32_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL256 } -# EMITTING VEXTRACTI32X8 (VEXTRACTI32X8-512-1) +# EMITTING VFPCLASSPS (VFPCLASSPS-512-1) { -ICLASS: VEXTRACTI32X8 +ICLASS: VFPCLASSPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x3B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() -OPERANDS: REG0=YMM_B3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 IMM0:r:b -IFORM: VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VFPCLASSPS_MASKmskw_MASKmskw_ZMMf32_IMM8_AVX512 } - -# EMITTING VEXTRACTI32X8 (VEXTRACTI32X8-512-2) { -ICLASS: VEXTRACTI32X8 +ICLASS: VFPCLASSPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE8 -PATTERN: EVV 0x3B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE8() -OPERANDS: MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 IMM0:r:b -IFORM: VEXTRACTI32X8_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL512 } -# EMITTING VEXTRACTI64X2 (VEXTRACTI64X2-256-1) +# EMITTING VFPCLASSSD (VFPCLASSSD-128-1) { -ICLASS: VEXTRACTI64X2 +ICLASS: VFPCLASSSD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x39 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() -OPERANDS: REG0=XMM_B3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 IMM0:r:b -IFORM: VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x67 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 NOEVSR ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512 } - -# EMITTING VEXTRACTI64X2 (VEXTRACTI64X2-256-2) { -ICLASS: VEXTRACTI64X2 +ICLASS: VFPCLASSSD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 -PATTERN: EVV 0x39 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() -OPERANDS: MEM0:w:dq:u64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 IMM0:r:b -IFORM: VEXTRACTI64X2_MEMu64_MASKmskw_YMMu64_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x67 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:q:f64 IMM0:r:b +IFORM: VFPCLASSSD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512 } -# EMITTING VEXTRACTI64X2 (VEXTRACTI64X2-512-1) +# EMITTING VFPCLASSSS (VFPCLASSSS-128-1) { -ICLASS: VEXTRACTI64X2 +ICLASS: VFPCLASSSS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x39 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() -OPERANDS: REG0=XMM_B3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 IMM0:r:b -IFORM: VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x67 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512 } - -# EMITTING VEXTRACTI64X2 (VEXTRACTI64X2-512-2) { -ICLASS: VEXTRACTI64X2 +ICLASS: VFPCLASSSS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 -PATTERN: EVV 0x39 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() -OPERANDS: MEM0:w:dq:u64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 IMM0:r:b -IFORM: VEXTRACTI64X2_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x67 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:d:f32 IMM0:r:b +IFORM: VFPCLASSSS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512 } -# EMITTING VFIXUPIMMPD (VFIXUPIMMPD-128-1) +# EMITTING VGATHERDPD (VGATHERDPD-128-2) { -ICLASS: VFIXUPIMMPD +ICLASS: VGATHERDPD CPL: 3 -CATEGORY: AVX512 +CATEGORY: GATHER EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E12 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b -IFORM: VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASKNOT0():rw:mskw MEM0:r:q:f64 +IFORM: VGATHERDPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128 } + +# EMITTING VGATHERDPD (VGATHERDPD-256-2) { -ICLASS: VFIXUPIMMPD +ICLASS: VGATHERDPD CPL: 3 -CATEGORY: AVX512 +CATEGORY: GATHER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b -IFORM: VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 +ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASKNOT0():rw:mskw MEM0:r:q:f64 +IFORM: VGATHERDPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256 } -# EMITTING VFIXUPIMMPD (VFIXUPIMMPD-256-1) +# EMITTING VGATHERDPS (VGATHERDPS-128-2) { -ICLASS: VFIXUPIMMPD +ICLASS: VGATHERDPS CPL: 3 -CATEGORY: AVX512 +CATEGORY: GATHER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() -OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 IMM0:r:b -IFORM: VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 +ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASKNOT0():rw:mskw MEM0:r:d:f32 +IFORM: VGATHERDPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128 } + +# EMITTING VGATHERDPS (VGATHERDPS-256-2) { -ICLASS: VFIXUPIMMPD +ICLASS: VGATHERDPS CPL: 3 -CATEGORY: AVX512 +CATEGORY: GATHER EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E12 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b -IFORM: VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 +ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASKNOT0():rw:mskw MEM0:r:d:f32 +IFORM: VGATHERDPS_YMMf32_MASKmskw_MEMf32_AVX512_VL256 } -# EMITTING VFIXUPIMMPS (VFIXUPIMMPS-128-1) +# EMITTING VGATHERQPD (VGATHERQPD-128-2) { -ICLASS: VFIXUPIMMPS +ICLASS: VGATHERQPD CPL: 3 -CATEGORY: AVX512 +CATEGORY: GATHER EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E12 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b -IFORM: VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASKNOT0():rw:mskw MEM0:r:q:f64 +IFORM: VGATHERQPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128 } + +# EMITTING VGATHERQPD (VGATHERQPD-256-2) { -ICLASS: VFIXUPIMMPS +ICLASS: VGATHERQPD CPL: 3 -CATEGORY: AVX512 +CATEGORY: GATHER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b -IFORM: VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 +ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASKNOT0():rw:mskw MEM0:r:q:f64 +IFORM: VGATHERQPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256 } -# EMITTING VFIXUPIMMPS (VFIXUPIMMPS-256-1) +# EMITTING VGATHERQPS (VGATHERQPS-128-2) { -ICLASS: VFIXUPIMMPS +ICLASS: VGATHERQPS CPL: 3 -CATEGORY: AVX512 +CATEGORY: GATHER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() -OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 IMM0:r:b -IFORM: VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 +ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASKNOT0():rw:mskw MEM0:r:d:f32 +IFORM: VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128 } + +# EMITTING VGATHERQPS (VGATHERQPS-256-2) { -ICLASS: VFIXUPIMMPS +ICLASS: VGATHERQPS CPL: 3 -CATEGORY: AVX512 +CATEGORY: GATHER EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E12 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b -IFORM: VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 +ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASKNOT0():rw:mskw MEM0:r:d:f32 +IFORM: VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL256 } -# EMITTING VFMADD132PD (VFMADD132PD-128-1) +# EMITTING VGETEXPPD (VGETEXPPD-128-1) { -ICLASS: VFMADD132PD +ICLASS: VGETEXPPD CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512 } { -ICLASS: VFMADD132PD +ICLASS: VGETEXPPD CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VFMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VGETEXPPD_XMMf64_MASKmskw_MEMf64_AVX512 } -# EMITTING VFMADD132PD (VFMADD132PD-256-1) +# EMITTING VGETEXPPD (VGETEXPPD-256-1) { -ICLASS: VFMADD132PD +ICLASS: VGETEXPPD CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 -IFORM: VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512 } { -ICLASS: VFMADD132PD +ICLASS: VGETEXPPD CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VFMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VGETEXPPD_YMMf64_MASKmskw_MEMf64_AVX512 } -# EMITTING VFMADD132PS (VFMADD132PS-128-1) +# EMITTING VGETEXPPS (VGETEXPPS-128-1) { -ICLASS: VFMADD132PS +ICLASS: VGETEXPPS CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512 } { -ICLASS: VFMADD132PS +ICLASS: VGETEXPPS CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VFMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VGETEXPPS_XMMf32_MASKmskw_MEMf32_AVX512 } -# EMITTING VFMADD132PS (VFMADD132PS-256-1) +# EMITTING VGETEXPPS (VGETEXPPS-256-1) { -ICLASS: VFMADD132PS +ICLASS: VGETEXPPS CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 -IFORM: VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512 } { -ICLASS: VFMADD132PS +ICLASS: VGETEXPPS CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VFMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VGETEXPPS_YMMf32_MASKmskw_MEMf32_AVX512 } -# EMITTING VFMADD213PD (VFMADD213PD-128-1) +# EMITTING VGETMANTPD (VGETMANTPD-128-1) { -ICLASS: VFMADD213PD +ICLASS: VGETMANTPD CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 } { -ICLASS: VFMADD213PD +ICLASS: VGETMANTPD CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VFMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VGETMANTPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 } -# EMITTING VFMADD213PD (VFMADD213PD-256-1) +# EMITTING VGETMANTPD (VGETMANTPD-256-1) { -ICLASS: VFMADD213PD +ICLASS: VGETMANTPD CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 -IFORM: VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 IMM0:r:b +IFORM: VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 } { -ICLASS: VFMADD213PD +ICLASS: VGETMANTPD CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VFMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VGETMANTPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 } -# EMITTING VFMADD213PS (VFMADD213PS-128-1) +# EMITTING VGETMANTPS (VGETMANTPS-128-1) { -ICLASS: VFMADD213PS +ICLASS: VGETMANTPS CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 } { -ICLASS: VFMADD213PS +ICLASS: VGETMANTPS CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VFMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VGETMANTPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 } -# EMITTING VFMADD213PS (VFMADD213PS-256-1) +# EMITTING VGETMANTPS (VGETMANTPS-256-1) { -ICLASS: VFMADD213PS +ICLASS: VGETMANTPS CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 -IFORM: VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 IMM0:r:b +IFORM: VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 } { -ICLASS: VFMADD213PS +ICLASS: VGETMANTPS CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VFMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VGETMANTPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 } -# EMITTING VFMADD231PD (VFMADD231PD-128-1) +# EMITTING VINSERTF32X4 (VINSERTF32X4-256-1) { -ICLASS: VFMADD231PD +ICLASS: VINSERTF32X4 CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x18 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512 } { -ICLASS: VFMADD231PD +ICLASS: VINSERTF32X4 CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VFMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x18 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:dq:f32 IMM0:r:b +IFORM: VINSERTF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 } -# EMITTING VFMADD231PD (VFMADD231PD-256-1) +# EMITTING VINSERTF32X8 (VINSERTF32X8-512-1) { -ICLASS: VFMADD231PD +ICLASS: VINSERTF32X8 CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 -IFORM: VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=YMM_B3():r:qq:f32 IMM0:r:b +IFORM: VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512 } { -ICLASS: VFMADD231PD +ICLASS: VINSERTF32X8 CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VFMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE8 +PATTERN: EVV 0x1A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE8() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:qq:f32 IMM0:r:b +IFORM: VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 } -# EMITTING VFMADD231PS (VFMADD231PS-128-1) +# EMITTING VINSERTF64X2 (VINSERTF64X2-256-1) { -ICLASS: VFMADD231PS +ICLASS: VINSERTF64X2 CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x18 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512 } { -ICLASS: VFMADD231PS +ICLASS: VINSERTF64X2 CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VFMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x18 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:dq:f64 IMM0:r:b +IFORM: VINSERTF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 } -# EMITTING VFMADD231PS (VFMADD231PS-256-1) +# EMITTING VINSERTF64X2 (VINSERTF64X2-512-1) { -ICLASS: VFMADD231PS +ICLASS: VINSERTF64X2 CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 -IFORM: VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x18 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512 } { -ICLASS: VFMADD231PS +ICLASS: VINSERTF64X2 CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VFMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x18 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:dq:f64 IMM0:r:b +IFORM: VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 } -# EMITTING VFMADDSUB132PD (VFMADDSUB132PD-128-1) +# EMITTING VINSERTI32X4 (VINSERTI32X4-256-1) { -ICLASS: VFMADDSUB132PD +ICLASS: VINSERTI32X4 CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x38 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=XMM_B3():r:dq:u32 IMM0:r:b +IFORM: VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512 } { -ICLASS: VFMADDSUB132PD +ICLASS: VINSERTI32X4 CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x38 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:dq:u32 IMM0:r:b +IFORM: VINSERTI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 } -# EMITTING VFMADDSUB132PD (VFMADDSUB132PD-256-1) +# EMITTING VINSERTI32X8 (VINSERTI32X8-512-1) { -ICLASS: VFMADDSUB132PD +ICLASS: VINSERTI32X8 CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 -IFORM: VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=YMM_B3():r:qq:u32 IMM0:r:b +IFORM: VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512 } { -ICLASS: VFMADDSUB132PD +ICLASS: VINSERTI32X8 CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE8 +PATTERN: EVV 0x3A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE8() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:qq:u32 IMM0:r:b +IFORM: VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 } -# EMITTING VFMADDSUB132PS (VFMADDSUB132PS-128-1) +# EMITTING VINSERTI64X2 (VINSERTI64X2-256-1) { -ICLASS: VFMADDSUB132PS +ICLASS: VINSERTI64X2 CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x38 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=XMM_B3():r:dq:u64 IMM0:r:b +IFORM: VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512 } { -ICLASS: VFMADDSUB132PS +ICLASS: VINSERTI64X2 CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x38 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:dq:u64 IMM0:r:b +IFORM: VINSERTI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 } -# EMITTING VFMADDSUB132PS (VFMADDSUB132PS-256-1) +# EMITTING VINSERTI64X2 (VINSERTI64X2-512-1) { -ICLASS: VFMADDSUB132PS +ICLASS: VINSERTI64X2 CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 -IFORM: VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x38 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=XMM_B3():r:dq:u64 IMM0:r:b +IFORM: VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512 } { -ICLASS: VFMADDSUB132PS +ICLASS: VINSERTI64X2 CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x38 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:dq:u64 IMM0:r:b +IFORM: VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 } -# EMITTING VFMADDSUB213PD (VFMADDSUB213PD-128-1) +# EMITTING VMAXPD (VMAXPD-128-1) { -ICLASS: VFMADDSUB213PD +ICLASS: VMAXPD CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VFMADDSUB213PD +ICLASS: VMAXPD CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 } -# EMITTING VFMADDSUB213PD (VFMADDSUB213PD-256-1) +# EMITTING VMAXPD (VMAXPD-256-1) { -ICLASS: VFMADDSUB213PD +ICLASS: VMAXPD CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 -IFORM: VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 } { -ICLASS: VFMADDSUB213PD +ICLASS: VMAXPD CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 } -# EMITTING VFMADDSUB213PS (VFMADDSUB213PS-128-1) +# EMITTING VMAXPS (VMAXPS-128-1) { -ICLASS: VFMADDSUB213PS +ICLASS: VMAXPS CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5F VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VFMADDSUB213PS +ICLASS: VMAXPS CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5F VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 } -# EMITTING VFMADDSUB213PS (VFMADDSUB213PS-256-1) +# EMITTING VMAXPS (VMAXPS-256-1) { -ICLASS: VFMADDSUB213PS +ICLASS: VMAXPS CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 -IFORM: VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5F VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 } { -ICLASS: VFMADDSUB213PS +ICLASS: VMAXPS CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5F VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 } -# EMITTING VFMADDSUB231PD (VFMADDSUB231PD-128-1) +# EMITTING VMINPD (VMINPD-128-1) { -ICLASS: VFMADDSUB231PD +ICLASS: VMINPD CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VFMADDSUB231PD +ICLASS: VMINPD CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VMINPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 } -# EMITTING VFMADDSUB231PD (VFMADDSUB231PD-256-1) +# EMITTING VMINPD (VMINPD-256-1) { -ICLASS: VFMADDSUB231PD +ICLASS: VMINPD CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 -IFORM: VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 } { -ICLASS: VFMADDSUB231PD +ICLASS: VMINPD CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VMINPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 } -# EMITTING VFMADDSUB231PS (VFMADDSUB231PS-128-1) +# EMITTING VMINPS (VMINPS-128-1) { -ICLASS: VFMADDSUB231PS +ICLASS: VMINPS CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5D VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VFMADDSUB231PS +ICLASS: VMINPS CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5D VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VMINPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 } -# EMITTING VFMADDSUB231PS (VFMADDSUB231PS-256-1) +# EMITTING VMINPS (VMINPS-256-1) { -ICLASS: VFMADDSUB231PS +ICLASS: VMINPS CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 -IFORM: VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5D VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 } { -ICLASS: VFMADDSUB231PS +ICLASS: VMINPS CPL: 3 -CATEGORY: VFMA +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5D VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VMINPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 } -# EMITTING VFMSUB132PD (VFMSUB132PD-128-1) +# EMITTING VMOVAPD (VMOVAPD-128-1) { -ICLASS: VFMSUB132PD +ICLASS: VMOVAPD CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E1 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x28 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512 } { -ICLASS: VFMSUB132PD +ICLASS: VMOVAPD CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E1 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VFMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x28 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f64 +IFORM: VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512 } -# EMITTING VFMSUB132PD (VFMSUB132PD-256-1) +# EMITTING VMOVAPD (VMOVAPD-128-2) { -ICLASS: VFMSUB132PD +ICLASS: VMOVAPD CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 -IFORM: VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x29 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f64 +IFORM: VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512 } + +# EMITTING VMOVAPD (VMOVAPD-128-3) { -ICLASS: VFMSUB132PD +ICLASS: VMOVAPD CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VFMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x29 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:dq:f64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f64 +IFORM: VMOVAPD_MEMf64_MASKmskw_XMMf64_AVX512 } -# EMITTING VFMSUB132PS (VFMSUB132PS-128-1) +# EMITTING VMOVAPD (VMOVAPD-256-1) { -ICLASS: VFMSUB132PS +ICLASS: VMOVAPD CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x28 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512 } { -ICLASS: VFMSUB132PS +ICLASS: VMOVAPD CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VFMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x28 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f64 +IFORM: VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512 } -# EMITTING VFMSUB132PS (VFMSUB132PS-256-1) +# EMITTING VMOVAPD (VMOVAPD-256-2) { -ICLASS: VFMSUB132PS +ICLASS: VMOVAPD CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E1 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 -IFORM: VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x29 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f64 +IFORM: VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512 } + +# EMITTING VMOVAPD (VMOVAPD-256-3) { -ICLASS: VFMSUB132PS +ICLASS: VMOVAPD CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E1 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VFMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x29 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:qq:f64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f64 +IFORM: VMOVAPD_MEMf64_MASKmskw_YMMf64_AVX512 } -# EMITTING VFMSUB213PD (VFMSUB213PD-128-1) +# EMITTING VMOVAPS (VMOVAPS-128-1) { -ICLASS: VFMSUB213PD +ICLASS: VMOVAPS CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E1 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x28 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512 } { -ICLASS: VFMSUB213PD +ICLASS: VMOVAPS CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E1 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VFMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x28 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32 +IFORM: VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512 } -# EMITTING VFMSUB213PD (VFMSUB213PD-256-1) +# EMITTING VMOVAPS (VMOVAPS-128-2) { -ICLASS: VFMSUB213PD +ICLASS: VMOVAPS CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 -IFORM: VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x29 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f32 +IFORM: VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512 } + +# EMITTING VMOVAPS (VMOVAPS-128-3) { -ICLASS: VFMSUB213PD +ICLASS: VMOVAPS CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VFMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x29 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:dq:f32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f32 +IFORM: VMOVAPS_MEMf32_MASKmskw_XMMf32_AVX512 } -# EMITTING VFMSUB213PS (VFMSUB213PS-128-1) +# EMITTING VMOVAPS (VMOVAPS-256-1) { -ICLASS: VFMSUB213PS +ICLASS: VMOVAPS CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x28 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512 } { -ICLASS: VFMSUB213PS +ICLASS: VMOVAPS CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VFMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x28 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32 +IFORM: VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512 } -# EMITTING VFMSUB213PS (VFMSUB213PS-256-1) +# EMITTING VMOVAPS (VMOVAPS-256-2) { -ICLASS: VFMSUB213PS +ICLASS: VMOVAPS CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E1 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 -IFORM: VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x29 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f32 +IFORM: VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512 } + +# EMITTING VMOVAPS (VMOVAPS-256-3) { -ICLASS: VFMSUB213PS +ICLASS: VMOVAPS CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E1 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VFMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x29 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:qq:f32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f32 +IFORM: VMOVAPS_MEMf32_MASKmskw_YMMf32_AVX512 } -# EMITTING VFMSUB231PD (VFMSUB231PD-128-1) +# EMITTING VMOVDDUP (VMOVDDUP-128-1) { -ICLASS: VFMSUB231PD +ICLASS: VMOVDDUP CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E5NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x12 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VMOVDDUP_XMMf64_MASKmskw_XMMf64_AVX512 } { -ICLASS: VFMSUB231PD +ICLASS: VMOVDDUP CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E5NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VFMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_MOVDDUP +PATTERN: EVV 0x12 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_MOVDDUP() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f64 +IFORM: VMOVDDUP_XMMf64_MASKmskw_MEMf64_AVX512 } -# EMITTING VFMSUB231PD (VFMSUB231PD-256-1) +# EMITTING VMOVDDUP (VMOVDDUP-256-1) { -ICLASS: VFMSUB231PD +ICLASS: VMOVDDUP CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E5NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 -IFORM: VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x12 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512 } { -ICLASS: VFMSUB231PD +ICLASS: VMOVDDUP CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E5NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VFMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_MOVDDUP +PATTERN: EVV 0x12 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_MOVDDUP() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f64 +IFORM: VMOVDDUP_YMMf64_MASKmskw_MEMf64_AVX512 } -# EMITTING VFMSUB231PS (VFMSUB231PS-128-1) +# EMITTING VMOVDQA32 (VMOVDQA32-128-1) { -ICLASS: VFMSUB231PS +ICLASS: VMOVDQA32 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E1 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 +IFORM: VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512 } { -ICLASS: VFMSUB231PS +ICLASS: VMOVDQA32 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E1 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VFMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u32 +IFORM: VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512 } -# EMITTING VFMSUB231PS (VFMSUB231PS-256-1) +# EMITTING VMOVDQA32 (VMOVDQA32-128-2) { -ICLASS: VFMSUB231PS +ICLASS: VMOVDQA32 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 -IFORM: VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32 +IFORM: VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512 } + +# EMITTING VMOVDQA32 (VMOVDQA32-128-3) { -ICLASS: VFMSUB231PS +ICLASS: VMOVDQA32 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VFMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32 +IFORM: VMOVDQA32_MEMu32_MASKmskw_XMMu32_AVX512 } -# EMITTING VFMSUBADD132PD (VFMSUBADD132PD-128-1) +# EMITTING VMOVDQA32 (VMOVDQA32-256-1) { -ICLASS: VFMSUBADD132PD +ICLASS: VMOVDQA32 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 +IFORM: VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512 } { -ICLASS: VFMSUBADD132PD +ICLASS: VMOVDQA32 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u32 +IFORM: VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512 } -# EMITTING VFMSUBADD132PD (VFMSUBADD132PD-256-1) +# EMITTING VMOVDQA32 (VMOVDQA32-256-2) { -ICLASS: VFMSUBADD132PD +ICLASS: VMOVDQA32 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E1 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 -IFORM: VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 +IFORM: VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512 } + +# EMITTING VMOVDQA32 (VMOVDQA32-256-3) { -ICLASS: VFMSUBADD132PD +ICLASS: VMOVDQA32 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E1 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 +IFORM: VMOVDQA32_MEMu32_MASKmskw_YMMu32_AVX512 } -# EMITTING VFMSUBADD132PS (VFMSUBADD132PS-128-1) +# EMITTING VMOVDQA64 (VMOVDQA64-128-1) { -ICLASS: VFMSUBADD132PS +ICLASS: VMOVDQA64 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E1 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 +IFORM: VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512 } { -ICLASS: VFMSUBADD132PS +ICLASS: VMOVDQA64 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E1 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u64 +IFORM: VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512 } -# EMITTING VFMSUBADD132PS (VFMSUBADD132PS-256-1) +# EMITTING VMOVDQA64 (VMOVDQA64-128-2) { -ICLASS: VFMSUBADD132PS +ICLASS: VMOVDQA64 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 -IFORM: VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 +IFORM: VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512 } + +# EMITTING VMOVDQA64 (VMOVDQA64-128-3) { -ICLASS: VFMSUBADD132PS +ICLASS: VMOVDQA64 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:dq:u64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 +IFORM: VMOVDQA64_MEMu64_MASKmskw_XMMu64_AVX512 } -# EMITTING VFMSUBADD213PD (VFMSUBADD213PD-128-1) +# EMITTING VMOVDQA64 (VMOVDQA64-256-1) { -ICLASS: VFMSUBADD213PD +ICLASS: VMOVDQA64 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 +IFORM: VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512 } { -ICLASS: VFMSUBADD213PD +ICLASS: VMOVDQA64 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u64 +IFORM: VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512 } -# EMITTING VFMSUBADD213PD (VFMSUBADD213PD-256-1) +# EMITTING VMOVDQA64 (VMOVDQA64-256-2) { -ICLASS: VFMSUBADD213PD +ICLASS: VMOVDQA64 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E1 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 -IFORM: VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 +IFORM: VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512 } + +# EMITTING VMOVDQA64 (VMOVDQA64-256-3) { -ICLASS: VFMSUBADD213PD +ICLASS: VMOVDQA64 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E1 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:qq:u64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 +IFORM: VMOVDQA64_MEMu64_MASKmskw_YMMu64_AVX512 } -# EMITTING VFMSUBADD213PS (VFMSUBADD213PS-128-1) +# EMITTING VMOVDQU16 (VMOVDQU16-128-1) { -ICLASS: VFMSUBADD213PS +ICLASS: VMOVDQU16 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 +IFORM: VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512 } { -ICLASS: VFMSUBADD213PS +ICLASS: VMOVDQU16 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 +IFORM: VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512 } -# EMITTING VFMSUBADD213PS (VFMSUBADD213PS-256-1) +# EMITTING VMOVDQU16 (VMOVDQU16-128-2) { -ICLASS: VFMSUBADD213PS +ICLASS: VMOVDQU16 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 -IFORM: VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u16 +IFORM: VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512 } + +# EMITTING VMOVDQU16 (VMOVDQU16-128-3) { -ICLASS: VFMSUBADD213PS +ICLASS: VMOVDQU16 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:dq:u16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u16 +IFORM: VMOVDQU16_MEMu16_MASKmskw_XMMu16_AVX512 } -# EMITTING VFMSUBADD231PD (VFMSUBADD231PD-128-1) +# EMITTING VMOVDQU16 (VMOVDQU16-256-1) { -ICLASS: VFMSUBADD231PD +ICLASS: VMOVDQU16 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 +IFORM: VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512 } { -ICLASS: VFMSUBADD231PD +ICLASS: VMOVDQU16 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 +IFORM: VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512 } -# EMITTING VFMSUBADD231PD (VFMSUBADD231PD-256-1) +# EMITTING VMOVDQU16 (VMOVDQU16-256-2) { -ICLASS: VFMSUBADD231PD +ICLASS: VMOVDQU16 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 -IFORM: VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u16 +IFORM: VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512 } + +# EMITTING VMOVDQU16 (VMOVDQU16-256-3) { -ICLASS: VFMSUBADD231PD +ICLASS: VMOVDQU16 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:qq:u16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u16 +IFORM: VMOVDQU16_MEMu16_MASKmskw_YMMu16_AVX512 } -# EMITTING VFMSUBADD231PS (VFMSUBADD231PS-128-1) +# EMITTING VMOVDQU16 (VMOVDQU16-512-1) { -ICLASS: VFMSUBADD231PS +ICLASS: VMOVDQU16 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 +IFORM: VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512 } { -ICLASS: VFMSUBADD231PS +ICLASS: VMOVDQU16 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 +IFORM: VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512 } -# EMITTING VFMSUBADD231PS (VFMSUBADD231PS-256-1) +# EMITTING VMOVDQU16 (VMOVDQU16-512-2) { -ICLASS: VFMSUBADD231PS +ICLASS: VMOVDQU16 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 -IFORM: VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu16 +IFORM: VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512 } + +# EMITTING VMOVDQU16 (VMOVDQU16-512-3) { -ICLASS: VFMSUBADD231PS +ICLASS: VMOVDQU16 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:zd:u16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu16 +IFORM: VMOVDQU16_MEMu16_MASKmskw_ZMMu16_AVX512 } -# EMITTING VFNMADD132PD (VFNMADD132PD-128-1) +# EMITTING VMOVDQU32 (VMOVDQU32-128-1) { -ICLASS: VFNMADD132PD +ICLASS: VMOVDQU32 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 -REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 +IFORM: VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512 } { -ICLASS: VFNMADD132PD +ICLASS: VMOVDQU32 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VFNMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u32 +IFORM: VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512 } -# EMITTING VFNMADD132PD (VFNMADD132PD-256-1) +# EMITTING VMOVDQU32 (VMOVDQU32-128-2) { -ICLASS: VFNMADD132PD +ICLASS: VMOVDQU32 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 -IFORM: VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32 +IFORM: VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512 } + +# EMITTING VMOVDQU32 (VMOVDQU32-128-3) { -ICLASS: VFNMADD132PD +ICLASS: VMOVDQU32 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VFNMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32 +IFORM: VMOVDQU32_MEMu32_MASKmskw_XMMu32_AVX512 } -# EMITTING VFNMADD132PS (VFNMADD132PS-128-1) +# EMITTING VMOVDQU32 (VMOVDQU32-256-1) { -ICLASS: VFNMADD132PS +ICLASS: VMOVDQU32 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 +IFORM: VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512 } { -ICLASS: VFNMADD132PS +ICLASS: VMOVDQU32 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VFNMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u32 +IFORM: VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512 } -# EMITTING VFNMADD132PS (VFNMADD132PS-256-1) +# EMITTING VMOVDQU32 (VMOVDQU32-256-2) { -ICLASS: VFNMADD132PS +ICLASS: VMOVDQU32 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 -IFORM: VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 +IFORM: VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512 } + +# EMITTING VMOVDQU32 (VMOVDQU32-256-3) { -ICLASS: VFNMADD132PS +ICLASS: VMOVDQU32 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VFNMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 +IFORM: VMOVDQU32_MEMu32_MASKmskw_YMMu32_AVX512 } -# EMITTING VFNMADD213PD (VFNMADD213PD-128-1) +# EMITTING VMOVDQU64 (VMOVDQU64-128-1) { -ICLASS: VFNMADD213PD +ICLASS: VMOVDQU64 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 +IFORM: VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512 } { -ICLASS: VFNMADD213PD +ICLASS: VMOVDQU64 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VFNMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u64 +IFORM: VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512 } -# EMITTING VFNMADD213PD (VFNMADD213PD-256-1) +# EMITTING VMOVDQU64 (VMOVDQU64-128-2) { -ICLASS: VFNMADD213PD +ICLASS: VMOVDQU64 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 -IFORM: VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 +IFORM: VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512 } + +# EMITTING VMOVDQU64 (VMOVDQU64-128-3) { -ICLASS: VFNMADD213PD +ICLASS: VMOVDQU64 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VFNMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:dq:u64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 +IFORM: VMOVDQU64_MEMu64_MASKmskw_XMMu64_AVX512 } -# EMITTING VFNMADD213PS (VFNMADD213PS-128-1) +# EMITTING VMOVDQU64 (VMOVDQU64-256-1) { -ICLASS: VFNMADD213PS +ICLASS: VMOVDQU64 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 +IFORM: VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512 } { -ICLASS: VFNMADD213PS +ICLASS: VMOVDQU64 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VFNMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u64 +IFORM: VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512 } -# EMITTING VFNMADD213PS (VFNMADD213PS-256-1) +# EMITTING VMOVDQU64 (VMOVDQU64-256-2) { -ICLASS: VFNMADD213PS +ICLASS: VMOVDQU64 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 -IFORM: VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 +IFORM: VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512 } + +# EMITTING VMOVDQU64 (VMOVDQU64-256-3) { -ICLASS: VFNMADD213PS +ICLASS: VMOVDQU64 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VFNMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:qq:u64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 +IFORM: VMOVDQU64_MEMu64_MASKmskw_YMMu64_AVX512 } -# EMITTING VFNMADD231PD (VFNMADD231PD-128-1) +# EMITTING VMOVDQU8 (VMOVDQU8-128-1) { -ICLASS: VFNMADD231PD +ICLASS: VMOVDQU8 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u8 +IFORM: VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512 } { -ICLASS: VFNMADD231PD +ICLASS: VMOVDQU8 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VFNMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u8 +IFORM: VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512 } -# EMITTING VFNMADD231PD (VFNMADD231PD-256-1) +# EMITTING VMOVDQU8 (VMOVDQU8-128-2) { -ICLASS: VFNMADD231PD +ICLASS: VMOVDQU8 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 -IFORM: VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u8 +IFORM: VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512 } + +# EMITTING VMOVDQU8 (VMOVDQU8-128-3) { -ICLASS: VFNMADD231PD +ICLASS: VMOVDQU8 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VFNMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:dq:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u8 +IFORM: VMOVDQU8_MEMu8_MASKmskw_XMMu8_AVX512 } -# EMITTING VFNMADD231PS (VFNMADD231PS-128-1) +# EMITTING VMOVDQU8 (VMOVDQU8-256-1) { -ICLASS: VFNMADD231PS +ICLASS: VMOVDQU8 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u8 +IFORM: VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512 } { -ICLASS: VFNMADD231PS +ICLASS: VMOVDQU8 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VFNMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u8 +IFORM: VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512 } -# EMITTING VFNMADD231PS (VFNMADD231PS-256-1) +# EMITTING VMOVDQU8 (VMOVDQU8-256-2) { -ICLASS: VFNMADD231PS +ICLASS: VMOVDQU8 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 -IFORM: VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u8 +IFORM: VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512 } + +# EMITTING VMOVDQU8 (VMOVDQU8-256-3) { -ICLASS: VFNMADD231PS +ICLASS: VMOVDQU8 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VFNMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:qq:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u8 +IFORM: VMOVDQU8_MEMu8_MASKmskw_YMMu8_AVX512 } -# EMITTING VFNMSUB132PD (VFNMSUB132PD-128-1) +# EMITTING VMOVDQU8 (VMOVDQU8-512-1) { -ICLASS: VFNMSUB132PD +ICLASS: VMOVDQU8 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu8 +IFORM: VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512 } { -ICLASS: VFNMSUB132PD +ICLASS: VMOVDQU8 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u8 +IFORM: VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512 } -# EMITTING VFNMSUB132PD (VFNMSUB132PD-256-1) +# EMITTING VMOVDQU8 (VMOVDQU8-512-2) { -ICLASS: VFNMSUB132PD +ICLASS: VMOVDQU8 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 -IFORM: VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu8 +IFORM: VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512 } + +# EMITTING VMOVDQU8 (VMOVDQU8-512-3) { -ICLASS: VFNMSUB132PD +ICLASS: VMOVDQU8 CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:zd:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu8 +IFORM: VMOVDQU8_MEMu8_MASKmskw_ZMMu8_AVX512 } -# EMITTING VFNMSUB132PS (VFNMSUB132PS-128-1) +# EMITTING VMOVNTDQ (VMOVNTDQ-128-1) { -ICLASS: VFNMSUB132PS +ICLASS: VMOVNTDQ CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E1NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0xE7 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:dq:u32 REG0=XMM_R3():r:dq:u32 +IFORM: VMOVNTDQ_MEMu32_XMMu32_AVX512 } + +# EMITTING VMOVNTDQ (VMOVNTDQ-256-1) { -ICLASS: VFNMSUB132PS +ICLASS: VMOVNTDQ CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0xE7 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:qq:u32 REG0=YMM_R3():r:qq:u32 +IFORM: VMOVNTDQ_MEMu32_YMMu32_AVX512 } -# EMITTING VFNMSUB132PS (VFNMSUB132PS-256-1) +# EMITTING VMOVNTDQA (VMOVNTDQA-128-1) { -ICLASS: VFNMSUB132PS +ICLASS: VMOVNTDQA CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 -IFORM: VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x2A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u32 MEM0:r:dq:u32 +IFORM: VMOVNTDQA_XMMu32_MEMu32_AVX512 } + +# EMITTING VMOVNTDQA (VMOVNTDQA-256-1) { -ICLASS: VFNMSUB132PS +ICLASS: VMOVNTDQA CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E1NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x2A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u32 MEM0:r:qq:u32 +IFORM: VMOVNTDQA_YMMu32_MEMu32_AVX512 } -# EMITTING VFNMSUB213PD (VFNMSUB213PD-128-1) +# EMITTING VMOVNTPD (VMOVNTPD-128-1) { -ICLASS: VFNMSUB213PD +ICLASS: VMOVNTPD CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E1NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x2B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:dq:f64 REG0=XMM_R3():r:dq:f64 +IFORM: VMOVNTPD_MEMf64_XMMf64_AVX512 } + +# EMITTING VMOVNTPD (VMOVNTPD-256-1) { -ICLASS: VFNMSUB213PD +ICLASS: VMOVNTPD CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x2B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:qq:f64 REG0=YMM_R3():r:qq:f64 +IFORM: VMOVNTPD_MEMf64_YMMf64_AVX512 } -# EMITTING VFNMSUB213PD (VFNMSUB213PD-256-1) +# EMITTING VMOVNTPS (VMOVNTPS-128-1) { -ICLASS: VFNMSUB213PD +ICLASS: VMOVNTPS CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 -IFORM: VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x2B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:dq:f32 REG0=XMM_R3():r:dq:f32 +IFORM: VMOVNTPS_MEMf32_XMMf32_AVX512 } + +# EMITTING VMOVNTPS (VMOVNTPS-256-1) { -ICLASS: VFNMSUB213PD +ICLASS: VMOVNTPS CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E1NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x2B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:qq:f32 REG0=YMM_R3():r:qq:f32 +IFORM: VMOVNTPS_MEMf32_YMMf32_AVX512 } -# EMITTING VFNMSUB213PS (VFNMSUB213PS-128-1) +# EMITTING VMOVSHDUP (VMOVSHDUP-128-1) { -ICLASS: VFNMSUB213PS +ICLASS: VMOVSHDUP CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x16 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VMOVSHDUP_XMMf32_MASKmskw_XMMf32_AVX512 } { -ICLASS: VFNMSUB213PS +ICLASS: VMOVSHDUP CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x16 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32 +IFORM: VMOVSHDUP_XMMf32_MASKmskw_MEMf32_AVX512 } -# EMITTING VFNMSUB213PS (VFNMSUB213PS-256-1) +# EMITTING VMOVSHDUP (VMOVSHDUP-256-1) { -ICLASS: VFNMSUB213PS +ICLASS: VMOVSHDUP CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 -IFORM: VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x16 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VMOVSHDUP_YMMf32_MASKmskw_YMMf32_AVX512 } { -ICLASS: VFNMSUB213PS +ICLASS: VMOVSHDUP CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x16 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32 +IFORM: VMOVSHDUP_YMMf32_MASKmskw_MEMf32_AVX512 } -# EMITTING VFNMSUB231PD (VFNMSUB231PD-128-1) +# EMITTING VMOVSLDUP (VMOVSLDUP-128-1) { -ICLASS: VFNMSUB231PD +ICLASS: VMOVSLDUP CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x12 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VMOVSLDUP_XMMf32_MASKmskw_XMMf32_AVX512 } { -ICLASS: VFNMSUB231PD +ICLASS: VMOVSLDUP CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x12 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32 +IFORM: VMOVSLDUP_XMMf32_MASKmskw_MEMf32_AVX512 } -# EMITTING VFNMSUB231PD (VFNMSUB231PD-256-1) +# EMITTING VMOVSLDUP (VMOVSLDUP-256-1) { -ICLASS: VFNMSUB231PD +ICLASS: VMOVSLDUP CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 -IFORM: VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x12 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512 } { -ICLASS: VFNMSUB231PD +ICLASS: VMOVSLDUP CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x12 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32 +IFORM: VMOVSLDUP_YMMf32_MASKmskw_MEMf32_AVX512 } -# EMITTING VFNMSUB231PS (VFNMSUB231PS-128-1) +# EMITTING VMOVUPD (VMOVUPD-128-1) { -ICLASS: VFNMSUB231PS +ICLASS: VMOVUPD CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x10 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512 } { -ICLASS: VFNMSUB231PS +ICLASS: VMOVUPD CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x10 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f64 +IFORM: VMOVUPD_XMMf64_MASKmskw_MEMf64_AVX512 } -# EMITTING VFNMSUB231PS (VFNMSUB231PS-256-1) +# EMITTING VMOVUPD (VMOVUPD-128-2) { -ICLASS: VFNMSUB231PS +ICLASS: VMOVUPD CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x11 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f64 +IFORM: VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512 +} + + +# EMITTING VMOVUPD (VMOVUPD-128-3) +{ +ICLASS: VMOVUPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x11 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:dq:f64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f64 +IFORM: VMOVUPD_MEMf64_MASKmskw_XMMf64_AVX512 +} + + +# EMITTING VMOVUPD (VMOVUPD-256-1) +{ +ICLASS: VMOVUPD +CPL: 3 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 -IFORM: VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x10 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512 } { -ICLASS: VFNMSUB231PS +ICLASS: VMOVUPD CPL: 3 -CATEGORY: VFMA +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x10 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f64 +IFORM: VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512 } -# EMITTING VFPCLASSPD (VFPCLASSPD-128-1) +# EMITTING VMOVUPD (VMOVUPD-256-2) { -ICLASS: VFPCLASSPD +ICLASS: VMOVUPD CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 UIMM8() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_B3():r:dq:f64 IMM0:r:b -IFORM: VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x11 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f64 +IFORM: VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512 } + +# EMITTING VMOVUPD (VMOVUPD-256-3) { -ICLASS: VFPCLASSPD +ICLASS: VMOVUPD CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b -IFORM: VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x11 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:qq:f64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f64 +IFORM: VMOVUPD_MEMf64_MASKmskw_YMMf64_AVX512 } -# EMITTING VFPCLASSPD (VFPCLASSPD-256-1) +# EMITTING VMOVUPS (VMOVUPS-128-1) { -ICLASS: VFPCLASSPD +ICLASS: VMOVUPS CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 UIMM8() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_B3():r:qq:f64 IMM0:r:b -IFORM: VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x10 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512 } { -ICLASS: VFPCLASSPD +ICLASS: VMOVUPS CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b -IFORM: VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x10 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32 +IFORM: VMOVUPS_XMMf32_MASKmskw_MEMf32_AVX512 } -# EMITTING VFPCLASSPD (VFPCLASSPD-512-1) +# EMITTING VMOVUPS (VMOVUPS-128-2) { -ICLASS: VFPCLASSPD +ICLASS: VMOVUPS CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 UIMM8() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf64 IMM0:r:b -IFORM: VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x11 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f32 +IFORM: VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512 } + +# EMITTING VMOVUPS (VMOVUPS-128-3) { -ICLASS: VFPCLASSPD +ICLASS: VMOVUPS CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b -IFORM: VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x11 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:dq:f32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f32 +IFORM: VMOVUPS_MEMf32_MASKmskw_XMMf32_AVX512 } -# EMITTING VFPCLASSPS (VFPCLASSPS-128-1) +# EMITTING VMOVUPS (VMOVUPS-256-1) { -ICLASS: VFPCLASSPS +ICLASS: VMOVUPS CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 UIMM8() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_B3():r:dq:f32 IMM0:r:b -IFORM: VFPCLASSPS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x10 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512 } { -ICLASS: VFPCLASSPS +ICLASS: VMOVUPS CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b -IFORM: VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x10 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32 +IFORM: VMOVUPS_YMMf32_MASKmskw_MEMf32_AVX512 } -# EMITTING VFPCLASSPS (VFPCLASSPS-256-1) +# EMITTING VMOVUPS (VMOVUPS-256-2) { -ICLASS: VFPCLASSPS +ICLASS: VMOVUPS CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 UIMM8() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_B3():r:qq:f32 IMM0:r:b -IFORM: VFPCLASSPS_MASKmskw_MASKmskw_YMMf32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x11 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f32 +IFORM: VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512 } + +# EMITTING VMOVUPS (VMOVUPS-256-3) { -ICLASS: VFPCLASSPS +ICLASS: VMOVUPS CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b -IFORM: VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x11 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:qq:f32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f32 +IFORM: VMOVUPS_MEMf32_MASKmskw_YMMf32_AVX512 } -# EMITTING VFPCLASSPS (VFPCLASSPS-512-1) +# EMITTING VMULPD (VMULPD-128-1) { -ICLASS: VFPCLASSPS +ICLASS: VMULPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 UIMM8() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf32 IMM0:r:b -IFORM: VFPCLASSPS_MASKmskw_MASKmskw_ZMMf32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x59 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VFPCLASSPS +ICLASS: VMULPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b -IFORM: VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x59 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VMULPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 } -# EMITTING VFPCLASSSD (VFPCLASSSD-128-1) +# EMITTING VMULPD (VMULPD-256-1) { -ICLASS: VFPCLASSSD +ICLASS: VMULPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_SCALAR -EXCEPTIONS: AVX512-E6 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x67 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 NOEVSR ZEROING=0 UIMM8() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_B3():r:dq:f64 IMM0:r:b -IFORM: VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x59 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 } { -ICLASS: VFPCLASSSD +ICLASS: VMULPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_SCALAR -EXCEPTIONS: AVX512-E6 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0x67 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:q:f64 IMM0:r:b -IFORM: VFPCLASSSD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x59 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VMULPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 } -# EMITTING VFPCLASSSS (VFPCLASSSS-128-1) +# EMITTING VMULPS (VMULPS-128-1) { -ICLASS: VFPCLASSSS +ICLASS: VMULPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_SCALAR -EXCEPTIONS: AVX512-E6 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x67 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 UIMM8() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_B3():r:dq:f32 IMM0:r:b -IFORM: VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x59 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VFPCLASSSS +ICLASS: VMULPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_SCALAR -EXCEPTIONS: AVX512-E6 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0x67 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:d:f32 IMM0:r:b -IFORM: VFPCLASSSS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x59 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VMULPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 } -# EMITTING VGATHERDPD (VGATHERDPD-128-1) +# EMITTING VMULPS (VMULPS-256-1) { -ICLASS: VGATHERDPD +ICLASS: VMULPS CPL: 3 -CATEGORY: GATHER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E12 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W1 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASKNOT0():rw:mskw MEM0:r:dq:f64 -IFORM: VGATHERDPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x59 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 } - -# EMITTING VGATHERDPD (VGATHERDPD-256-1) { -ICLASS: VGATHERDPD +ICLASS: VMULPS CPL: 3 -CATEGORY: GATHER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E12 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W1 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASKNOT0():rw:mskw MEM0:r:qq:f64 -IFORM: VGATHERDPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x59 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VMULPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 } -# EMITTING VGATHERDPS (VGATHERDPS-128-1) +# EMITTING VORPD (VORPD-128-1) { -ICLASS: VGATHERDPS +ICLASS: VORPD CPL: 3 -CATEGORY: GATHER +CATEGORY: LOGICAL_FP EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E12 +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W0 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASKNOT0():rw:mskw MEM0:r:dq:f32 -IFORM: VGATHERDPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x56 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 } - -# EMITTING VGATHERDPS (VGATHERDPS-256-1) { -ICLASS: VGATHERDPS +ICLASS: VORPD CPL: 3 -CATEGORY: GATHER +CATEGORY: LOGICAL_FP EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E12 +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W0 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASKNOT0():rw:mskw MEM0:r:qq:f32 -IFORM: VGATHERDPS_YMMf32_MASKmskw_MEMf32_AVX512_VL256 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x56 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 } -# EMITTING VGATHERQPD (VGATHERQPD-128-1) +# EMITTING VORPD (VORPD-256-1) { -ICLASS: VGATHERQPD +ICLASS: VORPD CPL: 3 -CATEGORY: GATHER +CATEGORY: LOGICAL_FP EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E12 +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W1 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASKNOT0():rw:mskw MEM0:r:dq:f64 -IFORM: VGATHERQPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x56 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 } - -# EMITTING VGATHERQPD (VGATHERQPD-256-1) { -ICLASS: VGATHERQPD +ICLASS: VORPD CPL: 3 -CATEGORY: GATHER +CATEGORY: LOGICAL_FP EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E12 +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASKNOT0():rw:mskw MEM0:r:qq:f64 -IFORM: VGATHERQPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x56 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 } -# EMITTING VGATHERQPS (VGATHERQPS-128-1) +# EMITTING VORPD (VORPD-512-1) { -ICLASS: VGATHERQPS +ICLASS: VORPD CPL: 3 -CATEGORY: GATHER +CATEGORY: LOGICAL_FP EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E12 +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W0 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASKNOT0():rw:mskw MEM0:r:q:f32 -IFORM: VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x56 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 } - -# EMITTING VGATHERQPS (VGATHERQPS-256-1) { -ICLASS: VGATHERQPS +ICLASS: VORPD CPL: 3 -CATEGORY: GATHER +CATEGORY: LOGICAL_FP EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E12 +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W0 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASKNOT0():rw:mskw MEM0:r:dq:f32 -IFORM: VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL256 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x56 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 } -# EMITTING VGETEXPPD (VGETEXPPD-128-1) +# EMITTING VORPS (VORPS-128-1) { -ICLASS: VGETEXPPD +ICLASS: VORPS CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL_FP EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 -IFORM: VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x56 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 } { -ICLASS: VGETEXPPD +ICLASS: VORPS CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL_FP EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VGETEXPPD_XMMf64_MASKmskw_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x56 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 } -# EMITTING VGETEXPPD (VGETEXPPD-256-1) +# EMITTING VORPS (VORPS-256-1) { -ICLASS: VGETEXPPD +ICLASS: VORPS CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL_FP EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 -IFORM: VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x56 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 } { -ICLASS: VGETEXPPD +ICLASS: VORPS CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL_FP EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VGETEXPPD_YMMf64_MASKmskw_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x56 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 } -# EMITTING VGETEXPPS (VGETEXPPS-128-1) +# EMITTING VORPS (VORPS-512-1) { -ICLASS: VGETEXPPS +ICLASS: VORPS CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL_FP EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 -IFORM: VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x56 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 } { -ICLASS: VGETEXPPS +ICLASS: VORPS CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL_FP EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VGETEXPPS_XMMf32_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x56 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 } -# EMITTING VGETEXPPS (VGETEXPPS-256-1) +# EMITTING VPABSB (VPABSB-128-1) { -ICLASS: VGETEXPPS +ICLASS: VPABSB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 -IFORM: VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPABSB_XMMi8_MASKmskw_XMMi8_AVX512 } { -ICLASS: VGETEXPPS +ICLASS: VPABSB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VGETEXPPS_YMMf32_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x1C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i8 +IFORM: VPABSB_XMMi8_MASKmskw_MEMi8_AVX512 } -# EMITTING VGETMANTPD (VGETMANTPD-128-1) +# EMITTING VPABSB (VPABSB-256-1) { -ICLASS: VGETMANTPD +ICLASS: VPABSB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR UIMM8() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 IMM0:r:b -IFORM: VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i8 +IFORM: VPABSB_YMMi8_MASKmskw_YMMi8_AVX512 } { -ICLASS: VGETMANTPD +ICLASS: VPABSB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b -IFORM: VGETMANTPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x1C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i8 +IFORM: VPABSB_YMMi8_MASKmskw_MEMi8_AVX512 } -# EMITTING VGETMANTPD (VGETMANTPD-256-1) +# EMITTING VPABSB (VPABSB-512-1) { -ICLASS: VGETMANTPD +ICLASS: VPABSB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 IMM0:r:b -IFORM: VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi8 +IFORM: VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512 } { -ICLASS: VGETMANTPD +ICLASS: VPABSB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b -IFORM: VGETMANTPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x1C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:i8 +IFORM: VPABSB_ZMMi8_MASKmskw_MEMi8_AVX512 } -# EMITTING VGETMANTPS (VGETMANTPS-128-1) +# EMITTING VPABSD (VPABSD-128-1) { -ICLASS: VGETMANTPS +ICLASS: VPABSD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 IMM0:r:b -IFORM: VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 +IFORM: VPABSD_XMMi32_MASKmskw_XMMi32_AVX512 } { -ICLASS: VGETMANTPS +ICLASS: VPABSD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b -IFORM: VGETMANTPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPABSD_XMMi32_MASKmskw_MEMi32_AVX512 } -# EMITTING VGETMANTPS (VGETMANTPS-256-1) +# EMITTING VPABSD (VPABSD-256-1) { -ICLASS: VGETMANTPS +ICLASS: VPABSD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 IMM0:r:b -IFORM: VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32 +IFORM: VPABSD_YMMi32_MASKmskw_YMMi32_AVX512 } { -ICLASS: VGETMANTPS +ICLASS: VPABSD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b -IFORM: VGETMANTPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPABSD_YMMi32_MASKmskw_MEMi32_AVX512 } -# EMITTING VINSERTF32X4 (VINSERTF32X4-256-1) +# EMITTING VPABSQ (VPABSQ-128-1) { -ICLASS: VINSERTF32X4 +ICLASS: VPABSQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x18 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b -IFORM: VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512 +PATTERN: EVV 0x1F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i64 +IFORM: VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512 } { -ICLASS: VINSERTF32X4 +ICLASS: VPABSQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 -PATTERN: EVV 0x18 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:dq:f32 IMM0:r:b -IFORM: VINSERTF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i64:TXT=BCASTSTR +IFORM: VPABSQ_XMMi64_MASKmskw_MEMi64_AVX512 } -# EMITTING VINSERTF32X8 (VINSERTF32X8-512-1) +# EMITTING VPABSQ (VPABSQ-256-1) { -ICLASS: VINSERTF32X8 +ICLASS: VPABSQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x1A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=YMM_B3():r:qq:f32 IMM0:r:b -IFORM: VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512 +PATTERN: EVV 0x1F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i64 +IFORM: VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512 } { -ICLASS: VINSERTF32X8 +ICLASS: VPABSQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE8 -PATTERN: EVV 0x1A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE8() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:qq:f32 IMM0:r:b -IFORM: VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i64:TXT=BCASTSTR +IFORM: VPABSQ_YMMi64_MASKmskw_MEMi64_AVX512 } -# EMITTING VINSERTF64X2 (VINSERTF64X2-256-1) +# EMITTING VPABSW (VPABSW-128-1) { -ICLASS: VINSERTF64X2 +ICLASS: VPABSW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x18 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b -IFORM: VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512 +PATTERN: EVV 0x1D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 +IFORM: VPABSW_XMMi16_MASKmskw_XMMi16_AVX512 } { -ICLASS: VINSERTF64X2 +ICLASS: VPABSW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 -PATTERN: EVV 0x18 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:dq:f64 IMM0:r:b -IFORM: VINSERTF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x1D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i16 +IFORM: VPABSW_XMMi16_MASKmskw_MEMi16_AVX512 } -# EMITTING VINSERTF64X2 (VINSERTF64X2-512-1) +# EMITTING VPABSW (VPABSW-256-1) { -ICLASS: VINSERTF64X2 +ICLASS: VPABSW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x18 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=XMM_B3():r:dq:f64 IMM0:r:b -IFORM: VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512 +PATTERN: EVV 0x1D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i16 +IFORM: VPABSW_YMMi16_MASKmskw_YMMi16_AVX512 } { -ICLASS: VINSERTF64X2 +ICLASS: VPABSW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 -PATTERN: EVV 0x18 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:dq:f64 IMM0:r:b -IFORM: VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x1D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i16 +IFORM: VPABSW_YMMi16_MASKmskw_MEMi16_AVX512 } -# EMITTING VINSERTI32X4 (VINSERTI32X4-256-1) +# EMITTING VPABSW (VPABSW-512-1) { -ICLASS: VINSERTI32X4 +ICLASS: VPABSW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x38 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=XMM_B3():r:dq:u32 IMM0:r:b -IFORM: VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512 +PATTERN: EVV 0x1D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi16 +IFORM: VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512 } { -ICLASS: VINSERTI32X4 +ICLASS: VPABSW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 -PATTERN: EVV 0x38 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:dq:u32 IMM0:r:b -IFORM: VINSERTI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x1D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:i16 +IFORM: VPABSW_ZMMi16_MASKmskw_MEMi16_AVX512 } -# EMITTING VINSERTI32X8 (VINSERTI32X8-512-1) +# EMITTING VPACKSSDW (VPACKSSDW-128-1) { -ICLASS: VINSERTI32X8 +ICLASS: VPACKSSDW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x3A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=YMM_B3():r:qq:u32 IMM0:r:b -IFORM: VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512 +PATTERN: EVV 0x6B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 REG3=XMM_B3():r:dq:i32 +IFORM: VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512 } { -ICLASS: VINSERTI32X8 +ICLASS: VPACKSSDW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE8 -PATTERN: EVV 0x3A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE8() -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:qq:u32 IMM0:r:b -IFORM: VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x6B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPACKSSDW_XMMi16_MASKmskw_XMMi32_MEMi32_AVX512 } -# EMITTING VINSERTI64X2 (VINSERTI64X2-256-1) +# EMITTING VPACKSSDW (VPACKSSDW-256-1) { -ICLASS: VINSERTI64X2 +ICLASS: VPACKSSDW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x38 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=XMM_B3():r:dq:u64 IMM0:r:b -IFORM: VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512 +PATTERN: EVV 0x6B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 REG3=YMM_B3():r:qq:i32 +IFORM: VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512 } { -ICLASS: VINSERTI64X2 +ICLASS: VPACKSSDW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 -PATTERN: EVV 0x38 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:dq:u64 IMM0:r:b -IFORM: VINSERTI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x6B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPACKSSDW_YMMi16_MASKmskw_YMMi32_MEMi32_AVX512 } -# EMITTING VINSERTI64X2 (VINSERTI64X2-512-1) +# EMITTING VPACKSSDW (VPACKSSDW-512-1) { -ICLASS: VINSERTI64X2 +ICLASS: VPACKSSDW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x38 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=XMM_B3():r:dq:u64 IMM0:r:b -IFORM: VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512 +PATTERN: EVV 0x6B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 REG3=ZMM_B3():r:zi32 +IFORM: VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512 } { -ICLASS: VINSERTI64X2 +ICLASS: VPACKSSDW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 -PATTERN: EVV 0x38 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:dq:u64 IMM0:r:b -IFORM: VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x6B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_MEMi32_AVX512 } -# EMITTING VMAXPD (VMAXPD-128-1) +# EMITTING VPACKSSWB (VPACKSSWB-128-1) { -ICLASS: VMAXPD +ICLASS: VPACKSSWB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x63 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 +IFORM: VPACKSSWB_XMMi8_MASKmskw_XMMi16_XMMi16_AVX512 } { -ICLASS: VMAXPD +ICLASS: VPACKSSWB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x5F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x63 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 +IFORM: VPACKSSWB_XMMi8_MASKmskw_XMMi16_MEMi16_AVX512 } -# EMITTING VMAXPD (VMAXPD-256-1) +# EMITTING VPACKSSWB (VPACKSSWB-256-1) { -ICLASS: VMAXPD +ICLASS: VPACKSSWB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 -IFORM: VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x63 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 +IFORM: VPACKSSWB_YMMi8_MASKmskw_YMMi16_YMMi16_AVX512 } { -ICLASS: VMAXPD +ICLASS: VPACKSSWB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x5F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x63 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 +IFORM: VPACKSSWB_YMMi8_MASKmskw_YMMi16_MEMi16_AVX512 } -# EMITTING VMAXPS (VMAXPS-128-1) +# EMITTING VPACKSSWB (VPACKSSWB-512-1) { -ICLASS: VMAXPS +ICLASS: VPACKSSWB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5F VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x63 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 +IFORM: VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512 } { -ICLASS: VMAXPS +ICLASS: VPACKSSWB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x5F VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x63 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 +IFORM: VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_MEMi16_AVX512 } -# EMITTING VMAXPS (VMAXPS-256-1) +# EMITTING VPACKUSDW (VPACKUSDW-128-1) { -ICLASS: VMAXPS +ICLASS: VPACKUSDW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5F VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 -IFORM: VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x2B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPACKUSDW_XMMu16_MASKmskw_XMMu32_XMMu32_AVX512 } { -ICLASS: VMAXPS +ICLASS: VPACKUSDW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x5F VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x2B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPACKUSDW_XMMu16_MASKmskw_XMMu32_MEMu32_AVX512 } -# EMITTING VMINPD (VMINPD-128-1) +# EMITTING VPACKUSDW (VPACKUSDW-256-1) { -ICLASS: VMINPD +ICLASS: VPACKUSDW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x2B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPACKUSDW_YMMu16_MASKmskw_YMMu32_YMMu32_AVX512 } { -ICLASS: VMINPD +ICLASS: VPACKUSDW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x5D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VMINPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x2B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPACKUSDW_YMMu16_MASKmskw_YMMu32_MEMu32_AVX512 } -# EMITTING VMINPD (VMINPD-256-1) +# EMITTING VPACKUSDW (VPACKUSDW-512-1) { -ICLASS: VMINPD +ICLASS: VPACKUSDW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 -IFORM: VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x2B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512 } { -ICLASS: VMINPD +ICLASS: VPACKUSDW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x5D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VMINPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x2B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_MEMu32_AVX512 } -# EMITTING VMINPS (VMINPS-128-1) +# EMITTING VPACKUSWB (VPACKUSWB-128-1) { -ICLASS: VMINPS +ICLASS: VPACKUSWB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5D VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x67 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPACKUSWB_XMMu8_MASKmskw_XMMu16_XMMu16_AVX512 } { -ICLASS: VMINPS +ICLASS: VPACKUSWB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x5D VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VMINPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x67 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPACKUSWB_XMMu8_MASKmskw_XMMu16_MEMu16_AVX512 } -# EMITTING VMINPS (VMINPS-256-1) +# EMITTING VPACKUSWB (VPACKUSWB-256-1) { -ICLASS: VMINPS +ICLASS: VPACKUSWB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5D VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 -IFORM: VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x67 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPACKUSWB_YMMu8_MASKmskw_YMMu16_YMMu16_AVX512 } { -ICLASS: VMINPS +ICLASS: VPACKUSWB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x5D VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VMINPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x67 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPACKUSWB_YMMu8_MASKmskw_YMMu16_MEMu16_AVX512 } -# EMITTING VMOVAPD (VMOVAPD-128-1) +# EMITTING VPACKUSWB (VPACKUSWB-512-1) { -ICLASS: VMOVAPD +ICLASS: VPACKUSWB CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E1 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x28 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 -IFORM: VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512 +PATTERN: EVV 0x67 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512 } { -ICLASS: VMOVAPD +ICLASS: VPACKUSWB CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E1 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x28 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f64 -IFORM: VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x67 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_MEMu16_AVX512 } -# EMITTING VMOVAPD (VMOVAPD-128-2) +# EMITTING VPADDB (VPADDB-128-1) { -ICLASS: VMOVAPD +ICLASS: VPADDB CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E1 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x29 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f64 -IFORM: VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512 +PATTERN: EVV 0xFC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPADDB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 } - -# EMITTING VMOVAPD (VMOVAPD-128-3) { -ICLASS: VMOVAPD +ICLASS: VPADDB CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E1 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x29 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() -OPERANDS: MEM0:w:dq:f64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f64 -IFORM: VMOVAPD_MEMf64_MASKmskw_XMMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xFC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPADDB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 } -# EMITTING VMOVAPD (VMOVAPD-256-1) +# EMITTING VPADDB (VPADDB-256-1) { -ICLASS: VMOVAPD +ICLASS: VPADDB CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E1 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x28 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 -IFORM: VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512 +PATTERN: EVV 0xFC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPADDB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 } { -ICLASS: VMOVAPD +ICLASS: VPADDB CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E1 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x28 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f64 -IFORM: VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xFC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPADDB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 } -# EMITTING VMOVAPD (VMOVAPD-256-2) +# EMITTING VPADDB (VPADDB-512-1) { -ICLASS: VMOVAPD +ICLASS: VPADDB CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E1 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x29 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR -OPERANDS: REG0=YMM_B3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f64 -IFORM: VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512 +PATTERN: EVV 0xFC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 } - -# EMITTING VMOVAPD (VMOVAPD-256-3) { -ICLASS: VMOVAPD +ICLASS: VPADDB CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E1 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x29 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() -OPERANDS: MEM0:w:qq:f64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f64 -IFORM: VMOVAPD_MEMf64_MASKmskw_YMMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xFC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPADDB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 } -# EMITTING VMOVAPS (VMOVAPS-128-1) +# EMITTING VPADDD (VPADDD-128-1) { -ICLASS: VMOVAPS +ICLASS: VPADDD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E1 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x28 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 -IFORM: VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512 +PATTERN: EVV 0xFE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPADDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 } { -ICLASS: VMOVAPS +ICLASS: VPADDD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E1 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x28 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32 -IFORM: VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xFE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPADDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 } -# EMITTING VMOVAPS (VMOVAPS-128-2) +# EMITTING VPADDD (VPADDD-256-1) { -ICLASS: VMOVAPS +ICLASS: VPADDD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E1 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x29 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f32 -IFORM: VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512 +PATTERN: EVV 0xFE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPADDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 } - -# EMITTING VMOVAPS (VMOVAPS-128-3) { -ICLASS: VMOVAPS +ICLASS: VPADDD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E1 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x29 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() -OPERANDS: MEM0:w:dq:f32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f32 -IFORM: VMOVAPS_MEMf32_MASKmskw_XMMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xFE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPADDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 } -# EMITTING VMOVAPS (VMOVAPS-256-1) +# EMITTING VPADDQ (VPADDQ-128-1) { -ICLASS: VMOVAPS +ICLASS: VPADDQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E1 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x28 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 -IFORM: VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512 +PATTERN: EVV 0xD4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPADDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 } { -ICLASS: VMOVAPS +ICLASS: VPADDQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E1 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x28 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32 -IFORM: VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xD4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPADDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 } -# EMITTING VMOVAPS (VMOVAPS-256-2) +# EMITTING VPADDQ (VPADDQ-256-1) { -ICLASS: VMOVAPS +ICLASS: VPADDQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E1 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x29 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=YMM_B3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f32 -IFORM: VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512 +PATTERN: EVV 0xD4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPADDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 } - -# EMITTING VMOVAPS (VMOVAPS-256-3) { -ICLASS: VMOVAPS +ICLASS: VPADDQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E1 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x29 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() -OPERANDS: MEM0:w:qq:f32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f32 -IFORM: VMOVAPS_MEMf32_MASKmskw_YMMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xD4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPADDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 } -# EMITTING VMOVDDUP (VMOVDDUP-128-1) +# EMITTING VPADDSB (VPADDSB-128-1) { -ICLASS: VMOVDDUP +ICLASS: VPADDSB CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E5NF +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x12 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 -IFORM: VMOVDDUP_XMMf64_MASKmskw_XMMf64_AVX512 +PATTERN: EVV 0xEC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 REG3=XMM_B3():r:dq:i8 +IFORM: VPADDSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 } { -ICLASS: VMOVDDUP +ICLASS: VPADDSB CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E5NF +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_MOVDDUP -PATTERN: EVV 0x12 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_MOVDDUP() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f64 -IFORM: VMOVDDUP_XMMf64_MASKmskw_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xEC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 MEM0:r:dq:i8 +IFORM: VPADDSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 } -# EMITTING VMOVDDUP (VMOVDDUP-256-1) +# EMITTING VPADDSB (VPADDSB-256-1) { -ICLASS: VMOVDDUP +ICLASS: VPADDSB CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E5NF +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x12 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 -IFORM: VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512 +PATTERN: EVV 0xEC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 REG3=YMM_B3():r:qq:i8 +IFORM: VPADDSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 } { -ICLASS: VMOVDDUP +ICLASS: VPADDSB CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E5NF +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_MOVDDUP -PATTERN: EVV 0x12 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_MOVDDUP() -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f64 -IFORM: VMOVDDUP_YMMf64_MASKmskw_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xEC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 MEM0:r:qq:i8 +IFORM: VPADDSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 } -# EMITTING VMOVDQA32 (VMOVDQA32-128-1) +# EMITTING VPADDSB (VPADDSB-512-1) { -ICLASS: VMOVDQA32 +ICLASS: VPADDSB CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E1 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 -IFORM: VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512 +PATTERN: EVV 0xEC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 REG3=ZMM_B3():r:zi8 +IFORM: VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 } { -ICLASS: VMOVDQA32 +ICLASS: VPADDSB CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E1 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u32 -IFORM: VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xEC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 MEM0:r:zd:i8 +IFORM: VPADDSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 } -# EMITTING VMOVDQA32 (VMOVDQA32-128-2) +# EMITTING VPADDSW (VPADDSW-128-1) { -ICLASS: VMOVDQA32 +ICLASS: VPADDSW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E1 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32 -IFORM: VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512 +PATTERN: EVV 0xED V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 +IFORM: VPADDSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 } - -# EMITTING VMOVDQA32 (VMOVDQA32-128-3) { -ICLASS: VMOVDQA32 +ICLASS: VPADDSW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E1 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() -OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32 -IFORM: VMOVDQA32_MEMu32_MASKmskw_XMMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xED V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 +IFORM: VPADDSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 } -# EMITTING VMOVDQA32 (VMOVDQA32-256-1) +# EMITTING VPADDSW (VPADDSW-256-1) { -ICLASS: VMOVDQA32 +ICLASS: VPADDSW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E1 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 -IFORM: VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512 +PATTERN: EVV 0xED V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 +IFORM: VPADDSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 } { -ICLASS: VMOVDQA32 +ICLASS: VPADDSW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E1 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u32 -IFORM: VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xED V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 +IFORM: VPADDSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 } -# EMITTING VMOVDQA32 (VMOVDQA32-256-2) +# EMITTING VPADDSW (VPADDSW-512-1) { -ICLASS: VMOVDQA32 +ICLASS: VPADDSW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E1 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=YMM_B3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 -IFORM: VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512 +PATTERN: EVV 0xED V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 +IFORM: VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 } - -# EMITTING VMOVDQA32 (VMOVDQA32-256-3) { -ICLASS: VMOVDQA32 +ICLASS: VPADDSW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E1 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() -OPERANDS: MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 -IFORM: VMOVDQA32_MEMu32_MASKmskw_YMMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xED V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 +IFORM: VPADDSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 } -# EMITTING VMOVDQA64 (VMOVDQA64-128-1) +# EMITTING VPADDUSB (VPADDUSB-128-1) { -ICLASS: VMOVDQA64 +ICLASS: VPADDUSB CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E1 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 -IFORM: VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512 +PATTERN: EVV 0xDC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPADDUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 } { -ICLASS: VMOVDQA64 +ICLASS: VPADDUSB CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E1 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u64 -IFORM: VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xDC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPADDUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 } -# EMITTING VMOVDQA64 (VMOVDQA64-128-2) +# EMITTING VPADDUSB (VPADDUSB-256-1) { -ICLASS: VMOVDQA64 +ICLASS: VPADDUSB CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E1 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 -IFORM: VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512 +PATTERN: EVV 0xDC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPADDUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 } - -# EMITTING VMOVDQA64 (VMOVDQA64-128-3) { -ICLASS: VMOVDQA64 +ICLASS: VPADDUSB CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E1 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() -OPERANDS: MEM0:w:dq:u64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 -IFORM: VMOVDQA64_MEMu64_MASKmskw_XMMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xDC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPADDUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 } -# EMITTING VMOVDQA64 (VMOVDQA64-256-1) +# EMITTING VPADDUSB (VPADDUSB-512-1) { -ICLASS: VMOVDQA64 +ICLASS: VPADDUSB CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E1 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 -IFORM: VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512 +PATTERN: EVV 0xDC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 } { -ICLASS: VMOVDQA64 +ICLASS: VPADDUSB CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E1 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u64 -IFORM: VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xDC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPADDUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 } -# EMITTING VMOVDQA64 (VMOVDQA64-256-2) +# EMITTING VPADDUSW (VPADDUSW-128-1) { -ICLASS: VMOVDQA64 +ICLASS: VPADDUSW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E1 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR -OPERANDS: REG0=YMM_B3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 -IFORM: VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512 +PATTERN: EVV 0xDD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPADDUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 } - -# EMITTING VMOVDQA64 (VMOVDQA64-256-3) { -ICLASS: VMOVDQA64 +ICLASS: VPADDUSW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E1 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() -OPERANDS: MEM0:w:qq:u64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 -IFORM: VMOVDQA64_MEMu64_MASKmskw_YMMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xDD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPADDUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 } -# EMITTING VMOVDQU16 (VMOVDQU16-128-1) +# EMITTING VPADDUSW (VPADDUSW-256-1) { -ICLASS: VMOVDQU16 +ICLASS: VPADDUSW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 +ISA_SET: AVX512BW_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 -IFORM: VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512 +PATTERN: EVV 0xDD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPADDUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 } { -ICLASS: VMOVDQU16 +ICLASS: VPADDUSW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 +ISA_SET: AVX512BW_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 -IFORM: VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512 +PATTERN: EVV 0xDD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPADDUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 } -# EMITTING VMOVDQU16 (VMOVDQU16-128-2) +# EMITTING VPADDUSW (VPADDUSW-512-1) { -ICLASS: VMOVDQU16 +ICLASS: VPADDUSW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 +ISA_SET: AVX512BW_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u16 -IFORM: VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512 +PATTERN: EVV 0xDD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 } - -# EMITTING VMOVDQU16 (VMOVDQU16-128-3) { -ICLASS: VMOVDQU16 +ICLASS: VPADDUSW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 +ISA_SET: AVX512BW_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: MEM0:w:dq:u16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u16 -IFORM: VMOVDQU16_MEMu16_MASKmskw_XMMu16_AVX512 +PATTERN: EVV 0xDD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPADDUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 } -# EMITTING VMOVDQU16 (VMOVDQU16-256-1) +# EMITTING VPADDW (VPADDW-128-1) { -ICLASS: VMOVDQU16 +ICLASS: VPADDW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 +ISA_SET: AVX512BW_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 -IFORM: VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512 +PATTERN: EVV 0xFD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPADDW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 } { -ICLASS: VMOVDQU16 +ICLASS: VPADDW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 +ISA_SET: AVX512BW_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 -IFORM: VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512 +PATTERN: EVV 0xFD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPADDW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 } -# EMITTING VMOVDQU16 (VMOVDQU16-256-2) +# EMITTING VPADDW (VPADDW-256-1) { -ICLASS: VMOVDQU16 +ICLASS: VPADDW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR -OPERANDS: REG0=YMM_B3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u16 -IFORM: VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512 +PATTERN: EVV 0xFD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPADDW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 } - -# EMITTING VMOVDQU16 (VMOVDQU16-256-3) { -ICLASS: VMOVDQU16 +ICLASS: VPADDW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: MEM0:w:qq:u16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u16 -IFORM: VMOVDQU16_MEMu16_MASKmskw_YMMu16_AVX512 +PATTERN: EVV 0xFD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPADDW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 } -# EMITTING VMOVDQU16 (VMOVDQU16-512-1) +# EMITTING VPADDW (VPADDW-512-1) { -ICLASS: VMOVDQU16 +ICLASS: VPADDW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 -IFORM: VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512 +PATTERN: EVV 0xFD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 } { -ICLASS: VMOVDQU16 +ICLASS: VPADDW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 -IFORM: VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512 +PATTERN: EVV 0xFD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPADDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 } -# EMITTING VMOVDQU16 (VMOVDQU16-512-2) +# EMITTING VPALIGNR (VPALIGNR-128-1) { -ICLASS: VMOVDQU16 +ICLASS: VPALIGNR CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR -OPERANDS: REG0=ZMM_B3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu16 -IFORM: VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512 +PATTERN: EVV 0x0F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 IMM0:r:b +IFORM: VPALIGNR_XMMu8_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 } - -# EMITTING VMOVDQU16 (VMOVDQU16-512-3) { -ICLASS: VMOVDQU16 +ICLASS: VPALIGNR CPL: 3 -CATEGORY: DATAXFER -EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: MEM0:w:zd:u16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu16 -IFORM: VMOVDQU16_MEMu16_MASKmskw_ZMMu16_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x0F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 UIMM8() ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 IMM0:r:b +IFORM: VPALIGNR_XMMu8_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 } -# EMITTING VMOVDQU32 (VMOVDQU32-128-1) +# EMITTING VPALIGNR (VPALIGNR-256-1) { -ICLASS: VMOVDQU32 +ICLASS: VPALIGNR CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 -IFORM: VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512 +PATTERN: EVV 0x0F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 IMM0:r:b +IFORM: VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 } { -ICLASS: VMOVDQU32 +ICLASS: VPALIGNR CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u32 -IFORM: VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x0F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 UIMM8() ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 IMM0:r:b +IFORM: VPALIGNR_YMMu8_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 } -# EMITTING VMOVDQU32 (VMOVDQU32-128-2) +# EMITTING VPALIGNR (VPALIGNR-512-1) { -ICLASS: VMOVDQU32 +ICLASS: VPALIGNR CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32 -IFORM: VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512 +PATTERN: EVV 0x0F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 IMM0:r:b +IFORM: VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 } - -# EMITTING VMOVDQU32 (VMOVDQU32-128-3) { -ICLASS: VMOVDQU32 +ICLASS: VPALIGNR CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() -OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32 -IFORM: VMOVDQU32_MEMu32_MASKmskw_XMMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x0F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 UIMM8() ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 IMM0:r:b +IFORM: VPALIGNR_ZMMu8_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 } -# EMITTING VMOVDQU32 (VMOVDQU32-256-1) +# EMITTING VPANDD (VPANDD-128-1) { -ICLASS: VMOVDQU32 +ICLASS: VPANDD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 -IFORM: VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512 +PATTERN: EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPANDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 } { -ICLASS: VMOVDQU32 +ICLASS: VPANDD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u32 -IFORM: VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPANDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 } -# EMITTING VMOVDQU32 (VMOVDQU32-256-2) +# EMITTING VPANDD (VPANDD-256-1) { -ICLASS: VMOVDQU32 +ICLASS: VPANDD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: LOGICAL EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=YMM_B3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 -IFORM: VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512 +PATTERN: EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPANDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 } - -# EMITTING VMOVDQU32 (VMOVDQU32-256-3) { -ICLASS: VMOVDQU32 +ICLASS: VPANDD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: LOGICAL EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() -OPERANDS: MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 -IFORM: VMOVDQU32_MEMu32_MASKmskw_YMMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPANDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 } -# EMITTING VMOVDQU64 (VMOVDQU64-128-1) +# EMITTING VPANDND (VPANDND-128-1) { -ICLASS: VMOVDQU64 +ICLASS: VPANDND CPL: 3 -CATEGORY: DATAXFER +CATEGORY: LOGICAL EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 -IFORM: VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512 +PATTERN: EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPANDND_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 } { -ICLASS: VMOVDQU64 +ICLASS: VPANDND CPL: 3 -CATEGORY: DATAXFER +CATEGORY: LOGICAL EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u64 -IFORM: VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPANDND_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 } -# EMITTING VMOVDQU64 (VMOVDQU64-128-2) +# EMITTING VPANDND (VPANDND-256-1) { -ICLASS: VMOVDQU64 +ICLASS: VPANDND CPL: 3 -CATEGORY: DATAXFER +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 -IFORM: VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512 +PATTERN: EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPANDND_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 } - -# EMITTING VMOVDQU64 (VMOVDQU64-128-3) { -ICLASS: VMOVDQU64 +ICLASS: VPANDND CPL: 3 -CATEGORY: DATAXFER +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() -OPERANDS: MEM0:w:dq:u64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 -IFORM: VMOVDQU64_MEMu64_MASKmskw_XMMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPANDND_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 } -# EMITTING VMOVDQU64 (VMOVDQU64-256-1) +# EMITTING VPANDNQ (VPANDNQ-128-1) { -ICLASS: VMOVDQU64 +ICLASS: VPANDNQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 -IFORM: VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512 +PATTERN: EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPANDNQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 } { -ICLASS: VMOVDQU64 +ICLASS: VPANDNQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u64 -IFORM: VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPANDNQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 } -# EMITTING VMOVDQU64 (VMOVDQU64-256-2) +# EMITTING VPANDNQ (VPANDNQ-256-1) { -ICLASS: VMOVDQU64 +ICLASS: VPANDNQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: LOGICAL EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR -OPERANDS: REG0=YMM_B3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 -IFORM: VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512 +PATTERN: EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPANDNQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 } - -# EMITTING VMOVDQU64 (VMOVDQU64-256-3) { -ICLASS: VMOVDQU64 +ICLASS: VPANDNQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: LOGICAL EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() -OPERANDS: MEM0:w:qq:u64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 -IFORM: VMOVDQU64_MEMu64_MASKmskw_YMMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPANDNQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 } -# EMITTING VMOVDQU8 (VMOVDQU8-128-1) +# EMITTING VPANDQ (VPANDQ-128-1) { -ICLASS: VMOVDQU8 +ICLASS: VPANDQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u8 -IFORM: VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512 +PATTERN: EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPANDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 } { -ICLASS: VMOVDQU8 +ICLASS: VPANDQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u8 -IFORM: VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPANDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 } -# EMITTING VMOVDQU8 (VMOVDQU8-128-2) +# EMITTING VPANDQ (VPANDQ-256-1) { -ICLASS: VMOVDQU8 +ICLASS: VPANDQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u8 -IFORM: VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512 +PATTERN: EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPANDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 } - -# EMITTING VMOVDQU8 (VMOVDQU8-128-3) { -ICLASS: VMOVDQU8 +ICLASS: VPANDQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: MEM0:w:dq:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u8 -IFORM: VMOVDQU8_MEMu8_MASKmskw_XMMu8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPANDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 } -# EMITTING VMOVDQU8 (VMOVDQU8-256-1) +# EMITTING VPAVGB (VPAVGB-128-1) { -ICLASS: VMOVDQU8 +ICLASS: VPAVGB CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 +ISA_SET: AVX512BW_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u8 -IFORM: VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512 +PATTERN: EVV 0xE0 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPAVGB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 } { -ICLASS: VMOVDQU8 +ICLASS: VPAVGB CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 +ISA_SET: AVX512BW_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u8 -IFORM: VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512 +PATTERN: EVV 0xE0 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPAVGB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 } -# EMITTING VMOVDQU8 (VMOVDQU8-256-2) +# EMITTING VPAVGB (VPAVGB-256-1) { -ICLASS: VMOVDQU8 +ICLASS: VPAVGB CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=YMM_B3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u8 -IFORM: VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512 +PATTERN: EVV 0xE0 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPAVGB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 } - -# EMITTING VMOVDQU8 (VMOVDQU8-256-3) { -ICLASS: VMOVDQU8 +ICLASS: VPAVGB CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: MEM0:w:qq:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u8 -IFORM: VMOVDQU8_MEMu8_MASKmskw_YMMu8_AVX512 +PATTERN: EVV 0xE0 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPAVGB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 } -# EMITTING VMOVDQU8 (VMOVDQU8-512-1) +# EMITTING VPAVGB (VPAVGB-512-1) { -ICLASS: VMOVDQU8 +ICLASS: VPAVGB CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu8 -IFORM: VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512 +PATTERN: EVV 0xE0 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 } { -ICLASS: VMOVDQU8 +ICLASS: VPAVGB CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u8 -IFORM: VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512 +PATTERN: EVV 0xE0 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPAVGB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 } -# EMITTING VMOVDQU8 (VMOVDQU8-512-2) +# EMITTING VPAVGW (VPAVGW-128-1) { -ICLASS: VMOVDQU8 +ICLASS: VPAVGW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 +ISA_SET: AVX512BW_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=ZMM_B3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu8 -IFORM: VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512 +PATTERN: EVV 0xE3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPAVGW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 } - -# EMITTING VMOVDQU8 (VMOVDQU8-512-3) { -ICLASS: VMOVDQU8 +ICLASS: VPAVGW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 +ISA_SET: AVX512BW_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: MEM0:w:zd:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu8 -IFORM: VMOVDQU8_MEMu8_MASKmskw_ZMMu8_AVX512 -} - - -# EMITTING VMOVNTDQ (VMOVNTDQ-128-1) -{ -ICLASS: VMOVNTDQ -CPL: 3 -CATEGORY: DATAXFER -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E1NF -REAL_OPCODE: Y -ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM -PATTERN: EVV 0xE7 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() -OPERANDS: MEM0:w:dq:u32 REG0=XMM_R3():r:dq:u32 -IFORM: VMOVNTDQ_MEMu32_XMMu32_AVX512 -} - - -# EMITTING VMOVNTDQ (VMOVNTDQ-256-1) -{ -ICLASS: VMOVNTDQ -CPL: 3 -CATEGORY: DATAXFER -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E1NF -REAL_OPCODE: Y -ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM -PATTERN: EVV 0xE7 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() -OPERANDS: MEM0:w:qq:u32 REG0=YMM_R3():r:qq:u32 -IFORM: VMOVNTDQ_MEMu32_YMMu32_AVX512 +PATTERN: EVV 0xE3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPAVGW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 } -# EMITTING VMOVNTDQA (VMOVNTDQA-128-1) +# EMITTING VPAVGW (VPAVGW-256-1) { -ICLASS: VMOVNTDQA +ICLASS: VPAVGW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E1NF +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM -PATTERN: EVV 0x2A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:u32 MEM0:r:dq:u32 -IFORM: VMOVNTDQA_XMMu32_MEMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPAVGW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 } - -# EMITTING VMOVNTDQA (VMOVNTDQA-256-1) { -ICLASS: VMOVNTDQA +ICLASS: VPAVGW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E1NF +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM -PATTERN: EVV 0x2A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:u32 MEM0:r:qq:u32 -IFORM: VMOVNTDQA_YMMu32_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPAVGW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 } -# EMITTING VMOVNTPD (VMOVNTPD-128-1) +# EMITTING VPAVGW (VPAVGW-512-1) { -ICLASS: VMOVNTPD +ICLASS: VPAVGW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E1NF +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM -PATTERN: EVV 0x2B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_FULLMEM() -OPERANDS: MEM0:w:dq:f64 REG0=XMM_R3():r:dq:f64 -IFORM: VMOVNTPD_MEMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 } - -# EMITTING VMOVNTPD (VMOVNTPD-256-1) { -ICLASS: VMOVNTPD +ICLASS: VPAVGW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E1NF +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM -PATTERN: EVV 0x2B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_FULLMEM() -OPERANDS: MEM0:w:qq:f64 REG0=YMM_R3():r:qq:f64 -IFORM: VMOVNTPD_MEMf64_YMMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPAVGW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 } -# EMITTING VMOVNTPS (VMOVNTPS-128-1) +# EMITTING VPBLENDMB (VPBLENDMB-128-1) { -ICLASS: VMOVNTPS +ICLASS: VPBLENDMB CPL: 3 -CATEGORY: DATAXFER +CATEGORY: BLEND EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E1NF +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM -PATTERN: EVV 0x2B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() -OPERANDS: MEM0:w:dq:f32 REG0=XMM_R3():r:dq:f32 -IFORM: VMOVNTPS_MEMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPBLENDMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 } - -# EMITTING VMOVNTPS (VMOVNTPS-256-1) { -ICLASS: VMOVNTPS +ICLASS: VPBLENDMB CPL: 3 -CATEGORY: DATAXFER +CATEGORY: BLEND EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E1NF +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM -PATTERN: EVV 0x2B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() -OPERANDS: MEM0:w:qq:f32 REG0=YMM_R3():r:qq:f32 -IFORM: VMOVNTPS_MEMf32_YMMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM MASK_AS_CONTROL +PATTERN: EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPBLENDMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 } -# EMITTING VMOVSHDUP (VMOVSHDUP-128-1) +# EMITTING VPBLENDMB (VPBLENDMB-256-1) { -ICLASS: VMOVSHDUP +ICLASS: VPBLENDMB CPL: 3 -CATEGORY: DATAXFER +CATEGORY: BLEND EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x16 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 -IFORM: VMOVSHDUP_XMMf32_MASKmskw_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPBLENDMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 } { -ICLASS: VMOVSHDUP +ICLASS: VPBLENDMB CPL: 3 -CATEGORY: DATAXFER +CATEGORY: BLEND EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x16 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32 -IFORM: VMOVSHDUP_XMMf32_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM MASK_AS_CONTROL +PATTERN: EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPBLENDMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 } -# EMITTING VMOVSHDUP (VMOVSHDUP-256-1) +# EMITTING VPBLENDMB (VPBLENDMB-512-1) { -ICLASS: VMOVSHDUP +ICLASS: VPBLENDMB CPL: 3 -CATEGORY: DATAXFER +CATEGORY: BLEND EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x16 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 -IFORM: VMOVSHDUP_YMMf32_MASKmskw_YMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 } { -ICLASS: VMOVSHDUP +ICLASS: VPBLENDMB CPL: 3 -CATEGORY: DATAXFER +CATEGORY: BLEND EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x16 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32 -IFORM: VMOVSHDUP_YMMf32_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM MASK_AS_CONTROL +PATTERN: EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 } -# EMITTING VMOVSLDUP (VMOVSLDUP-128-1) +# EMITTING VPBLENDMD (VPBLENDMD-128-1) { -ICLASS: VMOVSLDUP +ICLASS: VPBLENDMD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: BLEND EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x12 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 -IFORM: VMOVSLDUP_XMMf32_MASKmskw_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPBLENDMD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 } { -ICLASS: VMOVSLDUP +ICLASS: VPBLENDMD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: BLEND EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x12 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32 -IFORM: VMOVSLDUP_XMMf32_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL +PATTERN: EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPBLENDMD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 } -# EMITTING VMOVSLDUP (VMOVSLDUP-256-1) +# EMITTING VPBLENDMD (VPBLENDMD-256-1) { -ICLASS: VMOVSLDUP +ICLASS: VPBLENDMD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: BLEND EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x12 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 -IFORM: VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPBLENDMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 } { -ICLASS: VMOVSLDUP +ICLASS: VPBLENDMD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: BLEND EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x12 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32 -IFORM: VMOVSLDUP_YMMf32_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL +PATTERN: EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPBLENDMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 } -# EMITTING VMOVUPD (VMOVUPD-128-1) +# EMITTING VPBLENDMQ (VPBLENDMQ-128-1) { -ICLASS: VMOVUPD +ICLASS: VPBLENDMQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: BLEND EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x10 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 -IFORM: VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPBLENDMQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 } { -ICLASS: VMOVUPD +ICLASS: VPBLENDMQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: BLEND EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x10 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f64 -IFORM: VMOVUPD_XMMf64_MASKmskw_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL +PATTERN: EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPBLENDMQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 } -# EMITTING VMOVUPD (VMOVUPD-128-2) +# EMITTING VPBLENDMQ (VPBLENDMQ-256-1) { -ICLASS: VMOVUPD +ICLASS: VPBLENDMQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: BLEND EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x11 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f64 -IFORM: VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPBLENDMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 } - -# EMITTING VMOVUPD (VMOVUPD-128-3) { -ICLASS: VMOVUPD +ICLASS: VPBLENDMQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: BLEND EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x11 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() -OPERANDS: MEM0:w:dq:f64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f64 -IFORM: VMOVUPD_MEMf64_MASKmskw_XMMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL +PATTERN: EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPBLENDMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 } -# EMITTING VMOVUPD (VMOVUPD-256-1) +# EMITTING VPBLENDMW (VPBLENDMW-128-1) { -ICLASS: VMOVUPD +ICLASS: VPBLENDMW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: BLEND EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 +ISA_SET: AVX512BW_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x10 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 -IFORM: VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPBLENDMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 } { -ICLASS: VMOVUPD +ICLASS: VPBLENDMW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: BLEND EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 +ISA_SET: AVX512BW_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x10 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f64 -IFORM: VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM MASK_AS_CONTROL +PATTERN: EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPBLENDMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 } -# EMITTING VMOVUPD (VMOVUPD-256-2) +# EMITTING VPBLENDMW (VPBLENDMW-256-1) { -ICLASS: VMOVUPD +ICLASS: VPBLENDMW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: BLEND EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 +ISA_SET: AVX512BW_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x11 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR -OPERANDS: REG0=YMM_B3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f64 -IFORM: VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPBLENDMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 } - -# EMITTING VMOVUPD (VMOVUPD-256-3) { -ICLASS: VMOVUPD +ICLASS: VPBLENDMW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: BLEND EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 +ISA_SET: AVX512BW_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x11 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() -OPERANDS: MEM0:w:qq:f64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f64 -IFORM: VMOVUPD_MEMf64_MASKmskw_YMMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM MASK_AS_CONTROL +PATTERN: EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPBLENDMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 } -# EMITTING VMOVUPS (VMOVUPS-128-1) +# EMITTING VPBLENDMW (VPBLENDMW-512-1) { -ICLASS: VMOVUPS +ICLASS: VPBLENDMW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: BLEND EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512BW_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x10 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 -IFORM: VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 } { -ICLASS: VMOVUPS +ICLASS: VPBLENDMW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: BLEND EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512BW_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x10 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32 -IFORM: VMOVUPS_XMMf32_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM MASK_AS_CONTROL +PATTERN: EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 } -# EMITTING VMOVUPS (VMOVUPS-128-2) +# EMITTING VPBROADCASTB (VPBROADCASTB-128-1) { -ICLASS: VMOVUPS +ICLASS: VPBROADCASTB CPL: 3 -CATEGORY: DATAXFER +CATEGORY: BROADCAST EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x11 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f32 -IFORM: VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512 +PATTERN: EVV 0x78 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u8 EMX_BROADCAST_1TO16_8 +IFORM: VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512 } - -# EMITTING VMOVUPS (VMOVUPS-128-3) { -ICLASS: VMOVUPS +ICLASS: VPBROADCASTB CPL: 3 -CATEGORY: DATAXFER +CATEGORY: BROADCAST EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x11 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() -OPERANDS: MEM0:w:dq:f32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f32 -IFORM: VMOVUPS_MEMf32_MASKmskw_XMMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1_BYTE +PATTERN: EVV 0x78 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_8_BITS() NELEM_TUPLE1_BYTE() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:b:u8 EMX_BROADCAST_1TO16_8 +IFORM: VPBROADCASTB_XMMu8_MASKmskw_MEMu8_AVX512 } -# EMITTING VMOVUPS (VMOVUPS-256-1) +# EMITTING VPBROADCASTB (VPBROADCASTB-128-2) { -ICLASS: VMOVUPS +ICLASS: VPBROADCASTB CPL: 3 -CATEGORY: DATAXFER +CATEGORY: BROADCAST EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E7NM REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x10 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 -IFORM: VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512 +PATTERN: EVV 0x7A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u8 EMX_BROADCAST_1TO16_8 +IFORM: VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512 } + +# EMITTING VPBROADCASTB (VPBROADCASTB-256-1) { -ICLASS: VMOVUPS +ICLASS: VPBROADCASTB CPL: 3 -CATEGORY: DATAXFER +CATEGORY: BROADCAST EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x10 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32 -IFORM: VMOVUPS_YMMf32_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x78 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u8 EMX_BROADCAST_1TO32_8 +IFORM: VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512 } - -# EMITTING VMOVUPS (VMOVUPS-256-2) { -ICLASS: VMOVUPS +ICLASS: VPBROADCASTB CPL: 3 -CATEGORY: DATAXFER +CATEGORY: BROADCAST EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x11 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=YMM_B3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f32 -IFORM: VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1_BYTE +PATTERN: EVV 0x78 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_8_BITS() NELEM_TUPLE1_BYTE() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:b:u8 EMX_BROADCAST_1TO32_8 +IFORM: VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512 } -# EMITTING VMOVUPS (VMOVUPS-256-3) +# EMITTING VPBROADCASTB (VPBROADCASTB-256-2) { -ICLASS: VMOVUPS +ICLASS: VPBROADCASTB CPL: 3 -CATEGORY: DATAXFER +CATEGORY: BROADCAST EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E7NM REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x11 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() -OPERANDS: MEM0:w:qq:f32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f32 -IFORM: VMOVUPS_MEMf32_MASKmskw_YMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u8 EMX_BROADCAST_1TO32_8 +IFORM: VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512 } -# EMITTING VMULPD (VMULPD-128-1) +# EMITTING VPBROADCASTB (VPBROADCASTB-512-1) { -ICLASS: VMULPD +ICLASS: VPBROADCASTB CPL: 3 -CATEGORY: AVX512 +CATEGORY: BROADCAST EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x59 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x78 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u8 EMX_BROADCAST_1TO64_8 +IFORM: VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512 } { -ICLASS: VMULPD +ICLASS: VPBROADCASTB CPL: 3 -CATEGORY: AVX512 +CATEGORY: BROADCAST EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x59 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VMULPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1_BYTE +PATTERN: EVV 0x78 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_8_BITS() NELEM_TUPLE1_BYTE() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:b:u8 EMX_BROADCAST_1TO64_8 +IFORM: VPBROADCASTB_ZMMu8_MASKmskw_MEMu8_AVX512 } -# EMITTING VMULPD (VMULPD-256-1) +# EMITTING VPBROADCASTB (VPBROADCASTB-512-2) { -ICLASS: VMULPD +ICLASS: VPBROADCASTB CPL: 3 -CATEGORY: AVX512 +CATEGORY: BROADCAST EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E7NM REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x59 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 -IFORM: VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u8 EMX_BROADCAST_1TO64_8 +IFORM: VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512 } + +# EMITTING VPBROADCASTD (VPBROADCASTD-128-1) { -ICLASS: VMULPD +ICLASS: VPBROADCASTD CPL: 3 -CATEGORY: AVX512 +CATEGORY: BROADCAST EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x59 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VMULPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 +PATTERN: EVV 0x58 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:u32 EMX_BROADCAST_1TO4_32 +IFORM: VPBROADCASTD_XMMu32_MASKmskw_MEMu32_AVX512 } -# EMITTING VMULPS (VMULPS-128-1) +# EMITTING VPBROADCASTD (VPBROADCASTD-128-2) { -ICLASS: VMULPS +ICLASS: VPBROADCASTD CPL: 3 -CATEGORY: AVX512 +CATEGORY: BROADCAST EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x59 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x58 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_1TO4_32 +IFORM: VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512 } + +# EMITTING VPBROADCASTD (VPBROADCASTD-128-3) { -ICLASS: VMULPS +ICLASS: VPBROADCASTD CPL: 3 -CATEGORY: AVX512 +CATEGORY: BROADCAST EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E7NM REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x59 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VMULPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO4_32 +IFORM: VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512 +PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 mode64 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO4_32 +IFORM: VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512 } -# EMITTING VMULPS (VMULPS-256-1) +# EMITTING VPBROADCASTD (VPBROADCASTD-256-1) { -ICLASS: VMULPS +ICLASS: VPBROADCASTD CPL: 3 -CATEGORY: AVX512 +CATEGORY: BROADCAST EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x59 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 -IFORM: VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 +PATTERN: EVV 0x58 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:u32 EMX_BROADCAST_1TO8_32 +IFORM: VPBROADCASTD_YMMu32_MASKmskw_MEMu32_AVX512 } + +# EMITTING VPBROADCASTD (VPBROADCASTD-256-2) { -ICLASS: VMULPS +ICLASS: VPBROADCASTD CPL: 3 -CATEGORY: AVX512 +CATEGORY: BROADCAST EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x59 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VMULPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x58 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_1TO8_32 +IFORM: VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512 } -# EMITTING VORPD (VORPD-128-1) +# EMITTING VPBROADCASTD (VPBROADCASTD-256-3) { -ICLASS: VORPD +ICLASS: VPBROADCASTD CPL: 3 -CATEGORY: LOGICAL_FP +CATEGORY: BROADCAST EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E7NM REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x56 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VORPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 not64 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO8_32 +IFORM: VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512 +PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 mode64 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO8_32 +IFORM: VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512 } + +# EMITTING VPBROADCASTMB2Q (VPBROADCASTMB2Q-128-1) { -ICLASS: VORPD +ICLASS: VPBROADCASTMB2Q CPL: 3 -CATEGORY: LOGICAL_FP +CATEGORY: BROADCAST EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512CD_128 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x56 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VORPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +PATTERN: EVV 0x2A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK_B():r:mskw:u64 EMX_BROADCAST_1TO2_8 +IFORM: VPBROADCASTMB2Q_XMMu64_MASKu64_AVX512 } -# EMITTING VORPD (VORPD-256-1) +# EMITTING VPBROADCASTMB2Q (VPBROADCASTMB2Q-256-1) { -ICLASS: VORPD +ICLASS: VPBROADCASTMB2Q CPL: 3 -CATEGORY: LOGICAL_FP +CATEGORY: BROADCAST EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512CD_256 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x56 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 -IFORM: VORPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +PATTERN: EVV 0x2A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK_B():r:mskw:u64 EMX_BROADCAST_1TO4_8 +IFORM: VPBROADCASTMB2Q_YMMu64_MASKu64_AVX512 } + +# EMITTING VPBROADCASTMW2D (VPBROADCASTMW2D-128-1) { -ICLASS: VORPD +ICLASS: VPBROADCASTMW2D CPL: 3 -CATEGORY: LOGICAL_FP +CATEGORY: BROADCAST EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512CD_128 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x56 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VORPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +PATTERN: EVV 0x3A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK_B():r:mskw:u32 EMX_BROADCAST_1TO4_16 +IFORM: VPBROADCASTMW2D_XMMu32_MASKu32_AVX512 } -# EMITTING VORPD (VORPD-512-1) +# EMITTING VPBROADCASTMW2D (VPBROADCASTMW2D-256-1) { -ICLASS: VORPD +ICLASS: VPBROADCASTMW2D CPL: 3 -CATEGORY: LOGICAL_FP +CATEGORY: BROADCAST EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512CD_256 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x56 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VORPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +PATTERN: EVV 0x3A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK_B():r:mskw:u32 EMX_BROADCAST_1TO8_16 +IFORM: VPBROADCASTMW2D_YMMu32_MASKu32_AVX512 } + +# EMITTING VPBROADCASTQ (VPBROADCASTQ-128-1) { -ICLASS: VORPD +ICLASS: VPBROADCASTQ CPL: 3 -CATEGORY: LOGICAL_FP +CATEGORY: BROADCAST EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x56 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VORPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 +PATTERN: EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE1() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u64 EMX_BROADCAST_1TO2_64 +IFORM: VPBROADCASTQ_XMMu64_MASKmskw_MEMu64_AVX512 } -# EMITTING VORPS (VORPS-128-1) +# EMITTING VPBROADCASTQ (VPBROADCASTQ-128-2) { -ICLASS: VORPS +ICLASS: VPBROADCASTQ CPL: 3 -CATEGORY: LOGICAL_FP +CATEGORY: BROADCAST EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x56 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VORPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +PATTERN: EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 EMX_BROADCAST_1TO2_64 +IFORM: VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512 } + +# EMITTING VPBROADCASTQ (VPBROADCASTQ-128-3) { -ICLASS: VORPS +ICLASS: VPBROADCASTQ CPL: 3 -CATEGORY: LOGICAL_FP +CATEGORY: BROADCAST EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E7NM REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x56 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VORPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 mode64 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR64_B():r:q:u64 EMX_BROADCAST_1TO2_64 +IFORM: VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512 } -# EMITTING VORPS (VORPS-256-1) +# EMITTING VPBROADCASTQ (VPBROADCASTQ-256-1) { -ICLASS: VORPS +ICLASS: VPBROADCASTQ CPL: 3 -CATEGORY: LOGICAL_FP +CATEGORY: BROADCAST EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x56 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 -IFORM: VORPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 +PATTERN: EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE1() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u64 EMX_BROADCAST_1TO4_64 +IFORM: VPBROADCASTQ_YMMu64_MASKmskw_MEMu64_AVX512 } + +# EMITTING VPBROADCASTQ (VPBROADCASTQ-256-2) { -ICLASS: VORPS +ICLASS: VPBROADCASTQ CPL: 3 -CATEGORY: LOGICAL_FP +CATEGORY: BROADCAST EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x56 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VORPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 EMX_BROADCAST_1TO4_64 +IFORM: VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512 } -# EMITTING VORPS (VORPS-512-1) +# EMITTING VPBROADCASTQ (VPBROADCASTQ-256-3) { -ICLASS: VORPS +ICLASS: VPBROADCASTQ CPL: 3 -CATEGORY: LOGICAL_FP +CATEGORY: BROADCAST EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E7NM REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x56 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VORPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 mode64 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR64_B():r:q:u64 EMX_BROADCAST_1TO4_64 +IFORM: VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512 } + +# EMITTING VPBROADCASTW (VPBROADCASTW-128-1) { -ICLASS: VORPS +ICLASS: VPBROADCASTW CPL: 3 -CATEGORY: LOGICAL_FP +CATEGORY: BROADCAST EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x56 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VORPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x79 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 EMX_BROADCAST_1TO8_16 +IFORM: VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512 } - -# EMITTING VPABSB (VPABSB-128-1) { -ICLASS: VPABSB +ICLASS: VPBROADCASTW CPL: 3 -CATEGORY: AVX512 +CATEGORY: BROADCAST EXTENSION: AVX512EVEX ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x1C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 -IFORM: VPABSB_XMMi8_MASKmskw_XMMi8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1_WORD +PATTERN: EVV 0x79 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_TUPLE1_WORD() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:wrd:u16 EMX_BROADCAST_1TO8_16 +IFORM: VPBROADCASTW_XMMu16_MASKmskw_MEMu16_AVX512 } + +# EMITTING VPBROADCASTW (VPBROADCASTW-128-2) { -ICLASS: VPABSB +ICLASS: VPBROADCASTW CPL: 3 -CATEGORY: AVX512 +CATEGORY: BROADCAST EXTENSION: AVX512EVEX ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E7NM REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x1C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i8 -IFORM: VPABSB_XMMi8_MASKmskw_MEMi8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u16 EMX_BROADCAST_1TO8_16 +IFORM: VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512 } -# EMITTING VPABSB (VPABSB-256-1) +# EMITTING VPBROADCASTW (VPBROADCASTW-256-1) { -ICLASS: VPABSB +ICLASS: VPBROADCASTW CPL: 3 -CATEGORY: AVX512 +CATEGORY: BROADCAST EXTENSION: AVX512EVEX ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x1C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i8 -IFORM: VPABSB_YMMi8_MASKmskw_YMMi8_AVX512 +PATTERN: EVV 0x79 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 EMX_BROADCAST_1TO16_16 +IFORM: VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512 } { -ICLASS: VPABSB +ICLASS: VPBROADCASTW CPL: 3 -CATEGORY: AVX512 +CATEGORY: BROADCAST EXTENSION: AVX512EVEX ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x1C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i8 -IFORM: VPABSB_YMMi8_MASKmskw_MEMi8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1_WORD +PATTERN: EVV 0x79 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_TUPLE1_WORD() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:wrd:u16 EMX_BROADCAST_1TO16_16 +IFORM: VPBROADCASTW_YMMu16_MASKmskw_MEMu16_AVX512 } -# EMITTING VPABSB (VPABSB-512-1) +# EMITTING VPBROADCASTW (VPBROADCASTW-256-2) { -ICLASS: VPABSB +ICLASS: VPBROADCASTW CPL: 3 -CATEGORY: AVX512 +CATEGORY: BROADCAST EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E7NM REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x1C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi8 -IFORM: VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512 +PATTERN: EVV 0x7B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u16 EMX_BROADCAST_1TO16_16 +IFORM: VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512 } + +# EMITTING VPBROADCASTW (VPBROADCASTW-512-1) { -ICLASS: VPABSB +ICLASS: VPBROADCASTW CPL: 3 -CATEGORY: AVX512 +CATEGORY: BROADCAST EXTENSION: AVX512EVEX ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x1C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:i8 -IFORM: VPABSB_ZMMi8_MASKmskw_MEMi8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x79 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 EMX_BROADCAST_1TO32_16 +IFORM: VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512 } - -# EMITTING VPABSD (VPABSD-128-1) { -ICLASS: VPABSD +ICLASS: VPBROADCASTW CPL: 3 -CATEGORY: AVX512 +CATEGORY: BROADCAST EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x1E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 -IFORM: VPABSD_XMMi32_MASKmskw_XMMi32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1_WORD +PATTERN: EVV 0x79 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_TUPLE1_WORD() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:wrd:u16 EMX_BROADCAST_1TO32_16 +IFORM: VPBROADCASTW_ZMMu16_MASKmskw_MEMu16_AVX512 } + +# EMITTING VPBROADCASTW (VPBROADCASTW-512-2) { -ICLASS: VPABSD +ICLASS: VPBROADCASTW CPL: 3 -CATEGORY: AVX512 +CATEGORY: BROADCAST EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E7NM REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x1E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR -IFORM: VPABSD_XMMi32_MASKmskw_MEMi32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u16 EMX_BROADCAST_1TO32_16 +IFORM: VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512 } -# EMITTING VPABSD (VPABSD-256-1) +# EMITTING VPCMPB (VPCMPB-128-1) { -ICLASS: VPABSD +ICLASS: VPCMPB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 +ISA_SET: AVX512BW_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x1E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32 -IFORM: VPABSD_YMMi32_MASKmskw_YMMi32_AVX512 +PATTERN: EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i8 REG3=XMM_B3():r:dq:i8 IMM0:r:b +IFORM: VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512 } { -ICLASS: VPABSD +ICLASS: VPCMPB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 +ISA_SET: AVX512BW_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x1E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR -IFORM: VPABSD_YMMi32_MASKmskw_MEMi32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i8 MEM0:r:dq:i8 IMM0:r:b +IFORM: VPCMPB_MASKmskw_MASKmskw_XMMi8_MEMi8_IMM8_AVX512 } -# EMITTING VPABSQ (VPABSQ-128-1) +# EMITTING VPCMPB (VPCMPB-256-1) { -ICLASS: VPABSQ +ICLASS: VPCMPB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512BW_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x1F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i64 -IFORM: VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512 +PATTERN: EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i8 REG3=YMM_B3():r:qq:i8 IMM0:r:b +IFORM: VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512 } { -ICLASS: VPABSQ +ICLASS: VPCMPB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512BW_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x1F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i64:TXT=BCASTSTR -IFORM: VPABSQ_XMMi64_MASKmskw_MEMi64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i8 MEM0:r:qq:i8 IMM0:r:b +IFORM: VPCMPB_MASKmskw_MASKmskw_YMMi8_MEMi8_IMM8_AVX512 } -# EMITTING VPABSQ (VPABSQ-256-1) +# EMITTING VPCMPB (VPCMPB-512-1) { -ICLASS: VPABSQ +ICLASS: VPCMPB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 +ISA_SET: AVX512BW_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x1F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i64 -IFORM: VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512 +PATTERN: EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi8 REG3=ZMM_B3():r:zi8 IMM0:r:b +IFORM: VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512 } { -ICLASS: VPABSQ +ICLASS: VPCMPB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 +ISA_SET: AVX512BW_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x1F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i64:TXT=BCASTSTR -IFORM: VPABSQ_YMMi64_MASKmskw_MEMi64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi8 MEM0:r:zd:i8 IMM0:r:b +IFORM: VPCMPB_MASKmskw_MASKmskw_ZMMi8_MEMi8_IMM8_AVX512 } -# EMITTING VPABSW (VPABSW-128-1) +# EMITTING VPCMPD (VPCMPD-128-1) { -ICLASS: VPABSW +ICLASS: VPCMPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x1D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 -IFORM: VPABSW_XMMi16_MASKmskw_XMMi16_AVX512 +PATTERN: EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i32 REG3=XMM_B3():r:dq:i32 IMM0:r:b +IFORM: VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512 } { -ICLASS: VPABSW +ICLASS: VPCMPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x1D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i16 -IFORM: VPABSW_XMMi16_MASKmskw_MEMi16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i32 MEM0:r:vv:i32:TXT=BCASTSTR IMM0:r:b +IFORM: VPCMPD_MASKmskw_MASKmskw_XMMi32_MEMi32_IMM8_AVX512 } -# EMITTING VPABSW (VPABSW-256-1) +# EMITTING VPCMPD (VPCMPD-256-1) { -ICLASS: VPABSW +ICLASS: VPCMPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x1D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i16 -IFORM: VPABSW_YMMi16_MASKmskw_YMMi16_AVX512 +PATTERN: EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i32 REG3=YMM_B3():r:qq:i32 IMM0:r:b +IFORM: VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512 } { -ICLASS: VPABSW +ICLASS: VPCMPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x1D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i16 -IFORM: VPABSW_YMMi16_MASKmskw_MEMi16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i32 MEM0:r:vv:i32:TXT=BCASTSTR IMM0:r:b +IFORM: VPCMPD_MASKmskw_MASKmskw_YMMi32_MEMi32_IMM8_AVX512 } -# EMITTING VPABSW (VPABSW-512-1) +# EMITTING VPCMPEQB (VPCMPEQB-128-1) { -ICLASS: VPABSW +ICLASS: VPCMPEQB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 +ISA_SET: AVX512BW_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x1D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi16 -IFORM: VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512 +PATTERN: EVV 0x74 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPCMPEQB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 } { -ICLASS: VPABSW +ICLASS: VPCMPEQB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 +ISA_SET: AVX512BW_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x1D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:i16 -IFORM: VPABSW_ZMMi16_MASKmskw_MEMi16_AVX512 +PATTERN: EVV 0x74 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPCMPEQB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 } -# EMITTING VPACKSSDW (VPACKSSDW-128-1) +# EMITTING VPCMPEQB (VPCMPEQB-256-1) { -ICLASS: VPACKSSDW +ICLASS: VPCMPEQB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x6B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 REG3=XMM_B3():r:dq:i32 -IFORM: VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512 +PATTERN: EVV 0x74 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPCMPEQB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 } { -ICLASS: VPACKSSDW +ICLASS: VPCMPEQB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x6B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 MEM0:r:vv:i32:TXT=BCASTSTR -IFORM: VPACKSSDW_XMMi16_MASKmskw_XMMi32_MEMi32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x74 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPCMPEQB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 } -# EMITTING VPACKSSDW (VPACKSSDW-256-1) +# EMITTING VPCMPEQB (VPCMPEQB-512-1) { -ICLASS: VPACKSSDW +ICLASS: VPCMPEQB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x6B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 REG3=YMM_B3():r:qq:i32 -IFORM: VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512 +PATTERN: EVV 0x74 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 } { -ICLASS: VPACKSSDW +ICLASS: VPCMPEQB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x6B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 MEM0:r:vv:i32:TXT=BCASTSTR -IFORM: VPACKSSDW_YMMi16_MASKmskw_YMMi32_MEMi32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x74 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 } -# EMITTING VPACKSSDW (VPACKSSDW-512-1) +# EMITTING VPCMPEQD (VPCMPEQD-128-1) { -ICLASS: VPACKSSDW +ICLASS: VPCMPEQD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x6B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 REG3=ZMM_B3():r:zi32 -IFORM: VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512 +PATTERN: EVV 0x76 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPCMPEQD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512 } { -ICLASS: VPACKSSDW +ICLASS: VPCMPEQD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x6B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 MEM0:r:vv:i32:TXT=BCASTSTR -IFORM: VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_MEMi32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x76 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPCMPEQD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512 } -# EMITTING VPACKSSWB (VPACKSSWB-128-1) +# EMITTING VPCMPEQD (VPCMPEQD-256-1) { -ICLASS: VPACKSSWB +ICLASS: VPCMPEQD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x63 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 -OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 -IFORM: VPACKSSWB_XMMi8_MASKmskw_XMMi16_XMMi16_AVX512 +PATTERN: EVV 0x76 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPCMPEQD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512 } { -ICLASS: VPACKSSWB +ICLASS: VPCMPEQD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x63 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 -IFORM: VPACKSSWB_XMMi8_MASKmskw_XMMi16_MEMi16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x76 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPCMPEQD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512 } -# EMITTING VPACKSSWB (VPACKSSWB-256-1) +# EMITTING VPCMPEQQ (VPCMPEQQ-128-1) { -ICLASS: VPACKSSWB +ICLASS: VPCMPEQQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x63 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 -OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 -IFORM: VPACKSSWB_YMMi8_MASKmskw_YMMi16_YMMi16_AVX512 +PATTERN: EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512 } { -ICLASS: VPACKSSWB +ICLASS: VPCMPEQQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x63 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 -IFORM: VPACKSSWB_YMMi8_MASKmskw_YMMi16_MEMi16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512 } -# EMITTING VPACKSSWB (VPACKSSWB-512-1) +# EMITTING VPCMPEQQ (VPCMPEQQ-256-1) { -ICLASS: VPACKSSWB +ICLASS: VPCMPEQQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x63 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 -OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 -IFORM: VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512 +PATTERN: EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512 } { -ICLASS: VPACKSSWB +ICLASS: VPCMPEQQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x63 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 -IFORM: VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_MEMi16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512 } -# EMITTING VPACKUSDW (VPACKUSDW-128-1) +# EMITTING VPCMPEQW (VPCMPEQW-128-1) { -ICLASS: VPACKUSDW +ICLASS: VPCMPEQW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x2B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 -IFORM: VPACKUSDW_XMMu16_MASKmskw_XMMu32_XMMu32_AVX512 +PATTERN: EVV 0x75 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPCMPEQW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 } { -ICLASS: VPACKUSDW +ICLASS: VPCMPEQW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x2B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPACKUSDW_XMMu16_MASKmskw_XMMu32_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x75 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPCMPEQW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 } -# EMITTING VPACKUSDW (VPACKUSDW-256-1) +# EMITTING VPCMPEQW (VPCMPEQW-256-1) { -ICLASS: VPACKUSDW +ICLASS: VPCMPEQW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x2B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 -IFORM: VPACKUSDW_YMMu16_MASKmskw_YMMu32_YMMu32_AVX512 +PATTERN: EVV 0x75 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPCMPEQW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 } { -ICLASS: VPACKUSDW +ICLASS: VPCMPEQW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x2B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPACKUSDW_YMMu16_MASKmskw_YMMu32_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x75 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPCMPEQW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 } -# EMITTING VPACKUSDW (VPACKUSDW-512-1) +# EMITTING VPCMPEQW (VPCMPEQW-512-1) { -ICLASS: VPACKUSDW +ICLASS: VPCMPEQW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x2B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 -IFORM: VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512 +PATTERN: EVV 0x75 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 } { -ICLASS: VPACKUSDW +ICLASS: VPCMPEQW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x2B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x75 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 } -# EMITTING VPACKUSWB (VPACKUSWB-128-1) +# EMITTING VPCMPGTB (VPCMPGTB-128-1) { -ICLASS: VPACKUSWB +ICLASS: VPCMPGTB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x67 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 -OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 -IFORM: VPACKUSWB_XMMu8_MASKmskw_XMMu16_XMMu16_AVX512 +PATTERN: EVV 0x64 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPCMPGTB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 } { -ICLASS: VPACKUSWB +ICLASS: VPCMPGTB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x67 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 -IFORM: VPACKUSWB_XMMu8_MASKmskw_XMMu16_MEMu16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x64 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPCMPGTB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 } -# EMITTING VPACKUSWB (VPACKUSWB-256-1) +# EMITTING VPCMPGTB (VPCMPGTB-256-1) { -ICLASS: VPACKUSWB +ICLASS: VPCMPGTB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x67 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 -OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 -IFORM: VPACKUSWB_YMMu8_MASKmskw_YMMu16_YMMu16_AVX512 +PATTERN: EVV 0x64 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPCMPGTB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 } { -ICLASS: VPACKUSWB +ICLASS: VPCMPGTB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x67 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 -IFORM: VPACKUSWB_YMMu8_MASKmskw_YMMu16_MEMu16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x64 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPCMPGTB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 } -# EMITTING VPACKUSWB (VPACKUSWB-512-1) +# EMITTING VPCMPGTB (VPCMPGTB-512-1) { -ICLASS: VPACKUSWB +ICLASS: VPCMPGTB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x67 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 -OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 -IFORM: VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512 +PATTERN: EVV 0x64 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 } { -ICLASS: VPACKUSWB +ICLASS: VPCMPGTB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x67 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 -IFORM: VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_MEMu16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x64 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 } -# EMITTING VPADDB (VPADDB-128-1) +# EMITTING VPCMPGTD (VPCMPGTD-128-1) { -ICLASS: VPADDB +ICLASS: VPCMPGTD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xFC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 -OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 -IFORM: VPADDB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +PATTERN: EVV 0x66 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i32 REG3=XMM_B3():r:dq:i32 +IFORM: VPCMPGTD_MASKmskw_MASKmskw_XMMi32_XMMi32_AVX512 } { -ICLASS: VPADDB +ICLASS: VPCMPGTD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xFC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 -IFORM: VPADDB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x66 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i32 MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPCMPGTD_MASKmskw_MASKmskw_XMMi32_MEMi32_AVX512 } -# EMITTING VPADDB (VPADDB-256-1) +# EMITTING VPCMPGTD (VPCMPGTD-256-1) { -ICLASS: VPADDB +ICLASS: VPCMPGTD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xFC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 -OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 -IFORM: VPADDB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +PATTERN: EVV 0x66 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i32 REG3=YMM_B3():r:qq:i32 +IFORM: VPCMPGTD_MASKmskw_MASKmskw_YMMi32_YMMi32_AVX512 } { -ICLASS: VPADDB +ICLASS: VPCMPGTD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xFC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 -IFORM: VPADDB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x66 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i32 MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPCMPGTD_MASKmskw_MASKmskw_YMMi32_MEMi32_AVX512 } -# EMITTING VPADDB (VPADDB-512-1) +# EMITTING VPCMPGTQ (VPCMPGTQ-128-1) { -ICLASS: VPADDB +ICLASS: VPCMPGTQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xFC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 -OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 -IFORM: VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +PATTERN: EVV 0x37 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i64 REG3=XMM_B3():r:dq:i64 +IFORM: VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_XMMi64_AVX512 } { -ICLASS: VPADDB +ICLASS: VPCMPGTQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xFC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 -IFORM: VPADDB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x37 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i64 MEM0:r:vv:i64:TXT=BCASTSTR +IFORM: VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_MEMi64_AVX512 } -# EMITTING VPADDD (VPADDD-128-1) +# EMITTING VPCMPGTQ (VPCMPGTQ-256-1) { -ICLASS: VPADDD +ICLASS: VPCMPGTQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xFE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 -IFORM: VPADDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +PATTERN: EVV 0x37 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i64 REG3=YMM_B3():r:qq:i64 +IFORM: VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_YMMi64_AVX512 } { -ICLASS: VPADDD +ICLASS: VPCMPGTQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xFE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPADDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +PATTERN: EVV 0x37 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i64 MEM0:r:vv:i64:TXT=BCASTSTR +IFORM: VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_MEMi64_AVX512 } -# EMITTING VPADDD (VPADDD-256-1) +# EMITTING VPCMPGTW (VPCMPGTW-128-1) { -ICLASS: VPADDD +ICLASS: VPCMPGTW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 +ISA_SET: AVX512BW_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xFE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 -IFORM: VPADDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +PATTERN: EVV 0x65 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPCMPGTW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 } { -ICLASS: VPADDD +ICLASS: VPCMPGTW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 +ISA_SET: AVX512BW_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xFE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPADDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x65 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPCMPGTW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 } -# EMITTING VPADDQ (VPADDQ-128-1) +# EMITTING VPCMPGTW (VPCMPGTW-256-1) { -ICLASS: VPADDQ +ICLASS: VPCMPGTW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512BW_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xD4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 -IFORM: VPADDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +PATTERN: EVV 0x65 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPCMPGTW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 } { -ICLASS: VPADDQ +ICLASS: VPCMPGTW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512BW_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xD4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPADDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x65 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPCMPGTW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 } -# EMITTING VPADDQ (VPADDQ-256-1) +# EMITTING VPCMPGTW (VPCMPGTW-512-1) { -ICLASS: VPADDQ +ICLASS: VPCMPGTW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 +ISA_SET: AVX512BW_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xD4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 -IFORM: VPADDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +PATTERN: EVV 0x65 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 } { -ICLASS: VPADDQ +ICLASS: VPCMPGTW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 +ISA_SET: AVX512BW_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xD4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPADDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x65 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 } -# EMITTING VPADDSB (VPADDSB-128-1) +# EMITTING VPCMPQ (VPCMPQ-128-1) { -ICLASS: VPADDSB +ICLASS: VPCMPQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xEC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 -OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 REG3=XMM_B3():r:dq:i8 -IFORM: VPADDSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 +PATTERN: EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i64 REG3=XMM_B3():r:dq:i64 IMM0:r:b +IFORM: VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512 } { -ICLASS: VPADDSB +ICLASS: VPCMPQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xEC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 MEM0:r:dq:i8 -IFORM: VPADDSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i64 MEM0:r:vv:i64:TXT=BCASTSTR IMM0:r:b +IFORM: VPCMPQ_MASKmskw_MASKmskw_XMMi64_MEMi64_IMM8_AVX512 } -# EMITTING VPADDSB (VPADDSB-256-1) +# EMITTING VPCMPQ (VPCMPQ-256-1) { -ICLASS: VPADDSB +ICLASS: VPCMPQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xEC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 -OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 REG3=YMM_B3():r:qq:i8 -IFORM: VPADDSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 +PATTERN: EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i64 REG3=YMM_B3():r:qq:i64 IMM0:r:b +IFORM: VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512 } { -ICLASS: VPADDSB +ICLASS: VPCMPQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xEC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 MEM0:r:qq:i8 -IFORM: VPADDSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i64 MEM0:r:vv:i64:TXT=BCASTSTR IMM0:r:b +IFORM: VPCMPQ_MASKmskw_MASKmskw_YMMi64_MEMi64_IMM8_AVX512 } -# EMITTING VPADDSB (VPADDSB-512-1) +# EMITTING VPCMPUB (VPCMPUB-128-1) { -ICLASS: VPADDSB +ICLASS: VPCMPUB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 +ISA_SET: AVX512BW_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xEC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 -OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 REG3=ZMM_B3():r:zi8 -IFORM: VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 +PATTERN: EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 IMM0:r:b +IFORM: VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 } { -ICLASS: VPADDSB +ICLASS: VPCMPUB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 +ISA_SET: AVX512BW_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xEC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 MEM0:r:zd:i8 -IFORM: VPADDSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 +PATTERN: EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 IMM0:r:b +IFORM: VPCMPUB_MASKmskw_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 } -# EMITTING VPADDSW (VPADDSW-128-1) +# EMITTING VPCMPUB (VPCMPUB-256-1) { -ICLASS: VPADDSW +ICLASS: VPCMPUB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 +ISA_SET: AVX512BW_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xED V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 -OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 -IFORM: VPADDSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 +PATTERN: EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 IMM0:r:b +IFORM: VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 } { -ICLASS: VPADDSW +ICLASS: VPCMPUB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 +ISA_SET: AVX512BW_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xED V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 -IFORM: VPADDSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 +PATTERN: EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 IMM0:r:b +IFORM: VPCMPUB_MASKmskw_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 } -# EMITTING VPADDSW (VPADDSW-256-1) +# EMITTING VPCMPUB (VPCMPUB-512-1) { -ICLASS: VPADDSW +ICLASS: VPCMPUB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 +ISA_SET: AVX512BW_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xED V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 -OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 -IFORM: VPADDSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 +PATTERN: EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 IMM0:r:b +IFORM: VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 } { -ICLASS: VPADDSW +ICLASS: VPCMPUB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 +ISA_SET: AVX512BW_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xED V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 -IFORM: VPADDSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 +PATTERN: EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 IMM0:r:b +IFORM: VPCMPUB_MASKmskw_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 } -# EMITTING VPADDSW (VPADDSW-512-1) +# EMITTING VPCMPUD (VPCMPUD-128-1) { -ICLASS: VPADDSW +ICLASS: VPCMPUD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xED V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 -OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 -IFORM: VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 +PATTERN: EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 IMM0:r:b +IFORM: VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 } { -ICLASS: VPADDSW +ICLASS: VPCMPUD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xED V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 -IFORM: VPADDSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPCMPUD_MASKmskw_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 } -# EMITTING VPADDUSB (VPADDUSB-128-1) +# EMITTING VPCMPUD (VPCMPUD-256-1) { -ICLASS: VPADDUSB +ICLASS: VPCMPUD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xDC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 -OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 -IFORM: VPADDUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +PATTERN: EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 IMM0:r:b +IFORM: VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 } { -ICLASS: VPADDUSB +ICLASS: VPCMPUD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xDC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 -IFORM: VPADDUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPCMPUD_MASKmskw_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 } -# EMITTING VPADDUSB (VPADDUSB-256-1) +# EMITTING VPCMPUQ (VPCMPUQ-128-1) { -ICLASS: VPADDUSB +ICLASS: VPCMPUQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xDC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 -OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 -IFORM: VPADDUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +PATTERN: EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 IMM0:r:b +IFORM: VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 } { -ICLASS: VPADDUSB +ICLASS: VPCMPUQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xDC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 -IFORM: VPADDUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPCMPUQ_MASKmskw_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 } -# EMITTING VPADDUSB (VPADDUSB-512-1) +# EMITTING VPCMPUQ (VPCMPUQ-256-1) { -ICLASS: VPADDUSB +ICLASS: VPCMPUQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xDC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 -OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 -IFORM: VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +PATTERN: EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 } { -ICLASS: VPADDUSB +ICLASS: VPCMPUQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xDC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 -IFORM: VPADDUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPCMPUQ_MASKmskw_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 } -# EMITTING VPADDUSW (VPADDUSW-128-1) +# EMITTING VPCMPUW (VPCMPUW-128-1) { -ICLASS: VPADDUSW +ICLASS: VPCMPUW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -52615,13 +57106,13 @@ ISA_SET: AVX512BW_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xDD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 -OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 -IFORM: VPADDUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +PATTERN: EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 IMM0:r:b +IFORM: VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512 } { -ICLASS: VPADDUSW +ICLASS: VPCMPUW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -52629,15 +57120,15 @@ ISA_SET: AVX512BW_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xDD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 -IFORM: VPADDUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +PATTERN: EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 IMM0:r:b +IFORM: VPCMPUW_MASKmskw_MASKmskw_XMMu16_MEMu16_IMM8_AVX512 } -# EMITTING VPADDUSW (VPADDUSW-256-1) +# EMITTING VPCMPUW (VPCMPUW-256-1) { -ICLASS: VPADDUSW +ICLASS: VPCMPUW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -52645,13 +57136,13 @@ ISA_SET: AVX512BW_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xDD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 -OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 -IFORM: VPADDUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +PATTERN: EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 IMM0:r:b +IFORM: VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512 } { -ICLASS: VPADDUSW +ICLASS: VPCMPUW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -52659,15 +57150,15 @@ ISA_SET: AVX512BW_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xDD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 -IFORM: VPADDUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +PATTERN: EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 IMM0:r:b +IFORM: VPCMPUW_MASKmskw_MASKmskw_YMMu16_MEMu16_IMM8_AVX512 } -# EMITTING VPADDUSW (VPADDUSW-512-1) +# EMITTING VPCMPUW (VPCMPUW-512-1) { -ICLASS: VPADDUSW +ICLASS: VPCMPUW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -52675,13 +57166,13 @@ ISA_SET: AVX512BW_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xDD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 -OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 -IFORM: VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +PATTERN: EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 IMM0:r:b +IFORM: VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512 } { -ICLASS: VPADDUSW +ICLASS: VPCMPUW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -52689,15 +57180,15 @@ ISA_SET: AVX512BW_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xDD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 -IFORM: VPADDUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +PATTERN: EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 IMM0:r:b +IFORM: VPCMPUW_MASKmskw_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512 } -# EMITTING VPADDW (VPADDW-128-1) +# EMITTING VPCMPW (VPCMPW-128-1) { -ICLASS: VPADDW +ICLASS: VPCMPW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -52705,13 +57196,13 @@ ISA_SET: AVX512BW_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xFD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 -OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 -IFORM: VPADDW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +PATTERN: EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 IMM0:r:b +IFORM: VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512 } { -ICLASS: VPADDW +ICLASS: VPCMPW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -52719,15 +57210,15 @@ ISA_SET: AVX512BW_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xFD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 -IFORM: VPADDW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +PATTERN: EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 IMM0:r:b +IFORM: VPCMPW_MASKmskw_MASKmskw_XMMi16_MEMi16_IMM8_AVX512 } -# EMITTING VPADDW (VPADDW-256-1) +# EMITTING VPCMPW (VPCMPW-256-1) { -ICLASS: VPADDW +ICLASS: VPCMPW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -52735,13 +57226,13 @@ ISA_SET: AVX512BW_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xFD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 -OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 -IFORM: VPADDW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +PATTERN: EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 IMM0:r:b +IFORM: VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512 } { -ICLASS: VPADDW +ICLASS: VPCMPW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -52749,15 +57240,15 @@ ISA_SET: AVX512BW_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xFD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 -IFORM: VPADDW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +PATTERN: EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 IMM0:r:b +IFORM: VPCMPW_MASKmskw_MASKmskw_YMMi16_MEMi16_IMM8_AVX512 } -# EMITTING VPADDW (VPADDW-512-1) +# EMITTING VPCMPW (VPCMPW-512-1) { -ICLASS: VPADDW +ICLASS: VPCMPW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -52765,13 +57256,13 @@ ISA_SET: AVX512BW_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xFD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 -OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 -IFORM: VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +PATTERN: EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 IMM0:r:b +IFORM: VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512 } { -ICLASS: VPADDW +ICLASS: VPCMPW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -52779,2163 +57270,2254 @@ ISA_SET: AVX512BW_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xFD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 -IFORM: VPADDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +PATTERN: EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 IMM0:r:b +IFORM: VPCMPW_MASKmskw_MASKmskw_ZMMi16_MEMi16_IMM8_AVX512 } -# EMITTING VPALIGNR (VPALIGNR-128-1) -{ -ICLASS: VPALIGNR -CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4NF -REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x0F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 UIMM8() -OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 IMM0:r:b -IFORM: VPALIGNR_XMMu8_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 -} - +# EMITTING VPCOMPRESSD (VPCOMPRESSD-128-1) { -ICLASS: VPALIGNR +ICLASS: VPCOMPRESSD CPL: 3 -CATEGORY: AVX512 +CATEGORY: COMPRESS EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x0F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 UIMM8() ESIZE_64_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 IMM0:r:b -IFORM: VPALIGNR_XMMu8_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32 +IFORM: VPCOMPRESSD_MEMu32_MASKmskw_XMMu32_AVX512 } -# EMITTING VPALIGNR (VPALIGNR-256-1) +# EMITTING VPCOMPRESSD (VPCOMPRESSD-128-2) { -ICLASS: VPALIGNR +ICLASS: VPCOMPRESSD CPL: 3 -CATEGORY: AVX512 +CATEGORY: COMPRESS EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x0F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 UIMM8() -OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 IMM0:r:b -IFORM: VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 +PATTERN: EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32 +IFORM: VPCOMPRESSD_XMMu32_MASKmskw_XMMu32_AVX512 } + +# EMITTING VPCOMPRESSD (VPCOMPRESSD-256-1) { -ICLASS: VPALIGNR +ICLASS: VPCOMPRESSD CPL: 3 -CATEGORY: AVX512 +CATEGORY: COMPRESS EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x0F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 UIMM8() ESIZE_64_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 IMM0:r:b -IFORM: VPALIGNR_YMMu8_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 +IFORM: VPCOMPRESSD_MEMu32_MASKmskw_YMMu32_AVX512 } -# EMITTING VPALIGNR (VPALIGNR-512-1) +# EMITTING VPCOMPRESSD (VPCOMPRESSD-256-2) { -ICLASS: VPALIGNR +ICLASS: VPCOMPRESSD CPL: 3 -CATEGORY: AVX512 +CATEGORY: COMPRESS EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x0F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 UIMM8() -OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 IMM0:r:b -IFORM: VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 +PATTERN: EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 +IFORM: VPCOMPRESSD_YMMu32_MASKmskw_YMMu32_AVX512 } + +# EMITTING VPCOMPRESSQ (VPCOMPRESSQ-128-1) { -ICLASS: VPALIGNR +ICLASS: VPCOMPRESSQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: COMPRESS EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x0F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 UIMM8() ESIZE_64_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 IMM0:r:b -IFORM: VPALIGNR_ZMMu8_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:dq:u64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 +IFORM: VPCOMPRESSQ_MEMu64_MASKmskw_XMMu64_AVX512 } -# EMITTING VPANDD (VPANDD-128-1) +# EMITTING VPCOMPRESSQ (VPCOMPRESSQ-128-2) { -ICLASS: VPANDD +ICLASS: VPCOMPRESSQ CPL: 3 -CATEGORY: LOGICAL +CATEGORY: COMPRESS EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 -IFORM: VPANDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +PATTERN: EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 +IFORM: VPCOMPRESSQ_XMMu64_MASKmskw_XMMu64_AVX512 } + +# EMITTING VPCOMPRESSQ (VPCOMPRESSQ-256-1) { -ICLASS: VPANDD +ICLASS: VPCOMPRESSQ CPL: 3 -CATEGORY: LOGICAL +CATEGORY: COMPRESS EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPANDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:qq:u64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 +IFORM: VPCOMPRESSQ_MEMu64_MASKmskw_YMMu64_AVX512 } -# EMITTING VPANDD (VPANDD-256-1) +# EMITTING VPCOMPRESSQ (VPCOMPRESSQ-256-2) { -ICLASS: VPANDD +ICLASS: VPCOMPRESSQ CPL: 3 -CATEGORY: LOGICAL +CATEGORY: COMPRESS EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 -IFORM: VPANDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +PATTERN: EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 +IFORM: VPCOMPRESSQ_YMMu64_MASKmskw_YMMu64_AVX512 } + +# EMITTING VPCONFLICTD (VPCONFLICTD-128-1) { -ICLASS: VPANDD +ICLASS: VPCONFLICTD CPL: 3 -CATEGORY: LOGICAL +CATEGORY: CONFLICT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512CD_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPANDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 +IFORM: VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512 +} + +{ +ICLASS: VPCONFLICTD +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPCONFLICTD_XMMu32_MASKmskw_MEMu32_AVX512 } -# EMITTING VPANDND (VPANDND-128-1) +# EMITTING VPCONFLICTD (VPCONFLICTD-256-1) { -ICLASS: VPANDND +ICLASS: VPCONFLICTD CPL: 3 -CATEGORY: LOGICAL +CATEGORY: CONFLICT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512CD_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 -IFORM: VPANDND_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +PATTERN: EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 +IFORM: VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512 } { -ICLASS: VPANDND +ICLASS: VPCONFLICTD CPL: 3 -CATEGORY: LOGICAL +CATEGORY: CONFLICT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512CD_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPANDND_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPCONFLICTD_YMMu32_MASKmskw_MEMu32_AVX512 } -# EMITTING VPANDND (VPANDND-256-1) +# EMITTING VPCONFLICTQ (VPCONFLICTQ-128-1) { -ICLASS: VPANDND +ICLASS: VPCONFLICTQ CPL: 3 -CATEGORY: LOGICAL +CATEGORY: CONFLICT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512CD_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 -IFORM: VPANDND_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +PATTERN: EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 +IFORM: VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512 } { -ICLASS: VPANDND +ICLASS: VPCONFLICTQ CPL: 3 -CATEGORY: LOGICAL +CATEGORY: CONFLICT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512CD_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPANDND_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPCONFLICTQ_XMMu64_MASKmskw_MEMu64_AVX512 } -# EMITTING VPANDNQ (VPANDNQ-128-1) +# EMITTING VPCONFLICTQ (VPCONFLICTQ-256-1) { -ICLASS: VPANDNQ +ICLASS: VPCONFLICTQ CPL: 3 -CATEGORY: LOGICAL +CATEGORY: CONFLICT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512CD_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 -IFORM: VPANDNQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +PATTERN: EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 +IFORM: VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512 } { -ICLASS: VPANDNQ +ICLASS: VPCONFLICTQ CPL: 3 -CATEGORY: LOGICAL +CATEGORY: CONFLICT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512CD_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPANDNQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPCONFLICTQ_YMMu64_MASKmskw_MEMu64_AVX512 } -# EMITTING VPANDNQ (VPANDNQ-256-1) +# EMITTING VPERMD (VPERMD-256-1) { -ICLASS: VPANDNQ +ICLASS: VPERMD CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 -IFORM: VPANDNQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +PATTERN: EVV 0x36 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 } { -ICLASS: VPANDNQ +ICLASS: VPERMD CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPANDNQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x36 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPERMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 } -# EMITTING VPANDQ (VPANDQ-128-1) +# EMITTING VPERMI2D (VPERMI2D-128-1) { -ICLASS: VPANDQ +ICLASS: VPERMI2D CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 -IFORM: VPANDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +PATTERN: EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 } { -ICLASS: VPANDQ +ICLASS: VPERMI2D CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPANDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPERMI2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 } -# EMITTING VPANDQ (VPANDQ-256-1) +# EMITTING VPERMI2D (VPERMI2D-256-1) { -ICLASS: VPANDQ +ICLASS: VPERMI2D CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 -IFORM: VPANDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +PATTERN: EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 } { -ICLASS: VPANDQ +ICLASS: VPERMI2D CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPANDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPERMI2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 } -# EMITTING VPAVGB (VPAVGB-128-1) +# EMITTING VPERMI2PD (VPERMI2PD-128-1) { -ICLASS: VPAVGB +ICLASS: VPERMI2PD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xE0 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 -OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 -IFORM: VPAVGB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +PATTERN: EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VPAVGB +ICLASS: VPERMI2PD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xE0 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 -IFORM: VPAVGB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VPERMI2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 } -# EMITTING VPAVGB (VPAVGB-256-1) +# EMITTING VPERMI2PD (VPERMI2PD-256-1) { -ICLASS: VPAVGB +ICLASS: VPERMI2PD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xE0 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 -OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 -IFORM: VPAVGB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +PATTERN: EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 } { -ICLASS: VPAVGB +ICLASS: VPERMI2PD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xE0 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 -IFORM: VPAVGB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VPERMI2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 } -# EMITTING VPAVGB (VPAVGB-512-1) +# EMITTING VPERMI2PS (VPERMI2PS-128-1) { -ICLASS: VPAVGB +ICLASS: VPERMI2PS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xE0 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 -OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 -IFORM: VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +PATTERN: EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VPAVGB +ICLASS: VPERMI2PS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xE0 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 -IFORM: VPAVGB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VPERMI2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 } -# EMITTING VPAVGW (VPAVGW-128-1) +# EMITTING VPERMI2PS (VPERMI2PS-256-1) { -ICLASS: VPAVGW +ICLASS: VPERMI2PS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xE3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 -OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 -IFORM: VPAVGW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +PATTERN: EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 } { -ICLASS: VPAVGW +ICLASS: VPERMI2PS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xE3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 -IFORM: VPAVGW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VPERMI2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 } -# EMITTING VPAVGW (VPAVGW-256-1) +# EMITTING VPERMI2Q (VPERMI2Q-128-1) { -ICLASS: VPAVGW +ICLASS: VPERMI2Q CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xE3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 -OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 -IFORM: VPAVGW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +PATTERN: EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 } { -ICLASS: VPAVGW +ICLASS: VPERMI2Q CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xE3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 -IFORM: VPAVGW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPERMI2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 } -# EMITTING VPAVGW (VPAVGW-512-1) +# EMITTING VPERMI2Q (VPERMI2Q-256-1) { -ICLASS: VPAVGW +ICLASS: VPERMI2Q CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xE3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 -OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 -IFORM: VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +PATTERN: EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 } { -ICLASS: VPAVGW +ICLASS: VPERMI2Q CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xE3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 -IFORM: VPAVGW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPERMI2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 } -# EMITTING VPBLENDMB (VPBLENDMB-128-1) +# EMITTING VPERMI2W (VPERMI2W-128-1) { -ICLASS: VPBLENDMB +ICLASS: VPERMI2W CPL: 3 -CATEGORY: BLEND +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL -PATTERN: EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 -IFORM: VPBLENDMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 } { -ICLASS: VPBLENDMB +ICLASS: VPERMI2W CPL: 3 -CATEGORY: BLEND +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULLMEM -PATTERN: EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 -IFORM: VPBLENDMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPERMI2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 } -# EMITTING VPBLENDMB (VPBLENDMB-256-1) +# EMITTING VPERMI2W (VPERMI2W-256-1) { -ICLASS: VPBLENDMB +ICLASS: VPERMI2W CPL: 3 -CATEGORY: BLEND +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL -PATTERN: EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 -IFORM: VPBLENDMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 } { -ICLASS: VPBLENDMB +ICLASS: VPERMI2W CPL: 3 -CATEGORY: BLEND +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULLMEM -PATTERN: EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 -IFORM: VPBLENDMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPERMI2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 } -# EMITTING VPBLENDMB (VPBLENDMB-512-1) +# EMITTING VPERMI2W (VPERMI2W-512-1) { -ICLASS: VPBLENDMB +ICLASS: VPERMI2W CPL: 3 -CATEGORY: BLEND +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL -PATTERN: EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 -IFORM: VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 } { -ICLASS: VPBLENDMB +ICLASS: VPERMI2W CPL: 3 -CATEGORY: BLEND +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULLMEM -PATTERN: EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 -IFORM: VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPERMI2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 } -# EMITTING VPBLENDMD (VPBLENDMD-128-1) +# EMITTING VPERMILPD (VPERMILPD-128-1) { -ICLASS: VPBLENDMD +ICLASS: VPERMILPD CPL: 3 -CATEGORY: BLEND +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL -PATTERN: EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 -IFORM: VPBLENDMD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x05 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VPERMILPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 } { -ICLASS: VPBLENDMD +ICLASS: VPERMILPD CPL: 3 -CATEGORY: BLEND +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPBLENDMD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x05 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VPERMILPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 } -# EMITTING VPBLENDMD (VPBLENDMD-256-1) +# EMITTING VPERMILPD (VPERMILPD-128-2) { -ICLASS: VPBLENDMD +ICLASS: VPERMILPD CPL: 3 -CATEGORY: BLEND +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL -PATTERN: EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 -IFORM: VPBLENDMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x0D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VPERMILPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VPBLENDMD +ICLASS: VPERMILPD CPL: 3 -CATEGORY: BLEND +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPBLENDMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x0D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VPERMILPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 } -# EMITTING VPBLENDMQ (VPBLENDMQ-128-1) +# EMITTING VPERMILPD (VPERMILPD-256-1) { -ICLASS: VPBLENDMQ +ICLASS: VPERMILPD CPL: 3 -CATEGORY: BLEND +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL -PATTERN: EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 -IFORM: VPBLENDMQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x05 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 IMM0:r:b +IFORM: VPERMILPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 } { -ICLASS: VPBLENDMQ +ICLASS: VPERMILPD CPL: 3 -CATEGORY: BLEND +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPBLENDMQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x05 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VPERMILPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 } -# EMITTING VPBLENDMQ (VPBLENDMQ-256-1) +# EMITTING VPERMILPD (VPERMILPD-256-2) { -ICLASS: VPBLENDMQ +ICLASS: VPERMILPD CPL: 3 -CATEGORY: BLEND +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL -PATTERN: EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 -IFORM: VPBLENDMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x0D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VPERMILPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 } { -ICLASS: VPBLENDMQ +ICLASS: VPERMILPD CPL: 3 -CATEGORY: BLEND +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPBLENDMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x0D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VPERMILPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 } -# EMITTING VPBLENDMW (VPBLENDMW-128-1) +# EMITTING VPERMILPS (VPERMILPS-128-1) { -ICLASS: VPBLENDMW +ICLASS: VPERMILPS CPL: 3 -CATEGORY: BLEND +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL -PATTERN: EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 -IFORM: VPBLENDMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x04 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VPERMILPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 } { -ICLASS: VPBLENDMW +ICLASS: VPERMILPS CPL: 3 -CATEGORY: BLEND +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULLMEM -PATTERN: EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 -IFORM: VPBLENDMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x04 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VPERMILPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 } -# EMITTING VPBLENDMW (VPBLENDMW-256-1) +# EMITTING VPERMILPS (VPERMILPS-128-2) { -ICLASS: VPBLENDMW +ICLASS: VPERMILPS CPL: 3 -CATEGORY: BLEND +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4 -REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL -PATTERN: EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 -IFORM: VPBLENDMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x0C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VPERMILPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VPBLENDMW +ICLASS: VPERMILPS CPL: 3 -CATEGORY: BLEND +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULLMEM -PATTERN: EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 -IFORM: VPBLENDMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x0C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VPERMILPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 } -# EMITTING VPBLENDMW (VPBLENDMW-512-1) +# EMITTING VPERMILPS (VPERMILPS-256-1) { -ICLASS: VPBLENDMW +ICLASS: VPERMILPS CPL: 3 -CATEGORY: BLEND +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL -PATTERN: EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 -IFORM: VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x04 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 IMM0:r:b +IFORM: VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 } { -ICLASS: VPBLENDMW +ICLASS: VPERMILPS CPL: 3 -CATEGORY: BLEND +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULLMEM -PATTERN: EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 -IFORM: VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x04 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 } -# EMITTING VPBROADCASTB (VPBROADCASTB-128-1) +# EMITTING VPERMILPS (VPERMILPS-256-2) { -ICLASS: VPBROADCASTB +ICLASS: VPERMILPS CPL: 3 -CATEGORY: BROADCAST +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E6 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x78 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u8 EMX_BROADCAST_1TO16_8 -IFORM: VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512 +PATTERN: EVV 0x0C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VPERMILPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 } { -ICLASS: VPBROADCASTB +ICLASS: VPERMILPS CPL: 3 -CATEGORY: BROADCAST +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E6 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1_BYTE -PATTERN: EVV 0x78 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_8_BITS() NELEM_TUPLE1_BYTE() -OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:b:u8 EMX_BROADCAST_1TO16_8 -IFORM: VPBROADCASTB_XMMu8_MASKmskw_MEMu8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x0C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VPERMILPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 } -# EMITTING VPBROADCASTB (VPBROADCASTB-128-2) +# EMITTING VPERMPD (VPERMPD-256-1) { -ICLASS: VPBROADCASTB +ICLASS: VPERMPD CPL: 3 -CATEGORY: BROADCAST +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E7NM +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x7A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u8 EMX_BROADCAST_1TO16_8 -IFORM: VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512 +PATTERN: EVV 0x01 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 IMM0:r:b +IFORM: VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 } - -# EMITTING VPBROADCASTB (VPBROADCASTB-256-1) { -ICLASS: VPBROADCASTB +ICLASS: VPERMPD CPL: 3 -CATEGORY: BROADCAST +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E6 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x78 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u8 EMX_BROADCAST_1TO32_8 -IFORM: VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x01 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VPERMPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 } + +# EMITTING VPERMPD (VPERMPD-256-2) { -ICLASS: VPBROADCASTB +ICLASS: VPERMPD CPL: 3 -CATEGORY: BROADCAST +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E6 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1_BYTE -PATTERN: EVV 0x78 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_8_BITS() NELEM_TUPLE1_BYTE() -OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:b:u8 EMX_BROADCAST_1TO32_8 -IFORM: VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x16 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 } - -# EMITTING VPBROADCASTB (VPBROADCASTB-256-2) { -ICLASS: VPBROADCASTB +ICLASS: VPERMPD CPL: 3 -CATEGORY: BROADCAST +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E7NM +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x7A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u8 EMX_BROADCAST_1TO32_8 -IFORM: VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x16 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VPERMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 } -# EMITTING VPBROADCASTB (VPBROADCASTB-512-1) +# EMITTING VPERMPS (VPERMPS-256-1) { -ICLASS: VPBROADCASTB +ICLASS: VPERMPS CPL: 3 -CATEGORY: BROADCAST +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E6 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x78 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u8 EMX_BROADCAST_1TO64_8 -IFORM: VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512 +PATTERN: EVV 0x16 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 } { -ICLASS: VPBROADCASTB +ICLASS: VPERMPS CPL: 3 -CATEGORY: BROADCAST +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E6 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1_BYTE -PATTERN: EVV 0x78 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_8_BITS() NELEM_TUPLE1_BYTE() -OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:b:u8 EMX_BROADCAST_1TO64_8 -IFORM: VPBROADCASTB_ZMMu8_MASKmskw_MEMu8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x16 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VPERMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 } -# EMITTING VPBROADCASTB (VPBROADCASTB-512-2) +# EMITTING VPERMQ (VPERMQ-256-1) { -ICLASS: VPBROADCASTB +ICLASS: VPERMQ CPL: 3 -CATEGORY: BROADCAST +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E7NM +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x7A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u8 EMX_BROADCAST_1TO64_8 -IFORM: VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512 +PATTERN: EVV 0x00 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 } - -# EMITTING VPBROADCASTD (VPBROADCASTD-128-1) { -ICLASS: VPBROADCASTD +ICLASS: VPERMQ CPL: 3 -CATEGORY: BROADCAST +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E6 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 -PATTERN: EVV 0x58 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1() -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:u32 EMX_BROADCAST_1TO4_32 -IFORM: VPBROADCASTD_XMMu32_MASKmskw_MEMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x00 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 } -# EMITTING VPBROADCASTD (VPBROADCASTD-128-2) +# EMITTING VPERMQ (VPERMQ-256-2) { -ICLASS: VPBROADCASTD +ICLASS: VPERMQ CPL: 3 -CATEGORY: BROADCAST +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E6 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x58 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_1TO4_32 -IFORM: VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512 +PATTERN: EVV 0x36 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 } - -# EMITTING VPBROADCASTD (VPBROADCASTD-128-3) { -ICLASS: VPBROADCASTD +ICLASS: VPERMQ CPL: 3 -CATEGORY: BROADCAST +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E7NM +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO4_32 -IFORM: VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x36 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPERMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 } -# EMITTING VPBROADCASTD (VPBROADCASTD-256-1) +# EMITTING VPERMT2D (VPERMT2D-128-1) { -ICLASS: VPBROADCASTD +ICLASS: VPERMT2D CPL: 3 -CATEGORY: BROADCAST +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E6 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 -PATTERN: EVV 0x58 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1() -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:u32 EMX_BROADCAST_1TO8_32 -IFORM: VPBROADCASTD_YMMu32_MASKmskw_MEMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 } - -# EMITTING VPBROADCASTD (VPBROADCASTD-256-2) { -ICLASS: VPBROADCASTD +ICLASS: VPERMT2D CPL: 3 -CATEGORY: BROADCAST +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E6 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x58 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_1TO8_32 -IFORM: VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPERMT2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 } -# EMITTING VPBROADCASTD (VPBROADCASTD-256-3) +# EMITTING VPERMT2D (VPERMT2D-256-1) { -ICLASS: VPBROADCASTD +ICLASS: VPERMT2D CPL: 3 -CATEGORY: BROADCAST +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E7NM +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO8_32 -IFORM: VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512 +PATTERN: EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 } - -# EMITTING VPBROADCASTMB2Q (VPBROADCASTMB2Q-128-1) { -ICLASS: VPBROADCASTMB2Q +ICLASS: VPERMT2D CPL: 3 -CATEGORY: BROADCAST +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512CD_128 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -PATTERN: EVV 0x2A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK_B():r:mskw:u64 EMX_BROADCAST_1TO2_8 -IFORM: VPBROADCASTMB2Q_XMMu64_MASKu64_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPERMT2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 } -# EMITTING VPBROADCASTMB2Q (VPBROADCASTMB2Q-256-1) +# EMITTING VPERMT2PD (VPERMT2PD-128-1) { -ICLASS: VPBROADCASTMB2Q +ICLASS: VPERMT2PD CPL: 3 -CATEGORY: BROADCAST +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512CD_256 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -PATTERN: EVV 0x2A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK_B():r:mskw:u64 EMX_BROADCAST_1TO4_8 -IFORM: VPBROADCASTMB2Q_YMMu64_MASKu64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } - -# EMITTING VPBROADCASTMW2D (VPBROADCASTMW2D-128-1) { -ICLASS: VPBROADCASTMW2D +ICLASS: VPERMT2PD CPL: 3 -CATEGORY: BROADCAST +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512CD_128 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -PATTERN: EVV 0x3A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK_B():r:mskw:u32 EMX_BROADCAST_1TO4_16 -IFORM: VPBROADCASTMW2D_XMMu32_MASKu32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VPERMT2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 } -# EMITTING VPBROADCASTMW2D (VPBROADCASTMW2D-256-1) +# EMITTING VPERMT2PD (VPERMT2PD-256-1) { -ICLASS: VPBROADCASTMW2D +ICLASS: VPERMT2PD CPL: 3 -CATEGORY: BROADCAST +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512CD_256 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -PATTERN: EVV 0x3A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK_B():r:mskw:u32 EMX_BROADCAST_1TO8_16 -IFORM: VPBROADCASTMW2D_YMMu32_MASKu32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 } - -# EMITTING VPBROADCASTQ (VPBROADCASTQ-128-1) { -ICLASS: VPBROADCASTQ +ICLASS: VPERMT2PD CPL: 3 -CATEGORY: BROADCAST +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E6 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 -PATTERN: EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE1() -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u64 EMX_BROADCAST_1TO2_64 -IFORM: VPBROADCASTQ_XMMu64_MASKmskw_MEMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VPERMT2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 } -# EMITTING VPBROADCASTQ (VPBROADCASTQ-128-2) +# EMITTING VPERMT2PS (VPERMT2PS-128-1) { -ICLASS: VPBROADCASTQ +ICLASS: VPERMT2PS CPL: 3 -CATEGORY: BROADCAST +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E6 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 EMX_BROADCAST_1TO2_64 -IFORM: VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512 +PATTERN: EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } - -# EMITTING VPBROADCASTQ (VPBROADCASTQ-128-3) { -ICLASS: VPBROADCASTQ +ICLASS: VPERMT2PS CPL: 3 -CATEGORY: BROADCAST +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E7NM +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 mode64 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR64_B():r:q:u64 EMX_BROADCAST_1TO2_64 -IFORM: VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VPERMT2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 } -# EMITTING VPBROADCASTQ (VPBROADCASTQ-256-1) +# EMITTING VPERMT2PS (VPERMT2PS-256-1) { -ICLASS: VPBROADCASTQ +ICLASS: VPERMT2PS CPL: 3 -CATEGORY: BROADCAST +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E6 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 -PATTERN: EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE1() -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u64 EMX_BROADCAST_1TO4_64 -IFORM: VPBROADCASTQ_YMMu64_MASKmskw_MEMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 } - -# EMITTING VPBROADCASTQ (VPBROADCASTQ-256-2) { -ICLASS: VPBROADCASTQ +ICLASS: VPERMT2PS CPL: 3 -CATEGORY: BROADCAST +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E6 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 EMX_BROADCAST_1TO4_64 -IFORM: VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VPERMT2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 } -# EMITTING VPBROADCASTQ (VPBROADCASTQ-256-3) +# EMITTING VPERMT2Q (VPERMT2Q-128-1) { -ICLASS: VPBROADCASTQ +ICLASS: VPERMT2Q CPL: 3 -CATEGORY: BROADCAST +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E7NM +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 mode64 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR64_B():r:q:u64 EMX_BROADCAST_1TO4_64 -IFORM: VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512 +PATTERN: EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 } - -# EMITTING VPBROADCASTW (VPBROADCASTW-128-1) { -ICLASS: VPBROADCASTW +ICLASS: VPERMT2Q CPL: 3 -CATEGORY: BROADCAST +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E6 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x79 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 EMX_BROADCAST_1TO8_16 -IFORM: VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPERMT2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 } + +# EMITTING VPERMT2Q (VPERMT2Q-256-1) { -ICLASS: VPBROADCASTW +ICLASS: VPERMT2Q CPL: 3 -CATEGORY: BROADCAST +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E6 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1_WORD -PATTERN: EVV 0x79 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_TUPLE1_WORD() -OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:wrd:u16 EMX_BROADCAST_1TO8_16 -IFORM: VPBROADCASTW_XMMu16_MASKmskw_MEMu16_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 } - -# EMITTING VPBROADCASTW (VPBROADCASTW-128-2) { -ICLASS: VPBROADCASTW +ICLASS: VPERMT2Q CPL: 3 -CATEGORY: BROADCAST +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E7NM +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x7B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u16 EMX_BROADCAST_1TO8_16 -IFORM: VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPERMT2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 } -# EMITTING VPBROADCASTW (VPBROADCASTW-256-1) +# EMITTING VPERMT2W (VPERMT2W-128-1) { -ICLASS: VPBROADCASTW +ICLASS: VPERMT2W CPL: 3 -CATEGORY: BROADCAST +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E6 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x79 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 EMX_BROADCAST_1TO16_16 -IFORM: VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512 +PATTERN: EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 } { -ICLASS: VPBROADCASTW +ICLASS: VPERMT2W CPL: 3 -CATEGORY: BROADCAST +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E6 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1_WORD -PATTERN: EVV 0x79 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_TUPLE1_WORD() -OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:wrd:u16 EMX_BROADCAST_1TO16_16 -IFORM: VPBROADCASTW_YMMu16_MASKmskw_MEMu16_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPERMT2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 } -# EMITTING VPBROADCASTW (VPBROADCASTW-256-2) +# EMITTING VPERMT2W (VPERMT2W-256-1) { -ICLASS: VPBROADCASTW +ICLASS: VPERMT2W CPL: 3 -CATEGORY: BROADCAST +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E7NM +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x7B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u16 EMX_BROADCAST_1TO16_16 -IFORM: VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512 +PATTERN: EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 } - -# EMITTING VPBROADCASTW (VPBROADCASTW-512-1) { -ICLASS: VPBROADCASTW +ICLASS: VPERMT2W CPL: 3 -CATEGORY: BROADCAST +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E6 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x79 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 EMX_BROADCAST_1TO32_16 -IFORM: VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPERMT2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 } + +# EMITTING VPERMT2W (VPERMT2W-512-1) { -ICLASS: VPBROADCASTW +ICLASS: VPERMT2W CPL: 3 -CATEGORY: BROADCAST +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E6 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1_WORD -PATTERN: EVV 0x79 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_TUPLE1_WORD() -OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:wrd:u16 EMX_BROADCAST_1TO32_16 -IFORM: VPBROADCASTW_ZMMu16_MASKmskw_MEMu16_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 } - -# EMITTING VPBROADCASTW (VPBROADCASTW-512-2) { -ICLASS: VPBROADCASTW +ICLASS: VPERMT2W CPL: 3 -CATEGORY: BROADCAST +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E7NM +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x7B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u16 EMX_BROADCAST_1TO32_16 -IFORM: VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPERMT2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 } -# EMITTING VPCMPB (VPCMPB-128-1) +# EMITTING VPERMW (VPERMW-128-1) { -ICLASS: VPCMPB +ICLASS: VPERMW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i8 REG3=XMM_B3():r:dq:i8 IMM0:r:b -IFORM: VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512 +PATTERN: EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 } { -ICLASS: VPCMPB +ICLASS: VPERMW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i8 MEM0:r:dq:i8 IMM0:r:b -IFORM: VPCMPB_MASKmskw_MASKmskw_XMMi8_MEMi8_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPERMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 } -# EMITTING VPCMPB (VPCMPB-256-1) +# EMITTING VPERMW (VPERMW-256-1) { -ICLASS: VPCMPB +ICLASS: VPERMW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i8 REG3=YMM_B3():r:qq:i8 IMM0:r:b -IFORM: VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512 +PATTERN: EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 } { -ICLASS: VPCMPB +ICLASS: VPERMW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i8 MEM0:r:qq:i8 IMM0:r:b -IFORM: VPCMPB_MASKmskw_MASKmskw_YMMi8_MEMi8_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPERMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 } -# EMITTING VPCMPB (VPCMPB-512-1) +# EMITTING VPERMW (VPERMW-512-1) { -ICLASS: VPCMPB +ICLASS: VPERMW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi8 REG3=ZMM_B3():r:zi8 IMM0:r:b -IFORM: VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512 +PATTERN: EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 } { -ICLASS: VPCMPB +ICLASS: VPERMW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPERMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPEXPANDD (VPEXPANDD-128-1) +{ +ICLASS: VPEXPANDD +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi8 MEM0:r:zd:i8 IMM0:r:b -IFORM: VPCMPB_MASKmskw_MASKmskw_ZMMi8_MEMi8_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u32 +IFORM: VPEXPANDD_XMMu32_MASKmskw_MEMu32_AVX512 } -# EMITTING VPCMPD (VPCMPD-128-1) +# EMITTING VPEXPANDD (VPEXPANDD-128-2) { -ICLASS: VPCMPD +ICLASS: VPEXPANDD CPL: 3 -CATEGORY: AVX512 +CATEGORY: EXPAND EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i32 REG3=XMM_B3():r:dq:i32 IMM0:r:b -IFORM: VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512 +PATTERN: EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 +IFORM: VPEXPANDD_XMMu32_MASKmskw_XMMu32_AVX512 } + +# EMITTING VPEXPANDD (VPEXPANDD-256-1) { -ICLASS: VPCMPD +ICLASS: VPEXPANDD CPL: 3 -CATEGORY: AVX512 +CATEGORY: EXPAND EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i32 MEM0:r:vv:i32:TXT=BCASTSTR IMM0:r:b -IFORM: VPCMPD_MASKmskw_MASKmskw_XMMi32_MEMi32_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u32 +IFORM: VPEXPANDD_YMMu32_MASKmskw_MEMu32_AVX512 } -# EMITTING VPCMPD (VPCMPD-256-1) +# EMITTING VPEXPANDD (VPEXPANDD-256-2) { -ICLASS: VPCMPD +ICLASS: VPEXPANDD CPL: 3 -CATEGORY: AVX512 +CATEGORY: EXPAND EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i32 REG3=YMM_B3():r:qq:i32 IMM0:r:b -IFORM: VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512 +PATTERN: EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 +IFORM: VPEXPANDD_YMMu32_MASKmskw_YMMu32_AVX512 } + +# EMITTING VPEXPANDQ (VPEXPANDQ-128-1) { -ICLASS: VPCMPD +ICLASS: VPEXPANDQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: EXPAND EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i32 MEM0:r:vv:i32:TXT=BCASTSTR IMM0:r:b -IFORM: VPCMPD_MASKmskw_MASKmskw_YMMi32_MEMi32_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u64 +IFORM: VPEXPANDQ_XMMu64_MASKmskw_MEMu64_AVX512 } -# EMITTING VPCMPEQB (VPCMPEQB-128-1) +# EMITTING VPEXPANDQ (VPEXPANDQ-128-2) { -ICLASS: VPCMPEQB +ICLASS: VPEXPANDQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: EXPAND EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x74 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 -IFORM: VPCMPEQB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 +PATTERN: EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 +IFORM: VPEXPANDQ_XMMu64_MASKmskw_XMMu64_AVX512 } + +# EMITTING VPEXPANDQ (VPEXPANDQ-256-1) { -ICLASS: VPCMPEQB +ICLASS: VPEXPANDQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: EXPAND EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x74 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 -IFORM: VPCMPEQB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u64 +IFORM: VPEXPANDQ_YMMu64_MASKmskw_MEMu64_AVX512 } -# EMITTING VPCMPEQB (VPCMPEQB-256-1) +# EMITTING VPEXPANDQ (VPEXPANDQ-256-2) { -ICLASS: VPCMPEQB +ICLASS: VPEXPANDQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: EXPAND EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x74 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 -IFORM: VPCMPEQB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 +PATTERN: EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 +IFORM: VPEXPANDQ_YMMu64_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VPEXTRB (VPEXTRB-128-1) +{ +ICLASS: VPEXTRB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +PATTERN: EVV 0x14 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=GPR32_B():w:d:u8 REG1=XMM_R3():r:dq:u8 IMM0:r:b +IFORM: VPEXTRB_GPR32u8_XMMu8_IMM8_AVX512 } { -ICLASS: VPCMPEQB +ICLASS: VPEXTRB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_128N +EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x74 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 -IFORM: VPCMPEQB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 +ATTRIBUTES: DISP8_GPR_WRITER_STORE_BYTE +PATTERN: EVV 0x14 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_GPR_WRITER_STORE_BYTE() +OPERANDS: MEM0:w:b:u8 REG0=XMM_R3():r:dq:u8 IMM0:r:b +IFORM: VPEXTRB_MEMu8_XMMu8_IMM8_AVX512 } -# EMITTING VPCMPEQB (VPCMPEQB-512-1) +# EMITTING VPEXTRD (VPEXTRD-128-1) { -ICLASS: VPCMPEQB +ICLASS: VPEXTRD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512DQ_128N +EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x74 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 -IFORM: VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 +PATTERN: EVV 0x16 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 NOEVSR ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=GPR32_B():w:d:u32 REG1=XMM_R3():r:dq:u32 IMM0:r:b +IFORM: VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512 +PATTERN: EVV 0x16 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=GPR32_B():w:d:u32 REG1=XMM_R3():r:dq:u32 IMM0:r:b +IFORM: VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512 } { -ICLASS: VPCMPEQB +ICLASS: VPEXTRD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512DQ_128N +EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x74 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 -IFORM: VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 +ATTRIBUTES: DISP8_GPR_WRITER_STORE +PATTERN: EVV 0x16 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 not64 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_WRITER_STORE() +OPERANDS: MEM0:w:d:u32 REG0=XMM_R3():r:dq:u32 IMM0:r:b +IFORM: VPEXTRD_MEMu32_XMMu32_IMM8_AVX512 +PATTERN: EVV 0x16 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_WRITER_STORE() +OPERANDS: MEM0:w:d:u32 REG0=XMM_R3():r:dq:u32 IMM0:r:b +IFORM: VPEXTRD_MEMu32_XMMu32_IMM8_AVX512 } -# EMITTING VPCMPEQD (VPCMPEQD-128-1) +# EMITTING VPEXTRQ (VPEXTRQ-128-1) { -ICLASS: VPCMPEQD +ICLASS: VPEXTRQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512DQ_128N +EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x76 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 -IFORM: VPCMPEQD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512 +PATTERN: EVV 0x16 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=GPR64_B():w:q:u64 REG1=XMM_R3():r:dq:u64 IMM0:r:b +IFORM: VPEXTRQ_GPR64u64_XMMu64_IMM8_AVX512 } { -ICLASS: VPCMPEQD +ICLASS: VPEXTRQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512DQ_128N +EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x76 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPCMPEQD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512 +ATTRIBUTES: DISP8_GPR_WRITER_STORE +PATTERN: EVV 0x16 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_64_BITS() NELEM_GPR_WRITER_STORE() +OPERANDS: MEM0:w:q:u64 REG0=XMM_R3():r:dq:u64 IMM0:r:b +IFORM: VPEXTRQ_MEMu64_XMMu64_IMM8_AVX512 } -# EMITTING VPCMPEQD (VPCMPEQD-256-1) +# EMITTING VPEXTRW (VPEXTRW-128-1) { -ICLASS: VPCMPEQD +ICLASS: VPEXTRW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_128N +EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x76 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 -IFORM: VPCMPEQD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512 +PATTERN: EVV 0x15 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=GPR32_B():w:d:u16 REG1=XMM_R3():r:dq:u16 IMM0:r:b +IFORM: VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512 } { -ICLASS: VPCMPEQD +ICLASS: VPEXTRW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_128N +EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x76 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPCMPEQD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512 +ATTRIBUTES: DISP8_GPR_WRITER_STORE_WORD +PATTERN: EVV 0x15 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_16_BITS() NELEM_GPR_WRITER_STORE_WORD() +OPERANDS: MEM0:w:wrd:u16 REG0=XMM_R3():r:dq:u16 IMM0:r:b +IFORM: VPEXTRW_MEMu16_XMMu16_IMM8_AVX512 } -# EMITTING VPCMPEQQ (VPCMPEQQ-128-1) +# EMITTING VPEXTRW (VPEXTRW-128-2) { -ICLASS: VPCMPEQQ +ICLASS: VPEXTRW_C5 +DISASM: vpextrw CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_128N +EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 -IFORM: VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512 + +PATTERN: EVV 0xC5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() not64 +OPERANDS: REG0=GPR32_R():w:d:u16 REG1=XMM_B3():r:dq:u16 IMM0:r:b +IFORM: VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_C5 + +PATTERN: EVV 0xC5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() mode64 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:u16 REG1=XMM_B3():r:dq:u16 IMM0:r:b +IFORM: VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_C5 } + +# EMITTING VPGATHERDD (VPGATHERDD-128-2) { -ICLASS: VPCMPEQQ +ICLASS: VPGATHERDD CPL: 3 -CATEGORY: AVX512 +CATEGORY: GATHER EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E12 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512 +ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASKNOT0():rw:mskw MEM0:r:d:u32 +IFORM: VPGATHERDD_XMMu32_MASKmskw_MEMu32_AVX512_VL128 } -# EMITTING VPCMPEQQ (VPCMPEQQ-256-1) +# EMITTING VPGATHERDD (VPGATHERDD-256-2) { -ICLASS: VPCMPEQQ +ICLASS: VPGATHERDD CPL: 3 -CATEGORY: AVX512 +CATEGORY: GATHER EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E12 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 -IFORM: VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512 +ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASKNOT0():rw:mskw MEM0:r:d:u32 +IFORM: VPGATHERDD_YMMu32_MASKmskw_MEMu32_AVX512_VL256 } + +# EMITTING VPGATHERDQ (VPGATHERDQ-128-2) { -ICLASS: VPCMPEQQ +ICLASS: VPGATHERDQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASKNOT0():rw:mskw MEM0:r:q:u64 +IFORM: VPGATHERDQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128 +} + + +# EMITTING VPGATHERDQ (VPGATHERDQ-256-2) +{ +ICLASS: VPGATHERDQ +CPL: 3 +CATEGORY: GATHER EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E12 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512 +ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASKNOT0():rw:mskw MEM0:r:q:u64 +IFORM: VPGATHERDQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256 } -# EMITTING VPCMPEQW (VPCMPEQW-128-1) +# EMITTING VPGATHERQD (VPGATHERQD-128-2) { -ICLASS: VPCMPEQW +ICLASS: VPGATHERQD CPL: 3 -CATEGORY: AVX512 +CATEGORY: GATHER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x75 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 -IFORM: VPCMPEQW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 +ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASKNOT0():rw:mskw MEM0:r:d:u32 +IFORM: VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL128 } + +# EMITTING VPGATHERQD (VPGATHERQD-256-2) { -ICLASS: VPCMPEQW +ICLASS: VPGATHERQD CPL: 3 -CATEGORY: AVX512 +CATEGORY: GATHER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASKNOT0():rw:mskw MEM0:r:d:u32 +IFORM: VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL256 +} + + +# EMITTING VPGATHERQQ (VPGATHERQQ-128-2) +{ +ICLASS: VPGATHERQQ +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASKNOT0():rw:mskw MEM0:r:q:u64 +IFORM: VPGATHERQQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128 +} + + +# EMITTING VPGATHERQQ (VPGATHERQQ-256-2) +{ +ICLASS: VPGATHERQQ +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x75 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 -IFORM: VPCMPEQW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 +ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASKNOT0():rw:mskw MEM0:r:q:u64 +IFORM: VPGATHERQQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256 } -# EMITTING VPCMPEQW (VPCMPEQW-256-1) +# EMITTING VPINSRB (VPINSRB-128-1) { -ICLASS: VPCMPEQW +ICLASS: VPINSRB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_128N +EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x75 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 -IFORM: VPCMPEQW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 +PATTERN: EVV 0x20 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=XMM_N3():r:dq:u8 REG2=GPR32_B():r:d:u8 IMM0:r:b +IFORM: VPINSRB_XMMu8_XMMu8_GPR32u8_IMM8_AVX512 } { -ICLASS: VPCMPEQW +ICLASS: VPINSRB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_128N +EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x75 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 -IFORM: VPCMPEQW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 +ATTRIBUTES: DISP8_GPR_READER_BYTE +PATTERN: EVV 0x20 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_GPR_READER_BYTE() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=XMM_N3():r:dq:u8 MEM0:r:b:u8 IMM0:r:b +IFORM: VPINSRB_XMMu8_XMMu8_MEMu8_IMM8_AVX512 } -# EMITTING VPCMPEQW (VPCMPEQW-512-1) +# EMITTING VPINSRD (VPINSRD-128-1) { -ICLASS: VPCMPEQW +ICLASS: VPINSRD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512DQ_128N +EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x75 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 -IFORM: VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 +PATTERN: EVV 0x22 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=XMM_N3():r:dq:u32 REG2=GPR32_B():r:d:u32 IMM0:r:b +IFORM: VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512 +PATTERN: EVV 0x22 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 mode64 W0 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=XMM_N3():r:dq:u32 REG2=GPR32_B():r:d:u32 IMM0:r:b +IFORM: VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512 } { -ICLASS: VPCMPEQW +ICLASS: VPINSRD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512DQ_128N +EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x75 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 -IFORM: VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 +ATTRIBUTES: DISP8_GPR_READER +PATTERN: EVV 0x22 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 not64 ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=XMM_N3():r:dq:u32 MEM0:r:d:u32 IMM0:r:b +IFORM: VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512 +PATTERN: EVV 0x22 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 mode64 W0 ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=XMM_N3():r:dq:u32 MEM0:r:d:u32 IMM0:r:b +IFORM: VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512 } -# EMITTING VPCMPGTB (VPCMPGTB-128-1) +# EMITTING VPINSRQ (VPINSRQ-128-1) { -ICLASS: VPCMPGTB +ICLASS: VPINSRQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512DQ_128N +EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x64 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 -IFORM: VPCMPGTB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 +PATTERN: EVV 0x22 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 mode64 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=XMM_N3():r:dq:u64 REG2=GPR64_B():r:q:u64 IMM0:r:b +IFORM: VPINSRQ_XMMu64_XMMu64_GPR64u64_IMM8_AVX512 } { -ICLASS: VPCMPGTB +ICLASS: VPINSRQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512DQ_128N +EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x64 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 -IFORM: VPCMPGTB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 +ATTRIBUTES: DISP8_GPR_READER +PATTERN: EVV 0x22 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 mode64 ZEROING=0 MASK=0 UIMM8() ESIZE_64_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=XMM_N3():r:dq:u64 MEM0:r:q:u64 IMM0:r:b +IFORM: VPINSRQ_XMMu64_XMMu64_MEMu64_IMM8_AVX512 } -# EMITTING VPCMPGTB (VPCMPGTB-256-1) +# EMITTING VPINSRW (VPINSRW-128-1) { -ICLASS: VPCMPGTB +ICLASS: VPINSRW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_128N +EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x64 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 -IFORM: VPCMPGTB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 +PATTERN: EVV 0xC4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=XMM_N3():r:dq:u16 REG2=GPR32_B():r:d:u16 IMM0:r:b +IFORM: VPINSRW_XMMu16_XMMu16_GPR32u16_IMM8_AVX512 } { -ICLASS: VPCMPGTB +ICLASS: VPINSRW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_128N +EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x64 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 -IFORM: VPCMPGTB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 +ATTRIBUTES: DISP8_GPR_READER_WORD +PATTERN: EVV 0xC4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_16_BITS() NELEM_GPR_READER_WORD() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=XMM_N3():r:dq:u16 MEM0:r:wrd:u16 IMM0:r:b +IFORM: VPINSRW_XMMu16_XMMu16_MEMu16_IMM8_AVX512 } -# EMITTING VPCMPGTB (VPCMPGTB-512-1) +# EMITTING VPLZCNTD (VPLZCNTD-128-1) { -ICLASS: VPCMPGTB +ICLASS: VPLZCNTD CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONFLICT EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 +ISA_SET: AVX512CD_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x64 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 -IFORM: VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 +PATTERN: EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 +IFORM: VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512 } { -ICLASS: VPCMPGTB +ICLASS: VPLZCNTD CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONFLICT EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 +ISA_SET: AVX512CD_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x64 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 -IFORM: VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPLZCNTD_XMMu32_MASKmskw_MEMu32_AVX512 } -# EMITTING VPCMPGTD (VPCMPGTD-128-1) +# EMITTING VPLZCNTD (VPLZCNTD-256-1) { -ICLASS: VPCMPGTD +ICLASS: VPLZCNTD CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONFLICT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512CD_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x66 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i32 REG3=XMM_B3():r:dq:i32 -IFORM: VPCMPGTD_MASKmskw_MASKmskw_XMMi32_XMMi32_AVX512 +PATTERN: EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 +IFORM: VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512 } { -ICLASS: VPCMPGTD +ICLASS: VPLZCNTD CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONFLICT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512CD_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x66 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i32 MEM0:r:vv:i32:TXT=BCASTSTR -IFORM: VPCMPGTD_MASKmskw_MASKmskw_XMMi32_MEMi32_AVX512 +PATTERN: EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPLZCNTD_YMMu32_MASKmskw_MEMu32_AVX512 } -# EMITTING VPCMPGTD (VPCMPGTD-256-1) +# EMITTING VPLZCNTQ (VPLZCNTQ-128-1) { -ICLASS: VPCMPGTD +ICLASS: VPLZCNTQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONFLICT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 +ISA_SET: AVX512CD_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x66 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i32 REG3=YMM_B3():r:qq:i32 -IFORM: VPCMPGTD_MASKmskw_MASKmskw_YMMi32_YMMi32_AVX512 +PATTERN: EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 +IFORM: VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512 } { -ICLASS: VPCMPGTD +ICLASS: VPLZCNTQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONFLICT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 +ISA_SET: AVX512CD_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x66 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i32 MEM0:r:vv:i32:TXT=BCASTSTR -IFORM: VPCMPGTD_MASKmskw_MASKmskw_YMMi32_MEMi32_AVX512 +PATTERN: EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPLZCNTQ_XMMu64_MASKmskw_MEMu64_AVX512 } -# EMITTING VPCMPGTQ (VPCMPGTQ-128-1) +# EMITTING VPLZCNTQ (VPLZCNTQ-256-1) { -ICLASS: VPCMPGTQ +ICLASS: VPLZCNTQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONFLICT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512CD_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x37 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i64 REG3=XMM_B3():r:dq:i64 -IFORM: VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_XMMi64_AVX512 +PATTERN: EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 +IFORM: VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512 } { -ICLASS: VPCMPGTQ +ICLASS: VPLZCNTQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: CONFLICT EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512CD_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x37 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i64 MEM0:r:vv:i64:TXT=BCASTSTR -IFORM: VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_MEMi64_AVX512 +PATTERN: EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPLZCNTQ_YMMu64_MASKmskw_MEMu64_AVX512 } -# EMITTING VPCMPGTQ (VPCMPGTQ-256-1) +# EMITTING VPMADDUBSW (VPMADDUBSW-128-1) { -ICLASS: VPCMPGTQ +ICLASS: VPMADDUBSW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x37 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i64 REG3=YMM_B3():r:qq:i64 -IFORM: VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_YMMi64_AVX512 +PATTERN: EVV 0x04 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 +IFORM: VPMADDUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 } { -ICLASS: VPCMPGTQ +ICLASS: VPMADDUBSW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x37 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i64 MEM0:r:vv:i64:TXT=BCASTSTR -IFORM: VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_MEMi64_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x04 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 +IFORM: VPMADDUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 } -# EMITTING VPCMPGTW (VPCMPGTW-128-1) +# EMITTING VPMADDUBSW (VPMADDUBSW-256-1) { -ICLASS: VPCMPGTW +ICLASS: VPMADDUBSW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x65 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 -IFORM: VPCMPGTW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 +PATTERN: EVV 0x04 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 +IFORM: VPMADDUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 } { -ICLASS: VPCMPGTW +ICLASS: VPMADDUBSW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x65 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 -IFORM: VPCMPGTW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x04 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 +IFORM: VPMADDUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 } -# EMITTING VPCMPGTW (VPCMPGTW-256-1) +# EMITTING VPMADDUBSW (VPMADDUBSW-512-1) { -ICLASS: VPCMPGTW +ICLASS: VPMADDUBSW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x65 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 -IFORM: VPCMPGTW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 +PATTERN: EVV 0x04 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 +IFORM: VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 } { -ICLASS: VPCMPGTW +ICLASS: VPMADDUBSW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x65 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 -IFORM: VPCMPGTW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x04 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 +IFORM: VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 } -# EMITTING VPCMPGTW (VPCMPGTW-512-1) +# EMITTING VPMADDWD (VPMADDWD-128-1) { -ICLASS: VPCMPGTW +ICLASS: VPMADDWD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x65 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 -IFORM: VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 +PATTERN: EVV 0xF5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 +IFORM: VPMADDWD_XMMi32_MASKmskw_XMMi16_XMMi16_AVX512 } { -ICLASS: VPCMPGTW +ICLASS: VPMADDWD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x65 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 -IFORM: VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xF5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 +IFORM: VPMADDWD_XMMi32_MASKmskw_XMMi16_MEMi16_AVX512 } -# EMITTING VPCMPQ (VPCMPQ-128-1) +# EMITTING VPMADDWD (VPMADDWD-256-1) { -ICLASS: VPCMPQ +ICLASS: VPMADDWD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 UIMM8() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i64 REG3=XMM_B3():r:dq:i64 IMM0:r:b -IFORM: VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512 +PATTERN: EVV 0xF5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 +IFORM: VPMADDWD_YMMi32_MASKmskw_YMMi16_YMMi16_AVX512 } { -ICLASS: VPCMPQ +ICLASS: VPMADDWD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i64 MEM0:r:vv:i64:TXT=BCASTSTR IMM0:r:b -IFORM: VPCMPQ_MASKmskw_MASKmskw_XMMi64_MEMi64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xF5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 +IFORM: VPMADDWD_YMMi32_MASKmskw_YMMi16_MEMi16_AVX512 } -# EMITTING VPCMPQ (VPCMPQ-256-1) +# EMITTING VPMADDWD (VPMADDWD-512-1) { -ICLASS: VPCMPQ +ICLASS: VPMADDWD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 UIMM8() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i64 REG3=YMM_B3():r:qq:i64 IMM0:r:b -IFORM: VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512 +PATTERN: EVV 0xF5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 +IFORM: VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512 } { -ICLASS: VPCMPQ +ICLASS: VPMADDWD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i64 MEM0:r:vv:i64:TXT=BCASTSTR IMM0:r:b -IFORM: VPCMPQ_MASKmskw_MASKmskw_YMMi64_MEMi64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xF5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 +IFORM: VPMADDWD_ZMMi32_MASKmskw_ZMMi16_MEMi16_AVX512 } -# EMITTING VPCMPUB (VPCMPUB-128-1) +# EMITTING VPMAXSB (VPMAXSB-128-1) { -ICLASS: VPCMPUB +ICLASS: VPMAXSB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -54943,13 +59525,13 @@ ISA_SET: AVX512BW_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 IMM0:r:b -IFORM: VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 +PATTERN: EVV 0x3C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 REG3=XMM_B3():r:dq:i8 +IFORM: VPMAXSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 } { -ICLASS: VPCMPUB +ICLASS: VPMAXSB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -54957,15 +59539,15 @@ ISA_SET: AVX512BW_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 IMM0:r:b -IFORM: VPCMPUB_MASKmskw_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 +PATTERN: EVV 0x3C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 MEM0:r:dq:i8 +IFORM: VPMAXSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 } -# EMITTING VPCMPUB (VPCMPUB-256-1) +# EMITTING VPMAXSB (VPMAXSB-256-1) { -ICLASS: VPCMPUB +ICLASS: VPMAXSB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -54973,13 +59555,13 @@ ISA_SET: AVX512BW_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 IMM0:r:b -IFORM: VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 +PATTERN: EVV 0x3C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 REG3=YMM_B3():r:qq:i8 +IFORM: VPMAXSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 } { -ICLASS: VPCMPUB +ICLASS: VPMAXSB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -54987,15 +59569,15 @@ ISA_SET: AVX512BW_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 IMM0:r:b -IFORM: VPCMPUB_MASKmskw_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 +PATTERN: EVV 0x3C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 MEM0:r:qq:i8 +IFORM: VPMAXSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 } -# EMITTING VPCMPUB (VPCMPUB-512-1) +# EMITTING VPMAXSB (VPMAXSB-512-1) { -ICLASS: VPCMPUB +ICLASS: VPMAXSB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -55003,13 +59585,13 @@ ISA_SET: AVX512BW_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 IMM0:r:b -IFORM: VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 +PATTERN: EVV 0x3C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 REG3=ZMM_B3():r:zi8 +IFORM: VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 } { -ICLASS: VPCMPUB +ICLASS: VPMAXSB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -55017,15 +59599,15 @@ ISA_SET: AVX512BW_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 IMM0:r:b -IFORM: VPCMPUB_MASKmskw_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 +PATTERN: EVV 0x3C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 MEM0:r:zd:i8 +IFORM: VPMAXSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 } -# EMITTING VPCMPUD (VPCMPUD-128-1) +# EMITTING VPMAXSD (VPMAXSD-128-1) { -ICLASS: VPCMPUD +ICLASS: VPMAXSD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -55033,13 +59615,13 @@ ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 IMM0:r:b -IFORM: VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 +PATTERN: EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 REG3=XMM_B3():r:dq:i32 +IFORM: VPMAXSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512 } { -ICLASS: VPCMPUD +ICLASS: VPMAXSD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -55047,15 +59629,15 @@ ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b -IFORM: VPCMPUD_MASKmskw_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 +PATTERN: EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPMAXSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512 } -# EMITTING VPCMPUD (VPCMPUD-256-1) +# EMITTING VPMAXSD (VPMAXSD-256-1) { -ICLASS: VPCMPUD +ICLASS: VPMAXSD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -55063,13 +59645,13 @@ ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 IMM0:r:b -IFORM: VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 +PATTERN: EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 REG3=YMM_B3():r:qq:i32 +IFORM: VPMAXSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512 } { -ICLASS: VPCMPUD +ICLASS: VPMAXSD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -55077,15 +59659,15 @@ ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b -IFORM: VPCMPUD_MASKmskw_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 +PATTERN: EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPMAXSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512 } -# EMITTING VPCMPUQ (VPCMPUQ-128-1) +# EMITTING VPMAXSQ (VPMAXSQ-128-1) { -ICLASS: VPCMPUQ +ICLASS: VPMAXSQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -55093,13 +59675,13 @@ ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 UIMM8() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 IMM0:r:b -IFORM: VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 +PATTERN: EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i64 REG3=XMM_B3():r:dq:i64 +IFORM: VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512 } { -ICLASS: VPCMPUQ +ICLASS: VPMAXSQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -55107,15 +59689,15 @@ ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b -IFORM: VPCMPUQ_MASKmskw_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 +PATTERN: EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i64 MEM0:r:vv:i64:TXT=BCASTSTR +IFORM: VPMAXSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512 } -# EMITTING VPCMPUQ (VPCMPUQ-256-1) +# EMITTING VPMAXSQ (VPMAXSQ-256-1) { -ICLASS: VPCMPUQ +ICLASS: VPMAXSQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -55123,13 +59705,13 @@ ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 UIMM8() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 IMM0:r:b -IFORM: VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 +PATTERN: EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i64 REG3=YMM_B3():r:qq:i64 +IFORM: VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512 } { -ICLASS: VPCMPUQ +ICLASS: VPMAXSQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -55137,15 +59719,15 @@ ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b -IFORM: VPCMPUQ_MASKmskw_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 +PATTERN: EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i64 MEM0:r:vv:i64:TXT=BCASTSTR +IFORM: VPMAXSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512 } -# EMITTING VPCMPUW (VPCMPUW-128-1) +# EMITTING VPMAXSW (VPMAXSW-128-1) { -ICLASS: VPCMPUW +ICLASS: VPMAXSW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -55153,13 +59735,13 @@ ISA_SET: AVX512BW_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 UIMM8() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 IMM0:r:b -IFORM: VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512 +PATTERN: EVV 0xEE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 +IFORM: VPMAXSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 } { -ICLASS: VPCMPUW +ICLASS: VPMAXSW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -55167,15 +59749,15 @@ ISA_SET: AVX512BW_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 IMM0:r:b -IFORM: VPCMPUW_MASKmskw_MASKmskw_XMMu16_MEMu16_IMM8_AVX512 +PATTERN: EVV 0xEE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 +IFORM: VPMAXSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 } -# EMITTING VPCMPUW (VPCMPUW-256-1) +# EMITTING VPMAXSW (VPMAXSW-256-1) { -ICLASS: VPCMPUW +ICLASS: VPMAXSW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -55183,13 +59765,13 @@ ISA_SET: AVX512BW_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 UIMM8() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 IMM0:r:b -IFORM: VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512 +PATTERN: EVV 0xEE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 +IFORM: VPMAXSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 } { -ICLASS: VPCMPUW +ICLASS: VPMAXSW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -55197,15 +59779,15 @@ ISA_SET: AVX512BW_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 IMM0:r:b -IFORM: VPCMPUW_MASKmskw_MASKmskw_YMMu16_MEMu16_IMM8_AVX512 +PATTERN: EVV 0xEE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 +IFORM: VPMAXSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 } -# EMITTING VPCMPUW (VPCMPUW-512-1) +# EMITTING VPMAXSW (VPMAXSW-512-1) { -ICLASS: VPCMPUW +ICLASS: VPMAXSW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -55213,13 +59795,13 @@ ISA_SET: AVX512BW_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 UIMM8() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 IMM0:r:b -IFORM: VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512 +PATTERN: EVV 0xEE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 +IFORM: VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 } { -ICLASS: VPCMPUW +ICLASS: VPMAXSW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -55227,15 +59809,15 @@ ISA_SET: AVX512BW_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 IMM0:r:b -IFORM: VPCMPUW_MASKmskw_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512 +PATTERN: EVV 0xEE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 +IFORM: VPMAXSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 } -# EMITTING VPCMPW (VPCMPW-128-1) +# EMITTING VPMAXUB (VPMAXUB-128-1) { -ICLASS: VPCMPW +ICLASS: VPMAXUB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -55243,13 +59825,13 @@ ISA_SET: AVX512BW_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 UIMM8() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 IMM0:r:b -IFORM: VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512 +PATTERN: EVV 0xDE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPMAXUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 } { -ICLASS: VPCMPW +ICLASS: VPMAXUB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -55257,15 +59839,15 @@ ISA_SET: AVX512BW_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 IMM0:r:b -IFORM: VPCMPW_MASKmskw_MASKmskw_XMMi16_MEMi16_IMM8_AVX512 +PATTERN: EVV 0xDE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPMAXUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 } -# EMITTING VPCMPW (VPCMPW-256-1) +# EMITTING VPMAXUB (VPMAXUB-256-1) { -ICLASS: VPCMPW +ICLASS: VPMAXUB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -55273,13 +59855,13 @@ ISA_SET: AVX512BW_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 UIMM8() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 IMM0:r:b -IFORM: VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512 +PATTERN: EVV 0xDE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPMAXUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 } { -ICLASS: VPCMPW +ICLASS: VPMAXUB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -55287,15 +59869,15 @@ ISA_SET: AVX512BW_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 IMM0:r:b -IFORM: VPCMPW_MASKmskw_MASKmskw_YMMi16_MEMi16_IMM8_AVX512 +PATTERN: EVV 0xDE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPMAXUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 } -# EMITTING VPCMPW (VPCMPW-512-1) +# EMITTING VPMAXUB (VPMAXUB-512-1) { -ICLASS: VPCMPW +ICLASS: VPMAXUB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -55303,13 +59885,13 @@ ISA_SET: AVX512BW_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 UIMM8() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 IMM0:r:b -IFORM: VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512 +PATTERN: EVV 0xDE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 } { -ICLASS: VPCMPW +ICLASS: VPMAXUB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -55317,3046 +59899,3277 @@ ISA_SET: AVX512BW_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 IMM0:r:b -IFORM: VPCMPW_MASKmskw_MASKmskw_ZMMi16_MEMi16_IMM8_AVX512 +PATTERN: EVV 0xDE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPMAXUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 } -# EMITTING VPCOMPRESSD (VPCOMPRESSD-128-1) +# EMITTING VPMAXUD (VPMAXUD-128-1) { -ICLASS: VPCOMPRESSD +ICLASS: VPMAXUD CPL: 3 -CATEGORY: COMPRESS +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() -OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32 -IFORM: VPCOMPRESSD_MEMu32_MASKmskw_XMMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPMAXUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 } - -# EMITTING VPCOMPRESSD (VPCOMPRESSD-128-2) { -ICLASS: VPCOMPRESSD +ICLASS: VPMAXUD CPL: 3 -CATEGORY: COMPRESS +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32 -IFORM: VPCOMPRESSD_XMMu32_MASKmskw_XMMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPMAXUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 } -# EMITTING VPCOMPRESSD (VPCOMPRESSD-256-1) +# EMITTING VPMAXUD (VPMAXUD-256-1) { -ICLASS: VPCOMPRESSD +ICLASS: VPMAXUD CPL: 3 -CATEGORY: COMPRESS +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() -OPERANDS: MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 -IFORM: VPCOMPRESSD_MEMu32_MASKmskw_YMMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPMAXUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 } - -# EMITTING VPCOMPRESSD (VPCOMPRESSD-256-2) { -ICLASS: VPCOMPRESSD +ICLASS: VPMAXUD CPL: 3 -CATEGORY: COMPRESS +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=YMM_B3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 -IFORM: VPCOMPRESSD_YMMu32_MASKmskw_YMMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPMAXUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 } -# EMITTING VPCOMPRESSQ (VPCOMPRESSQ-128-1) +# EMITTING VPMAXUQ (VPMAXUQ-128-1) { -ICLASS: VPCOMPRESSQ +ICLASS: VPMAXUQ CPL: 3 -CATEGORY: COMPRESS +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() -OPERANDS: MEM0:w:dq:u64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 -IFORM: VPCOMPRESSQ_MEMu64_MASKmskw_XMMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 } - -# EMITTING VPCOMPRESSQ (VPCOMPRESSQ-128-2) { -ICLASS: VPCOMPRESSQ +ICLASS: VPMAXUQ CPL: 3 -CATEGORY: COMPRESS +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 -IFORM: VPCOMPRESSQ_XMMu64_MASKmskw_XMMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMAXUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 } -# EMITTING VPCOMPRESSQ (VPCOMPRESSQ-256-1) +# EMITTING VPMAXUQ (VPMAXUQ-256-1) { -ICLASS: VPCOMPRESSQ +ICLASS: VPMAXUQ CPL: 3 -CATEGORY: COMPRESS +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() -OPERANDS: MEM0:w:qq:u64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 -IFORM: VPCOMPRESSQ_MEMu64_MASKmskw_YMMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 } - -# EMITTING VPCOMPRESSQ (VPCOMPRESSQ-256-2) { -ICLASS: VPCOMPRESSQ +ICLASS: VPMAXUQ CPL: 3 -CATEGORY: COMPRESS +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMAXUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPMAXUW (VPMAXUW-128-1) +{ +ICLASS: VPMAXUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR -OPERANDS: REG0=YMM_B3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 -IFORM: VPCOMPRESSQ_YMMu64_MASKmskw_YMMu64_AVX512 +PATTERN: EVV 0x3E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPMAXUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPMAXUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPMAXUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 } -# EMITTING VPCONFLICTD (VPCONFLICTD-128-1) +# EMITTING VPMAXUW (VPMAXUW-256-1) { -ICLASS: VPCONFLICTD +ICLASS: VPMAXUW CPL: 3 -CATEGORY: CONFLICT +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512CD_128 +ISA_SET: AVX512BW_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 -IFORM: VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512 +PATTERN: EVV 0x3E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPMAXUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 } { -ICLASS: VPCONFLICTD +ICLASS: VPMAXUW CPL: 3 -CATEGORY: CONFLICT +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512CD_128 +ISA_SET: AVX512BW_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPCONFLICTD_XMMu32_MASKmskw_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPMAXUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 } -# EMITTING VPCONFLICTD (VPCONFLICTD-256-1) +# EMITTING VPMAXUW (VPMAXUW-512-1) { -ICLASS: VPCONFLICTD +ICLASS: VPMAXUW CPL: 3 -CATEGORY: CONFLICT +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512CD_256 +ISA_SET: AVX512BW_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 -IFORM: VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512 +PATTERN: EVV 0x3E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 } { -ICLASS: VPCONFLICTD +ICLASS: VPMAXUW CPL: 3 -CATEGORY: CONFLICT +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512CD_256 +ISA_SET: AVX512BW_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPCONFLICTD_YMMu32_MASKmskw_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPMAXUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 } -# EMITTING VPCONFLICTQ (VPCONFLICTQ-128-1) +# EMITTING VPMINSB (VPMINSB-128-1) { -ICLASS: VPCONFLICTQ +ICLASS: VPMINSB CPL: 3 -CATEGORY: CONFLICT +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512CD_128 +ISA_SET: AVX512BW_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 -IFORM: VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512 +PATTERN: EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 REG3=XMM_B3():r:dq:i8 +IFORM: VPMINSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 } { -ICLASS: VPCONFLICTQ +ICLASS: VPMINSB CPL: 3 -CATEGORY: CONFLICT +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512CD_128 +ISA_SET: AVX512BW_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPCONFLICTQ_XMMu64_MASKmskw_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 MEM0:r:dq:i8 +IFORM: VPMINSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 } -# EMITTING VPCONFLICTQ (VPCONFLICTQ-256-1) +# EMITTING VPMINSB (VPMINSB-256-1) { -ICLASS: VPCONFLICTQ +ICLASS: VPMINSB CPL: 3 -CATEGORY: CONFLICT +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512CD_256 +ISA_SET: AVX512BW_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 -IFORM: VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512 +PATTERN: EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 REG3=YMM_B3():r:qq:i8 +IFORM: VPMINSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 } { -ICLASS: VPCONFLICTQ +ICLASS: VPMINSB CPL: 3 -CATEGORY: CONFLICT +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512CD_256 +ISA_SET: AVX512BW_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPCONFLICTQ_YMMu64_MASKmskw_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 MEM0:r:qq:i8 +IFORM: VPMINSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 } -# EMITTING VPERMD (VPERMD-256-1) +# EMITTING VPMINSB (VPMINSB-512-1) { -ICLASS: VPERMD +ICLASS: VPMINSB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x36 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 -IFORM: VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +PATTERN: EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 REG3=ZMM_B3():r:zi8 +IFORM: VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 } { -ICLASS: VPERMD +ICLASS: VPMINSB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x36 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPERMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 MEM0:r:zd:i8 +IFORM: VPMINSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 } -# EMITTING VPERMI2D (VPERMI2D-128-1) +# EMITTING VPMINSD (VPMINSD-128-1) { -ICLASS: VPERMI2D +ICLASS: VPMINSD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 -IFORM: VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +PATTERN: EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 REG3=XMM_B3():r:dq:i32 +IFORM: VPMINSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512 } { -ICLASS: VPERMI2D +ICLASS: VPMINSD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPERMI2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPMINSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512 } -# EMITTING VPERMI2D (VPERMI2D-256-1) +# EMITTING VPMINSD (VPMINSD-256-1) { -ICLASS: VPERMI2D +ICLASS: VPMINSD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 -IFORM: VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +PATTERN: EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 REG3=YMM_B3():r:qq:i32 +IFORM: VPMINSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512 } { -ICLASS: VPERMI2D +ICLASS: VPMINSD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPERMI2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPMINSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512 } -# EMITTING VPERMI2PD (VPERMI2PD-128-1) +# EMITTING VPMINSQ (VPMINSQ-128-1) { -ICLASS: VPERMI2PD +ICLASS: VPMINSQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +PATTERN: EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i64 REG3=XMM_B3():r:dq:i64 +IFORM: VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512 } { -ICLASS: VPERMI2PD +ICLASS: VPMINSQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VPERMI2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i64 MEM0:r:vv:i64:TXT=BCASTSTR +IFORM: VPMINSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512 } -# EMITTING VPERMI2PD (VPERMI2PD-256-1) +# EMITTING VPMINSQ (VPMINSQ-256-1) { -ICLASS: VPERMI2PD +ICLASS: VPMINSQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 -IFORM: VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +PATTERN: EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i64 REG3=YMM_B3():r:qq:i64 +IFORM: VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512 +} + +{ +ICLASS: VPMINSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i64 MEM0:r:vv:i64:TXT=BCASTSTR +IFORM: VPMINSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512 +} + + +# EMITTING VPMINSW (VPMINSW-128-1) +{ +ICLASS: VPMINSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 +IFORM: VPMINSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 } { -ICLASS: VPERMI2PD +ICLASS: VPMINSW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VPERMI2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xEA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 +IFORM: VPMINSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 } -# EMITTING VPERMI2PS (VPERMI2PS-128-1) +# EMITTING VPMINSW (VPMINSW-256-1) { -ICLASS: VPERMI2PS +ICLASS: VPMINSW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +PATTERN: EVV 0xEA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 +IFORM: VPMINSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 } { -ICLASS: VPERMI2PS +ICLASS: VPMINSW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VPERMI2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xEA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 +IFORM: VPMINSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 } -# EMITTING VPERMI2PS (VPERMI2PS-256-1) +# EMITTING VPMINSW (VPMINSW-512-1) { -ICLASS: VPERMI2PS +ICLASS: VPMINSW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 -IFORM: VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +PATTERN: EVV 0xEA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 +IFORM: VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 } { -ICLASS: VPERMI2PS +ICLASS: VPMINSW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VPERMI2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xEA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 +IFORM: VPMINSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 } -# EMITTING VPERMI2Q (VPERMI2Q-128-1) +# EMITTING VPMINUB (VPMINUB-128-1) { -ICLASS: VPERMI2Q +ICLASS: VPMINUB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 -IFORM: VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +PATTERN: EVV 0xDA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPMINUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 } { -ICLASS: VPERMI2Q +ICLASS: VPMINUB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPERMI2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xDA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPMINUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 } -# EMITTING VPERMI2Q (VPERMI2Q-256-1) +# EMITTING VPMINUB (VPMINUB-256-1) { -ICLASS: VPERMI2Q +ICLASS: VPMINUB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 -IFORM: VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +PATTERN: EVV 0xDA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPMINUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 } { -ICLASS: VPERMI2Q +ICLASS: VPMINUB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPERMI2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xDA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPMINUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 } -# EMITTING VPERMI2W (VPERMI2W-128-1) +# EMITTING VPMINUB (VPMINUB-512-1) { -ICLASS: VPERMI2W +ICLASS: VPMINUB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 -IFORM: VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +PATTERN: EVV 0xDA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 } { -ICLASS: VPERMI2W +ICLASS: VPMINUB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 -IFORM: VPERMI2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xDA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPMINUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 } -# EMITTING VPERMI2W (VPERMI2W-256-1) +# EMITTING VPMINUD (VPMINUD-128-1) { -ICLASS: VPERMI2W +ICLASS: VPMINUD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 -IFORM: VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +PATTERN: EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPMINUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 } { -ICLASS: VPERMI2W +ICLASS: VPMINUD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 -IFORM: VPERMI2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPMINUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 } -# EMITTING VPERMI2W (VPERMI2W-512-1) +# EMITTING VPMINUD (VPMINUD-256-1) { -ICLASS: VPERMI2W +ICLASS: VPMINUD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 -IFORM: VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +PATTERN: EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPMINUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 } { -ICLASS: VPERMI2W +ICLASS: VPMINUD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 -IFORM: VPERMI2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPMINUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 } -# EMITTING VPERMILPD (VPERMILPD-128-1) +# EMITTING VPMINUQ (VPMINUQ-128-1) { -ICLASS: VPERMILPD +ICLASS: VPMINUQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x05 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR UIMM8() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 IMM0:r:b -IFORM: VPERMILPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 +PATTERN: EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 } { -ICLASS: VPERMILPD +ICLASS: VPMINUQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x05 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b -IFORM: VPERMILPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMINUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 } -# EMITTING VPERMILPD (VPERMILPD-128-2) +# EMITTING VPMINUQ (VPMINUQ-256-1) { -ICLASS: VPERMILPD +ICLASS: VPMINUQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x0D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VPERMILPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +PATTERN: EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 } { -ICLASS: VPERMILPD +ICLASS: VPMINUQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x0D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VPERMILPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMINUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 } -# EMITTING VPERMILPD (VPERMILPD-256-1) +# EMITTING VPMINUW (VPMINUW-128-1) { -ICLASS: VPERMILPD +ICLASS: VPMINUW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x05 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 IMM0:r:b -IFORM: VPERMILPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 +PATTERN: EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPMINUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 } { -ICLASS: VPERMILPD +ICLASS: VPMINUW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x05 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b -IFORM: VPERMILPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPMINUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 } -# EMITTING VPERMILPD (VPERMILPD-256-2) +# EMITTING VPMINUW (VPMINUW-256-1) { -ICLASS: VPERMILPD +ICLASS: VPMINUW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x0D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 -IFORM: VPERMILPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +PATTERN: EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPMINUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 } { -ICLASS: VPERMILPD +ICLASS: VPMINUW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x0D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VPERMILPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPMINUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 } -# EMITTING VPERMILPS (VPERMILPS-128-1) +# EMITTING VPMINUW (VPMINUW-512-1) { -ICLASS: VPERMILPS +ICLASS: VPMINUW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x04 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 IMM0:r:b -IFORM: VPERMILPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 +PATTERN: EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 } { -ICLASS: VPERMILPS +ICLASS: VPMINUW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x04 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b -IFORM: VPERMILPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPMINUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 } -# EMITTING VPERMILPS (VPERMILPS-128-2) +# EMITTING VPMOVB2M (VPMOVB2M-128-1) { -ICLASS: VPERMILPS +ICLASS: VPMOVB2M CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E7NM REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x0C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VPERMILPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +PATTERN: EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=XMM_B3():r:dq:u8 +IFORM: VPMOVB2M_MASKmskw_XMMu8_AVX512 } + +# EMITTING VPMOVB2M (VPMOVB2M-256-1) { -ICLASS: VPERMILPS +ICLASS: VPMOVB2M CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E7NM REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x0C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VPERMILPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +PATTERN: EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=YMM_B3():r:qq:u8 +IFORM: VPMOVB2M_MASKmskw_YMMu8_AVX512 } -# EMITTING VPERMILPS (VPERMILPS-256-1) +# EMITTING VPMOVB2M (VPMOVB2M-512-1) { -ICLASS: VPERMILPS +ICLASS: VPMOVB2M CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E7NM REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x04 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 IMM0:r:b -IFORM: VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 +PATTERN: EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=ZMM_B3():r:zu8 +IFORM: VPMOVB2M_MASKmskw_ZMMu8_AVX512 } + +# EMITTING VPMOVD2M (VPMOVD2M-128-1) { -ICLASS: VPERMILPS +ICLASS: VPMOVD2M CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E7NM REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x04 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b -IFORM: VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 +PATTERN: EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=XMM_B3():r:dq:u32 +IFORM: VPMOVD2M_MASKmskw_XMMu32_AVX512 } -# EMITTING VPERMILPS (VPERMILPS-256-2) +# EMITTING VPMOVD2M (VPMOVD2M-256-1) { -ICLASS: VPERMILPS +ICLASS: VPMOVD2M CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E7NM REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x0C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 -IFORM: VPERMILPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +PATTERN: EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=YMM_B3():r:qq:u32 +IFORM: VPMOVD2M_MASKmskw_YMMu32_AVX512 } + +# EMITTING VPMOVD2M (VPMOVD2M-512-1) { -ICLASS: VPERMILPS +ICLASS: VPMOVD2M CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E7NM REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x0C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VPERMILPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +PATTERN: EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=ZMM_B3():r:zu32 +IFORM: VPMOVD2M_MASKmskw_ZMMu32_AVX512 } -# EMITTING VPERMPD (VPERMPD-256-1) +# EMITTING VPMOVDB (VPMOVDB-128-1) { -ICLASS: VPERMPD +ICLASS: VPMOVDB CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x01 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 IMM0:r:b -IFORM: VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 +PATTERN: EVV 0x31 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32 +IFORM: VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512 } + +# EMITTING VPMOVDB (VPMOVDB-128-2) { -ICLASS: VPERMPD +ICLASS: VPMOVDB CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x01 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b -IFORM: VPERMPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x31 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:d:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32 +IFORM: VPMOVDB_MEMu8_MASKmskw_XMMu32_AVX512 } -# EMITTING VPERMPD (VPERMPD-256-2) +# EMITTING VPMOVDB (VPMOVDB-256-1) { -ICLASS: VPERMPD +ICLASS: VPMOVDB CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x16 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 -IFORM: VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +PATTERN: EVV 0x31 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 +IFORM: VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512 +} + + +# EMITTING VPMOVDB (VPMOVDB-256-2) +{ +ICLASS: VPMOVDB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x31 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 +IFORM: VPMOVDB_MEMu8_MASKmskw_YMMu32_AVX512 } + +# EMITTING VPMOVDW (VPMOVDW-128-1) { -ICLASS: VPERMPD +ICLASS: VPMOVDW CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x16 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VPERMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x33 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32 +IFORM: VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512 } -# EMITTING VPERMPS (VPERMPS-256-1) +# EMITTING VPMOVDW (VPMOVDW-128-2) { -ICLASS: VPERMPS +ICLASS: VPMOVDW CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x16 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 -IFORM: VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x33 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:q:u16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32 +IFORM: VPMOVDW_MEMu16_MASKmskw_XMMu32_AVX512 } + +# EMITTING VPMOVDW (VPMOVDW-256-1) { -ICLASS: VPERMPS +ICLASS: VPMOVDW CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x16 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VPERMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x33 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 +IFORM: VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512 } -# EMITTING VPERMQ (VPERMQ-256-1) +# EMITTING VPMOVDW (VPMOVDW-256-2) { -ICLASS: VPERMQ +ICLASS: VPMOVDW CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x00 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b -IFORM: VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x33 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:dq:u16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 +IFORM: VPMOVDW_MEMu16_MASKmskw_YMMu32_AVX512 } + +# EMITTING VPMOVM2B (VPMOVM2B-128-1) { -ICLASS: VPERMQ +ICLASS: VPMOVM2B CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E7NM REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x00 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b -IFORM: VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 +PATTERN: EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK_B():r:mskw +IFORM: VPMOVM2B_XMMu8_MASKmskw_AVX512 } -# EMITTING VPERMQ (VPERMQ-256-2) +# EMITTING VPMOVM2B (VPMOVM2B-256-1) { -ICLASS: VPERMQ +ICLASS: VPMOVM2B CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E7NM REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x36 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 -IFORM: VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +PATTERN: EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK_B():r:mskw +IFORM: VPMOVM2B_YMMu8_MASKmskw_AVX512 } + +# EMITTING VPMOVM2B (VPMOVM2B-512-1) { -ICLASS: VPERMQ +ICLASS: VPMOVM2B CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E7NM REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x36 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPERMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +PATTERN: EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK_B():r:mskw +IFORM: VPMOVM2B_ZMMu8_MASKmskw_AVX512 } -# EMITTING VPERMT2D (VPERMT2D-128-1) +# EMITTING VPMOVM2D (VPMOVM2D-128-1) { -ICLASS: VPERMT2D +ICLASS: VPMOVM2D CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E7NM REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 -IFORM: VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +PATTERN: EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK_B():r:mskw +IFORM: VPMOVM2D_XMMu32_MASKmskw_AVX512 } + +# EMITTING VPMOVM2D (VPMOVM2D-256-1) { -ICLASS: VPERMT2D +ICLASS: VPMOVM2D CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E7NM REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPERMT2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +PATTERN: EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK_B():r:mskw +IFORM: VPMOVM2D_YMMu32_MASKmskw_AVX512 } -# EMITTING VPERMT2D (VPERMT2D-256-1) +# EMITTING VPMOVM2D (VPMOVM2D-512-1) { -ICLASS: VPERMT2D +ICLASS: VPMOVM2D CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E7NM REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 -IFORM: VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +PATTERN: EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK_B():r:mskw +IFORM: VPMOVM2D_ZMMu32_MASKmskw_AVX512 } + +# EMITTING VPMOVM2Q (VPMOVM2Q-128-1) { -ICLASS: VPERMT2D +ICLASS: VPMOVM2Q CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E7NM REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPERMT2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +PATTERN: EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK_B():r:mskw +IFORM: VPMOVM2Q_XMMu64_MASKmskw_AVX512 } -# EMITTING VPERMT2PD (VPERMT2PD-128-1) +# EMITTING VPMOVM2Q (VPMOVM2Q-256-1) { -ICLASS: VPERMT2PD +ICLASS: VPMOVM2Q CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E7NM REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +PATTERN: EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK_B():r:mskw +IFORM: VPMOVM2Q_YMMu64_MASKmskw_AVX512 } + +# EMITTING VPMOVM2Q (VPMOVM2Q-512-1) { -ICLASS: VPERMT2PD +ICLASS: VPMOVM2Q CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E7NM REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VPERMT2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +PATTERN: EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK_B():r:mskw +IFORM: VPMOVM2Q_ZMMu64_MASKmskw_AVX512 } -# EMITTING VPERMT2PD (VPERMT2PD-256-1) +# EMITTING VPMOVM2W (VPMOVM2W-128-1) { -ICLASS: VPERMT2PD +ICLASS: VPMOVM2W CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E7NM REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 -IFORM: VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +PATTERN: EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK_B():r:mskw +IFORM: VPMOVM2W_XMMu16_MASKmskw_AVX512 } + +# EMITTING VPMOVM2W (VPMOVM2W-256-1) { -ICLASS: VPERMT2PD +ICLASS: VPMOVM2W CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E7NM REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VPERMT2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +PATTERN: EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK_B():r:mskw +IFORM: VPMOVM2W_YMMu16_MASKmskw_AVX512 } -# EMITTING VPERMT2PS (VPERMT2PS-128-1) +# EMITTING VPMOVM2W (VPMOVM2W-512-1) { -ICLASS: VPERMT2PS +ICLASS: VPMOVM2W CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E7NM REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +PATTERN: EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK_B():r:mskw +IFORM: VPMOVM2W_ZMMu16_MASKmskw_AVX512 } + +# EMITTING VPMOVQ2M (VPMOVQ2M-128-1) { -ICLASS: VPERMT2PS +ICLASS: VPMOVQ2M CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E7NM REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VPERMT2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +PATTERN: EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=XMM_B3():r:dq:u64 +IFORM: VPMOVQ2M_MASKmskw_XMMu64_AVX512 } -# EMITTING VPERMT2PS (VPERMT2PS-256-1) +# EMITTING VPMOVQ2M (VPMOVQ2M-256-1) { -ICLASS: VPERMT2PS +ICLASS: VPMOVQ2M CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E7NM REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 -IFORM: VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +PATTERN: EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=YMM_B3():r:qq:u64 +IFORM: VPMOVQ2M_MASKmskw_YMMu64_AVX512 } + +# EMITTING VPMOVQ2M (VPMOVQ2M-512-1) { -ICLASS: VPERMT2PS +ICLASS: VPMOVQ2M CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E7NM REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VPERMT2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +PATTERN: EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=ZMM_B3():r:zu64 +IFORM: VPMOVQ2M_MASKmskw_ZMMu64_AVX512 } -# EMITTING VPERMT2Q (VPERMT2Q-128-1) +# EMITTING VPMOVQB (VPMOVQB-128-1) { -ICLASS: VPERMT2Q +ICLASS: VPMOVQB CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 -IFORM: VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +PATTERN: EVV 0x32 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 +IFORM: VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512 } + +# EMITTING VPMOVQB (VPMOVQB-128-2) { -ICLASS: VPERMT2Q +ICLASS: VPMOVQB CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPERMT2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x32 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: MEM0:w:wrd:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 +IFORM: VPMOVQB_MEMu8_MASKmskw_XMMu64_AVX512 } -# EMITTING VPERMT2Q (VPERMT2Q-256-1) +# EMITTING VPMOVQB (VPMOVQB-256-1) { -ICLASS: VPERMT2Q +ICLASS: VPMOVQB CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 -IFORM: VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +PATTERN: EVV 0x32 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 +IFORM: VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512 } + +# EMITTING VPMOVQB (VPMOVQB-256-2) { -ICLASS: VPERMT2Q +ICLASS: VPMOVQB CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPERMT2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x32 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: MEM0:w:d:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 +IFORM: VPMOVQB_MEMu8_MASKmskw_YMMu64_AVX512 } -# EMITTING VPERMT2W (VPERMT2W-128-1) +# EMITTING VPMOVQD (VPMOVQD-128-1) { -ICLASS: VPERMT2W +ICLASS: VPMOVQD CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 -IFORM: VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +PATTERN: EVV 0x35 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 +IFORM: VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512 } + +# EMITTING VPMOVQD (VPMOVQD-128-2) { -ICLASS: VPERMT2W +ICLASS: VPMOVQD CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 -IFORM: VPERMT2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x35 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:q:u32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 +IFORM: VPMOVQD_MEMu32_MASKmskw_XMMu64_AVX512 } -# EMITTING VPERMT2W (VPERMT2W-256-1) +# EMITTING VPMOVQD (VPMOVQD-256-1) { -ICLASS: VPERMT2W +ICLASS: VPMOVQD CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 -IFORM: VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +PATTERN: EVV 0x35 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 +IFORM: VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512 } + +# EMITTING VPMOVQD (VPMOVQD-256-2) { -ICLASS: VPERMT2W +ICLASS: VPMOVQD CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 -IFORM: VPERMT2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x35 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 +IFORM: VPMOVQD_MEMu32_MASKmskw_YMMu64_AVX512 } -# EMITTING VPERMT2W (VPERMT2W-512-1) +# EMITTING VPMOVQW (VPMOVQW-128-1) { -ICLASS: VPERMT2W +ICLASS: VPMOVQW CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 -IFORM: VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +PATTERN: EVV 0x34 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 +IFORM: VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512 } + +# EMITTING VPMOVQW (VPMOVQW-128-2) { -ICLASS: VPERMT2W +ICLASS: VPMOVQW CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 -IFORM: VPERMT2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x34 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:d:u16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 +IFORM: VPMOVQW_MEMu16_MASKmskw_XMMu64_AVX512 } -# EMITTING VPERMW (VPERMW-128-1) +# EMITTING VPMOVQW (VPMOVQW-256-1) { -ICLASS: VPERMW +ICLASS: VPMOVQW CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 -IFORM: VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +PATTERN: EVV 0x34 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 +IFORM: VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VPMOVQW (VPMOVQW-256-2) +{ +ICLASS: VPMOVQW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x34 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:q:u16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 +IFORM: VPMOVQW_MEMu16_MASKmskw_YMMu64_AVX512 } + +# EMITTING VPMOVSDB (VPMOVSDB-128-1) { -ICLASS: VPERMW +ICLASS: VPMOVSDB CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 -IFORM: VPERMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x21 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:i32 +IFORM: VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512 } -# EMITTING VPERMW (VPERMW-256-1) +# EMITTING VPMOVSDB (VPMOVSDB-128-2) { -ICLASS: VPERMW +ICLASS: VPMOVSDB CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 -IFORM: VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x21 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:d:i8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:i32 +IFORM: VPMOVSDB_MEMi8_MASKmskw_XMMi32_AVX512 } + +# EMITTING VPMOVSDB (VPMOVSDB-256-1) { -ICLASS: VPERMW +ICLASS: VPMOVSDB CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 -IFORM: VPERMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x21 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:i32 +IFORM: VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512 } -# EMITTING VPERMW (VPERMW-512-1) +# EMITTING VPMOVSDB (VPMOVSDB-256-2) { -ICLASS: VPERMW +ICLASS: VPMOVSDB CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 -IFORM: VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x21 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:q:i8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:i32 +IFORM: VPMOVSDB_MEMi8_MASKmskw_YMMi32_AVX512 } + +# EMITTING VPMOVSDW (VPMOVSDW-128-1) { -ICLASS: VPERMW +ICLASS: VPMOVSDW CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 -IFORM: VPERMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x23 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:i32 +IFORM: VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512 } -# EMITTING VPEXPANDD (VPEXPANDD-128-1) +# EMITTING VPMOVSDW (VPMOVSDW-128-2) { -ICLASS: VPEXPANDD +ICLASS: VPMOVSDW CPL: 3 -CATEGORY: EXPAND +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT() -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u32 -IFORM: VPEXPANDD_XMMu32_MASKmskw_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x23 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:q:i16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:i32 +IFORM: VPMOVSDW_MEMi16_MASKmskw_XMMi32_AVX512 } -# EMITTING VPEXPANDD (VPEXPANDD-128-2) +# EMITTING VPMOVSDW (VPMOVSDW-256-1) { -ICLASS: VPEXPANDD +ICLASS: VPMOVSDW CPL: 3 -CATEGORY: EXPAND +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 -IFORM: VPEXPANDD_XMMu32_MASKmskw_XMMu32_AVX512 +PATTERN: EVV 0x23 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:i32 +IFORM: VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512 } -# EMITTING VPEXPANDD (VPEXPANDD-256-1) +# EMITTING VPMOVSDW (VPMOVSDW-256-2) { -ICLASS: VPEXPANDD +ICLASS: VPMOVSDW CPL: 3 -CATEGORY: EXPAND +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT() -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u32 -IFORM: VPEXPANDD_YMMu32_MASKmskw_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x23 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:dq:i16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:i32 +IFORM: VPMOVSDW_MEMi16_MASKmskw_YMMi32_AVX512 } -# EMITTING VPEXPANDD (VPEXPANDD-256-2) +# EMITTING VPMOVSQB (VPMOVSQB-128-1) { -ICLASS: VPEXPANDD +ICLASS: VPMOVSQB CPL: 3 -CATEGORY: EXPAND +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 -IFORM: VPEXPANDD_YMMu32_MASKmskw_YMMu32_AVX512 +PATTERN: EVV 0x22 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:i64 +IFORM: VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512 } -# EMITTING VPEXPANDQ (VPEXPANDQ-128-1) +# EMITTING VPMOVSQB (VPMOVSQB-128-2) { -ICLASS: VPEXPANDQ +ICLASS: VPMOVSQB CPL: 3 -CATEGORY: EXPAND +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT() -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u64 -IFORM: VPEXPANDQ_XMMu64_MASKmskw_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x22 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: MEM0:w:wrd:i8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:i64 +IFORM: VPMOVSQB_MEMi8_MASKmskw_XMMi64_AVX512 } -# EMITTING VPEXPANDQ (VPEXPANDQ-128-2) +# EMITTING VPMOVSQB (VPMOVSQB-256-1) { -ICLASS: VPEXPANDQ +ICLASS: VPMOVSQB CPL: 3 -CATEGORY: EXPAND +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 -IFORM: VPEXPANDQ_XMMu64_MASKmskw_XMMu64_AVX512 +PATTERN: EVV 0x22 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:i64 +IFORM: VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512 } -# EMITTING VPEXPANDQ (VPEXPANDQ-256-1) +# EMITTING VPMOVSQB (VPMOVSQB-256-2) { -ICLASS: VPEXPANDQ +ICLASS: VPMOVSQB CPL: 3 -CATEGORY: EXPAND +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT() -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u64 -IFORM: VPEXPANDQ_YMMu64_MASKmskw_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x22 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: MEM0:w:d:i8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:i64 +IFORM: VPMOVSQB_MEMi8_MASKmskw_YMMi64_AVX512 } -# EMITTING VPEXPANDQ (VPEXPANDQ-256-2) +# EMITTING VPMOVSQD (VPMOVSQD-128-1) { -ICLASS: VPEXPANDQ +ICLASS: VPMOVSQD CPL: 3 -CATEGORY: EXPAND +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 -IFORM: VPEXPANDQ_YMMu64_MASKmskw_YMMu64_AVX512 +PATTERN: EVV 0x25 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:i64 +IFORM: VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512 } -# EMITTING VPEXTRB (VPEXTRB-128-1) +# EMITTING VPMOVSQD (VPMOVSQD-128-2) { -ICLASS: VPEXTRB +ICLASS: VPMOVSQD CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128N -EXCEPTIONS: AVX512-E9NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -PATTERN: EVV 0x14 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() -OPERANDS: REG0=GPR32_B():w:d:u8 REG1=XMM_R3():r:dq:u8 IMM0:r:b -IFORM: VPEXTRB_GPR32u8_XMMu8_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x25 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:q:i32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:i64 +IFORM: VPMOVSQD_MEMi32_MASKmskw_XMMi64_AVX512 } + +# EMITTING VPMOVSQD (VPMOVSQD-256-1) { -ICLASS: VPEXTRB +ICLASS: VPMOVSQD CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128N -EXCEPTIONS: AVX512-E9NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: DISP8_GPR_WRITER_STORE_BYTE -PATTERN: EVV 0x14 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_GPR_WRITER_STORE_BYTE() -OPERANDS: MEM0:w:b:u8 REG0=XMM_R3():r:dq:u8 IMM0:r:b -IFORM: VPEXTRB_MEMu8_XMMu8_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x25 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:i64 +IFORM: VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512 } -# EMITTING VPEXTRD (VPEXTRD-128-1) +# EMITTING VPMOVSQD (VPMOVSQD-256-2) { -ICLASS: VPEXTRD +ICLASS: VPMOVSQD CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128N -EXCEPTIONS: AVX512-E9NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -PATTERN: EVV 0x16 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0 UIMM8() -OPERANDS: REG0=GPR32_B():w:d:u32 REG1=XMM_R3():r:dq:u32 IMM0:r:b -IFORM: VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x25 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:dq:i32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:i64 +IFORM: VPMOVSQD_MEMi32_MASKmskw_YMMi64_AVX512 } + +# EMITTING VPMOVSQW (VPMOVSQW-128-1) { -ICLASS: VPEXTRD +ICLASS: VPMOVSQW CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128N -EXCEPTIONS: AVX512-E9NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: DISP8_GPR_WRITER_STORE -PATTERN: EVV 0x16 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_WRITER_STORE() -OPERANDS: MEM0:w:d:u32 REG0=XMM_R3():r:dq:u32 IMM0:r:b -IFORM: VPEXTRD_MEMu32_XMMu32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x24 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:i64 +IFORM: VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512 } -# EMITTING VPEXTRQ (VPEXTRQ-128-1) +# EMITTING VPMOVSQW (VPMOVSQW-128-2) { -ICLASS: VPEXTRQ +ICLASS: VPMOVSQW CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128N -EXCEPTIONS: AVX512-E9NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -PATTERN: EVV 0x16 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 UIMM8() -OPERANDS: REG0=GPR64_B():w:q:u64 REG1=XMM_R3():r:dq:u64 IMM0:r:b -IFORM: VPEXTRQ_GPR64u64_XMMu64_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x24 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:d:i16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:i64 +IFORM: VPMOVSQW_MEMi16_MASKmskw_XMMi64_AVX512 } + +# EMITTING VPMOVSQW (VPMOVSQW-256-1) { -ICLASS: VPEXTRQ +ICLASS: VPMOVSQW CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128N -EXCEPTIONS: AVX512-E9NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: DISP8_GPR_WRITER_STORE -PATTERN: EVV 0x16 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_64_BITS() NELEM_GPR_WRITER_STORE() -OPERANDS: MEM0:w:q:u64 REG0=XMM_R3():r:dq:u64 IMM0:r:b -IFORM: VPEXTRQ_MEMu64_XMMu64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x24 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:i64 +IFORM: VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512 } -# EMITTING VPEXTRW (VPEXTRW-128-1) +# EMITTING VPMOVSQW (VPMOVSQW-256-2) { -ICLASS: VPEXTRW +ICLASS: VPMOVSQW CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128N -EXCEPTIONS: AVX512-E9NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -PATTERN: EVV 0x15 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() -OPERANDS: REG0=GPR32_B():w:d:u16 REG1=XMM_R3():r:dq:u16 IMM0:r:b -IFORM: VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x24 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:q:i16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:i64 +IFORM: VPMOVSQW_MEMi16_MASKmskw_YMMi64_AVX512 } + +# EMITTING VPMOVSWB (VPMOVSWB-128-1) { -ICLASS: VPEXTRW +ICLASS: VPMOVSWB CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128N -EXCEPTIONS: AVX512-E9NF +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: DISP8_GPR_WRITER_STORE_WORD -PATTERN: EVV 0x15 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_16_BITS() NELEM_GPR_WRITER_STORE_WORD() -OPERANDS: MEM0:w:wrd:u16 REG0=XMM_R3():r:dq:u16 IMM0:r:b -IFORM: VPEXTRW_MEMu16_XMMu16_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x20 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:i16 +IFORM: VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512 } -# EMITTING VPEXTRW (VPEXTRW-128-2) +# EMITTING VPMOVSWB (VPMOVSWB-128-2) { -ICLASS: VPEXTRW +ICLASS: VPMOVSWB CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128N -EXCEPTIONS: AVX512-E9NF +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -PATTERN: EVV 0xC5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() -OPERANDS: REG0=GPR32_R():w:d:u16 REG1=XMM_B3():r:dq:u16 IMM0:r:b -IFORM: VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x20 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:q:i8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:i16 +IFORM: VPMOVSWB_MEMi8_MASKmskw_XMMi16_AVX512 } -# EMITTING VPGATHERDD (VPGATHERDD-128-1) +# EMITTING VPMOVSWB (VPMOVSWB-256-1) { -ICLASS: VPGATHERDD +ICLASS: VPMOVSWB CPL: 3 -CATEGORY: GATHER +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E12 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W0 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASKNOT0():rw:mskw MEM0:r:dq:u32 -IFORM: VPGATHERDD_XMMu32_MASKmskw_MEMu32_AVX512_VL128 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x20 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:i16 +IFORM: VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512 } -# EMITTING VPGATHERDD (VPGATHERDD-256-1) +# EMITTING VPMOVSWB (VPMOVSWB-256-2) { -ICLASS: VPGATHERDD +ICLASS: VPMOVSWB CPL: 3 -CATEGORY: GATHER +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E12 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W0 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASKNOT0():rw:mskw MEM0:r:qq:u32 -IFORM: VPGATHERDD_YMMu32_MASKmskw_MEMu32_AVX512_VL256 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x20 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:dq:i8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:i16 +IFORM: VPMOVSWB_MEMi8_MASKmskw_YMMi16_AVX512 } -# EMITTING VPGATHERDQ (VPGATHERDQ-128-1) +# EMITTING VPMOVSWB (VPMOVSWB-512-1) { -ICLASS: VPGATHERDQ +ICLASS: VPMOVSWB CPL: 3 -CATEGORY: GATHER +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E12 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W1 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASKNOT0():rw:mskw MEM0:r:dq:u64 -IFORM: VPGATHERDQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x20 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zi16 +IFORM: VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512 } -# EMITTING VPGATHERDQ (VPGATHERDQ-256-1) +# EMITTING VPMOVSWB (VPMOVSWB-512-2) { -ICLASS: VPGATHERDQ +ICLASS: VPMOVSWB CPL: 3 -CATEGORY: GATHER +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E12 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W1 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASKNOT0():rw:mskw MEM0:r:qq:u64 -IFORM: VPGATHERDQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x20 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:qq:i8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zi16 +IFORM: VPMOVSWB_MEMi8_MASKmskw_ZMMi16_AVX512 } -# EMITTING VPGATHERQD (VPGATHERQD-128-1) +# EMITTING VPMOVSXBD (VPMOVSXBD-128-1) { -ICLASS: VPGATHERQD +ICLASS: VPMOVSXBD CPL: 3 -CATEGORY: GATHER +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E12 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W0 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASKNOT0():rw:mskw MEM0:r:q:u32 -IFORM: VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL128 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x21 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVSXBD_XMMi32_MASKmskw_XMMi8_AVX512 } - -# EMITTING VPGATHERQD (VPGATHERQD-256-1) { -ICLASS: VPGATHERQD +ICLASS: VPMOVSXBD CPL: 3 -CATEGORY: GATHER +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E12 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W0 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASKNOT0():rw:mskw MEM0:r:dq:u32 -IFORM: VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL256 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x21 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i8 +IFORM: VPMOVSXBD_XMMi32_MASKmskw_MEMi8_AVX512 } -# EMITTING VPGATHERQQ (VPGATHERQQ-128-1) +# EMITTING VPMOVSXBD (VPMOVSXBD-256-1) { -ICLASS: VPGATHERQQ +ICLASS: VPMOVSXBD CPL: 3 -CATEGORY: GATHER +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E12 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W1 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASKNOT0():rw:mskw MEM0:r:dq:u64 -IFORM: VPGATHERQQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x21 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVSXBD_YMMi32_MASKmskw_XMMi8_AVX512 } - -# EMITTING VPGATHERQQ (VPGATHERQQ-256-1) { -ICLASS: VPGATHERQQ +ICLASS: VPMOVSXBD CPL: 3 -CATEGORY: GATHER +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E12 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASKNOT0():rw:mskw MEM0:r:qq:u64 -IFORM: VPGATHERQQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x21 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8 +IFORM: VPMOVSXBD_YMMi32_MASKmskw_MEMi8_AVX512 } -# EMITTING VPINSRB (VPINSRB-128-1) +# EMITTING VPMOVSXBQ (VPMOVSXBQ-128-1) { -ICLASS: VPINSRB +ICLASS: VPMOVSXBQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128N -EXCEPTIONS: AVX512-E9NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -PATTERN: EVV 0x20 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 UIMM8() -OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=XMM_N3():r:dq:u8 REG2=GPR32_B():r:d:u8 IMM0:r:b -IFORM: VPINSRB_XMMu8_XMMu8_GPR32u8_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x22 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVSXBQ_XMMi64_MASKmskw_XMMi8_AVX512 } { -ICLASS: VPINSRB +ICLASS: VPMOVSXBQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128N -EXCEPTIONS: AVX512-E9NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: DISP8_GPR_READER_BYTE -PATTERN: EVV 0x20 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_GPR_READER_BYTE() -OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=XMM_N3():r:dq:u8 MEM0:r:b:u8 IMM0:r:b -IFORM: VPINSRB_XMMu8_XMMu8_MEMu8_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x22 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:wrd:i8 +IFORM: VPMOVSXBQ_XMMi64_MASKmskw_MEMi8_AVX512 } -# EMITTING VPINSRD (VPINSRD-128-1) +# EMITTING VPMOVSXBQ (VPMOVSXBQ-256-1) { -ICLASS: VPINSRD +ICLASS: VPMOVSXBQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128N -EXCEPTIONS: AVX512-E9NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -PATTERN: EVV 0x22 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 MASK=0 UIMM8() -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=XMM_N3():r:dq:u32 REG2=GPR32_B():r:d:u32 IMM0:r:b -IFORM: VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x22 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVSXBQ_YMMi64_MASKmskw_XMMi8_AVX512 } { -ICLASS: VPINSRD +ICLASS: VPMOVSXBQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128N -EXCEPTIONS: AVX512-E9NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: DISP8_GPR_READER -PATTERN: EVV 0x22 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_READER() -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=XMM_N3():r:dq:u32 MEM0:r:d:u32 IMM0:r:b -IFORM: VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x22 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i8 +IFORM: VPMOVSXBQ_YMMi64_MASKmskw_MEMi8_AVX512 } -# EMITTING VPINSRQ (VPINSRQ-128-1) +# EMITTING VPMOVSXBW (VPMOVSXBW-128-1) { -ICLASS: VPINSRQ +ICLASS: VPMOVSXBW CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128N -EXCEPTIONS: AVX512-E9NF +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -PATTERN: EVV 0x22 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 mode64 ZEROING=0 MASK=0 UIMM8() -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=XMM_N3():r:dq:u64 REG2=GPR64_B():r:q:u64 IMM0:r:b -IFORM: VPINSRQ_XMMu64_XMMu64_GPR64u64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x20 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVSXBW_XMMi16_MASKmskw_XMMi8_AVX512 } { -ICLASS: VPINSRQ +ICLASS: VPMOVSXBW CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128N -EXCEPTIONS: AVX512-E9NF +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: DISP8_GPR_READER -PATTERN: EVV 0x22 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 mode64 ZEROING=0 MASK=0 UIMM8() ESIZE_64_BITS() NELEM_GPR_READER() -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=XMM_N3():r:dq:u64 MEM0:r:q:u64 IMM0:r:b -IFORM: VPINSRQ_XMMu64_XMMu64_MEMu64_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x20 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8 +IFORM: VPMOVSXBW_XMMi16_MASKmskw_MEMi8_AVX512 } -# EMITTING VPINSRW (VPINSRW-128-1) +# EMITTING VPMOVSXBW (VPMOVSXBW-256-1) { -ICLASS: VPINSRW +ICLASS: VPMOVSXBW CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128N -EXCEPTIONS: AVX512-E9NF +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -PATTERN: EVV 0xC4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 UIMM8() -OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=XMM_N3():r:dq:u16 REG2=GPR32_B():r:d:u16 IMM0:r:b -IFORM: VPINSRW_XMMu16_XMMu16_GPR32u16_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x20 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVSXBW_YMMi16_MASKmskw_XMMi8_AVX512 } { -ICLASS: VPINSRW +ICLASS: VPMOVSXBW CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128N -EXCEPTIONS: AVX512-E9NF +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: DISP8_GPR_READER_WORD -PATTERN: EVV 0xC4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_16_BITS() NELEM_GPR_READER_WORD() -OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=XMM_N3():r:dq:u16 MEM0:r:wrd:u16 IMM0:r:b -IFORM: VPINSRW_XMMu16_XMMu16_MEMu16_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x20 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i8 +IFORM: VPMOVSXBW_YMMi16_MASKmskw_MEMi8_AVX512 } -# EMITTING VPLZCNTD (VPLZCNTD-128-1) +# EMITTING VPMOVSXBW (VPMOVSXBW-512-1) { -ICLASS: VPLZCNTD +ICLASS: VPMOVSXBW CPL: 3 -CATEGORY: CONFLICT +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512CD_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 -IFORM: VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512 +PATTERN: EVV 0x20 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i8 +IFORM: VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512 } { -ICLASS: VPLZCNTD +ICLASS: VPMOVSXBW CPL: 3 -CATEGORY: CONFLICT +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512CD_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPLZCNTD_XMMu32_MASKmskw_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x20 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i8 +IFORM: VPMOVSXBW_ZMMi16_MASKmskw_MEMi8_AVX512 } -# EMITTING VPLZCNTD (VPLZCNTD-256-1) +# EMITTING VPMOVSXDQ (VPMOVSXDQ-128-1) { -ICLASS: VPLZCNTD +ICLASS: VPMOVSXDQ CPL: 3 -CATEGORY: CONFLICT +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512CD_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 -IFORM: VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512 +PATTERN: EVV 0x25 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 +IFORM: VPMOVSXDQ_XMMi64_MASKmskw_XMMi32_AVX512 } { -ICLASS: VPLZCNTD +ICLASS: VPMOVSXDQ CPL: 3 -CATEGORY: CONFLICT +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512CD_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPLZCNTD_YMMu32_MASKmskw_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x25 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i32 +IFORM: VPMOVSXDQ_XMMi64_MASKmskw_MEMi32_AVX512 } -# EMITTING VPLZCNTQ (VPLZCNTQ-128-1) +# EMITTING VPMOVSXDQ (VPMOVSXDQ-256-1) { -ICLASS: VPLZCNTQ +ICLASS: VPMOVSXDQ CPL: 3 -CATEGORY: CONFLICT +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512CD_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 -IFORM: VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512 +PATTERN: EVV 0x25 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 +IFORM: VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512 } { -ICLASS: VPLZCNTQ +ICLASS: VPMOVSXDQ CPL: 3 -CATEGORY: CONFLICT +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512CD_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPLZCNTQ_XMMu64_MASKmskw_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x25 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i32 +IFORM: VPMOVSXDQ_YMMi64_MASKmskw_MEMi32_AVX512 } -# EMITTING VPLZCNTQ (VPLZCNTQ-256-1) +# EMITTING VPMOVSXWD (VPMOVSXWD-128-1) { -ICLASS: VPLZCNTQ +ICLASS: VPMOVSXWD CPL: 3 -CATEGORY: CONFLICT +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512CD_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 -IFORM: VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512 +PATTERN: EVV 0x23 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 +IFORM: VPMOVSXWD_XMMi32_MASKmskw_XMMi16_AVX512 } { -ICLASS: VPLZCNTQ +ICLASS: VPMOVSXWD CPL: 3 -CATEGORY: CONFLICT +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512CD_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPLZCNTQ_YMMu64_MASKmskw_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x23 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i16 +IFORM: VPMOVSXWD_XMMi32_MASKmskw_MEMi16_AVX512 } -# EMITTING VPMADDUBSW (VPMADDUBSW-128-1) +# EMITTING VPMOVSXWD (VPMOVSXWD-256-1) { -ICLASS: VPMADDUBSW +ICLASS: VPMOVSXWD CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x04 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 -OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 -IFORM: VPMADDUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 +PATTERN: EVV 0x23 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 +IFORM: VPMOVSXWD_YMMi32_MASKmskw_XMMi16_AVX512 } { -ICLASS: VPMADDUBSW +ICLASS: VPMOVSXWD CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x04 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 -IFORM: VPMADDUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x23 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i16 +IFORM: VPMOVSXWD_YMMi32_MASKmskw_MEMi16_AVX512 } -# EMITTING VPMADDUBSW (VPMADDUBSW-256-1) +# EMITTING VPMOVSXWQ (VPMOVSXWQ-128-1) { -ICLASS: VPMADDUBSW +ICLASS: VPMOVSXWQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x04 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 -OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 -IFORM: VPMADDUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 +PATTERN: EVV 0x24 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 +IFORM: VPMOVSXWQ_XMMi64_MASKmskw_XMMi16_AVX512 } { -ICLASS: VPMADDUBSW +ICLASS: VPMOVSXWQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x04 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 -IFORM: VPMADDUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x24 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i16 +IFORM: VPMOVSXWQ_XMMi64_MASKmskw_MEMi16_AVX512 } -# EMITTING VPMADDUBSW (VPMADDUBSW-512-1) +# EMITTING VPMOVSXWQ (VPMOVSXWQ-256-1) { -ICLASS: VPMADDUBSW +ICLASS: VPMOVSXWQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x04 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 -OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 -IFORM: VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 +PATTERN: EVV 0x24 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 +IFORM: VPMOVSXWQ_YMMi64_MASKmskw_XMMi16_AVX512 } { -ICLASS: VPMADDUBSW +ICLASS: VPMOVSXWQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x04 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 -IFORM: VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x24 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i16 +IFORM: VPMOVSXWQ_YMMi64_MASKmskw_MEMi16_AVX512 } -# EMITTING VPMADDWD (VPMADDWD-128-1) +# EMITTING VPMOVUSDB (VPMOVUSDB-128-1) { -ICLASS: VPMADDWD +ICLASS: VPMOVUSDB CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xF5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 -OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 -IFORM: VPMADDWD_XMMi32_MASKmskw_XMMi16_XMMi16_AVX512 +PATTERN: EVV 0x11 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32 +IFORM: VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512 } + +# EMITTING VPMOVUSDB (VPMOVUSDB-128-2) { -ICLASS: VPMADDWD +ICLASS: VPMOVUSDB CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xF5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 -IFORM: VPMADDWD_XMMi32_MASKmskw_XMMi16_MEMi16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x11 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:d:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32 +IFORM: VPMOVUSDB_MEMu8_MASKmskw_XMMu32_AVX512 } -# EMITTING VPMADDWD (VPMADDWD-256-1) +# EMITTING VPMOVUSDB (VPMOVUSDB-256-1) { -ICLASS: VPMADDWD +ICLASS: VPMOVUSDB CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xF5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 -OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 -IFORM: VPMADDWD_YMMi32_MASKmskw_YMMi16_YMMi16_AVX512 +PATTERN: EVV 0x11 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 +IFORM: VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512 } + +# EMITTING VPMOVUSDB (VPMOVUSDB-256-2) { -ICLASS: VPMADDWD +ICLASS: VPMOVUSDB CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xF5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 -IFORM: VPMADDWD_YMMi32_MASKmskw_YMMi16_MEMi16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x11 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 +IFORM: VPMOVUSDB_MEMu8_MASKmskw_YMMu32_AVX512 } -# EMITTING VPMADDWD (VPMADDWD-512-1) +# EMITTING VPMOVUSDW (VPMOVUSDW-128-1) { -ICLASS: VPMADDWD +ICLASS: VPMOVUSDW CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xF5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 -OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 -IFORM: VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512 +PATTERN: EVV 0x13 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32 +IFORM: VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512 } + +# EMITTING VPMOVUSDW (VPMOVUSDW-128-2) { -ICLASS: VPMADDWD +ICLASS: VPMOVUSDW CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xF5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 -IFORM: VPMADDWD_ZMMi32_MASKmskw_ZMMi16_MEMi16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x13 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:q:u16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32 +IFORM: VPMOVUSDW_MEMu16_MASKmskw_XMMu32_AVX512 } -# EMITTING VPMAXSB (VPMAXSB-128-1) +# EMITTING VPMOVUSDW (VPMOVUSDW-256-1) { -ICLASS: VPMAXSB +ICLASS: VPMOVUSDW CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x3C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 -OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 REG3=XMM_B3():r:dq:i8 -IFORM: VPMAXSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 +PATTERN: EVV 0x13 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 +IFORM: VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512 } + +# EMITTING VPMOVUSDW (VPMOVUSDW-256-2) { -ICLASS: VPMAXSB +ICLASS: VPMOVUSDW CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x3C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 MEM0:r:dq:i8 -IFORM: VPMAXSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x13 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:dq:u16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 +IFORM: VPMOVUSDW_MEMu16_MASKmskw_YMMu32_AVX512 } -# EMITTING VPMAXSB (VPMAXSB-256-1) +# EMITTING VPMOVUSQB (VPMOVUSQB-128-1) { -ICLASS: VPMAXSB +ICLASS: VPMOVUSQB CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x3C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 -OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 REG3=YMM_B3():r:qq:i8 -IFORM: VPMAXSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 +PATTERN: EVV 0x12 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 +IFORM: VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512 } + +# EMITTING VPMOVUSQB (VPMOVUSQB-128-2) { -ICLASS: VPMAXSB +ICLASS: VPMOVUSQB CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x3C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 MEM0:r:qq:i8 -IFORM: VPMAXSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x12 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: MEM0:w:wrd:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 +IFORM: VPMOVUSQB_MEMu8_MASKmskw_XMMu64_AVX512 } -# EMITTING VPMAXSB (VPMAXSB-512-1) +# EMITTING VPMOVUSQB (VPMOVUSQB-256-1) { -ICLASS: VPMAXSB +ICLASS: VPMOVUSQB CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x3C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 -OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 REG3=ZMM_B3():r:zi8 -IFORM: VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 +PATTERN: EVV 0x12 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 +IFORM: VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512 } + +# EMITTING VPMOVUSQB (VPMOVUSQB-256-2) { -ICLASS: VPMAXSB +ICLASS: VPMOVUSQB CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x3C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 MEM0:r:zd:i8 -IFORM: VPMAXSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x12 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: MEM0:w:d:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 +IFORM: VPMOVUSQB_MEMu8_MASKmskw_YMMu64_AVX512 } -# EMITTING VPMAXSD (VPMAXSD-128-1) +# EMITTING VPMOVUSQD (VPMOVUSQD-128-1) { -ICLASS: VPMAXSD +ICLASS: VPMOVUSQD CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 REG3=XMM_B3():r:dq:i32 -IFORM: VPMAXSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512 +PATTERN: EVV 0x15 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 +IFORM: VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512 } + +# EMITTING VPMOVUSQD (VPMOVUSQD-128-2) { -ICLASS: VPMAXSD +ICLASS: VPMOVUSQD CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 MEM0:r:vv:i32:TXT=BCASTSTR -IFORM: VPMAXSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x15 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:q:u32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 +IFORM: VPMOVUSQD_MEMu32_MASKmskw_XMMu64_AVX512 } -# EMITTING VPMAXSD (VPMAXSD-256-1) +# EMITTING VPMOVUSQD (VPMOVUSQD-256-1) { -ICLASS: VPMAXSD +ICLASS: VPMOVUSQD CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 REG3=YMM_B3():r:qq:i32 -IFORM: VPMAXSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512 +PATTERN: EVV 0x15 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 +IFORM: VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512 } + +# EMITTING VPMOVUSQD (VPMOVUSQD-256-2) { -ICLASS: VPMAXSD +ICLASS: VPMOVUSQD CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 MEM0:r:vv:i32:TXT=BCASTSTR -IFORM: VPMAXSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x15 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 +IFORM: VPMOVUSQD_MEMu32_MASKmskw_YMMu64_AVX512 } -# EMITTING VPMAXSQ (VPMAXSQ-128-1) +# EMITTING VPMOVUSQW (VPMOVUSQW-128-1) { -ICLASS: VPMAXSQ +ICLASS: VPMOVUSQW CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i64 REG3=XMM_B3():r:dq:i64 -IFORM: VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512 +PATTERN: EVV 0x14 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 +IFORM: VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512 } + +# EMITTING VPMOVUSQW (VPMOVUSQW-128-2) { -ICLASS: VPMAXSQ +ICLASS: VPMOVUSQW CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i64 MEM0:r:vv:i64:TXT=BCASTSTR -IFORM: VPMAXSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x14 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:d:u16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 +IFORM: VPMOVUSQW_MEMu16_MASKmskw_XMMu64_AVX512 } -# EMITTING VPMAXSQ (VPMAXSQ-256-1) +# EMITTING VPMOVUSQW (VPMOVUSQW-256-1) { -ICLASS: VPMAXSQ +ICLASS: VPMOVUSQW CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i64 REG3=YMM_B3():r:qq:i64 -IFORM: VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512 +PATTERN: EVV 0x14 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 +IFORM: VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512 } + +# EMITTING VPMOVUSQW (VPMOVUSQW-256-2) { -ICLASS: VPMAXSQ +ICLASS: VPMOVUSQW CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i64 MEM0:r:vv:i64:TXT=BCASTSTR -IFORM: VPMAXSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x14 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:q:u16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 +IFORM: VPMOVUSQW_MEMu16_MASKmskw_YMMu64_AVX512 } -# EMITTING VPMAXSW (VPMAXSW-128-1) +# EMITTING VPMOVUSWB (VPMOVUSWB-128-1) { -ICLASS: VPMAXSW +ICLASS: VPMOVUSWB CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xEE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 -OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 -IFORM: VPMAXSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 +PATTERN: EVV 0x10 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u16 +IFORM: VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512 } + +# EMITTING VPMOVUSWB (VPMOVUSWB-128-2) { -ICLASS: VPMAXSW +ICLASS: VPMOVUSWB CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xEE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 -IFORM: VPMAXSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x10 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u16 +IFORM: VPMOVUSWB_MEMu8_MASKmskw_XMMu16_AVX512 } -# EMITTING VPMAXSW (VPMAXSW-256-1) +# EMITTING VPMOVUSWB (VPMOVUSWB-256-1) { -ICLASS: VPMAXSW +ICLASS: VPMOVUSWB CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xEE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 -OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 -IFORM: VPMAXSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 +PATTERN: EVV 0x10 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u16 +IFORM: VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512 } + +# EMITTING VPMOVUSWB (VPMOVUSWB-256-2) { -ICLASS: VPMAXSW +ICLASS: VPMOVUSWB CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xEE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 -IFORM: VPMAXSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x10 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:dq:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u16 +IFORM: VPMOVUSWB_MEMu8_MASKmskw_YMMu16_AVX512 } -# EMITTING VPMAXSW (VPMAXSW-512-1) +# EMITTING VPMOVUSWB (VPMOVUSWB-512-1) { -ICLASS: VPMAXSW +ICLASS: VPMOVUSWB CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xEE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 -OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 -IFORM: VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 +PATTERN: EVV 0x10 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu16 +IFORM: VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512 } + +# EMITTING VPMOVUSWB (VPMOVUSWB-512-2) { -ICLASS: VPMAXSW +ICLASS: VPMOVUSWB CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xEE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 -IFORM: VPMAXSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x10 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:qq:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu16 +IFORM: VPMOVUSWB_MEMu8_MASKmskw_ZMMu16_AVX512 } -# EMITTING VPMAXUB (VPMAXUB-128-1) +# EMITTING VPMOVW2M (VPMOVW2M-128-1) { -ICLASS: VPMAXUB +ICLASS: VPMOVW2M CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=XMM_B3():r:dq:u16 +IFORM: VPMOVW2M_MASKmskw_XMMu16_AVX512 +} + + +# EMITTING VPMOVW2M (VPMOVW2M-256-1) +{ +ICLASS: VPMOVW2M +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=YMM_B3():r:qq:u16 +IFORM: VPMOVW2M_MASKmskw_YMMu16_AVX512 +} + + +# EMITTING VPMOVW2M (VPMOVW2M-512-1) +{ +ICLASS: VPMOVW2M +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=ZMM_B3():r:zu16 +IFORM: VPMOVW2M_MASKmskw_ZMMu16_AVX512 +} + + +# EMITTING VPMOVWB (VPMOVWB-128-1) +{ +ICLASS: VPMOVWB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xDE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 -OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 -IFORM: VPMAXUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +PATTERN: EVV 0x30 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u16 +IFORM: VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512 } + +# EMITTING VPMOVWB (VPMOVWB-128-2) { -ICLASS: VPMAXUB +ICLASS: VPMOVWB CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xDE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 -IFORM: VPMAXUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x30 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u16 +IFORM: VPMOVWB_MEMu8_MASKmskw_XMMu16_AVX512 } -# EMITTING VPMAXUB (VPMAXUB-256-1) +# EMITTING VPMOVWB (VPMOVWB-256-1) { -ICLASS: VPMAXUB +ICLASS: VPMOVWB CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xDE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 -OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 -IFORM: VPMAXUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +PATTERN: EVV 0x30 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u16 +IFORM: VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512 } + +# EMITTING VPMOVWB (VPMOVWB-256-2) { -ICLASS: VPMAXUB +ICLASS: VPMOVWB CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xDE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 -IFORM: VPMAXUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x30 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:dq:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u16 +IFORM: VPMOVWB_MEMu8_MASKmskw_YMMu16_AVX512 } -# EMITTING VPMAXUB (VPMAXUB-512-1) +# EMITTING VPMOVWB (VPMOVWB-512-1) { -ICLASS: VPMAXUB +ICLASS: VPMOVWB CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E6NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xDE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 -OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 -IFORM: VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +PATTERN: EVV 0x30 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu16 +IFORM: VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512 } + +# EMITTING VPMOVWB (VPMOVWB-512-2) { -ICLASS: VPMAXUB +ICLASS: VPMOVWB CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E6 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xDE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 -IFORM: VPMAXUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x30 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:qq:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu16 +IFORM: VPMOVWB_MEMu8_MASKmskw_ZMMu16_AVX512 } -# EMITTING VPMAXUD (VPMAXUD-128-1) +# EMITTING VPMOVZXBD (VPMOVZXBD-128-1) { -ICLASS: VPMAXUD +ICLASS: VPMOVZXBD CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 -IFORM: VPMAXUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +PATTERN: EVV 0x31 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVZXBD_XMMi32_MASKmskw_XMMi8_AVX512 } { -ICLASS: VPMAXUD +ICLASS: VPMOVZXBD CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPMAXUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x31 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i8 +IFORM: VPMOVZXBD_XMMi32_MASKmskw_MEMi8_AVX512 } -# EMITTING VPMAXUD (VPMAXUD-256-1) +# EMITTING VPMOVZXBD (VPMOVZXBD-256-1) { -ICLASS: VPMAXUD +ICLASS: VPMOVZXBD CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 -IFORM: VPMAXUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +PATTERN: EVV 0x31 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVZXBD_YMMi32_MASKmskw_XMMi8_AVX512 } { -ICLASS: VPMAXUD +ICLASS: VPMOVZXBD CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPMAXUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x31 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8 +IFORM: VPMOVZXBD_YMMi32_MASKmskw_MEMi8_AVX512 } -# EMITTING VPMAXUQ (VPMAXUQ-128-1) +# EMITTING VPMOVZXBQ (VPMOVZXBQ-128-1) { -ICLASS: VPMAXUQ +ICLASS: VPMOVZXBQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 -IFORM: VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +PATTERN: EVV 0x32 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVZXBQ_XMMi64_MASKmskw_XMMi8_AVX512 } { -ICLASS: VPMAXUQ +ICLASS: VPMOVZXBQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPMAXUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x32 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:wrd:i8 +IFORM: VPMOVZXBQ_XMMi64_MASKmskw_MEMi8_AVX512 } -# EMITTING VPMAXUQ (VPMAXUQ-256-1) +# EMITTING VPMOVZXBQ (VPMOVZXBQ-256-1) { -ICLASS: VPMAXUQ +ICLASS: VPMOVZXBQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 -IFORM: VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +PATTERN: EVV 0x32 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVZXBQ_YMMi64_MASKmskw_XMMi8_AVX512 } { -ICLASS: VPMAXUQ +ICLASS: VPMOVZXBQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPMAXUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x32 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i8 +IFORM: VPMOVZXBQ_YMMi64_MASKmskw_MEMi8_AVX512 } -# EMITTING VPMAXUW (VPMAXUW-128-1) +# EMITTING VPMOVZXBW (VPMOVZXBW-128-1) { -ICLASS: VPMAXUW +ICLASS: VPMOVZXBW CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x3E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 -OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 -IFORM: VPMAXUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +PATTERN: EVV 0x30 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVZXBW_XMMi16_MASKmskw_XMMi8_AVX512 +} + +{ +ICLASS: VPMOVZXBW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x30 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8 +IFORM: VPMOVZXBW_XMMi16_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPMOVZXBW (VPMOVZXBW-256-1) +{ +ICLASS: VPMOVZXBW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x30 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVZXBW_YMMi16_MASKmskw_XMMi8_AVX512 } { -ICLASS: VPMAXUW +ICLASS: VPMOVZXBW CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x3E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 -IFORM: VPMAXUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x30 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i8 +IFORM: VPMOVZXBW_YMMi16_MASKmskw_MEMi8_AVX512 } -# EMITTING VPMAXUW (VPMAXUW-256-1) +# EMITTING VPMOVZXBW (VPMOVZXBW-512-1) { -ICLASS: VPMAXUW +ICLASS: VPMOVZXBW CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x3E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 -OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 -IFORM: VPMAXUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +PATTERN: EVV 0x30 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i8 +IFORM: VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512 } { -ICLASS: VPMAXUW +ICLASS: VPMOVZXBW CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x3E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 -IFORM: VPMAXUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x30 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i8 +IFORM: VPMOVZXBW_ZMMi16_MASKmskw_MEMi8_AVX512 } -# EMITTING VPMAXUW (VPMAXUW-512-1) +# EMITTING VPMOVZXDQ (VPMOVZXDQ-128-1) { -ICLASS: VPMAXUW +ICLASS: VPMOVZXDQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x3E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 -OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 -IFORM: VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +PATTERN: EVV 0x35 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 +IFORM: VPMOVZXDQ_XMMi64_MASKmskw_XMMi32_AVX512 } { -ICLASS: VPMAXUW +ICLASS: VPMOVZXDQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x3E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 -IFORM: VPMAXUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x35 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i32 +IFORM: VPMOVZXDQ_XMMi64_MASKmskw_MEMi32_AVX512 } -# EMITTING VPMINSB (VPMINSB-128-1) +# EMITTING VPMOVZXDQ (VPMOVZXDQ-256-1) { -ICLASS: VPMINSB +ICLASS: VPMOVZXDQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 -OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 REG3=XMM_B3():r:dq:i8 -IFORM: VPMINSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 +PATTERN: EVV 0x35 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 +IFORM: VPMOVZXDQ_YMMi64_MASKmskw_XMMi32_AVX512 } { -ICLASS: VPMINSB +ICLASS: VPMOVZXDQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 MEM0:r:dq:i8 -IFORM: VPMINSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x35 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i32 +IFORM: VPMOVZXDQ_YMMi64_MASKmskw_MEMi32_AVX512 } -# EMITTING VPMINSB (VPMINSB-256-1) +# EMITTING VPMOVZXWD (VPMOVZXWD-128-1) { -ICLASS: VPMINSB +ICLASS: VPMOVZXWD CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 -OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 REG3=YMM_B3():r:qq:i8 -IFORM: VPMINSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 +PATTERN: EVV 0x33 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 +IFORM: VPMOVZXWD_XMMi32_MASKmskw_XMMi16_AVX512 } { -ICLASS: VPMINSB +ICLASS: VPMOVZXWD CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 MEM0:r:qq:i8 -IFORM: VPMINSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x33 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i16 +IFORM: VPMOVZXWD_XMMi32_MASKmskw_MEMi16_AVX512 } -# EMITTING VPMINSB (VPMINSB-512-1) +# EMITTING VPMOVZXWD (VPMOVZXWD-256-1) { -ICLASS: VPMINSB +ICLASS: VPMOVZXWD CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 -OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 REG3=ZMM_B3():r:zi8 -IFORM: VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 +PATTERN: EVV 0x33 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 +IFORM: VPMOVZXWD_YMMi32_MASKmskw_XMMi16_AVX512 } { -ICLASS: VPMINSB +ICLASS: VPMOVZXWD CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 MEM0:r:zd:i8 -IFORM: VPMINSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x33 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i16 +IFORM: VPMOVZXWD_YMMi32_MASKmskw_MEMi16_AVX512 } -# EMITTING VPMINSD (VPMINSD-128-1) +# EMITTING VPMOVZXWQ (VPMOVZXWQ-128-1) { -ICLASS: VPMINSD +ICLASS: VPMOVZXWQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 REG3=XMM_B3():r:dq:i32 -IFORM: VPMINSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512 +PATTERN: EVV 0x34 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 +IFORM: VPMOVZXWQ_XMMi64_MASKmskw_XMMi16_AVX512 } { -ICLASS: VPMINSD +ICLASS: VPMOVZXWQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 MEM0:r:vv:i32:TXT=BCASTSTR -IFORM: VPMINSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x34 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i16 +IFORM: VPMOVZXWQ_XMMi64_MASKmskw_MEMi16_AVX512 } -# EMITTING VPMINSD (VPMINSD-256-1) +# EMITTING VPMOVZXWQ (VPMOVZXWQ-256-1) { -ICLASS: VPMINSD +ICLASS: VPMOVZXWQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 REG3=YMM_B3():r:qq:i32 -IFORM: VPMINSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512 +PATTERN: EVV 0x34 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 +IFORM: VPMOVZXWQ_YMMi64_MASKmskw_XMMi16_AVX512 } { -ICLASS: VPMINSD +ICLASS: VPMOVZXWQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: DATAXFER EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E5 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 MEM0:r:vv:i32:TXT=BCASTSTR -IFORM: VPMINSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x34 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i16 +IFORM: VPMOVZXWQ_YMMi64_MASKmskw_MEMi16_AVX512 } -# EMITTING VPMINSQ (VPMINSQ-128-1) +# EMITTING VPMULDQ (VPMULDQ-128-1) { -ICLASS: VPMINSQ +ICLASS: VPMULDQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y +COMMENT: Strange instruction that uses 32b of each 64b input element ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +PATTERN: EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i64 REG3=XMM_B3():r:dq:i64 -IFORM: VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512 +IFORM: VPMULDQ_XMMi64_MASKmskw_XMMi32_XMMi32_AVX512 } { -ICLASS: VPMINSQ +ICLASS: VPMULDQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +COMMENT: Strange instruction that uses 32b of each 64b input element +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP DISP8_FULL BROADCAST_ENABLED MASKOP_EVEX +PATTERN: EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i64 MEM0:r:vv:i64:TXT=BCASTSTR -IFORM: VPMINSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512 +IFORM: VPMULDQ_XMMi64_MASKmskw_XMMi32_MEMi32_AVX512 } -# EMITTING VPMINSQ (VPMINSQ-256-1) +# EMITTING VPMULDQ (VPMULDQ-256-1) { -ICLASS: VPMINSQ +ICLASS: VPMULDQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y +COMMENT: Strange instruction that uses 32b of each 64b input element ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +PATTERN: EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i64 REG3=YMM_B3():r:qq:i64 -IFORM: VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512 +IFORM: VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512 } { -ICLASS: VPMINSQ +ICLASS: VPMULDQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +COMMENT: Strange instruction that uses 32b of each 64b input element +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP DISP8_FULL BROADCAST_ENABLED MASKOP_EVEX +PATTERN: EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i64 MEM0:r:vv:i64:TXT=BCASTSTR -IFORM: VPMINSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512 +IFORM: VPMULDQ_YMMi64_MASKmskw_YMMi32_MEMi32_AVX512 } -# EMITTING VPMINSW (VPMINSW-128-1) +# EMITTING VPMULHRSW (VPMULHRSW-128-1) { -ICLASS: VPMINSW +ICLASS: VPMULHRSW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -58364,13 +63177,13 @@ ISA_SET: AVX512BW_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xEA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +PATTERN: EVV 0x0B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 -IFORM: VPMINSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 +IFORM: VPMULHRSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 } { -ICLASS: VPMINSW +ICLASS: VPMULHRSW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -58378,15 +63191,15 @@ ISA_SET: AVX512BW_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xEA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +PATTERN: EVV 0x0B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 -IFORM: VPMINSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 +IFORM: VPMULHRSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 } -# EMITTING VPMINSW (VPMINSW-256-1) +# EMITTING VPMULHRSW (VPMULHRSW-256-1) { -ICLASS: VPMINSW +ICLASS: VPMULHRSW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -58394,13 +63207,13 @@ ISA_SET: AVX512BW_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xEA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +PATTERN: EVV 0x0B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 -IFORM: VPMINSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 +IFORM: VPMULHRSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 } { -ICLASS: VPMINSW +ICLASS: VPMULHRSW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -58408,15 +63221,15 @@ ISA_SET: AVX512BW_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xEA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +PATTERN: EVV 0x0B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 -IFORM: VPMINSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 +IFORM: VPMULHRSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 } -# EMITTING VPMINSW (VPMINSW-512-1) +# EMITTING VPMULHRSW (VPMULHRSW-512-1) { -ICLASS: VPMINSW +ICLASS: VPMULHRSW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -58424,13 +63237,13 @@ ISA_SET: AVX512BW_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xEA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +PATTERN: EVV 0x0B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 -IFORM: VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 +IFORM: VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 } { -ICLASS: VPMINSW +ICLASS: VPMULHRSW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -58438,15 +63251,15 @@ ISA_SET: AVX512BW_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xEA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +PATTERN: EVV 0x0B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 -IFORM: VPMINSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 +IFORM: VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 } -# EMITTING VPMINUB (VPMINUB-128-1) +# EMITTING VPMULHUW (VPMULHUW-128-1) { -ICLASS: VPMINUB +ICLASS: VPMULHUW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -58454,13 +63267,13 @@ ISA_SET: AVX512BW_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xDA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 -OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 -IFORM: VPMINUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +PATTERN: EVV 0xE4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPMULHUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 } { -ICLASS: VPMINUB +ICLASS: VPMULHUW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -58468,15 +63281,15 @@ ISA_SET: AVX512BW_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xDA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 -IFORM: VPMINUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +PATTERN: EVV 0xE4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPMULHUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 } -# EMITTING VPMINUB (VPMINUB-256-1) +# EMITTING VPMULHUW (VPMULHUW-256-1) { -ICLASS: VPMINUB +ICLASS: VPMULHUW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -58484,13 +63297,13 @@ ISA_SET: AVX512BW_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xDA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 -OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 -IFORM: VPMINUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +PATTERN: EVV 0xE4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPMULHUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 } { -ICLASS: VPMINUB +ICLASS: VPMULHUW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -58498,15 +63311,15 @@ ISA_SET: AVX512BW_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xDA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 -IFORM: VPMINUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +PATTERN: EVV 0xE4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPMULHUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 } -# EMITTING VPMINUB (VPMINUB-512-1) +# EMITTING VPMULHUW (VPMULHUW-512-1) { -ICLASS: VPMINUB +ICLASS: VPMULHUW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -58514,13 +63327,13 @@ ISA_SET: AVX512BW_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xDA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 -OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 -IFORM: VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +PATTERN: EVV 0xE4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 } { -ICLASS: VPMINUB +ICLASS: VPMULHUW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -58528,2763 +63341,2631 @@ ISA_SET: AVX512BW_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xDA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 -IFORM: VPMINUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 -} - - -# EMITTING VPMINUD (VPMINUD-128-1) -{ -ICLASS: VPMINUD -CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 -REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 -IFORM: VPMINUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 -} - -{ -ICLASS: VPMINUD -CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 -REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPMINUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 -} - - -# EMITTING VPMINUD (VPMINUD-256-1) -{ -ICLASS: VPMINUD -CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 -REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 -IFORM: VPMINUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 -} - -{ -ICLASS: VPMINUD -CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 -REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPMINUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +PATTERN: EVV 0xE4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPMULHUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 } -# EMITTING VPMINUQ (VPMINUQ-128-1) +# EMITTING VPMULHW (VPMULHW-128-1) { -ICLASS: VPMINUQ +ICLASS: VPMULHW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512BW_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 -IFORM: VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +PATTERN: EVV 0xE5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPMULHW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 } { -ICLASS: VPMINUQ +ICLASS: VPMULHW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512BW_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPMINUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPMULHW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 } -# EMITTING VPMINUQ (VPMINUQ-256-1) +# EMITTING VPMULHW (VPMULHW-256-1) { -ICLASS: VPMINUQ +ICLASS: VPMULHW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 +ISA_SET: AVX512BW_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 -IFORM: VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +PATTERN: EVV 0xE5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPMULHW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 } { -ICLASS: VPMINUQ +ICLASS: VPMULHW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 +ISA_SET: AVX512BW_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPMINUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPMULHW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 } -# EMITTING VPMINUW (VPMINUW-128-1) +# EMITTING VPMULHW (VPMULHW-512-1) { -ICLASS: VPMINUW +ICLASS: VPMULHW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 +ISA_SET: AVX512BW_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 -OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 -IFORM: VPMINUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +PATTERN: EVV 0xE5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 } { -ICLASS: VPMINUW +ICLASS: VPMULHW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 +ISA_SET: AVX512BW_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 -IFORM: VPMINUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +PATTERN: EVV 0xE5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPMULHW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 } -# EMITTING VPMINUW (VPMINUW-256-1) +# EMITTING VPMULLD (VPMULLD-128-1) { -ICLASS: VPMINUW +ICLASS: VPMULLD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 -OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 -IFORM: VPMINUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +PATTERN: EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPMULLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 } { -ICLASS: VPMINUW +ICLASS: VPMULLD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 -IFORM: VPMINUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPMULLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 } -# EMITTING VPMINUW (VPMINUW-512-1) +# EMITTING VPMULLD (VPMULLD-256-1) { -ICLASS: VPMINUW +ICLASS: VPMULLD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 -OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 -IFORM: VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +PATTERN: EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPMULLD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 } { -ICLASS: VPMINUW +ICLASS: VPMULLD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 -IFORM: VPMINUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPMULLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 } -# EMITTING VPMOVB2M (VPMOVB2M-128-1) +# EMITTING VPMULLQ (VPMULLQ-128-1) { -ICLASS: VPMOVB2M +ICLASS: VPMULLQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E7NM +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -PATTERN: EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=XMM_B3():r:dq:u8 -IFORM: VPMOVB2M_MASKmskw_XMMu8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 } - -# EMITTING VPMOVB2M (VPMOVB2M-256-1) { -ICLASS: VPMOVB2M +ICLASS: VPMULLQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E7NM +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -PATTERN: EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=YMM_B3():r:qq:u8 -IFORM: VPMOVB2M_MASKmskw_YMMu8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMULLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 } -# EMITTING VPMOVB2M (VPMOVB2M-512-1) +# EMITTING VPMULLQ (VPMULLQ-256-1) { -ICLASS: VPMOVB2M +ICLASS: VPMULLQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E7NM +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -PATTERN: EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=ZMM_B3():r:zu8 -IFORM: VPMOVB2M_MASKmskw_ZMMu8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 } - -# EMITTING VPMOVD2M (VPMOVD2M-128-1) { -ICLASS: VPMOVD2M +ICLASS: VPMULLQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128 -EXCEPTIONS: AVX512-E7NM +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -PATTERN: EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=XMM_B3():r:dq:u32 -IFORM: VPMOVD2M_MASKmskw_XMMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMULLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 } -# EMITTING VPMOVD2M (VPMOVD2M-256-1) +# EMITTING VPMULLQ (VPMULLQ-512-1) { -ICLASS: VPMOVD2M +ICLASS: VPMULLQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 -EXCEPTIONS: AVX512-E7NM +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -PATTERN: EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=YMM_B3():r:qq:u32 -IFORM: VPMOVD2M_MASKmskw_YMMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 } - -# EMITTING VPMOVD2M (VPMOVD2M-512-1) { -ICLASS: VPMOVD2M +ICLASS: VPMULLQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E7NM +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -PATTERN: EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=ZMM_B3():r:zu32 -IFORM: VPMOVD2M_MASKmskw_ZMMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMULLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 } -# EMITTING VPMOVDB (VPMOVDB-128-1) +# EMITTING VPMULLW (VPMULLW-128-1) { -ICLASS: VPMOVDB +ICLASS: VPMULLW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x31 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32 -IFORM: VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512 +PATTERN: EVV 0xD5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPMULLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 } - -# EMITTING VPMOVDB (VPMOVDB-128-2) { -ICLASS: VPMOVDB +ICLASS: VPMULLW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM -PATTERN: EVV 0x31 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() -OPERANDS: MEM0:w:d:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32 -IFORM: VPMOVDB_MEMu8_MASKmskw_XMMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xD5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPMULLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 } -# EMITTING VPMOVDB (VPMOVDB-256-1) +# EMITTING VPMULLW (VPMULLW-256-1) { -ICLASS: VPMOVDB +ICLASS: VPMULLW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x31 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 -IFORM: VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512 +PATTERN: EVV 0xD5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPMULLW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 } - -# EMITTING VPMOVDB (VPMOVDB-256-2) { -ICLASS: VPMOVDB +ICLASS: VPMULLW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM -PATTERN: EVV 0x31 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() -OPERANDS: MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 -IFORM: VPMOVDB_MEMu8_MASKmskw_YMMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xD5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPMULLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 } -# EMITTING VPMOVDW (VPMOVDW-128-1) +# EMITTING VPMULLW (VPMULLW-512-1) { -ICLASS: VPMOVDW +ICLASS: VPMULLW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x33 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32 -IFORM: VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512 +PATTERN: EVV 0xD5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 } - -# EMITTING VPMOVDW (VPMOVDW-128-2) { -ICLASS: VPMOVDW +ICLASS: VPMULLW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM -PATTERN: EVV 0x33 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() -OPERANDS: MEM0:w:q:u16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32 -IFORM: VPMOVDW_MEMu16_MASKmskw_XMMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xD5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPMULLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 } -# EMITTING VPMOVDW (VPMOVDW-256-1) +# EMITTING VPMULUDQ (VPMULUDQ-128-1) { -ICLASS: VPMOVDW +ICLASS: VPMULUDQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y +COMMENT: Strange instruction that uses 32b of each 64b input element ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x33 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 -IFORM: VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512 -} - - -# EMITTING VPMOVDW (VPMOVDW-256-2) -{ -ICLASS: VPMOVDW -CPL: 3 -CATEGORY: DATAXFER -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E6NF -REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM -PATTERN: EVV 0x33 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() -OPERANDS: MEM0:w:dq:u16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 -IFORM: VPMOVDW_MEMu16_MASKmskw_YMMu32_AVX512 +PATTERN: EVV 0xF4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPMULUDQ_XMMu64_MASKmskw_XMMu32_XMMu32_AVX512 } - -# EMITTING VPMOVM2B (VPMOVM2B-128-1) { -ICLASS: VPMOVM2B +ICLASS: VPMULUDQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E7NM +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -PATTERN: EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK_B():r:mskw -IFORM: VPMOVM2B_XMMu8_MASKmskw_AVX512 +COMMENT: Strange instruction that uses 32b of each 64b input element +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP DISP8_FULL BROADCAST_ENABLED MASKOP_EVEX +PATTERN: EVV 0xF4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMULUDQ_XMMu64_MASKmskw_XMMu32_MEMu32_AVX512 } -# EMITTING VPMOVM2B (VPMOVM2B-256-1) +# EMITTING VPMULUDQ (VPMULUDQ-256-1) { -ICLASS: VPMOVM2B +ICLASS: VPMULUDQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E7NM +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -PATTERN: EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK_B():r:mskw -IFORM: VPMOVM2B_YMMu8_MASKmskw_AVX512 +COMMENT: Strange instruction that uses 32b of each 64b input element +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPMULUDQ_YMMu64_MASKmskw_YMMu32_YMMu32_AVX512 } - -# EMITTING VPMOVM2B (VPMOVM2B-512-1) { -ICLASS: VPMOVM2B +ICLASS: VPMULUDQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E7NM +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -PATTERN: EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK_B():r:mskw -IFORM: VPMOVM2B_ZMMu8_MASKmskw_AVX512 +COMMENT: Strange instruction that uses 32b of each 64b input element +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP DISP8_FULL BROADCAST_ENABLED MASKOP_EVEX +PATTERN: EVV 0xF4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMULUDQ_YMMu64_MASKmskw_YMMu32_MEMu32_AVX512 } -# EMITTING VPMOVM2D (VPMOVM2D-128-1) +# EMITTING VPORD (VPORD-128-1) { -ICLASS: VPMOVM2D +ICLASS: VPORD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128 -EXCEPTIONS: AVX512-E7NM +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -PATTERN: EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK_B():r:mskw -IFORM: VPMOVM2D_XMMu32_MASKmskw_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 } - -# EMITTING VPMOVM2D (VPMOVM2D-256-1) { -ICLASS: VPMOVM2D +ICLASS: VPORD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 -EXCEPTIONS: AVX512-E7NM +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -PATTERN: EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK_B():r:mskw -IFORM: VPMOVM2D_YMMu32_MASKmskw_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 } -# EMITTING VPMOVM2D (VPMOVM2D-512-1) +# EMITTING VPORD (VPORD-256-1) { -ICLASS: VPMOVM2D +ICLASS: VPORD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E7NM +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -PATTERN: EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK_B():r:mskw -IFORM: VPMOVM2D_ZMMu32_MASKmskw_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 } - -# EMITTING VPMOVM2Q (VPMOVM2Q-128-1) { -ICLASS: VPMOVM2Q +ICLASS: VPORD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128 -EXCEPTIONS: AVX512-E7NM +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -PATTERN: EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK_B():r:mskw -IFORM: VPMOVM2Q_XMMu64_MASKmskw_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 } -# EMITTING VPMOVM2Q (VPMOVM2Q-256-1) +# EMITTING VPORQ (VPORQ-128-1) { -ICLASS: VPMOVM2Q +ICLASS: VPORQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 -EXCEPTIONS: AVX512-E7NM +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -PATTERN: EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK_B():r:mskw -IFORM: VPMOVM2Q_YMMu64_MASKmskw_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 } - -# EMITTING VPMOVM2Q (VPMOVM2Q-512-1) { -ICLASS: VPMOVM2Q +ICLASS: VPORQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E7NM +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -PATTERN: EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK_B():r:mskw -IFORM: VPMOVM2Q_ZMMu64_MASKmskw_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 } -# EMITTING VPMOVM2W (VPMOVM2W-128-1) +# EMITTING VPORQ (VPORQ-256-1) { -ICLASS: VPMOVM2W +ICLASS: VPORQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E7NM +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -PATTERN: EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK_B():r:mskw -IFORM: VPMOVM2W_XMMu16_MASKmskw_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 } - -# EMITTING VPMOVM2W (VPMOVM2W-256-1) { -ICLASS: VPMOVM2W +ICLASS: VPORQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E7NM +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -PATTERN: EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK_B():r:mskw -IFORM: VPMOVM2W_YMMu16_MASKmskw_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 } -# EMITTING VPMOVM2W (VPMOVM2W-512-1) +# EMITTING VPROLD (VPROLD-128-1) { -ICLASS: VPMOVM2W +ICLASS: VPROLD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E7NM +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -PATTERN: EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK_B():r:mskw -IFORM: VPMOVM2W_ZMMu16_MASKmskw_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL128 W0 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b +IFORM: VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 } - -# EMITTING VPMOVQ2M (VPMOVQ2M-128-1) { -ICLASS: VPMOVQ2M +ICLASS: VPROLD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128 -EXCEPTIONS: AVX512-E7NM +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -PATTERN: EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=XMM_B3():r:dq:u64 -IFORM: VPMOVQ2M_MASKmskw_XMMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPROLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 } -# EMITTING VPMOVQ2M (VPMOVQ2M-256-1) +# EMITTING VPROLD (VPROLD-256-1) { -ICLASS: VPMOVQ2M +ICLASS: VPROLD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 -EXCEPTIONS: AVX512-E7NM +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -PATTERN: EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=YMM_B3():r:qq:u64 -IFORM: VPMOVQ2M_MASKmskw_YMMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b +IFORM: VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 } - -# EMITTING VPMOVQ2M (VPMOVQ2M-512-1) { -ICLASS: VPMOVQ2M +ICLASS: VPROLD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E7NM -REAL_OPCODE: Y -PATTERN: EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=ZMM_B3():r:zu64 -IFORM: VPMOVQ2M_MASKmskw_ZMMu64_AVX512 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPROLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 } -# EMITTING VPMOVQB (VPMOVQB-128-1) +# EMITTING VPROLQ (VPROLQ-128-1) { -ICLASS: VPMOVQB +ICLASS: VPROLQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x32 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 -IFORM: VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512 +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 IMM0:r:b +IFORM: VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 } - -# EMITTING VPMOVQB (VPMOVQB-128-2) { -ICLASS: VPMOVQB +ICLASS: VPROLQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM -PATTERN: EVV 0x32 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() -OPERANDS: MEM0:w:wrd:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 -IFORM: VPMOVQB_MEMu8_MASKmskw_XMMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPROLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 } -# EMITTING VPMOVQB (VPMOVQB-256-1) +# EMITTING VPROLQ (VPROLQ-256-1) { -ICLASS: VPMOVQB +ICLASS: VPROLQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x32 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 -IFORM: VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512 +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 } - -# EMITTING VPMOVQB (VPMOVQB-256-2) { -ICLASS: VPMOVQB +ICLASS: VPROLQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM -PATTERN: EVV 0x32 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() -OPERANDS: MEM0:w:d:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 -IFORM: VPMOVQB_MEMu8_MASKmskw_YMMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPROLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 } -# EMITTING VPMOVQD (VPMOVQD-128-1) +# EMITTING VPROLVD (VPROLVD-128-1) { -ICLASS: VPMOVQD +ICLASS: VPROLVD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x35 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 -IFORM: VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512 +PATTERN: EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 } - -# EMITTING VPMOVQD (VPMOVQD-128-2) { -ICLASS: VPMOVQD +ICLASS: VPROLVD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM -PATTERN: EVV 0x35 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() -OPERANDS: MEM0:w:q:u32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 -IFORM: VPMOVQD_MEMu32_MASKmskw_XMMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPROLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 } -# EMITTING VPMOVQD (VPMOVQD-256-1) +# EMITTING VPROLVD (VPROLVD-256-1) { -ICLASS: VPMOVQD +ICLASS: VPROLVD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x35 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 -IFORM: VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512 +PATTERN: EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 } - -# EMITTING VPMOVQD (VPMOVQD-256-2) { -ICLASS: VPMOVQD +ICLASS: VPROLVD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM -PATTERN: EVV 0x35 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() -OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 -IFORM: VPMOVQD_MEMu32_MASKmskw_YMMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPROLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 } -# EMITTING VPMOVQW (VPMOVQW-128-1) +# EMITTING VPROLVQ (VPROLVQ-128-1) { -ICLASS: VPMOVQW +ICLASS: VPROLVQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x34 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 -IFORM: VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512 +PATTERN: EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 } - -# EMITTING VPMOVQW (VPMOVQW-128-2) { -ICLASS: VPMOVQW +ICLASS: VPROLVQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM -PATTERN: EVV 0x34 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() -OPERANDS: MEM0:w:d:u16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 -IFORM: VPMOVQW_MEMu16_MASKmskw_XMMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPROLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 } -# EMITTING VPMOVQW (VPMOVQW-256-1) +# EMITTING VPROLVQ (VPROLVQ-256-1) { -ICLASS: VPMOVQW +ICLASS: VPROLVQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x34 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 -IFORM: VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512 +PATTERN: EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 } - -# EMITTING VPMOVQW (VPMOVQW-256-2) { -ICLASS: VPMOVQW +ICLASS: VPROLVQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM -PATTERN: EVV 0x34 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() -OPERANDS: MEM0:w:q:u16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 -IFORM: VPMOVQW_MEMu16_MASKmskw_YMMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPROLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 } -# EMITTING VPMOVSDB (VPMOVSDB-128-1) +# EMITTING VPRORD (VPRORD-128-1) { -ICLASS: VPMOVSDB +ICLASS: VPRORD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x21 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:i32 -IFORM: VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512 +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL128 W0 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b +IFORM: VPRORD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 } - -# EMITTING VPMOVSDB (VPMOVSDB-128-2) { -ICLASS: VPMOVSDB +ICLASS: VPRORD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM -PATTERN: EVV 0x21 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() -OPERANDS: MEM0:w:d:i8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:i32 -IFORM: VPMOVSDB_MEMi8_MASKmskw_XMMi32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPRORD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 } -# EMITTING VPMOVSDB (VPMOVSDB-256-1) +# EMITTING VPRORD (VPRORD-256-1) { -ICLASS: VPMOVSDB +ICLASS: VPRORD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x21 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:i32 -IFORM: VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512 +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b +IFORM: VPRORD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 } - -# EMITTING VPMOVSDB (VPMOVSDB-256-2) { -ICLASS: VPMOVSDB +ICLASS: VPRORD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM -PATTERN: EVV 0x21 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() -OPERANDS: MEM0:w:q:i8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:i32 -IFORM: VPMOVSDB_MEMi8_MASKmskw_YMMi32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPRORD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 } -# EMITTING VPMOVSDW (VPMOVSDW-128-1) +# EMITTING VPRORQ (VPRORQ-128-1) { -ICLASS: VPMOVSDW +ICLASS: VPRORQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x23 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:i32 -IFORM: VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512 +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 IMM0:r:b +IFORM: VPRORQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 } - -# EMITTING VPMOVSDW (VPMOVSDW-128-2) { -ICLASS: VPMOVSDW +ICLASS: VPRORQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM -PATTERN: EVV 0x23 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() -OPERANDS: MEM0:w:q:i16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:i32 -IFORM: VPMOVSDW_MEMi16_MASKmskw_XMMi32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPRORQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 } -# EMITTING VPMOVSDW (VPMOVSDW-256-1) +# EMITTING VPRORQ (VPRORQ-256-1) { -ICLASS: VPMOVSDW +ICLASS: VPRORQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x23 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:i32 -IFORM: VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512 +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VPRORQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 } - -# EMITTING VPMOVSDW (VPMOVSDW-256-2) { -ICLASS: VPMOVSDW +ICLASS: VPRORQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM -PATTERN: EVV 0x23 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() -OPERANDS: MEM0:w:dq:i16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:i32 -IFORM: VPMOVSDW_MEMi16_MASKmskw_YMMi32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPRORQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 } -# EMITTING VPMOVSQB (VPMOVSQB-128-1) +# EMITTING VPRORVD (VPRORVD-128-1) { -ICLASS: VPMOVSQB +ICLASS: VPRORVD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x22 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:i64 -IFORM: VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512 +PATTERN: EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 } - -# EMITTING VPMOVSQB (VPMOVSQB-128-2) { -ICLASS: VPMOVSQB +ICLASS: VPRORVD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM -PATTERN: EVV 0x22 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() -OPERANDS: MEM0:w:wrd:i8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:i64 -IFORM: VPMOVSQB_MEMi8_MASKmskw_XMMi64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPRORVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 } -# EMITTING VPMOVSQB (VPMOVSQB-256-1) +# EMITTING VPRORVD (VPRORVD-256-1) { -ICLASS: VPMOVSQB +ICLASS: VPRORVD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x22 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:i64 -IFORM: VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512 +PATTERN: EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 } - -# EMITTING VPMOVSQB (VPMOVSQB-256-2) { -ICLASS: VPMOVSQB +ICLASS: VPRORVD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM -PATTERN: EVV 0x22 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() -OPERANDS: MEM0:w:d:i8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:i64 -IFORM: VPMOVSQB_MEMi8_MASKmskw_YMMi64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPRORVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 } -# EMITTING VPMOVSQD (VPMOVSQD-128-1) +# EMITTING VPRORVQ (VPRORVQ-128-1) { -ICLASS: VPMOVSQD +ICLASS: VPRORVQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x25 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:i64 -IFORM: VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512 +PATTERN: EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 } - -# EMITTING VPMOVSQD (VPMOVSQD-128-2) { -ICLASS: VPMOVSQD +ICLASS: VPRORVQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM -PATTERN: EVV 0x25 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() -OPERANDS: MEM0:w:q:i32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:i64 -IFORM: VPMOVSQD_MEMi32_MASKmskw_XMMi64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPRORVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 } -# EMITTING VPMOVSQD (VPMOVSQD-256-1) +# EMITTING VPRORVQ (VPRORVQ-256-1) { -ICLASS: VPMOVSQD +ICLASS: VPRORVQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x25 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:i64 -IFORM: VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512 +PATTERN: EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 } - -# EMITTING VPMOVSQD (VPMOVSQD-256-2) { -ICLASS: VPMOVSQD +ICLASS: VPRORVQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM -PATTERN: EVV 0x25 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() -OPERANDS: MEM0:w:dq:i32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:i64 -IFORM: VPMOVSQD_MEMi32_MASKmskw_YMMi64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPRORVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 } -# EMITTING VPMOVSQW (VPMOVSQW-128-1) +# EMITTING VPSADBW (VPSADBW-128-1) { -ICLASS: VPMOVSQW +ICLASS: VPSADBW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x24 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:i64 -IFORM: VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512 +PATTERN: EVV 0xF6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=XMM_N3():r:dq:u8 REG2=XMM_B3():r:dq:u8 +IFORM: VPSADBW_XMMu16_XMMu8_XMMu8_AVX512 } - -# EMITTING VPMOVSQW (VPMOVSQW-128-2) { -ICLASS: VPMOVSQW +ICLASS: VPSADBW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM -PATTERN: EVV 0x24 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() -OPERANDS: MEM0:w:d:i16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:i64 -IFORM: VPMOVSQW_MEMi16_MASKmskw_XMMi64_AVX512 +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0xF6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPSADBW_XMMu16_XMMu8_MEMu8_AVX512 } -# EMITTING VPMOVSQW (VPMOVSQW-256-1) +# EMITTING VPSADBW (VPSADBW-256-1) { -ICLASS: VPMOVSQW +ICLASS: VPSADBW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x24 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:i64 -IFORM: VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512 +PATTERN: EVV 0xF6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 MASK=0 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=YMM_N3():r:qq:u8 REG2=YMM_B3():r:qq:u8 +IFORM: VPSADBW_YMMu16_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPSADBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0xF6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPSADBW_YMMu16_YMMu8_MEMu8_AVX512 } -# EMITTING VPMOVSQW (VPMOVSQW-256-2) +# EMITTING VPSADBW (VPSADBW-512-1) { -ICLASS: VPMOVSQW +ICLASS: VPSADBW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +PATTERN: EVV 0xF6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 MASK=0 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=ZMM_N3():r:zu8 REG2=ZMM_B3():r:zu8 +IFORM: VPSADBW_ZMMu16_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPSADBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM -PATTERN: EVV 0x24 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() -OPERANDS: MEM0:w:q:i16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:i64 -IFORM: VPMOVSQW_MEMi16_MASKmskw_YMMi64_AVX512 +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0xF6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPSADBW_ZMMu16_ZMMu8_MEMu8_AVX512 } -# EMITTING VPMOVSWB (VPMOVSWB-128-1) +# EMITTING VPSCATTERDD (VPSCATTERDD-128-1) { -ICLASS: VPMOVSWB +ICLASS: VPSCATTERDD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: SCATTER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x20 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:i16 -IFORM: VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512 +ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:d:u32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:u32 +IFORM: VPSCATTERDD_MEMu32_MASKmskw_XMMu32_AVX512_VL128 } -# EMITTING VPMOVSWB (VPMOVSWB-128-2) +# EMITTING VPSCATTERDD (VPSCATTERDD-256-1) { -ICLASS: VPMOVSWB +ICLASS: VPSCATTERDD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: SCATTER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM -PATTERN: EVV 0x20 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() -OPERANDS: MEM0:w:q:i8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:i16 -IFORM: VPMOVSWB_MEMi8_MASKmskw_XMMi16_AVX512 +ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:d:u32 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:u32 +IFORM: VPSCATTERDD_MEMu32_MASKmskw_YMMu32_AVX512_VL256 } -# EMITTING VPMOVSWB (VPMOVSWB-256-1) +# EMITTING VPSCATTERDQ (VPSCATTERDQ-128-1) { -ICLASS: VPMOVSWB +ICLASS: VPSCATTERDQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: SCATTER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x20 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:i16 -IFORM: VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512 +ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:q:u64 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:u64 +IFORM: VPSCATTERDQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128 } -# EMITTING VPMOVSWB (VPMOVSWB-256-2) +# EMITTING VPSCATTERDQ (VPSCATTERDQ-256-1) { -ICLASS: VPMOVSWB +ICLASS: VPSCATTERDQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: SCATTER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM -PATTERN: EVV 0x20 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() -OPERANDS: MEM0:w:dq:i8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:i16 -IFORM: VPMOVSWB_MEMi8_MASKmskw_YMMi16_AVX512 +ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:q:u64 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:u64 +IFORM: VPSCATTERDQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256 } -# EMITTING VPMOVSWB (VPMOVSWB-512-1) +# EMITTING VPSCATTERQD (VPSCATTERQD-128-1) { -ICLASS: VPMOVSWB +ICLASS: VPSCATTERQD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: SCATTER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x20 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=YMM_B3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zi16 -IFORM: VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512 +ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:d:u32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:u32 +IFORM: VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128 } -# EMITTING VPMOVSWB (VPMOVSWB-512-2) +# EMITTING VPSCATTERQD (VPSCATTERQD-256-1) { -ICLASS: VPMOVSWB +ICLASS: VPSCATTERQD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: SCATTER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM -PATTERN: EVV 0x20 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() -OPERANDS: MEM0:w:qq:i8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zi16 -IFORM: VPMOVSWB_MEMi8_MASKmskw_ZMMi16_AVX512 +ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:d:u32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:u32 +IFORM: VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL256 } -# EMITTING VPMOVSXBD (VPMOVSXBD-128-1) +# EMITTING VPSCATTERQQ (VPSCATTERQQ-128-1) { -ICLASS: VPMOVSXBD +ICLASS: VPSCATTERQQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: SCATTER EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E5 +EXCEPTIONS: AVX512-E12 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x21 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 -IFORM: VPMOVSXBD_XMMi32_MASKmskw_XMMi8_AVX512 +ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:q:u64 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:u64 +IFORM: VPSCATTERQQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128 } + +# EMITTING VPSCATTERQQ (VPSCATTERQQ-256-1) { -ICLASS: VPMOVSXBD +ICLASS: VPSCATTERQQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: SCATTER EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E5 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM -PATTERN: EVV 0x21 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM() -OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i8 -IFORM: VPMOVSXBD_XMMi32_MASKmskw_MEMi8_AVX512 +ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:q:u64 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:u64 +IFORM: VPSCATTERQQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256 } -# EMITTING VPMOVSXBD (VPMOVSXBD-256-1) +# EMITTING VPSHUFB (VPSHUFB-128-1) { -ICLASS: VPMOVSXBD +ICLASS: VPSHUFB CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E5 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x21 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 -IFORM: VPMOVSXBD_YMMi32_MASKmskw_XMMi8_AVX512 +PATTERN: EVV 0x00 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPSHUFB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 } { -ICLASS: VPMOVSXBD +ICLASS: VPSHUFB CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E5 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM -PATTERN: EVV 0x21 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM() -OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8 -IFORM: VPMOVSXBD_YMMi32_MASKmskw_MEMi8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x00 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPSHUFB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 } -# EMITTING VPMOVSXBQ (VPMOVSXBQ-128-1) +# EMITTING VPSHUFB (VPSHUFB-256-1) { -ICLASS: VPMOVSXBQ +ICLASS: VPSHUFB CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E5 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x22 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 -IFORM: VPMOVSXBQ_XMMi64_MASKmskw_XMMi8_AVX512 +PATTERN: EVV 0x00 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPSHUFB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 } { -ICLASS: VPMOVSXBQ +ICLASS: VPSHUFB CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E5 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM -PATTERN: EVV 0x22 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM() -OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:wrd:i8 -IFORM: VPMOVSXBQ_XMMi64_MASKmskw_MEMi8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x00 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPSHUFB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 } -# EMITTING VPMOVSXBQ (VPMOVSXBQ-256-1) +# EMITTING VPSHUFB (VPSHUFB-512-1) { -ICLASS: VPMOVSXBQ +ICLASS: VPSHUFB CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E5 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x22 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 -IFORM: VPMOVSXBQ_YMMi64_MASKmskw_XMMi8_AVX512 +PATTERN: EVV 0x00 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 } { -ICLASS: VPMOVSXBQ +ICLASS: VPSHUFB CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E5 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM -PATTERN: EVV 0x22 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM() -OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i8 -IFORM: VPMOVSXBQ_YMMi64_MASKmskw_MEMi8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x00 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPSHUFB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 } -# EMITTING VPMOVSXBW (VPMOVSXBW-128-1) +# EMITTING VPSHUFD (VPSHUFD-128-1) { -ICLASS: VPMOVSXBW +ICLASS: VPSHUFD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E5 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x20 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 -IFORM: VPMOVSXBW_XMMi16_MASKmskw_XMMi8_AVX512 +PATTERN: EVV 0x70 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b +IFORM: VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 } { -ICLASS: VPMOVSXBW +ICLASS: VPSHUFD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E5 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM -PATTERN: EVV 0x20 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM() -OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8 -IFORM: VPMOVSXBW_XMMi16_MASKmskw_MEMi8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x70 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSHUFD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 } -# EMITTING VPMOVSXBW (VPMOVSXBW-256-1) +# EMITTING VPSHUFD (VPSHUFD-256-1) { -ICLASS: VPMOVSXBW +ICLASS: VPSHUFD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E5 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x20 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 -IFORM: VPMOVSXBW_YMMi16_MASKmskw_XMMi8_AVX512 +PATTERN: EVV 0x70 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b +IFORM: VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 } { -ICLASS: VPMOVSXBW +ICLASS: VPSHUFD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E5 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM -PATTERN: EVV 0x20 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM() -OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i8 -IFORM: VPMOVSXBW_YMMi16_MASKmskw_MEMi8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x70 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSHUFD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 } -# EMITTING VPMOVSXBW (VPMOVSXBW-512-1) +# EMITTING VPSHUFHW (VPSHUFHW-128-1) { -ICLASS: VPMOVSXBW +ICLASS: VPSHUFHW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E5 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x20 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i8 -IFORM: VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512 +PATTERN: EVV 0x70 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 IMM0:r:b +IFORM: VPSHUFHW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 } { -ICLASS: VPMOVSXBW +ICLASS: VPSHUFHW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E5 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM -PATTERN: EVV 0x20 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM() -OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i8 -IFORM: VPMOVSXBW_ZMMi16_MASKmskw_MEMi8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x70 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 IMM0:r:b +IFORM: VPSHUFHW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 } -# EMITTING VPMOVSXDQ (VPMOVSXDQ-128-1) +# EMITTING VPSHUFHW (VPSHUFHW-256-1) { -ICLASS: VPMOVSXDQ +ICLASS: VPSHUFHW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E5 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x25 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 -IFORM: VPMOVSXDQ_XMMi64_MASKmskw_XMMi32_AVX512 +PATTERN: EVV 0x70 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 IMM0:r:b +IFORM: VPSHUFHW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 } { -ICLASS: VPMOVSXDQ +ICLASS: VPSHUFHW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E5 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM -PATTERN: EVV 0x25 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM() -OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i32 -IFORM: VPMOVSXDQ_XMMi64_MASKmskw_MEMi32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x70 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 IMM0:r:b +IFORM: VPSHUFHW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 } -# EMITTING VPMOVSXDQ (VPMOVSXDQ-256-1) +# EMITTING VPSHUFHW (VPSHUFHW-512-1) { -ICLASS: VPMOVSXDQ +ICLASS: VPSHUFHW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E5 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x25 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 -IFORM: VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512 +PATTERN: EVV 0x70 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 IMM0:r:b +IFORM: VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 } { -ICLASS: VPMOVSXDQ +ICLASS: VPSHUFHW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E5 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM -PATTERN: EVV 0x25 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM() -OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i32 -IFORM: VPMOVSXDQ_YMMi64_MASKmskw_MEMi32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x70 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 IMM0:r:b +IFORM: VPSHUFHW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 } -# EMITTING VPMOVSXWD (VPMOVSXWD-128-1) +# EMITTING VPSHUFLW (VPSHUFLW-128-1) { -ICLASS: VPMOVSXWD +ICLASS: VPSHUFLW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E5 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x23 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 -IFORM: VPMOVSXWD_XMMi32_MASKmskw_XMMi16_AVX512 +PATTERN: EVV 0x70 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 IMM0:r:b +IFORM: VPSHUFLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 } { -ICLASS: VPMOVSXWD +ICLASS: VPSHUFLW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E5 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM -PATTERN: EVV 0x23 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() -OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i16 -IFORM: VPMOVSXWD_XMMi32_MASKmskw_MEMi16_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x70 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 IMM0:r:b +IFORM: VPSHUFLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 } -# EMITTING VPMOVSXWD (VPMOVSXWD-256-1) +# EMITTING VPSHUFLW (VPSHUFLW-256-1) { -ICLASS: VPMOVSXWD +ICLASS: VPSHUFLW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E5 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x23 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 -IFORM: VPMOVSXWD_YMMi32_MASKmskw_XMMi16_AVX512 +PATTERN: EVV 0x70 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 IMM0:r:b +IFORM: VPSHUFLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 } { -ICLASS: VPMOVSXWD +ICLASS: VPSHUFLW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E5 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM -PATTERN: EVV 0x23 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() -OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i16 -IFORM: VPMOVSXWD_YMMi32_MASKmskw_MEMi16_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x70 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 IMM0:r:b +IFORM: VPSHUFLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 } -# EMITTING VPMOVSXWQ (VPMOVSXWQ-128-1) +# EMITTING VPSHUFLW (VPSHUFLW-512-1) { -ICLASS: VPMOVSXWQ +ICLASS: VPSHUFLW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E5 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x24 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 -IFORM: VPMOVSXWQ_XMMi64_MASKmskw_XMMi16_AVX512 +PATTERN: EVV 0x70 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 IMM0:r:b +IFORM: VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 } { -ICLASS: VPMOVSXWQ +ICLASS: VPSHUFLW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E5 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM -PATTERN: EVV 0x24 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM() -OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i16 -IFORM: VPMOVSXWQ_XMMi64_MASKmskw_MEMi16_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x70 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 IMM0:r:b +IFORM: VPSHUFLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 } -# EMITTING VPMOVSXWQ (VPMOVSXWQ-256-1) +# EMITTING VPSLLD (VPSLLD-128-1) { -ICLASS: VPMOVSXWQ +ICLASS: VPSLLD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E5 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x24 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 -IFORM: VPMOVSXWQ_YMMi64_MASKmskw_XMMi16_AVX512 +PATTERN: EVV 0xF2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSLLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 } { -ICLASS: VPMOVSXWQ +ICLASS: VPSLLD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E5 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM -PATTERN: EVV 0x24 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM() -OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i16 -IFORM: VPMOVSXWQ_YMMi64_MASKmskw_MEMi16_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xF2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_32_BITS() NELEM_MEM128() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:dq:u32 +IFORM: VPSLLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 } -# EMITTING VPMOVUSDB (VPMOVUSDB-128-1) +# EMITTING VPSLLD (VPSLLD-128-3) { -ICLASS: VPMOVUSDB +ICLASS: VPSLLD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x11 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32 -IFORM: VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512 +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL128 W0 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b +IFORM: VPSLLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 } - -# EMITTING VPMOVUSDB (VPMOVUSDB-128-2) { -ICLASS: VPMOVUSDB +ICLASS: VPSLLD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM -PATTERN: EVV 0x11 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() -OPERANDS: MEM0:w:d:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32 -IFORM: VPMOVUSDB_MEMu8_MASKmskw_XMMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSLLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 } -# EMITTING VPMOVUSDB (VPMOVUSDB-256-1) +# EMITTING VPSLLD (VPSLLD-256-1) { -ICLASS: VPMOVUSDB +ICLASS: VPSLLD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x11 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 -IFORM: VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512 +PATTERN: EVV 0xF2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSLLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 } - -# EMITTING VPMOVUSDB (VPMOVUSDB-256-2) { -ICLASS: VPMOVUSDB +ICLASS: VPSLLD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM -PATTERN: EVV 0x11 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() -OPERANDS: MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 -IFORM: VPMOVUSDB_MEMu8_MASKmskw_YMMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xF2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_32_BITS() NELEM_MEM128() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:dq:u32 +IFORM: VPSLLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 } -# EMITTING VPMOVUSDW (VPMOVUSDW-128-1) +# EMITTING VPSLLD (VPSLLD-256-3) { -ICLASS: VPMOVUSDW +ICLASS: VPSLLD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x13 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32 -IFORM: VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512 +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b +IFORM: VPSLLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 } - -# EMITTING VPMOVUSDW (VPMOVUSDW-128-2) { -ICLASS: VPMOVUSDW +ICLASS: VPSLLD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM -PATTERN: EVV 0x13 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() -OPERANDS: MEM0:w:q:u16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32 -IFORM: VPMOVUSDW_MEMu16_MASKmskw_XMMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSLLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 } -# EMITTING VPMOVUSDW (VPMOVUSDW-256-1) +# EMITTING VPSLLDQ (VPSLLDQ-128-2) { -ICLASS: VPMOVUSDW +ICLASS: VPSLLDQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x13 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 -IFORM: VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512 +PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b111] RM[nnn] VL128 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u8 REG1=XMM_B3():r:dq:u8 IMM0:r:b +IFORM: VPSLLDQ_XMMu8_XMMu8_IMM8_AVX512 } - -# EMITTING VPMOVUSDW (VPMOVUSDW-256-2) { -ICLASS: VPMOVUSDW +ICLASS: VPSLLDQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM -PATTERN: EVV 0x13 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() -OPERANDS: MEM0:w:dq:u16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 -IFORM: VPMOVUSDW_MEMu16_MASKmskw_YMMu32_AVX512 +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b111] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_N3():w:dq:u8 MEM0:r:dq:u8 IMM0:r:b +IFORM: VPSLLDQ_XMMu8_MEMu8_IMM8_AVX512 } -# EMITTING VPMOVUSQB (VPMOVUSQB-128-1) +# EMITTING VPSLLDQ (VPSLLDQ-256-2) { -ICLASS: VPMOVUSQB +ICLASS: VPSLLDQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x12 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 -IFORM: VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512 +PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b111] RM[nnn] VL256 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u8 REG1=YMM_B3():r:qq:u8 IMM0:r:b +IFORM: VPSLLDQ_YMMu8_YMMu8_IMM8_AVX512 } - -# EMITTING VPMOVUSQB (VPMOVUSQB-128-2) { -ICLASS: VPMOVUSQB +ICLASS: VPSLLDQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM -PATTERN: EVV 0x12 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() -OPERANDS: MEM0:w:wrd:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 -IFORM: VPMOVUSQB_MEMu8_MASKmskw_XMMu64_AVX512 +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b111] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_N3():w:qq:u8 MEM0:r:qq:u8 IMM0:r:b +IFORM: VPSLLDQ_YMMu8_MEMu8_IMM8_AVX512 } -# EMITTING VPMOVUSQB (VPMOVUSQB-256-1) +# EMITTING VPSLLDQ (VPSLLDQ-512-1) { -ICLASS: VPMOVUSQB +ICLASS: VPSLLDQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x12 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 -IFORM: VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512 +PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b111] RM[nnn] VL512 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu8 REG1=ZMM_B3():r:zu8 IMM0:r:b +IFORM: VPSLLDQ_ZMMu8_ZMMu8_IMM8_AVX512 } - -# EMITTING VPMOVUSQB (VPMOVUSQB-256-2) { -ICLASS: VPMOVUSQB +ICLASS: VPSLLDQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM -PATTERN: EVV 0x12 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() -OPERANDS: MEM0:w:d:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 -IFORM: VPMOVUSQB_MEMu8_MASKmskw_YMMu64_AVX512 +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b111] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_N3():w:zu8 MEM0:r:zd:u8 IMM0:r:b +IFORM: VPSLLDQ_ZMMu8_MEMu8_IMM8_AVX512 } -# EMITTING VPMOVUSQD (VPMOVUSQD-128-1) +# EMITTING VPSLLQ (VPSLLQ-128-1) { -ICLASS: VPMOVUSQD +ICLASS: VPSLLQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x15 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 -IFORM: VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512 +PATTERN: EVV 0xF3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSLLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 } - -# EMITTING VPMOVUSQD (VPMOVUSQD-128-2) { -ICLASS: VPMOVUSQD +ICLASS: VPSLLQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM -PATTERN: EVV 0x15 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() -OPERANDS: MEM0:w:q:u32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 -IFORM: VPMOVUSQD_MEMu32_MASKmskw_XMMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xF3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_64_BITS() NELEM_MEM128() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:dq:u64 +IFORM: VPSLLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 } -# EMITTING VPMOVUSQD (VPMOVUSQD-256-1) +# EMITTING VPSLLQ (VPSLLQ-128-3) { -ICLASS: VPMOVUSQD +ICLASS: VPSLLQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x15 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 -IFORM: VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512 +PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 IMM0:r:b +IFORM: VPSLLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 } - -# EMITTING VPMOVUSQD (VPMOVUSQD-256-2) { -ICLASS: VPMOVUSQD +ICLASS: VPSLLQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM -PATTERN: EVV 0x15 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() -OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 -IFORM: VPMOVUSQD_MEMu32_MASKmskw_YMMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPSLLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 } -# EMITTING VPMOVUSQW (VPMOVUSQW-128-1) +# EMITTING VPSLLQ (VPSLLQ-256-1) { -ICLASS: VPMOVUSQW +ICLASS: VPSLLQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x14 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 -IFORM: VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512 +PATTERN: EVV 0xF3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSLLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 } - -# EMITTING VPMOVUSQW (VPMOVUSQW-128-2) { -ICLASS: VPMOVUSQW +ICLASS: VPSLLQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM -PATTERN: EVV 0x14 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() -OPERANDS: MEM0:w:d:u16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 -IFORM: VPMOVUSQW_MEMu16_MASKmskw_XMMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xF3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_64_BITS() NELEM_MEM128() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:dq:u64 +IFORM: VPSLLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 } -# EMITTING VPMOVUSQW (VPMOVUSQW-256-1) +# EMITTING VPSLLQ (VPSLLQ-256-3) { -ICLASS: VPMOVUSQW +ICLASS: VPSLLQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x14 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 -IFORM: VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512 +PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VPSLLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 } - -# EMITTING VPMOVUSQW (VPMOVUSQW-256-2) { -ICLASS: VPMOVUSQW +ICLASS: VPSLLQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM -PATTERN: EVV 0x14 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() -OPERANDS: MEM0:w:q:u16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 -IFORM: VPMOVUSQW_MEMu16_MASKmskw_YMMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPSLLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 } -# EMITTING VPMOVUSWB (VPMOVUSWB-128-1) +# EMITTING VPSLLVD (VPSLLVD-128-1) { -ICLASS: VPMOVUSWB +ICLASS: VPSLLVD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x10 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u16 -IFORM: VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512 +PATTERN: EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSLLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 } - -# EMITTING VPMOVUSWB (VPMOVUSWB-128-2) { -ICLASS: VPMOVUSWB +ICLASS: VPSLLVD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM -PATTERN: EVV 0x10 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() -OPERANDS: MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u16 -IFORM: VPMOVUSWB_MEMu8_MASKmskw_XMMu16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSLLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 } -# EMITTING VPMOVUSWB (VPMOVUSWB-256-1) +# EMITTING VPSLLVD (VPSLLVD-256-1) { -ICLASS: VPMOVUSWB +ICLASS: VPSLLVD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x10 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u16 -IFORM: VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512 +PATTERN: EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPSLLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 } - -# EMITTING VPMOVUSWB (VPMOVUSWB-256-2) { -ICLASS: VPMOVUSWB +ICLASS: VPSLLVD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM -PATTERN: EVV 0x10 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() -OPERANDS: MEM0:w:dq:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u16 -IFORM: VPMOVUSWB_MEMu8_MASKmskw_YMMu16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSLLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 } -# EMITTING VPMOVUSWB (VPMOVUSWB-512-1) +# EMITTING VPSLLVQ (VPSLLVQ-128-1) { -ICLASS: VPMOVUSWB +ICLASS: VPSLLVQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E6NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x10 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=YMM_B3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu16 -IFORM: VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512 -} - - -# EMITTING VPMOVUSWB (VPMOVUSWB-512-2) -{ -ICLASS: VPMOVUSWB -CPL: 3 -CATEGORY: DATAXFER -EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E6NF -REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM -PATTERN: EVV 0x10 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() -OPERANDS: MEM0:w:qq:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu16 -IFORM: VPMOVUSWB_MEMu8_MASKmskw_ZMMu16_AVX512 +PATTERN: EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSLLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 } - -# EMITTING VPMOVW2M (VPMOVW2M-128-1) { -ICLASS: VPMOVW2M +ICLASS: VPSLLVQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E7NM +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -PATTERN: EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=XMM_B3():r:dq:u16 -IFORM: VPMOVW2M_MASKmskw_XMMu16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSLLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 } -# EMITTING VPMOVW2M (VPMOVW2M-256-1) +# EMITTING VPSLLVQ (VPSLLVQ-256-1) { -ICLASS: VPMOVW2M +ICLASS: VPSLLVQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E7NM +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -PATTERN: EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=YMM_B3():r:qq:u16 -IFORM: VPMOVW2M_MASKmskw_YMMu16_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPSLLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 } - -# EMITTING VPMOVW2M (VPMOVW2M-512-1) { -ICLASS: VPMOVW2M +ICLASS: VPSLLVQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E7NM +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -PATTERN: EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 MASK=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=ZMM_B3():r:zu16 -IFORM: VPMOVW2M_MASKmskw_ZMMu16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSLLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 } -# EMITTING VPMOVWB (VPMOVWB-128-1) +# EMITTING VPSLLVW (VPSLLVW-128-1) { -ICLASS: VPMOVWB +ICLASS: VPSLLVW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x30 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u16 -IFORM: VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512 +PATTERN: EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 } - -# EMITTING VPMOVWB (VPMOVWB-128-2) { -ICLASS: VPMOVWB +ICLASS: VPSLLVW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM -PATTERN: EVV 0x30 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() -OPERANDS: MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u16 -IFORM: VPMOVWB_MEMu8_MASKmskw_XMMu16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPSLLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 } -# EMITTING VPMOVWB (VPMOVWB-256-1) +# EMITTING VPSLLVW (VPSLLVW-256-1) { -ICLASS: VPMOVWB +ICLASS: VPSLLVW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x30 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u16 -IFORM: VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512 +PATTERN: EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 } - -# EMITTING VPMOVWB (VPMOVWB-256-2) { -ICLASS: VPMOVWB +ICLASS: VPSLLVW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM -PATTERN: EVV 0x30 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() -OPERANDS: MEM0:w:dq:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u16 -IFORM: VPMOVWB_MEMu8_MASKmskw_YMMu16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPSLLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 } -# EMITTING VPMOVWB (VPMOVWB-512-1) +# EMITTING VPSLLVW (VPSLLVW-512-1) { -ICLASS: VPMOVWB +ICLASS: VPSLLVW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x30 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR -OPERANDS: REG0=YMM_B3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu16 -IFORM: VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512 +PATTERN: EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 } - -# EMITTING VPMOVWB (VPMOVWB-512-2) { -ICLASS: VPMOVWB +ICLASS: VPSLLVW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E6NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM -PATTERN: EVV 0x30 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() -OPERANDS: MEM0:w:qq:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu16 -IFORM: VPMOVWB_MEMu8_MASKmskw_ZMMu16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPSLLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 } -# EMITTING VPMOVZXBD (VPMOVZXBD-128-1) +# EMITTING VPSLLW (VPSLLW-128-1) { -ICLASS: VPMOVZXBD +ICLASS: VPSLLW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E5 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x31 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 -IFORM: VPMOVZXBD_XMMi32_MASKmskw_XMMi8_AVX512 +PATTERN: EVV 0xF1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSLLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 } { -ICLASS: VPMOVZXBD +ICLASS: VPSLLW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E5 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM -PATTERN: EVV 0x31 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM() -OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i8 -IFORM: VPMOVZXBD_XMMi32_MASKmskw_MEMi8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xF1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_MEM128() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPSLLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 } -# EMITTING VPMOVZXBD (VPMOVZXBD-256-1) +# EMITTING VPSLLW (VPSLLW-128-3) { -ICLASS: VPMOVZXBD +ICLASS: VPSLLW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E5 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x31 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 -IFORM: VPMOVZXBD_YMMi32_MASKmskw_XMMi8_AVX512 +PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL128 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 IMM0:r:b +IFORM: VPSLLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 } { -ICLASS: VPMOVZXBD +ICLASS: VPSLLW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E5 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM -PATTERN: EVV 0x31 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM() -OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8 -IFORM: VPMOVZXBD_YMMi32_MASKmskw_MEMi8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 MODRM() VL128 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_N3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 IMM0:r:b +IFORM: VPSLLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 } -# EMITTING VPMOVZXBQ (VPMOVZXBQ-128-1) +# EMITTING VPSLLW (VPSLLW-256-1) { -ICLASS: VPMOVZXBQ +ICLASS: VPSLLW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E5 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x32 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 -IFORM: VPMOVZXBQ_XMMi64_MASKmskw_XMMi8_AVX512 +PATTERN: EVV 0xF1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSLLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 } { -ICLASS: VPMOVZXBQ +ICLASS: VPSLLW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E5 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM -PATTERN: EVV 0x32 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM() -OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:wrd:i8 -IFORM: VPMOVZXBQ_XMMi64_MASKmskw_MEMi8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xF1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_MEM128() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:dq:u16 +IFORM: VPSLLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 } -# EMITTING VPMOVZXBQ (VPMOVZXBQ-256-1) +# EMITTING VPSLLW (VPSLLW-256-3) { -ICLASS: VPMOVZXBQ +ICLASS: VPSLLW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E5 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x32 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 -IFORM: VPMOVZXBQ_YMMi64_MASKmskw_XMMi8_AVX512 +PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL256 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 IMM0:r:b +IFORM: VPSLLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 } { -ICLASS: VPMOVZXBQ +ICLASS: VPSLLW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E5 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM -PATTERN: EVV 0x32 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM() -OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i8 -IFORM: VPMOVZXBQ_YMMi64_MASKmskw_MEMi8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 MODRM() VL256 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_N3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 IMM0:r:b +IFORM: VPSLLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 } -# EMITTING VPMOVZXBW (VPMOVZXBW-128-1) +# EMITTING VPSLLW (VPSLLW-512-1) { -ICLASS: VPMOVZXBW +ICLASS: VPSLLW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E5 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x30 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 -IFORM: VPMOVZXBW_XMMi16_MASKmskw_XMMi8_AVX512 +PATTERN: EVV 0xF1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 } { -ICLASS: VPMOVZXBW +ICLASS: VPSLLW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E5 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM -PATTERN: EVV 0x30 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM() -OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8 -IFORM: VPMOVZXBW_XMMi16_MASKmskw_MEMi8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xF1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_MEM128() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:dq:u16 +IFORM: VPSLLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 } -# EMITTING VPMOVZXBW (VPMOVZXBW-256-1) +# EMITTING VPSLLW (VPSLLW-512-2) { -ICLASS: VPMOVZXBW +ICLASS: VPSLLW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E5 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x30 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 -IFORM: VPMOVZXBW_YMMi16_MASKmskw_XMMi8_AVX512 +PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL512 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 IMM0:r:b +IFORM: VPSLLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 } { -ICLASS: VPMOVZXBW +ICLASS: VPSLLW CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E5 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM -PATTERN: EVV 0x30 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM() -OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i8 -IFORM: VPMOVZXBW_YMMi16_MASKmskw_MEMi8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 MODRM() VL512 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_N3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 IMM0:r:b +IFORM: VPSLLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 } -# EMITTING VPMOVZXBW (VPMOVZXBW-512-1) +# EMITTING VPSRAD (VPSRAD-128-1) { -ICLASS: VPMOVZXBW +ICLASS: VPSRAD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E5 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x30 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR -OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i8 -IFORM: VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512 +PATTERN: EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSRAD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 } { -ICLASS: VPMOVZXBW +ICLASS: VPSRAD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E5 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM -PATTERN: EVV 0x30 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM() -OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i8 -IFORM: VPMOVZXBW_ZMMi16_MASKmskw_MEMi8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_32_BITS() NELEM_MEM128() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:dq:u32 +IFORM: VPSRAD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 } -# EMITTING VPMOVZXDQ (VPMOVZXDQ-128-1) +# EMITTING VPSRAD (VPSRAD-128-3) { -ICLASS: VPMOVZXDQ +ICLASS: VPSRAD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E5 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x35 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 -IFORM: VPMOVZXDQ_XMMi64_MASKmskw_XMMi32_AVX512 +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL128 W0 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b +IFORM: VPSRAD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 } { -ICLASS: VPMOVZXDQ +ICLASS: VPSRAD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E5 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM -PATTERN: EVV 0x35 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM() -OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i32 -IFORM: VPMOVZXDQ_XMMi64_MASKmskw_MEMi32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSRAD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 } -# EMITTING VPMOVZXDQ (VPMOVZXDQ-256-1) +# EMITTING VPSRAD (VPSRAD-256-1) { -ICLASS: VPMOVZXDQ +ICLASS: VPSRAD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E5 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x35 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 -IFORM: VPMOVZXDQ_YMMi64_MASKmskw_XMMi32_AVX512 +PATTERN: EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSRAD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 } { -ICLASS: VPMOVZXDQ +ICLASS: VPSRAD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E5 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM -PATTERN: EVV 0x35 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM() -OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i32 -IFORM: VPMOVZXDQ_YMMi64_MASKmskw_MEMi32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_32_BITS() NELEM_MEM128() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:dq:u32 +IFORM: VPSRAD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 } -# EMITTING VPMOVZXWD (VPMOVZXWD-128-1) +# EMITTING VPSRAD (VPSRAD-256-3) { -ICLASS: VPMOVZXWD +ICLASS: VPSRAD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E5 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x33 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 -IFORM: VPMOVZXWD_XMMi32_MASKmskw_XMMi16_AVX512 +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b +IFORM: VPSRAD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 } { -ICLASS: VPMOVZXWD +ICLASS: VPSRAD CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E5 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM -PATTERN: EVV 0x33 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() -OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i16 -IFORM: VPMOVZXWD_XMMi32_MASKmskw_MEMi16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSRAD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 } -# EMITTING VPMOVZXWD (VPMOVZXWD-256-1) +# EMITTING VPSRAQ (VPSRAQ-128-1) { -ICLASS: VPMOVZXWD +ICLASS: VPSRAQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E5 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x33 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 -IFORM: VPMOVZXWD_YMMi32_MASKmskw_XMMi16_AVX512 +PATTERN: EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 } { -ICLASS: VPMOVZXWD +ICLASS: VPSRAQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E5 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM -PATTERN: EVV 0x33 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() -OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i16 -IFORM: VPMOVZXWD_YMMi32_MASKmskw_MEMi16_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_64_BITS() NELEM_MEM128() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:dq:u64 +IFORM: VPSRAQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 } -# EMITTING VPMOVZXWQ (VPMOVZXWQ-128-1) +# EMITTING VPSRAQ (VPSRAQ-128-2) { -ICLASS: VPMOVZXWQ +ICLASS: VPSRAQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E5 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x34 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 -IFORM: VPMOVZXWQ_XMMi64_MASKmskw_XMMi16_AVX512 +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 IMM0:r:b +IFORM: VPSRAQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 } { -ICLASS: VPMOVZXWQ +ICLASS: VPSRAQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E5 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM -PATTERN: EVV 0x34 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM() -OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i16 -IFORM: VPMOVZXWQ_XMMi64_MASKmskw_MEMi16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPSRAQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 } -# EMITTING VPMOVZXWQ (VPMOVZXWQ-256-1) +# EMITTING VPSRAQ (VPSRAQ-256-1) { -ICLASS: VPMOVZXWQ +ICLASS: VPSRAQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E5 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x34 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 -IFORM: VPMOVZXWQ_YMMi64_MASKmskw_XMMi16_AVX512 +PATTERN: EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 } { -ICLASS: VPMOVZXWQ +ICLASS: VPSRAQ CPL: 3 -CATEGORY: DATAXFER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E5 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM -PATTERN: EVV 0x34 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM() -OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i16 -IFORM: VPMOVZXWQ_YMMi64_MASKmskw_MEMi16_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_64_BITS() NELEM_MEM128() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:dq:u64 +IFORM: VPSRAQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 } -# EMITTING VPMULDQ (VPMULDQ-128-1) +# EMITTING VPSRAQ (VPSRAQ-256-2) { -ICLASS: VPMULDQ +ICLASS: VPSRAQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 REG3=XMM_B3():r:dq:i32 -IFORM: VPMULDQ_XMMi64_MASKmskw_XMMi32_XMMi32_AVX512 +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VPSRAQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 } { -ICLASS: VPMULDQ +ICLASS: VPSRAQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 MEM0:r:vv:i32:TXT=BCASTSTR -IFORM: VPMULDQ_XMMi64_MASKmskw_XMMi32_MEMi32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPSRAQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 } -# EMITTING VPMULDQ (VPMULDQ-256-1) +# EMITTING VPSRAVD (VPSRAVD-128-1) { -ICLASS: VPMULDQ +ICLASS: VPSRAVD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 REG3=YMM_B3():r:qq:i32 -IFORM: VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512 +PATTERN: EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSRAVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 } { -ICLASS: VPMULDQ +ICLASS: VPSRAVD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 MEM0:r:vv:i32:TXT=BCASTSTR -IFORM: VPMULDQ_YMMi64_MASKmskw_YMMi32_MEMi32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSRAVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 } -# EMITTING VPMULHRSW (VPMULHRSW-128-1) +# EMITTING VPSRAVD (VPSRAVD-256-1) { -ICLASS: VPMULHRSW +ICLASS: VPSRAVD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x0B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 -OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 -IFORM: VPMULHRSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 +PATTERN: EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPSRAVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 } { -ICLASS: VPMULHRSW +ICLASS: VPSRAVD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x0B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 -IFORM: VPMULHRSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSRAVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 } -# EMITTING VPMULHRSW (VPMULHRSW-256-1) +# EMITTING VPSRAVQ (VPSRAVQ-128-1) { -ICLASS: VPMULHRSW +ICLASS: VPSRAVQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x0B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 -OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 -IFORM: VPMULHRSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 +PATTERN: EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 } { -ICLASS: VPMULHRSW +ICLASS: VPSRAVQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x0B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 -IFORM: VPMULHRSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSRAVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 } -# EMITTING VPMULHRSW (VPMULHRSW-512-1) +# EMITTING VPSRAVQ (VPSRAVQ-256-1) { -ICLASS: VPMULHRSW +ICLASS: VPSRAVQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x0B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 -OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 -IFORM: VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 +PATTERN: EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 } { -ICLASS: VPMULHRSW +ICLASS: VPSRAVQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x0B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 -IFORM: VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSRAVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 } -# EMITTING VPMULHUW (VPMULHUW-128-1) +# EMITTING VPSRAVW (VPSRAVW-128-1) { -ICLASS: VPMULHUW +ICLASS: VPSRAVW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -61292,13 +65973,13 @@ ISA_SET: AVX512BW_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xE4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +PATTERN: EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 -IFORM: VPMULHUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +IFORM: VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 } { -ICLASS: VPMULHUW +ICLASS: VPSRAVW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -61306,15 +65987,15 @@ ISA_SET: AVX512BW_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xE4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +PATTERN: EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 -IFORM: VPMULHUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +IFORM: VPSRAVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 } -# EMITTING VPMULHUW (VPMULHUW-256-1) +# EMITTING VPSRAVW (VPSRAVW-256-1) { -ICLASS: VPMULHUW +ICLASS: VPSRAVW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -61322,13 +66003,13 @@ ISA_SET: AVX512BW_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xE4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +PATTERN: EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 -IFORM: VPMULHUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +IFORM: VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 } { -ICLASS: VPMULHUW +ICLASS: VPSRAVW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -61336,15 +66017,15 @@ ISA_SET: AVX512BW_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xE4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +PATTERN: EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 -IFORM: VPMULHUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +IFORM: VPSRAVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 } -# EMITTING VPMULHUW (VPMULHUW-512-1) +# EMITTING VPSRAVW (VPSRAVW-512-1) { -ICLASS: VPMULHUW +ICLASS: VPSRAVW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -61352,13 +66033,13 @@ ISA_SET: AVX512BW_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xE4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +PATTERN: EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 -IFORM: VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +IFORM: VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 } { -ICLASS: VPMULHUW +ICLASS: VPSRAVW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -61366,525 +66047,522 @@ ISA_SET: AVX512BW_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xE4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +PATTERN: EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 -IFORM: VPMULHUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +IFORM: VPSRAVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 } -# EMITTING VPMULHW (VPMULHW-128-1) +# EMITTING VPSRAW (VPSRAW-128-1) { -ICLASS: VPMULHW +ICLASS: VPSRAW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xE5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +PATTERN: EVV 0xE1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 -IFORM: VPMULHW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +IFORM: VPSRAW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 } { -ICLASS: VPMULHW +ICLASS: VPSRAW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xE5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xE1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_MEM128() OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 -IFORM: VPMULHW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +IFORM: VPSRAW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 } -# EMITTING VPMULHW (VPMULHW-256-1) +# EMITTING VPSRAW (VPSRAW-128-2) { -ICLASS: VPMULHW +ICLASS: VPSRAW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 +ISA_SET: AVX512BW_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xE5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 -OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 -IFORM: VPMULHW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL128 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 IMM0:r:b +IFORM: VPSRAW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 } { -ICLASS: VPMULHW +ICLASS: VPSRAW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 +ISA_SET: AVX512BW_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xE5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 -IFORM: VPMULHW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] BCRC=0 MODRM() VL128 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_N3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 IMM0:r:b +IFORM: VPSRAW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 } -# EMITTING VPMULHW (VPMULHW-512-1) +# EMITTING VPSRAW (VPSRAW-256-1) { -ICLASS: VPMULHW +ICLASS: VPSRAW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xE5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 -OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 -IFORM: VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +PATTERN: EVV 0xE1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSRAW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 } { -ICLASS: VPMULHW +ICLASS: VPSRAW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xE5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 -IFORM: VPMULHW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xE1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_MEM128() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:dq:u16 +IFORM: VPSRAW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 } -# EMITTING VPMULLD (VPMULLD-128-1) +# EMITTING VPSRAW (VPSRAW-256-2) { -ICLASS: VPMULLD +ICLASS: VPSRAW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512BW_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 -IFORM: VPMULLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL256 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 IMM0:r:b +IFORM: VPSRAW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 } { -ICLASS: VPMULLD +ICLASS: VPSRAW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512BW_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPMULLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] BCRC=0 MODRM() VL256 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_N3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 IMM0:r:b +IFORM: VPSRAW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 } -# EMITTING VPMULLD (VPMULLD-256-1) +# EMITTING VPSRAW (VPSRAW-512-1) { -ICLASS: VPMULLD +ICLASS: VPSRAW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 -IFORM: VPMULLD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +PATTERN: EVV 0xE1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 } { -ICLASS: VPMULLD +ICLASS: VPSRAW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPMULLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xE1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_MEM128() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:dq:u16 +IFORM: VPSRAW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 } -# EMITTING VPMULLQ (VPMULLQ-128-1) +# EMITTING VPSRAW (VPSRAW-512-2) { -ICLASS: VPMULLQ +ICLASS: VPSRAW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128 +ISA_SET: AVX512BW_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 -IFORM: VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL512 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 IMM0:r:b +IFORM: VPSRAW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 } { -ICLASS: VPMULLQ +ICLASS: VPSRAW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128 +ISA_SET: AVX512BW_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPMULLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] BCRC=0 MODRM() VL512 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_N3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 IMM0:r:b +IFORM: VPSRAW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 } -# EMITTING VPMULLQ (VPMULLQ-256-1) +# EMITTING VPSRLD (VPSRLD-128-1) { -ICLASS: VPMULLQ +ICLASS: VPSRLD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 -IFORM: VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +PATTERN: EVV 0xD2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 } { -ICLASS: VPMULLQ +ICLASS: VPSRLD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPMULLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xD2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_32_BITS() NELEM_MEM128() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:dq:u32 +IFORM: VPSRLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 } -# EMITTING VPMULLQ (VPMULLQ-512-1) +# EMITTING VPSRLD (VPSRLD-128-2) { -ICLASS: VPMULLQ +ICLASS: VPSRLD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 -IFORM: VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL128 W0 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b +IFORM: VPSRLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 } { -ICLASS: VPMULLQ +ICLASS: VPSRLD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPMULLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSRLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 } -# EMITTING VPMULLW (VPMULLW-128-1) +# EMITTING VPSRLD (VPSRLD-256-1) { -ICLASS: VPMULLW +ICLASS: VPSRLD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xD5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 -OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 -IFORM: VPMULLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +PATTERN: EVV 0xD2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 } { -ICLASS: VPMULLW +ICLASS: VPSRLD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xD5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 -IFORM: VPMULLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xD2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_32_BITS() NELEM_MEM128() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:dq:u32 +IFORM: VPSRLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 } -# EMITTING VPMULLW (VPMULLW-256-1) +# EMITTING VPSRLD (VPSRLD-256-2) { -ICLASS: VPMULLW +ICLASS: VPSRLD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xD5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 -OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 -IFORM: VPMULLW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b +IFORM: VPSRLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 } { -ICLASS: VPMULLW +ICLASS: VPSRLD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xD5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 -IFORM: VPMULLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSRLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 } -# EMITTING VPMULLW (VPMULLW-512-1) +# EMITTING VPSRLDQ (VPSRLDQ-128-1) { -ICLASS: VPMULLW +ICLASS: VPSRLDQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xD5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 -OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 -IFORM: VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b011] RM[nnn] VL128 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u8 REG1=XMM_B3():r:dq:u8 IMM0:r:b +IFORM: VPSRLDQ_XMMu8_XMMu8_IMM8_AVX512 } { -ICLASS: VPMULLW +ICLASS: VPSRLDQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xD5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 -IFORM: VPMULLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b011] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_N3():w:dq:u8 MEM0:r:dq:u8 IMM0:r:b +IFORM: VPSRLDQ_XMMu8_MEMu8_IMM8_AVX512 } -# EMITTING VPMULUDQ (VPMULUDQ-128-1) +# EMITTING VPSRLDQ (VPSRLDQ-256-1) { -ICLASS: VPMULUDQ +ICLASS: VPSRLDQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xF4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 -IFORM: VPMULUDQ_XMMu64_MASKmskw_XMMu32_XMMu32_AVX512 +PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b011] RM[nnn] VL256 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u8 REG1=YMM_B3():r:qq:u8 IMM0:r:b +IFORM: VPSRLDQ_YMMu8_YMMu8_IMM8_AVX512 } { -ICLASS: VPMULUDQ +ICLASS: VPSRLDQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xF4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPMULUDQ_XMMu64_MASKmskw_XMMu32_MEMu32_AVX512 +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b011] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_N3():w:qq:u8 MEM0:r:qq:u8 IMM0:r:b +IFORM: VPSRLDQ_YMMu8_MEMu8_IMM8_AVX512 } -# EMITTING VPMULUDQ (VPMULUDQ-256-1) +# EMITTING VPSRLDQ (VPSRLDQ-512-1) { -ICLASS: VPMULUDQ +ICLASS: VPSRLDQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xF4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 -IFORM: VPMULUDQ_YMMu64_MASKmskw_YMMu32_YMMu32_AVX512 +PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b011] RM[nnn] VL512 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu8 REG1=ZMM_B3():r:zu8 IMM0:r:b +IFORM: VPSRLDQ_ZMMu8_ZMMu8_IMM8_AVX512 } { -ICLASS: VPMULUDQ +ICLASS: VPSRLDQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xF4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPMULUDQ_YMMu64_MASKmskw_YMMu32_MEMu32_AVX512 +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b011] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_N3():w:zu8 MEM0:r:zd:u8 IMM0:r:b +IFORM: VPSRLDQ_ZMMu8_MEMu8_IMM8_AVX512 } -# EMITTING VPORD (VPORD-128-1) +# EMITTING VPSRLQ (VPSRLQ-128-1) { -ICLASS: VPORD +ICLASS: VPSRLQ CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 -IFORM: VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +PATTERN: EVV 0xD3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 } { -ICLASS: VPORD +ICLASS: VPSRLQ CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xD3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_64_BITS() NELEM_MEM128() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:dq:u64 +IFORM: VPSRLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 } -# EMITTING VPORD (VPORD-256-1) +# EMITTING VPSRLQ (VPSRLQ-128-2) { -ICLASS: VPORD +ICLASS: VPSRLQ CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 -IFORM: VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 IMM0:r:b +IFORM: VPSRLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 } { -ICLASS: VPORD +ICLASS: VPSRLQ CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPSRLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 } -# EMITTING VPORQ (VPORQ-128-1) +# EMITTING VPSRLQ (VPSRLQ-256-1) { -ICLASS: VPORQ +ICLASS: VPSRLQ CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 -IFORM: VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +PATTERN: EVV 0xD3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 } { -ICLASS: VPORQ +ICLASS: VPSRLQ CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xD3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_64_BITS() NELEM_MEM128() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:dq:u64 +IFORM: VPSRLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 } -# EMITTING VPORQ (VPORQ-256-1) +# EMITTING VPSRLQ (VPSRLQ-256-2) { -ICLASS: VPORQ +ICLASS: VPSRLQ CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 -IFORM: VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VPSRLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 } { -ICLASS: VPORQ +ICLASS: VPSRLQ CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPSRLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 } -# EMITTING VPROLD (VPROLD-128-1) +# EMITTING VPSRLVD (VPSRLVD-128-1) { -ICLASS: VPROLD +ICLASS: VPSRLVD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -61892,13 +66570,13 @@ ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL128 W0 UIMM8() -OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b -IFORM: VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 +PATTERN: EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSRLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 } { -ICLASS: VPROLD +ICLASS: VPSRLVD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -61906,15 +66584,15 @@ ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b -IFORM: VPROLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 +PATTERN: EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSRLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 } -# EMITTING VPROLD (VPROLD-256-1) +# EMITTING VPSRLVD (VPSRLVD-256-1) { -ICLASS: VPROLD +ICLASS: VPSRLVD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -61922,13 +66600,13 @@ ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL256 W0 UIMM8() -OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b -IFORM: VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 +PATTERN: EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPSRLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 } { -ICLASS: VPROLD +ICLASS: VPSRLVD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -61936,15 +66614,15 @@ ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b -IFORM: VPROLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 +PATTERN: EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSRLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 } -# EMITTING VPROLQ (VPROLQ-128-1) +# EMITTING VPSRLVQ (VPSRLVQ-128-1) { -ICLASS: VPROLQ +ICLASS: VPSRLVQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -61952,13 +66630,13 @@ ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL128 W1 UIMM8() -OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 IMM0:r:b -IFORM: VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 +PATTERN: EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSRLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 } { -ICLASS: VPROLQ +ICLASS: VPSRLVQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -61966,15 +66644,15 @@ ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b -IFORM: VPROLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 +PATTERN: EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSRLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 } -# EMITTING VPROLQ (VPROLQ-256-1) +# EMITTING VPSRLVQ (VPSRLVQ-256-1) { -ICLASS: VPROLQ +ICLASS: VPSRLVQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -61982,13 +66660,13 @@ ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL256 W1 UIMM8() -OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b -IFORM: VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 +PATTERN: EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPSRLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 } { -ICLASS: VPROLQ +ICLASS: VPSRLVQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -61996,1817 +66674,1845 @@ ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b -IFORM: VPROLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 +PATTERN: EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSRLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 } -# EMITTING VPROLVD (VPROLVD-128-1) +# EMITTING VPSRLVW (VPSRLVW-128-1) { -ICLASS: VPROLVD +ICLASS: VPSRLVW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512BW_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 -IFORM: VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +PATTERN: EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 } { -ICLASS: VPROLVD +ICLASS: VPSRLVW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512BW_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPROLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPSRLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 } -# EMITTING VPROLVD (VPROLVD-256-1) +# EMITTING VPSRLVW (VPSRLVW-256-1) { -ICLASS: VPROLVD +ICLASS: VPSRLVW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 +ISA_SET: AVX512BW_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 -IFORM: VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +PATTERN: EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 } { -ICLASS: VPROLVD +ICLASS: VPSRLVW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 +ISA_SET: AVX512BW_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPROLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPSRLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 } -# EMITTING VPROLVQ (VPROLVQ-128-1) +# EMITTING VPSRLVW (VPSRLVW-512-1) { -ICLASS: VPROLVQ +ICLASS: VPSRLVW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512BW_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 -IFORM: VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +PATTERN: EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 } { -ICLASS: VPROLVQ +ICLASS: VPSRLVW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512BW_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPROLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPSRLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 } -# EMITTING VPROLVQ (VPROLVQ-256-1) +# EMITTING VPSRLW (VPSRLW-128-1) { -ICLASS: VPROLVQ +ICLASS: VPSRLW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 -IFORM: VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +PATTERN: EVV 0xD1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSRLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 } { -ICLASS: VPROLVQ +ICLASS: VPSRLW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPROLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xD1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_MEM128() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPSRLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 } -# EMITTING VPRORD (VPRORD-128-1) +# EMITTING VPSRLW (VPSRLW-128-2) { -ICLASS: VPRORD +ICLASS: VPSRLW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512BW_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL128 W0 UIMM8() -OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b -IFORM: VPRORD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 +PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL128 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 IMM0:r:b +IFORM: VPSRLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 } { -ICLASS: VPRORD +ICLASS: VPSRLW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512BW_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b -IFORM: VPRORD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 MODRM() VL128 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_N3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 IMM0:r:b +IFORM: VPSRLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 } -# EMITTING VPRORD (VPRORD-256-1) +# EMITTING VPSRLW (VPSRLW-256-1) { -ICLASS: VPRORD +ICLASS: VPSRLW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL256 W0 UIMM8() -OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b -IFORM: VPRORD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 +PATTERN: EVV 0xD1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 } { -ICLASS: VPRORD +ICLASS: VPSRLW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b -IFORM: VPRORD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xD1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_MEM128() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:dq:u16 +IFORM: VPSRLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 } -# EMITTING VPRORQ (VPRORQ-128-1) +# EMITTING VPSRLW (VPSRLW-256-2) { -ICLASS: VPRORQ +ICLASS: VPSRLW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512BW_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL128 W1 UIMM8() -OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 IMM0:r:b -IFORM: VPRORQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 +PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL256 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 IMM0:r:b +IFORM: VPSRLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 } { -ICLASS: VPRORQ +ICLASS: VPSRLW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512BW_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b -IFORM: VPRORQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 MODRM() VL256 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_N3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 IMM0:r:b +IFORM: VPSRLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 } -# EMITTING VPRORQ (VPRORQ-256-1) +# EMITTING VPSRLW (VPSRLW-512-1) { -ICLASS: VPRORQ +ICLASS: VPSRLW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL256 W1 UIMM8() -OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b -IFORM: VPRORQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 +PATTERN: EVV 0xD1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 } { -ICLASS: VPRORQ +ICLASS: VPSRLW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b -IFORM: VPRORQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xD1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_MEM128() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:dq:u16 +IFORM: VPSRLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 } -# EMITTING VPRORVD (VPRORVD-128-1) +# EMITTING VPSRLW (VPSRLW-512-2) { -ICLASS: VPRORVD +ICLASS: VPSRLW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512BW_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 -IFORM: VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL512 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 IMM0:r:b +IFORM: VPSRLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 } { -ICLASS: VPRORVD +ICLASS: VPSRLW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512BW_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPRORVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 MODRM() VL512 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_N3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 IMM0:r:b +IFORM: VPSRLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 } -# EMITTING VPRORVD (VPRORVD-256-1) +# EMITTING VPSUBB (VPSUBB-128-1) { -ICLASS: VPRORVD +ICLASS: VPSUBB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 +ISA_SET: AVX512BW_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 -IFORM: VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +PATTERN: EVV 0xF8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPSUBB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 } { -ICLASS: VPRORVD +ICLASS: VPSUBB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 +ISA_SET: AVX512BW_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPRORVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xF8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPSUBB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 } -# EMITTING VPRORVQ (VPRORVQ-128-1) +# EMITTING VPSUBB (VPSUBB-256-1) { -ICLASS: VPRORVQ +ICLASS: VPSUBB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512BW_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 -IFORM: VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +PATTERN: EVV 0xF8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPSUBB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 } { -ICLASS: VPRORVQ +ICLASS: VPSUBB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512BW_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPRORVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xF8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPSUBB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 } -# EMITTING VPRORVQ (VPRORVQ-256-1) +# EMITTING VPSUBB (VPSUBB-512-1) { -ICLASS: VPRORVQ +ICLASS: VPSUBB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 +ISA_SET: AVX512BW_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 -IFORM: VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +PATTERN: EVV 0xF8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 } { -ICLASS: VPRORVQ +ICLASS: VPSUBB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 +ISA_SET: AVX512BW_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPRORVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xF8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPSUBB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 } -# EMITTING VPSADBW (VPSADBW-128-1) +# EMITTING VPSUBD (VPSUBD-128-1) { -ICLASS: VPSADBW +ICLASS: VPSUBD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -PATTERN: EVV 0xF6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 -OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=XMM_N3():r:dq:u8 REG2=XMM_B3():r:dq:u8 -IFORM: VPSADBW_XMMu16_XMMu8_XMMu8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xFA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSUBD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 } { -ICLASS: VPSADBW +ICLASS: VPSUBD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: DISP8_FULLMEM -PATTERN: EVV 0xF6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=XMM_N3():r:dq:u8 MEM0:r:dq:u8 -IFORM: VPSADBW_XMMu16_XMMu8_MEMu8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xFA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSUBD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 } -# EMITTING VPSADBW (VPSADBW-256-1) +# EMITTING VPSUBD (VPSUBD-256-1) { -ICLASS: VPSADBW +ICLASS: VPSUBD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -PATTERN: EVV 0xF6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 MASK=0 -OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=YMM_N3():r:qq:u8 REG2=YMM_B3():r:qq:u8 -IFORM: VPSADBW_YMMu16_YMMu8_YMMu8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xFA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPSUBD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 } { -ICLASS: VPSADBW +ICLASS: VPSUBD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: DISP8_FULLMEM -PATTERN: EVV 0xF6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=YMM_N3():r:qq:u8 MEM0:r:qq:u8 -IFORM: VPSADBW_YMMu16_YMMu8_MEMu8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xFA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSUBD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 } -# EMITTING VPSADBW (VPSADBW-512-1) +# EMITTING VPSUBQ (VPSUBQ-128-1) { -ICLASS: VPSADBW +ICLASS: VPSUBQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -PATTERN: EVV 0xF6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 MASK=0 -OPERANDS: REG0=ZMM_R3():w:zu16 REG1=ZMM_N3():r:zu8 REG2=ZMM_B3():r:zu8 -IFORM: VPSADBW_ZMMu16_ZMMu8_ZMMu8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xFB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSUBQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 } { -ICLASS: VPSADBW +ICLASS: VPSUBQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: DISP8_FULLMEM -PATTERN: EVV 0xF6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zu16 REG1=ZMM_N3():r:zu8 MEM0:r:zd:u8 -IFORM: VPSADBW_ZMMu16_ZMMu8_MEMu8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xFB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSUBQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 } -# EMITTING VPSCATTERDD (VPSCATTERDD-128-1) +# EMITTING VPSUBQ (VPSUBQ-256-1) { -ICLASS: VPSCATTERDD +ICLASS: VPSUBQ CPL: 3 -CATEGORY: SCATTER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E12 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W0 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() -OPERANDS: MEM0:w:dq:u32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:u32 -IFORM: VPSCATTERDD_MEMu32_MASKmskw_XMMu32_AVX512_VL128 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xFB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPSUBQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 } - -# EMITTING VPSCATTERDD (VPSCATTERDD-256-1) { -ICLASS: VPSCATTERDD +ICLASS: VPSUBQ CPL: 3 -CATEGORY: SCATTER +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E12 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W0 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() -OPERANDS: MEM0:w:qq:u32 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:u32 -IFORM: VPSCATTERDD_MEMu32_MASKmskw_YMMu32_AVX512_VL256 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xFB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSUBQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 } -# EMITTING VPSCATTERDQ (VPSCATTERDQ-128-1) +# EMITTING VPSUBSB (VPSUBSB-128-1) { -ICLASS: VPSCATTERDQ +ICLASS: VPSUBSB CPL: 3 -CATEGORY: SCATTER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E12 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W1 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() -OPERANDS: MEM0:w:dq:u64 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:u64 -IFORM: VPSCATTERDQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 REG3=XMM_B3():r:dq:i8 +IFORM: VPSUBSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 } - -# EMITTING VPSCATTERDQ (VPSCATTERDQ-256-1) { -ICLASS: VPSCATTERDQ +ICLASS: VPSUBSB CPL: 3 -CATEGORY: SCATTER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E12 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W1 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() -OPERANDS: MEM0:w:qq:u64 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:u64 -IFORM: VPSCATTERDQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 MEM0:r:dq:i8 +IFORM: VPSUBSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 } -# EMITTING VPSCATTERQD (VPSCATTERQD-128-1) +# EMITTING VPSUBSB (VPSUBSB-256-1) { -ICLASS: VPSCATTERQD +ICLASS: VPSUBSB CPL: 3 -CATEGORY: SCATTER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E12 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W0 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() -OPERANDS: MEM0:w:q:u32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:u32 -IFORM: VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 REG3=YMM_B3():r:qq:i8 +IFORM: VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 } - -# EMITTING VPSCATTERQD (VPSCATTERQD-256-1) { -ICLASS: VPSCATTERQD +ICLASS: VPSUBSB CPL: 3 -CATEGORY: SCATTER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E12 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W0 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() -OPERANDS: MEM0:w:dq:u32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:u32 -IFORM: VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL256 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 MEM0:r:qq:i8 +IFORM: VPSUBSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 } -# EMITTING VPSCATTERQQ (VPSCATTERQQ-128-1) +# EMITTING VPSUBSB (VPSUBSB-512-1) { -ICLASS: VPSCATTERQQ +ICLASS: VPSUBSB CPL: 3 -CATEGORY: SCATTER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E12 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W1 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() -OPERANDS: MEM0:w:dq:u64 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:u64 -IFORM: VPSCATTERQQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 REG3=ZMM_B3():r:zi8 +IFORM: VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 } - -# EMITTING VPSCATTERQQ (VPSCATTERQQ-256-1) { -ICLASS: VPSCATTERQQ +ICLASS: VPSUBSB CPL: 3 -CATEGORY: SCATTER +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E12 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() -OPERANDS: MEM0:w:qq:u64 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:u64 -IFORM: VPSCATTERQQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 MEM0:r:zd:i8 +IFORM: VPSUBSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 } -# EMITTING VPSHUFB (VPSHUFB-128-1) +# EMITTING VPSUBSW (VPSUBSW-128-1) { -ICLASS: VPSHUFB +ICLASS: VPSUBSW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x00 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 -OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 -IFORM: VPSHUFB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +PATTERN: EVV 0xE9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 +IFORM: VPSUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 } { -ICLASS: VPSHUFB +ICLASS: VPSUBSW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x00 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 -IFORM: VPSHUFB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 +IFORM: VPSUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 } -# EMITTING VPSHUFB (VPSHUFB-256-1) +# EMITTING VPSUBSW (VPSUBSW-256-1) { -ICLASS: VPSHUFB +ICLASS: VPSUBSW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x00 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 -OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 -IFORM: VPSHUFB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +PATTERN: EVV 0xE9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 +IFORM: VPSUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 } { -ICLASS: VPSHUFB +ICLASS: VPSUBSW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x00 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 -IFORM: VPSHUFB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 +IFORM: VPSUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 } -# EMITTING VPSHUFB (VPSHUFB-512-1) +# EMITTING VPSUBSW (VPSUBSW-512-1) { -ICLASS: VPSHUFB +ICLASS: VPSUBSW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x00 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 -OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 -IFORM: VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +PATTERN: EVV 0xE9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 +IFORM: VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 } { -ICLASS: VPSHUFB +ICLASS: VPSUBSW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x00 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 -IFORM: VPSHUFB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 +IFORM: VPSUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 } -# EMITTING VPSHUFD (VPSHUFD-128-1) +# EMITTING VPSUBUSB (VPSUBUSB-128-1) { -ICLASS: VPSHUFD +ICLASS: VPSUBUSB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x70 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b -IFORM: VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 +PATTERN: EVV 0xD8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPSUBUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 } { -ICLASS: VPSHUFD +ICLASS: VPSUBUSB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x70 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b -IFORM: VPSHUFD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xD8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPSUBUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 } -# EMITTING VPSHUFD (VPSHUFD-256-1) +# EMITTING VPSUBUSB (VPSUBUSB-256-1) { -ICLASS: VPSHUFD +ICLASS: VPSUBUSB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x70 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b -IFORM: VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 +PATTERN: EVV 0xD8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPSUBUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 } { -ICLASS: VPSHUFD +ICLASS: VPSUBUSB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x70 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b -IFORM: VPSHUFD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xD8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPSUBUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 } -# EMITTING VPSHUFHW (VPSHUFHW-128-1) +# EMITTING VPSUBUSB (VPSUBUSB-512-1) { -ICLASS: VPSHUFHW +ICLASS: VPSUBUSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPSUBUSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xD8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPSUBUSW (VPSUBUSW-128-1) +{ +ICLASS: VPSUBUSW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x70 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR UIMM8() -OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 IMM0:r:b -IFORM: VPSHUFHW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 +PATTERN: EVV 0xD9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSUBUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 } { -ICLASS: VPSHUFHW +ICLASS: VPSUBUSW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x70 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 IMM0:r:b -IFORM: VPSHUFHW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xD9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPSUBUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 } -# EMITTING VPSHUFHW (VPSHUFHW-256-1) +# EMITTING VPSUBUSW (VPSUBUSW-256-1) { -ICLASS: VPSHUFHW +ICLASS: VPSUBUSW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x70 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR UIMM8() -OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 IMM0:r:b -IFORM: VPSHUFHW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 +PATTERN: EVV 0xD9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPSUBUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 } { -ICLASS: VPSHUFHW +ICLASS: VPSUBUSW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x70 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 IMM0:r:b -IFORM: VPSHUFHW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xD9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPSUBUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 } -# EMITTING VPSHUFHW (VPSHUFHW-512-1) +# EMITTING VPSUBUSW (VPSUBUSW-512-1) { -ICLASS: VPSHUFHW +ICLASS: VPSUBUSW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x70 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR UIMM8() -OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 IMM0:r:b -IFORM: VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 +PATTERN: EVV 0xD9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 } { -ICLASS: VPSHUFHW +ICLASS: VPSUBUSW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x70 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 IMM0:r:b -IFORM: VPSHUFHW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xD9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 } -# EMITTING VPSHUFLW (VPSHUFLW-128-1) +# EMITTING VPSUBW (VPSUBW-128-1) { -ICLASS: VPSHUFLW +ICLASS: VPSUBW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x70 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR UIMM8() -OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 IMM0:r:b -IFORM: VPSHUFLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 +PATTERN: EVV 0xF9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSUBW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 } { -ICLASS: VPSHUFLW +ICLASS: VPSUBW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x70 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 IMM0:r:b -IFORM: VPSHUFLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xF9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPSUBW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 } -# EMITTING VPSHUFLW (VPSHUFLW-256-1) +# EMITTING VPSUBW (VPSUBW-256-1) { -ICLASS: VPSHUFLW +ICLASS: VPSUBW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x70 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR UIMM8() -OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 IMM0:r:b -IFORM: VPSHUFLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 +PATTERN: EVV 0xF9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPSUBW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 } { -ICLASS: VPSHUFLW +ICLASS: VPSUBW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x70 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 IMM0:r:b -IFORM: VPSHUFLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xF9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPSUBW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 } -# EMITTING VPSHUFLW (VPSHUFLW-512-1) +# EMITTING VPSUBW (VPSUBW-512-1) { -ICLASS: VPSHUFLW +ICLASS: VPSUBW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x70 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR UIMM8() -OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 IMM0:r:b -IFORM: VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 +PATTERN: EVV 0xF9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 } { -ICLASS: VPSHUFLW +ICLASS: VPSUBW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x70 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 IMM0:r:b -IFORM: VPSHUFLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xF9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPSUBW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 } -# EMITTING VPSLLD (VPSLLD-128-1) +# EMITTING VPTERNLOGD (VPTERNLOGD-128-1) { -ICLASS: VPSLLD +ICLASS: VPTERNLOGD CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xF2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 -IFORM: VPSLLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +PATTERN: EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() +OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 IMM0:r:b +IFORM: VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 } { -ICLASS: VPSLLD +ICLASS: VPTERNLOGD CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 -PATTERN: EVV 0xF2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_32_BITS() NELEM_MEM128() -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:dq:u32 -IFORM: VPSLLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPTERNLOGD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 } -# EMITTING VPSLLD (VPSLLD-128-3) +# EMITTING VPTERNLOGD (VPTERNLOGD-256-1) { -ICLASS: VPSLLD +ICLASS: VPTERNLOGD CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL128 W0 UIMM8() -OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b -IFORM: VPSLLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 +PATTERN: EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 IMM0:r:b +IFORM: VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 } { -ICLASS: VPSLLD +ICLASS: VPTERNLOGD CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b -IFORM: VPSLLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 +PATTERN: EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPTERNLOGD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 } -# EMITTING VPSLLD (VPSLLD-256-1) +# EMITTING VPTERNLOGQ (VPTERNLOGQ-128-1) { -ICLASS: VPSLLD +ICLASS: VPTERNLOGQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xF2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=XMM_B3():r:dq:u32 -IFORM: VPSLLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 +PATTERN: EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 IMM0:r:b +IFORM: VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 } { -ICLASS: VPSLLD +ICLASS: VPTERNLOGQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 -PATTERN: EVV 0xF2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_32_BITS() NELEM_MEM128() -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:dq:u32 -IFORM: VPSLLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 } -# EMITTING VPSLLD (VPSLLD-256-3) +# EMITTING VPTERNLOGQ (VPTERNLOGQ-256-1) { -ICLASS: VPSLLD +ICLASS: VPTERNLOGQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL256 W0 UIMM8() -OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b -IFORM: VPSLLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 +PATTERN: EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 } { -ICLASS: VPSLLD +ICLASS: VPTERNLOGQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b -IFORM: VPSLLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 +PATTERN: EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 } -# EMITTING VPSLLDQ (VPSLLDQ-128-2) +# EMITTING VPTESTMB (VPTESTMB-128-1) { -ICLASS: VPSLLDQ +ICLASS: VPTESTMB CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4NF -REAL_OPCODE: Y -PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b111] RM[nnn] VL128 ZEROING=0 MASK=0 UIMM8() -OPERANDS: REG0=XMM_N3():w:dq:u8 REG1=XMM_B3():r:dq:u8 IMM0:r:b -IFORM: VPSLLDQ_XMMu8_XMMu8_IMM8_AVX512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPTESTMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 } { -ICLASS: VPSLLDQ +ICLASS: VPTESTMB CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: DISP8_FULLMEM -PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b111] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_N3():w:dq:u8 MEM0:r:dq:u8 IMM0:r:b -IFORM: VPSLLDQ_XMMu8_MEMu8_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPTESTMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 } -# EMITTING VPSLLDQ (VPSLLDQ-256-2) +# EMITTING VPTESTMB (VPTESTMB-256-1) { -ICLASS: VPSLLDQ +ICLASS: VPTESTMB CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b111] RM[nnn] VL256 ZEROING=0 MASK=0 UIMM8() -OPERANDS: REG0=YMM_N3():w:qq:u8 REG1=YMM_B3():r:qq:u8 IMM0:r:b -IFORM: VPSLLDQ_YMMu8_YMMu8_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 } { -ICLASS: VPSLLDQ +ICLASS: VPTESTMB CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: DISP8_FULLMEM -PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b111] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_N3():w:qq:u8 MEM0:r:qq:u8 IMM0:r:b -IFORM: VPSLLDQ_YMMu8_MEMu8_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPTESTMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 } -# EMITTING VPSLLDQ (VPSLLDQ-512-1) +# EMITTING VPTESTMB (VPTESTMB-512-1) { -ICLASS: VPSLLDQ +ICLASS: VPTESTMB CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b111] RM[nnn] VL512 ZEROING=0 MASK=0 UIMM8() -OPERANDS: REG0=ZMM_N3():w:zu8 REG1=ZMM_B3():r:zu8 IMM0:r:b -IFORM: VPSLLDQ_ZMMu8_ZMMu8_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPTESTMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 } { -ICLASS: VPSLLDQ +ICLASS: VPTESTMB CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: DISP8_FULLMEM -PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b111] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_N3():w:zu8 MEM0:r:zd:u8 IMM0:r:b -IFORM: VPSLLDQ_ZMMu8_MEMu8_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPTESTMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 } -# EMITTING VPSLLQ (VPSLLQ-128-1) +# EMITTING VPTESTMD (VPTESTMD-128-1) { -ICLASS: VPSLLQ +ICLASS: VPTESTMD CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xF3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 -IFORM: VPSLLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +PATTERN: EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPTESTMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512 } { -ICLASS: VPSLLQ +ICLASS: VPTESTMD CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 -PATTERN: EVV 0xF3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_64_BITS() NELEM_MEM128() -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:dq:u64 -IFORM: VPSLLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPTESTMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512 } -# EMITTING VPSLLQ (VPSLLQ-128-3) +# EMITTING VPTESTMD (VPTESTMD-256-1) { -ICLASS: VPSLLQ +ICLASS: VPTESTMD CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL128 W1 UIMM8() -OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 IMM0:r:b -IFORM: VPSLLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 +PATTERN: EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512 } { -ICLASS: VPSLLQ +ICLASS: VPTESTMD CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b -IFORM: VPSLLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 +PATTERN: EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPTESTMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512 } -# EMITTING VPSLLQ (VPSLLQ-256-1) +# EMITTING VPTESTMQ (VPTESTMQ-128-1) { -ICLASS: VPSLLQ +ICLASS: VPTESTMQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xF3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=XMM_B3():r:dq:u64 -IFORM: VPSLLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 +PATTERN: EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPTESTMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512 } { -ICLASS: VPSLLQ +ICLASS: VPTESTMQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 -PATTERN: EVV 0xF3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_64_BITS() NELEM_MEM128() -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:dq:u64 -IFORM: VPSLLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPTESTMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512 } -# EMITTING VPSLLQ (VPSLLQ-256-3) +# EMITTING VPTESTMQ (VPTESTMQ-256-1) { -ICLASS: VPSLLQ +ICLASS: VPTESTMQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL256 W1 UIMM8() -OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b -IFORM: VPSLLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 +PATTERN: EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPTESTMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512 } { -ICLASS: VPSLLQ +ICLASS: VPTESTMQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b -IFORM: VPSLLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 +PATTERN: EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPTESTMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512 } -# EMITTING VPSLLVD (VPSLLVD-128-1) +# EMITTING VPTESTMW (VPTESTMW-128-1) { -ICLASS: VPSLLVD +ICLASS: VPTESTMW CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512BW_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 -IFORM: VPSLLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +PATTERN: EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPTESTMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 } { -ICLASS: VPSLLVD +ICLASS: VPTESTMW CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512BW_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPSLLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPTESTMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 } -# EMITTING VPSLLVD (VPSLLVD-256-1) +# EMITTING VPTESTMW (VPTESTMW-256-1) { -ICLASS: VPSLLVD +ICLASS: VPTESTMW CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 +ISA_SET: AVX512BW_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 -IFORM: VPSLLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +PATTERN: EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPTESTMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 } { -ICLASS: VPSLLVD +ICLASS: VPTESTMW CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 +ISA_SET: AVX512BW_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPSLLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPTESTMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 } -# EMITTING VPSLLVQ (VPSLLVQ-128-1) +# EMITTING VPTESTMW (VPTESTMW-512-1) { -ICLASS: VPSLLVQ +ICLASS: VPTESTMW CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512BW_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 -IFORM: VPSLLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +PATTERN: EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 } { -ICLASS: VPSLLVQ +ICLASS: VPTESTMW CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512BW_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPSLLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPTESTMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 } -# EMITTING VPSLLVQ (VPSLLVQ-256-1) +# EMITTING VPTESTNMB (VPTESTNMB-128-1) { -ICLASS: VPSLLVQ +ICLASS: VPTESTNMB CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 +ISA_SET: AVX512BW_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 -IFORM: VPSLLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +PATTERN: EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPTESTNMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 } { -ICLASS: VPSLLVQ +ICLASS: VPTESTNMB CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 +ISA_SET: AVX512BW_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPSLLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPTESTNMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 } -# EMITTING VPSLLVW (VPSLLVW-128-1) +# EMITTING VPTESTNMB (VPTESTNMB-256-1) { -ICLASS: VPSLLVW +ICLASS: VPTESTNMB CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 +ISA_SET: AVX512BW_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 -IFORM: VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +PATTERN: EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPTESTNMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 } { -ICLASS: VPSLLVW +ICLASS: VPTESTNMB CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 +ISA_SET: AVX512BW_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 -IFORM: VPSLLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +PATTERN: EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPTESTNMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 } -# EMITTING VPSLLVW (VPSLLVW-256-1) +# EMITTING VPTESTNMB (VPTESTNMB-512-1) { -ICLASS: VPSLLVW +ICLASS: VPTESTNMB CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 +ISA_SET: AVX512BW_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 -IFORM: VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +PATTERN: EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 } { -ICLASS: VPSLLVW +ICLASS: VPTESTNMB CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 +ISA_SET: AVX512BW_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 -IFORM: VPSLLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +PATTERN: EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 } -# EMITTING VPSLLVW (VPSLLVW-512-1) +# EMITTING VPTESTNMD (VPTESTNMD-128-1) { -ICLASS: VPSLLVW +ICLASS: VPTESTNMD CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 -IFORM: VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +PATTERN: EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPTESTNMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512 } { -ICLASS: VPSLLVW +ICLASS: VPTESTNMD CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 -IFORM: VPSLLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPTESTNMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512 } -# EMITTING VPSLLW (VPSLLW-128-1) +# EMITTING VPTESTNMD (VPTESTNMD-256-1) { -ICLASS: VPSLLW +ICLASS: VPTESTNMD CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xF1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 -OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 -IFORM: VPSLLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +PATTERN: EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPTESTNMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512 } { -ICLASS: VPSLLW +ICLASS: VPTESTNMD CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 -PATTERN: EVV 0xF1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_MEM128() -OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 -IFORM: VPSLLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPTESTNMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512 } -# EMITTING VPSLLW (VPSLLW-128-3) +# EMITTING VPTESTNMQ (VPTESTNMQ-128-1) { -ICLASS: VPSLLW +ICLASS: VPTESTNMQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL128 UIMM8() -OPERANDS: REG0=XMM_N3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 IMM0:r:b -IFORM: VPSLLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 +PATTERN: EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512 } { -ICLASS: VPSLLW +ICLASS: VPTESTNMQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 MODRM() VL128 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_N3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 IMM0:r:b -IFORM: VPSLLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512 } -# EMITTING VPSLLW (VPSLLW-256-1) +# EMITTING VPTESTNMQ (VPTESTNMQ-256-1) { -ICLASS: VPSLLW +ICLASS: VPTESTNMQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xF1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 -OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=XMM_B3():r:dq:u16 -IFORM: VPSLLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 +PATTERN: EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512 } { -ICLASS: VPSLLW +ICLASS: VPTESTNMQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 -PATTERN: EVV 0xF1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_MEM128() -OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:dq:u16 -IFORM: VPSLLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512 } -# EMITTING VPSLLW (VPSLLW-256-3) +# EMITTING VPTESTNMW (VPTESTNMW-128-1) { -ICLASS: VPSLLW +ICLASS: VPTESTNMW CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 +ISA_SET: AVX512BW_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL256 UIMM8() -OPERANDS: REG0=YMM_N3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 IMM0:r:b -IFORM: VPSLLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 +PATTERN: EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPTESTNMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 } { -ICLASS: VPSLLW +ICLASS: VPTESTNMW CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 +ISA_SET: AVX512BW_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 MODRM() VL256 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_N3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 IMM0:r:b -IFORM: VPSLLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 +PATTERN: EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPTESTNMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 } -# EMITTING VPSLLW (VPSLLW-512-1) +# EMITTING VPTESTNMW (VPTESTNMW-256-1) { -ICLASS: VPSLLW +ICLASS: VPTESTNMW CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xF1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 -OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=XMM_B3():r:dq:u16 -IFORM: VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 +PATTERN: EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPTESTNMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 } { -ICLASS: VPSLLW +ICLASS: VPTESTNMW CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 -PATTERN: EVV 0xF1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_MEM128() -OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:dq:u16 -IFORM: VPSLLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPTESTNMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 } -# EMITTING VPSLLW (VPSLLW-512-2) +# EMITTING VPTESTNMW (VPTESTNMW-512-1) { -ICLASS: VPSLLW +ICLASS: VPTESTNMW CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX ISA_SET: AVX512BW_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL512 UIMM8() -OPERANDS: REG0=ZMM_N3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 IMM0:r:b -IFORM: VPSLLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 +PATTERN: EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 } { -ICLASS: VPSLLW +ICLASS: VPTESTNMW CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX ISA_SET: AVX512BW_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 MODRM() VL512 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_N3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 IMM0:r:b -IFORM: VPSLLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 +PATTERN: EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 } -# EMITTING VPSRAD (VPSRAD-128-1) +# EMITTING VPUNPCKHBW (VPUNPCKHBW-128-1) { -ICLASS: VPSRAD +ICLASS: VPUNPCKHBW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512BW_128 EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 -IFORM: VPSRAD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +PATTERN: EVV 0x68 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 } { -ICLASS: VPSRAD +ICLASS: VPUNPCKHBW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512BW_128 EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 -PATTERN: EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_32_BITS() NELEM_MEM128() -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:dq:u32 -IFORM: VPSRAD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x68 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 } -# EMITTING VPSRAD (VPSRAD-128-3) +# EMITTING VPUNPCKHBW (VPUNPCKHBW-256-1) { -ICLASS: VPSRAD +ICLASS: VPUNPCKHBW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL128 W0 UIMM8() -OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b -IFORM: VPSRAD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 +PATTERN: EVV 0x68 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 } { -ICLASS: VPSRAD +ICLASS: VPUNPCKHBW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b -IFORM: VPSRAD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x68 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 } -# EMITTING VPSRAD (VPSRAD-256-1) +# EMITTING VPUNPCKHBW (VPUNPCKHBW-512-1) { -ICLASS: VPSRAD +ICLASS: VPUNPCKHBW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 +ISA_SET: AVX512BW_512 EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=XMM_B3():r:dq:u32 -IFORM: VPSRAD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 +PATTERN: EVV 0x68 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 } { -ICLASS: VPSRAD +ICLASS: VPUNPCKHBW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 +ISA_SET: AVX512BW_512 EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 -PATTERN: EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_32_BITS() NELEM_MEM128() -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:dq:u32 -IFORM: VPSRAD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x68 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 } -# EMITTING VPSRAD (VPSRAD-256-3) +# EMITTING VPUNPCKHDQ (VPUNPCKHDQ-128-1) { -ICLASS: VPSRAD +ICLASS: VPUNPCKHDQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL256 W0 UIMM8() -OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b -IFORM: VPSRAD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 +PATTERN: EVV 0x6A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 } { -ICLASS: VPSRAD +ICLASS: VPUNPCKHDQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b -IFORM: VPSRAD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x6A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 } -# EMITTING VPSRAQ (VPSRAQ-128-1) +# EMITTING VPUNPCKHDQ (VPUNPCKHDQ-256-1) { -ICLASS: VPSRAQ +ICLASS: VPUNPCKHDQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 -IFORM: VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +PATTERN: EVV 0x6A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 } { -ICLASS: VPSRAQ +ICLASS: VPUNPCKHDQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 -PATTERN: EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_64_BITS() NELEM_MEM128() -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:dq:u64 -IFORM: VPSRAQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x6A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 } -# EMITTING VPSRAQ (VPSRAQ-128-2) +# EMITTING VPUNPCKHQDQ (VPUNPCKHQDQ-128-1) { -ICLASS: VPSRAQ +ICLASS: VPUNPCKHQDQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL128 W1 UIMM8() -OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 IMM0:r:b -IFORM: VPSRAQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 +PATTERN: EVV 0x6D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 } { -ICLASS: VPSRAQ +ICLASS: VPUNPCKHQDQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b -IFORM: VPSRAQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x6D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 } -# EMITTING VPSRAQ (VPSRAQ-256-1) +# EMITTING VPUNPCKHQDQ (VPUNPCKHQDQ-256-1) { -ICLASS: VPSRAQ +ICLASS: VPUNPCKHQDQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -63814,389 +68520,389 @@ ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=XMM_B3():r:dq:u64 -IFORM: VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 +PATTERN: EVV 0x6D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 } { -ICLASS: VPSRAQ +ICLASS: VPUNPCKHQDQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 -PATTERN: EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_64_BITS() NELEM_MEM128() -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:dq:u64 -IFORM: VPSRAQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x6D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 } -# EMITTING VPSRAQ (VPSRAQ-256-2) +# EMITTING VPUNPCKHWD (VPUNPCKHWD-128-1) { -ICLASS: VPSRAQ +ICLASS: VPUNPCKHWD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL256 W1 UIMM8() -OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b -IFORM: VPSRAQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 +PATTERN: EVV 0x69 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 } { -ICLASS: VPSRAQ +ICLASS: VPUNPCKHWD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b -IFORM: VPSRAQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x69 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 } -# EMITTING VPSRAVD (VPSRAVD-128-1) +# EMITTING VPUNPCKHWD (VPUNPCKHWD-256-1) { -ICLASS: VPSRAVD +ICLASS: VPUNPCKHWD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 -IFORM: VPSRAVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +PATTERN: EVV 0x69 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 } { -ICLASS: VPSRAVD +ICLASS: VPUNPCKHWD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPSRAVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x69 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 } -# EMITTING VPSRAVD (VPSRAVD-256-1) +# EMITTING VPUNPCKHWD (VPUNPCKHWD-512-1) { -ICLASS: VPSRAVD +ICLASS: VPUNPCKHWD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 -IFORM: VPSRAVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +PATTERN: EVV 0x69 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 } { -ICLASS: VPSRAVD +ICLASS: VPUNPCKHWD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPSRAVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x69 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 } -# EMITTING VPSRAVQ (VPSRAVQ-128-1) +# EMITTING VPUNPCKLBW (VPUNPCKLBW-128-1) { -ICLASS: VPSRAVQ +ICLASS: VPUNPCKLBW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 -IFORM: VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +PATTERN: EVV 0x60 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 } { -ICLASS: VPSRAVQ +ICLASS: VPUNPCKLBW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPSRAVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x60 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 } -# EMITTING VPSRAVQ (VPSRAVQ-256-1) +# EMITTING VPUNPCKLBW (VPUNPCKLBW-256-1) { -ICLASS: VPSRAVQ +ICLASS: VPUNPCKLBW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 -IFORM: VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +PATTERN: EVV 0x60 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 } { -ICLASS: VPSRAVQ +ICLASS: VPUNPCKLBW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPSRAVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x60 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 } -# EMITTING VPSRAVW (VPSRAVW-128-1) +# EMITTING VPUNPCKLBW (VPUNPCKLBW-512-1) { -ICLASS: VPSRAVW +ICLASS: VPUNPCKLBW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 -IFORM: VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +PATTERN: EVV 0x60 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 } { -ICLASS: VPSRAVW +ICLASS: VPUNPCKLBW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 -IFORM: VPSRAVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x60 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 } -# EMITTING VPSRAVW (VPSRAVW-256-1) +# EMITTING VPUNPCKLDQ (VPUNPCKLDQ-128-1) { -ICLASS: VPSRAVW +ICLASS: VPUNPCKLDQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 -IFORM: VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +PATTERN: EVV 0x62 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 } { -ICLASS: VPSRAVW +ICLASS: VPUNPCKLDQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 -IFORM: VPSRAVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x62 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 } -# EMITTING VPSRAVW (VPSRAVW-512-1) +# EMITTING VPUNPCKLDQ (VPUNPCKLDQ-256-1) { -ICLASS: VPSRAVW +ICLASS: VPUNPCKLDQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 -IFORM: VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +PATTERN: EVV 0x62 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 } { -ICLASS: VPSRAVW +ICLASS: VPUNPCKLDQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 -IFORM: VPSRAVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x62 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 } -# EMITTING VPSRAW (VPSRAW-128-1) +# EMITTING VPUNPCKLQDQ (VPUNPCKLQDQ-128-1) { -ICLASS: VPSRAW +ICLASS: VPUNPCKLQDQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xE1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 -OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 -IFORM: VPSRAW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +PATTERN: EVV 0x6C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 } { -ICLASS: VPSRAW +ICLASS: VPUNPCKLQDQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 -PATTERN: EVV 0xE1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_MEM128() -OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 -IFORM: VPSRAW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x6C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 } -# EMITTING VPSRAW (VPSRAW-128-2) +# EMITTING VPUNPCKLQDQ (VPUNPCKLQDQ-256-1) { -ICLASS: VPSRAW +ICLASS: VPUNPCKLQDQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL128 UIMM8() -OPERANDS: REG0=XMM_N3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 IMM0:r:b -IFORM: VPSRAW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 +PATTERN: EVV 0x6C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 } { -ICLASS: VPSRAW +ICLASS: VPUNPCKLQDQ CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] BCRC=0 MODRM() VL128 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_N3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 IMM0:r:b -IFORM: VPSRAW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x6C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 } -# EMITTING VPSRAW (VPSRAW-256-1) +# EMITTING VPUNPCKLWD (VPUNPCKLWD-128-1) { -ICLASS: VPSRAW +ICLASS: VPUNPCKLWD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 +ISA_SET: AVX512BW_128 EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xE1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 -OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=XMM_B3():r:dq:u16 -IFORM: VPSRAW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 +PATTERN: EVV 0x61 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 } { -ICLASS: VPSRAW +ICLASS: VPUNPCKLWD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 +ISA_SET: AVX512BW_128 EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 -PATTERN: EVV 0xE1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_MEM128() -OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:dq:u16 -IFORM: VPSRAW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x61 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 } -# EMITTING VPSRAW (VPSRAW-256-2) +# EMITTING VPUNPCKLWD (VPUNPCKLWD-256-1) { -ICLASS: VPSRAW +ICLASS: VPUNPCKLWD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL256 UIMM8() -OPERANDS: REG0=YMM_N3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 IMM0:r:b -IFORM: VPSRAW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 +PATTERN: EVV 0x61 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 } { -ICLASS: VPSRAW +ICLASS: VPUNPCKLWD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] BCRC=0 MODRM() VL256 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_N3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 IMM0:r:b -IFORM: VPSRAW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x61 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 } -# EMITTING VPSRAW (VPSRAW-512-1) +# EMITTING VPUNPCKLWD (VPUNPCKLWD-512-1) { -ICLASS: VPSRAW +ICLASS: VPUNPCKLWD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX @@ -64204,5814 +68910,6206 @@ ISA_SET: AVX512BW_512 EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xE1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 -OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=XMM_B3():r:dq:u16 -IFORM: VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 +PATTERN: EVV 0x61 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 } { -ICLASS: VPSRAW +ICLASS: VPUNPCKLWD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_512 EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 -PATTERN: EVV 0xE1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_MEM128() -OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:dq:u16 -IFORM: VPSRAW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x61 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 } -# EMITTING VPSRAW (VPSRAW-512-2) +# EMITTING VPXORD (VPXORD-128-1) { -ICLASS: VPSRAW +ICLASS: VPXORD CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL512 UIMM8() -OPERANDS: REG0=ZMM_N3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 IMM0:r:b -IFORM: VPSRAW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 +PATTERN: EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 } { -ICLASS: VPSRAW +ICLASS: VPXORD CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] BCRC=0 MODRM() VL512 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_N3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 IMM0:r:b -IFORM: VPSRAW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPXORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 } -# EMITTING VPSRLD (VPSRLD-128-1) +# EMITTING VPXORD (VPXORD-256-1) { -ICLASS: VPSRLD +ICLASS: VPXORD CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xD2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 -IFORM: VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +PATTERN: EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 } { -ICLASS: VPSRLD +ICLASS: VPXORD CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 -PATTERN: EVV 0xD2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_32_BITS() NELEM_MEM128() -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:dq:u32 -IFORM: VPSRLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPXORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 } -# EMITTING VPSRLD (VPSRLD-128-2) +# EMITTING VPXORQ (VPXORQ-128-1) { -ICLASS: VPSRLD +ICLASS: VPXORQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL128 W0 UIMM8() -OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b -IFORM: VPSRLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 +PATTERN: EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 } { -ICLASS: VPSRLD +ICLASS: VPXORQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b -IFORM: VPSRLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 +PATTERN: EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPXORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 } -# EMITTING VPSRLD (VPSRLD-256-1) +# EMITTING VPXORQ (VPXORQ-256-1) { -ICLASS: VPSRLD +ICLASS: VPXORQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xD2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=XMM_B3():r:dq:u32 -IFORM: VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 +PATTERN: EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 } { -ICLASS: VPSRLD +ICLASS: VPXORQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 -PATTERN: EVV 0xD2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_32_BITS() NELEM_MEM128() -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:dq:u32 -IFORM: VPSRLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPXORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 } -# EMITTING VPSRLD (VPSRLD-256-2) +# EMITTING VRANGEPD (VRANGEPD-128-1) { -ICLASS: VPSRLD +ICLASS: VRANGEPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL256 W0 UIMM8() -OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b -IFORM: VPSRLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 } { -ICLASS: VPSRLD +ICLASS: VRANGEPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b -IFORM: VPSRLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VRANGEPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 } -# EMITTING VPSRLDQ (VPSRLDQ-128-1) +# EMITTING VRANGEPD (VRANGEPD-256-1) { -ICLASS: VPSRLDQ +ICLASS: VRANGEPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b011] RM[nnn] VL128 ZEROING=0 MASK=0 UIMM8() -OPERANDS: REG0=XMM_N3():w:dq:u8 REG1=XMM_B3():r:dq:u8 IMM0:r:b -IFORM: VPSRLDQ_XMMu8_XMMu8_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 IMM0:r:b +IFORM: VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 } { -ICLASS: VPSRLDQ +ICLASS: VRANGEPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: DISP8_FULLMEM -PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b011] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_N3():w:dq:u8 MEM0:r:dq:u8 IMM0:r:b -IFORM: VPSRLDQ_XMMu8_MEMu8_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VRANGEPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 } -# EMITTING VPSRLDQ (VPSRLDQ-256-1) +# EMITTING VRANGEPD (VRANGEPD-512-1) { -ICLASS: VPSRLDQ +ICLASS: VRANGEPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b011] RM[nnn] VL256 ZEROING=0 MASK=0 UIMM8() -OPERANDS: REG0=YMM_N3():w:qq:u8 REG1=YMM_B3():r:qq:u8 IMM0:r:b -IFORM: VPSRLDQ_YMMu8_YMMu8_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 } { -ICLASS: VPSRLDQ +ICLASS: VRANGEPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: DISP8_FULLMEM -PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b011] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_N3():w:qq:u8 MEM0:r:qq:u8 IMM0:r:b -IFORM: VPSRLDQ_YMMu8_MEMu8_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 +} + +{ +ICLASS: VRANGEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VRANGEPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 } -# EMITTING VPSRLDQ (VPSRLDQ-512-1) +# EMITTING VRANGEPS (VRANGEPS-128-1) { -ICLASS: VPSRLDQ +ICLASS: VRANGEPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b011] RM[nnn] VL512 ZEROING=0 MASK=0 UIMM8() -OPERANDS: REG0=ZMM_N3():w:zu8 REG1=ZMM_B3():r:zu8 IMM0:r:b -IFORM: VPSRLDQ_ZMMu8_ZMMu8_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 } { -ICLASS: VPSRLDQ +ICLASS: VRANGEPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: DISP8_FULLMEM -PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b011] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_N3():w:zu8 MEM0:r:zd:u8 IMM0:r:b -IFORM: VPSRLDQ_ZMMu8_MEMu8_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VRANGEPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 } -# EMITTING VPSRLQ (VPSRLQ-128-1) +# EMITTING VRANGEPS (VRANGEPS-256-1) { -ICLASS: VPSRLQ +ICLASS: VRANGEPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xD3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 -IFORM: VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 IMM0:r:b +IFORM: VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 } { -ICLASS: VPSRLQ +ICLASS: VRANGEPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 -PATTERN: EVV 0xD3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_64_BITS() NELEM_MEM128() -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:dq:u64 -IFORM: VPSRLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VRANGEPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 } -# EMITTING VPSRLQ (VPSRLQ-128-2) +# EMITTING VRANGEPS (VRANGEPS-512-1) { -ICLASS: VPSRLQ +ICLASS: VRANGEPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL128 W1 UIMM8() -OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 IMM0:r:b -IFORM: VPSRLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 } { -ICLASS: VPSRLQ +ICLASS: VRANGEPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b -IFORM: VPSRLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 +} + +{ +ICLASS: VRANGEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VRANGEPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 } -# EMITTING VPSRLQ (VPSRLQ-256-1) +# EMITTING VRANGESD (VRANGESD-128-1) { -ICLASS: VPSRLQ +ICLASS: VRANGESD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xD3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=XMM_B3():r:dq:u64 -IFORM: VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x51 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 } { -ICLASS: VPSRLQ +ICLASS: VRANGESD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 -PATTERN: EVV 0xD3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_64_BITS() NELEM_MEM128() -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:dq:u64 -IFORM: VPSRLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x51 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VRANGESD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x51 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b +IFORM: VRANGESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 } -# EMITTING VPSRLQ (VPSRLQ-256-2) +# EMITTING VRANGESS (VRANGESS-128-1) { -ICLASS: VPSRLQ +ICLASS: VRANGESS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL256 W1 UIMM8() -OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b -IFORM: VPSRLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x51 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 } { -ICLASS: VPSRLQ +ICLASS: VRANGESS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b -IFORM: VPSRLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x51 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VRANGESS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x51 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b +IFORM: VRANGESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 } -# EMITTING VPSRLVD (VPSRLVD-128-1) +# EMITTING VRCP14PD (VRCP14PD-128-1) { -ICLASS: VPSRLVD +ICLASS: VRCP14PD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 -IFORM: VPSRLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512 } { -ICLASS: VPSRLVD +ICLASS: VRCP14PD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPSRLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VRCP14PD_XMMf64_MASKmskw_MEMf64_AVX512 } -# EMITTING VPSRLVD (VPSRLVD-256-1) +# EMITTING VRCP14PD (VRCP14PD-256-1) { -ICLASS: VPSRLVD +ICLASS: VRCP14PD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 -IFORM: VPSRLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512 } { -ICLASS: VPSRLVD +ICLASS: VRCP14PD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPSRLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VRCP14PD_YMMf64_MASKmskw_MEMf64_AVX512 } -# EMITTING VPSRLVQ (VPSRLVQ-128-1) +# EMITTING VRCP14PS (VRCP14PS-128-1) { -ICLASS: VPSRLVQ +ICLASS: VRCP14PS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 -IFORM: VPSRLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512 } { -ICLASS: VPSRLVQ +ICLASS: VRCP14PS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPSRLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VRCP14PS_XMMf32_MASKmskw_MEMf32_AVX512 } -# EMITTING VPSRLVQ (VPSRLVQ-256-1) +# EMITTING VRCP14PS (VRCP14PS-256-1) { -ICLASS: VPSRLVQ +ICLASS: VRCP14PS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 -IFORM: VPSRLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512 } { -ICLASS: VPSRLVQ +ICLASS: VRCP14PS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPSRLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VRCP14PS_YMMf32_MASKmskw_MEMf32_AVX512 } -# EMITTING VPSRLVW (VPSRLVW-128-1) +# EMITTING VREDUCEPD (VREDUCEPD-128-1) { -ICLASS: VPSRLVW +ICLASS: VREDUCEPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 -IFORM: VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 } { -ICLASS: VPSRLVW +ICLASS: VREDUCEPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 -IFORM: VPSRLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VREDUCEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 } -# EMITTING VPSRLVW (VPSRLVW-256-1) +# EMITTING VREDUCEPD (VREDUCEPD-256-1) { -ICLASS: VPSRLVW +ICLASS: VREDUCEPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 -IFORM: VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 IMM0:r:b +IFORM: VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 } { -ICLASS: VPSRLVW +ICLASS: VREDUCEPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 -IFORM: VPSRLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VREDUCEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 } -# EMITTING VPSRLVW (VPSRLVW-512-1) +# EMITTING VREDUCEPD (VREDUCEPD-512-1) { -ICLASS: VPSRLVW +ICLASS: VREDUCEPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 -IFORM: VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 } { -ICLASS: VPSRLVW +ICLASS: VREDUCEPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 -IFORM: VPSRLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 } - -# EMITTING VPSRLW (VPSRLW-128-1) { -ICLASS: VPSRLW +ICLASS: VREDUCEPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xD1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 -OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 -IFORM: VPSRLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VREDUCEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 } + +# EMITTING VREDUCEPS (VREDUCEPS-128-1) { -ICLASS: VPSRLW +ICLASS: VREDUCEPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 -PATTERN: EVV 0xD1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_MEM128() -OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 -IFORM: VPSRLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 } - -# EMITTING VPSRLW (VPSRLW-128-2) { -ICLASS: VPSRLW +ICLASS: VREDUCEPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL128 UIMM8() -OPERANDS: REG0=XMM_N3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 IMM0:r:b -IFORM: VPSRLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VREDUCEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 } + +# EMITTING VREDUCEPS (VREDUCEPS-256-1) { -ICLASS: VPSRLW +ICLASS: VREDUCEPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 MODRM() VL128 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_N3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 IMM0:r:b -IFORM: VPSRLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 IMM0:r:b +IFORM: VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 } - -# EMITTING VPSRLW (VPSRLW-256-1) { -ICLASS: VPSRLW +ICLASS: VREDUCEPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xD1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 -OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=XMM_B3():r:dq:u16 -IFORM: VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VREDUCEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 } + +# EMITTING VREDUCEPS (VREDUCEPS-512-1) { -ICLASS: VPSRLW +ICLASS: VREDUCEPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 -PATTERN: EVV 0xD1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_MEM128() -OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:dq:u16 -IFORM: VPSRLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 } - -# EMITTING VPSRLW (VPSRLW-256-2) { -ICLASS: VPSRLW +ICLASS: VREDUCEPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL256 UIMM8() -OPERANDS: REG0=YMM_N3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 IMM0:r:b -IFORM: VPSRLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 } { -ICLASS: VPSRLW +ICLASS: VREDUCEPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 MODRM() VL256 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_N3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 IMM0:r:b -IFORM: VPSRLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VREDUCEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 } -# EMITTING VPSRLW (VPSRLW-512-1) +# EMITTING VREDUCESD (VREDUCESD-128-1) { -ICLASS: VPSRLW +ICLASS: VREDUCESD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xD1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 -OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=XMM_B3():r:dq:u16 -IFORM: VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x57 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 } { -ICLASS: VPSRLW +ICLASS: VREDUCESD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 -PATTERN: EVV 0xD1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_MEM128() -OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:dq:u16 -IFORM: VPSRLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x57 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 } - -# EMITTING VPSRLW (VPSRLW-512-2) { -ICLASS: VPSRLW +ICLASS: VREDUCESD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL512 UIMM8() -OPERANDS: REG0=ZMM_N3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 IMM0:r:b -IFORM: VPSRLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x57 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b +IFORM: VREDUCESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 } + +# EMITTING VREDUCESS (VREDUCESS-128-1) { -ICLASS: VPSRLW +ICLASS: VREDUCESS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 MODRM() VL512 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_N3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 IMM0:r:b -IFORM: VPSRLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x57 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 } - -# EMITTING VPSUBB (VPSUBB-128-1) { -ICLASS: VPSUBB +ICLASS: VREDUCESS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xF8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 -OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 -IFORM: VPSUBB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x57 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 } { -ICLASS: VPSUBB +ICLASS: VREDUCESS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E3 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xF8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 -IFORM: VPSUBB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x57 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b +IFORM: VREDUCESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 } -# EMITTING VPSUBB (VPSUBB-256-1) +# EMITTING VRNDSCALEPD (VRNDSCALEPD-128-1) { -ICLASS: VPSUBB +ICLASS: VRNDSCALEPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xF8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 -OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 -IFORM: VPSUBB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x09 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 } { -ICLASS: VPSUBB +ICLASS: VRNDSCALEPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xF8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 -IFORM: VPSUBB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x09 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VRNDSCALEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 } -# EMITTING VPSUBB (VPSUBB-512-1) +# EMITTING VRNDSCALEPD (VRNDSCALEPD-256-1) { -ICLASS: VPSUBB +ICLASS: VRNDSCALEPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xF8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 -OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 -IFORM: VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x09 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 IMM0:r:b +IFORM: VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 } { -ICLASS: VPSUBB +ICLASS: VRNDSCALEPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xF8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 -IFORM: VPSUBB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x09 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VRNDSCALEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 } -# EMITTING VPSUBD (VPSUBD-128-1) +# EMITTING VRNDSCALEPS (VRNDSCALEPS-128-1) { -ICLASS: VPSUBD +ICLASS: VRNDSCALEPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xFA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 -IFORM: VPSUBD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x08 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 } { -ICLASS: VPSUBD +ICLASS: VRNDSCALEPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xFA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPSUBD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x08 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VRNDSCALEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 } -# EMITTING VPSUBD (VPSUBD-256-1) +# EMITTING VRNDSCALEPS (VRNDSCALEPS-256-1) { -ICLASS: VPSUBD +ICLASS: VRNDSCALEPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xFA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 -IFORM: VPSUBD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x08 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 IMM0:r:b +IFORM: VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 } { -ICLASS: VPSUBD +ICLASS: VRNDSCALEPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xFA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPSUBD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x08 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VRNDSCALEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 } -# EMITTING VPSUBQ (VPSUBQ-128-1) +# EMITTING VRSQRT14PD (VRSQRT14PD-128-1) { -ICLASS: VPSUBQ +ICLASS: VRSQRT14PD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xFB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 -IFORM: VPSUBQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512 } { -ICLASS: VPSUBQ +ICLASS: VRSQRT14PD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xFB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPSUBQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VRSQRT14PD_XMMf64_MASKmskw_MEMf64_AVX512 } -# EMITTING VPSUBQ (VPSUBQ-256-1) +# EMITTING VRSQRT14PD (VRSQRT14PD-256-1) { -ICLASS: VPSUBQ +ICLASS: VRSQRT14PD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xFB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 -IFORM: VPSUBQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512 } { -ICLASS: VPSUBQ +ICLASS: VRSQRT14PD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xFB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPSUBQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VRSQRT14PD_YMMf64_MASKmskw_MEMf64_AVX512 } -# EMITTING VPSUBSB (VPSUBSB-128-1) +# EMITTING VRSQRT14PS (VRSQRT14PS-128-1) { -ICLASS: VPSUBSB +ICLASS: VRSQRT14PS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xE8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 -OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 REG3=XMM_B3():r:dq:i8 -IFORM: VPSUBSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512 } { -ICLASS: VPSUBSB +ICLASS: VRSQRT14PS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 +ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xE8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 MEM0:r:dq:i8 -IFORM: VPSUBSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VRSQRT14PS_XMMf32_MASKmskw_MEMf32_AVX512 } -# EMITTING VPSUBSB (VPSUBSB-256-1) +# EMITTING VRSQRT14PS (VRSQRT14PS-256-1) { -ICLASS: VPSUBSB +ICLASS: VRSQRT14PS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xE8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 -OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 REG3=YMM_B3():r:qq:i8 -IFORM: VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512 } { -ICLASS: VPSUBSB +ICLASS: VRSQRT14PS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 +ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xE8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 MEM0:r:qq:i8 -IFORM: VPSUBSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512 } -# EMITTING VPSUBSB (VPSUBSB-512-1) +# EMITTING VSCALEFPD (VSCALEFPD-128-1) { -ICLASS: VPSUBSB +ICLASS: VSCALEFPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xE8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 -OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 REG3=ZMM_B3():r:zi8 -IFORM: VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VSCALEFPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VSCALEFPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VSCALEFPD (VSCALEFPD-256-1) +{ +ICLASS: VSCALEFPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 } { -ICLASS: VPSUBSB +ICLASS: VSCALEFPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xE8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 MEM0:r:zd:i8 -IFORM: VPSUBSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VSCALEFPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 } -# EMITTING VPSUBSW (VPSUBSW-128-1) +# EMITTING VSCALEFPS (VSCALEFPS-128-1) { -ICLASS: VPSUBSW +ICLASS: VSCALEFPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xE9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 -OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 -IFORM: VPSUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VPSUBSW +ICLASS: VSCALEFPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xE9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 -IFORM: VPSUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VSCALEFPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 } -# EMITTING VPSUBSW (VPSUBSW-256-1) +# EMITTING VSCALEFPS (VSCALEFPS-256-1) { -ICLASS: VPSUBSW +ICLASS: VSCALEFPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xE9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 -OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 -IFORM: VPSUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 } { -ICLASS: VPSUBSW +ICLASS: VSCALEFPS CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xE9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 -IFORM: VPSUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VSCALEFPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 } -# EMITTING VPSUBSW (VPSUBSW-512-1) +# EMITTING VSCATTERDPD (VSCATTERDPD-128-1) { -ICLASS: VPSUBSW +ICLASS: VSCATTERDPD CPL: 3 -CATEGORY: AVX512 +CATEGORY: SCATTER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xE9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 -OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 -IFORM: VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 +ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:q:f64 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:f64 +IFORM: VSCATTERDPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128 } + +# EMITTING VSCATTERDPD (VSCATTERDPD-256-1) { -ICLASS: VPSUBSW +ICLASS: VSCATTERDPD CPL: 3 -CATEGORY: AVX512 +CATEGORY: SCATTER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xE9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 -IFORM: VPSUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 +ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:q:f64 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:f64 +IFORM: VSCATTERDPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256 } -# EMITTING VPSUBUSB (VPSUBUSB-128-1) +# EMITTING VSCATTERDPS (VSCATTERDPS-128-1) { -ICLASS: VPSUBUSB +ICLASS: VSCATTERDPS CPL: 3 -CATEGORY: AVX512 +CATEGORY: SCATTER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xD8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 -OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 -IFORM: VPSUBUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:d:f32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:f32 +IFORM: VSCATTERDPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128 } + +# EMITTING VSCATTERDPS (VSCATTERDPS-256-1) { -ICLASS: VPSUBUSB +ICLASS: VSCATTERDPS CPL: 3 -CATEGORY: AVX512 +CATEGORY: SCATTER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xD8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 -IFORM: VPSUBUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:d:f32 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:f32 +IFORM: VSCATTERDPS_MEMf32_MASKmskw_YMMf32_AVX512_VL256 } -# EMITTING VPSUBUSB (VPSUBUSB-256-1) +# EMITTING VSCATTERQPD (VSCATTERQPD-128-1) { -ICLASS: VPSUBUSB +ICLASS: VSCATTERQPD CPL: 3 -CATEGORY: AVX512 +CATEGORY: SCATTER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xD8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 -OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 -IFORM: VPSUBUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:q:f64 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:f64 +IFORM: VSCATTERQPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128 } + +# EMITTING VSCATTERQPD (VSCATTERQPD-256-1) { -ICLASS: VPSUBUSB +ICLASS: VSCATTERQPD CPL: 3 -CATEGORY: AVX512 +CATEGORY: SCATTER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xD8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 -IFORM: VPSUBUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:q:f64 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:f64 +IFORM: VSCATTERQPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256 } -# EMITTING VPSUBUSB (VPSUBUSB-512-1) +# EMITTING VSCATTERQPS (VSCATTERQPS-128-1) { -ICLASS: VPSUBUSB +ICLASS: VSCATTERQPS CPL: 3 -CATEGORY: AVX512 +CATEGORY: SCATTER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xD8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 -OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 -IFORM: VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:d:f32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:f32 +IFORM: VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128 } + +# EMITTING VSCATTERQPS (VSCATTERQPS-256-1) { -ICLASS: VPSUBUSB +ICLASS: VSCATTERQPS CPL: 3 -CATEGORY: AVX512 +CATEGORY: SCATTER EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xD8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 -IFORM: VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:d:f32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:f32 +IFORM: VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL256 } -# EMITTING VPSUBUSW (VPSUBUSW-128-1) +# EMITTING VSHUFF32X4 (VSHUFF32X4-256-1) { -ICLASS: VPSUBUSW +ICLASS: VSHUFF32X4 CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xD9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 -OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 -IFORM: VPSUBUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +PATTERN: EVV 0x23 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 IMM0:r:b +IFORM: VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 } { -ICLASS: VPSUBUSW +ICLASS: VSHUFF32X4 CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xD9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 -IFORM: VPSUBUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x23 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 } -# EMITTING VPSUBUSW (VPSUBUSW-256-1) +# EMITTING VSHUFF64X2 (VSHUFF64X2-256-1) { -ICLASS: VPSUBUSW +ICLASS: VSHUFF64X2 CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xD9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 -OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 -IFORM: VPSUBUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +PATTERN: EVV 0x23 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 IMM0:r:b +IFORM: VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 } { -ICLASS: VPSUBUSW +ICLASS: VSHUFF64X2 CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xD9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 -IFORM: VPSUBUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x23 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 } -# EMITTING VPSUBUSW (VPSUBUSW-512-1) +# EMITTING VSHUFI32X4 (VSHUFI32X4-256-1) { -ICLASS: VPSUBUSW +ICLASS: VSHUFI32X4 CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xD9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 -OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 -IFORM: VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +PATTERN: EVV 0x43 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 IMM0:r:b +IFORM: VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 } { -ICLASS: VPSUBUSW +ICLASS: VSHUFI32X4 CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xD9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 -IFORM: VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x43 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 } -# EMITTING VPSUBW (VPSUBW-128-1) +# EMITTING VSHUFI64X2 (VSHUFI64X2-256-1) { -ICLASS: VPSUBW +ICLASS: VSHUFI64X2 CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xF9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 -OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 -IFORM: VPSUBW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +PATTERN: EVV 0x43 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 } { -ICLASS: VPSUBW +ICLASS: VSHUFI64X2 CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xF9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 -IFORM: VPSUBW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x43 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 } -# EMITTING VPSUBW (VPSUBW-256-1) +# EMITTING VSHUFPD (VSHUFPD-128-1) { -ICLASS: VPSUBW +ICLASS: VSHUFPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xF9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 -OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 -IFORM: VPSUBW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +PATTERN: EVV 0xC6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VSHUFPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 } { -ICLASS: VPSUBW +ICLASS: VSHUFPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xF9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 -IFORM: VPSUBW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 } -# EMITTING VPSUBW (VPSUBW-512-1) +# EMITTING VSHUFPD (VSHUFPD-256-1) { -ICLASS: VPSUBW +ICLASS: VSHUFPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xF9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 -OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 -IFORM: VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +PATTERN: EVV 0xC6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 IMM0:r:b +IFORM: VSHUFPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 } { -ICLASS: VPSUBW +ICLASS: VSHUFPD CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0xF9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 -IFORM: VPSUBW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 } -# EMITTING VPTERNLOGD (VPTERNLOGD-128-1) +# EMITTING VSHUFPS (VSHUFPS-128-1) { -ICLASS: VPTERNLOGD +ICLASS: VSHUFPS CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() -OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 IMM0:r:b -IFORM: VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 +PATTERN: EVV 0xC6 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VSHUFPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 } { -ICLASS: VPTERNLOGD +ICLASS: VSHUFPS CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b -IFORM: VPTERNLOGD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC6 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 } -# EMITTING VPTERNLOGD (VPTERNLOGD-256-1) +# EMITTING VSHUFPS (VSHUFPS-256-1) { -ICLASS: VPTERNLOGD +ICLASS: VSHUFPS CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() -OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 IMM0:r:b -IFORM: VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 +PATTERN: EVV 0xC6 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 IMM0:r:b +IFORM: VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 } { -ICLASS: VPTERNLOGD +ICLASS: VSHUFPS CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b -IFORM: VPTERNLOGD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC6 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 } -# EMITTING VPTERNLOGQ (VPTERNLOGQ-128-1) +# EMITTING VSQRTPD (VSQRTPD-128-1) { -ICLASS: VPTERNLOGQ +ICLASS: VSQRTPD CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() -OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 IMM0:r:b -IFORM: VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x51 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VSQRTPD_XMMf64_MASKmskw_XMMf64_AVX512 } { -ICLASS: VPTERNLOGQ +ICLASS: VSQRTPD CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b -IFORM: VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x51 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VSQRTPD_XMMf64_MASKmskw_MEMf64_AVX512 } -# EMITTING VPTERNLOGQ (VPTERNLOGQ-256-1) +# EMITTING VSQRTPD (VSQRTPD-256-1) { -ICLASS: VPTERNLOGQ +ICLASS: VSQRTPD CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() -OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 IMM0:r:b -IFORM: VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x51 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512 } { -ICLASS: VPTERNLOGQ +ICLASS: VSQRTPD CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 -REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b -IFORM: VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 -} - - -# EMITTING VPTESTMB (VPTESTMB-128-1) -{ -ICLASS: VPTESTMB -CPL: 3 -CATEGORY: LOGICAL -EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 -REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 -IFORM: VPTESTMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 -} - -{ -ICLASS: VPTESTMB -CPL: 3 -CATEGORY: LOGICAL -EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 -IFORM: VPTESTMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x51 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VSQRTPD_YMMf64_MASKmskw_MEMf64_AVX512 } -# EMITTING VPTESTMB (VPTESTMB-256-1) +# EMITTING VSQRTPS (VSQRTPS-128-1) { -ICLASS: VPTESTMB +ICLASS: VSQRTPS CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 -IFORM: VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x51 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VSQRTPS_XMMf32_MASKmskw_XMMf32_AVX512 } { -ICLASS: VPTESTMB +ICLASS: VSQRTPS CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 -IFORM: VPTESTMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x51 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VSQRTPS_XMMf32_MASKmskw_MEMf32_AVX512 } -# EMITTING VPTESTMB (VPTESTMB-512-1) +# EMITTING VSQRTPS (VSQRTPS-256-1) { -ICLASS: VPTESTMB +ICLASS: VSQRTPS CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 -IFORM: VPTESTMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x51 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512 } { -ICLASS: VPTESTMB +ICLASS: VSQRTPS CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 -IFORM: VPTESTMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x51 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VSQRTPS_YMMf32_MASKmskw_MEMf32_AVX512 } -# EMITTING VPTESTMD (VPTESTMD-128-1) +# EMITTING VSUBPD (VSUBPD-128-1) { -ICLASS: VPTESTMD +ICLASS: VSUBPD CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 -IFORM: VPTESTMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VSUBPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VPTESTMD +ICLASS: VSUBPD CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPTESTMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VSUBPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 } -# EMITTING VPTESTMD (VPTESTMD-256-1) +# EMITTING VSUBPD (VSUBPD-256-1) { -ICLASS: VPTESTMD +ICLASS: VSUBPD CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 -IFORM: VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 } { -ICLASS: VPTESTMD +ICLASS: VSUBPD CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPTESTMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VSUBPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 } -# EMITTING VPTESTMQ (VPTESTMQ-128-1) +# EMITTING VSUBPS (VSUBPS-128-1) { -ICLASS: VPTESTMQ +ICLASS: VSUBPS CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 -IFORM: VPTESTMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5C VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VSUBPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VPTESTMQ +ICLASS: VSUBPS CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPTESTMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5C VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VSUBPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 } -# EMITTING VPTESTMQ (VPTESTMQ-256-1) +# EMITTING VSUBPS (VSUBPS-256-1) { -ICLASS: VPTESTMQ +ICLASS: VSUBPS CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 -IFORM: VPTESTMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512 +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5C VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 } { -ICLASS: VPTESTMQ +ICLASS: VSUBPS CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E2 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPTESTMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5C VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VSUBPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 } -# EMITTING VPTESTMW (VPTESTMW-128-1) +# EMITTING VUNPCKHPD (VUNPCKHPD-128-1) { -ICLASS: VPTESTMW +ICLASS: VUNPCKHPD CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 -IFORM: VPTESTMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 +PATTERN: EVV 0x15 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VUNPCKHPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VPTESTMW +ICLASS: VUNPCKHPD CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 -IFORM: VPTESTMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x15 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VUNPCKHPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 } -# EMITTING VPTESTMW (VPTESTMW-256-1) +# EMITTING VUNPCKHPD (VUNPCKHPD-256-1) { -ICLASS: VPTESTMW +ICLASS: VUNPCKHPD CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 -IFORM: VPTESTMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 +PATTERN: EVV 0x15 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 } { -ICLASS: VPTESTMW +ICLASS: VUNPCKHPD CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 -IFORM: VPTESTMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x15 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VUNPCKHPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 } -# EMITTING VPTESTMW (VPTESTMW-512-1) +# EMITTING VUNPCKHPS (VUNPCKHPS-128-1) { -ICLASS: VPTESTMW +ICLASS: VUNPCKHPS CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 -IFORM: VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 +PATTERN: EVV 0x15 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VUNPCKHPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VPTESTMW +ICLASS: VUNPCKHPS CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 -IFORM: VPTESTMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x15 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VUNPCKHPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 } -# EMITTING VPTESTNMB (VPTESTNMB-128-1) +# EMITTING VUNPCKHPS (VUNPCKHPS-256-1) { -ICLASS: VPTESTNMB +ICLASS: VUNPCKHPS CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 -IFORM: VPTESTNMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 +PATTERN: EVV 0x15 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VUNPCKHPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 } { -ICLASS: VPTESTNMB +ICLASS: VUNPCKHPS CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 -IFORM: VPTESTNMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x15 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VUNPCKHPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 } -# EMITTING VPTESTNMB (VPTESTNMB-256-1) +# EMITTING VUNPCKLPD (VUNPCKLPD-128-1) { -ICLASS: VPTESTNMB +ICLASS: VUNPCKLPD CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 -IFORM: VPTESTNMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 +PATTERN: EVV 0x14 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VUNPCKLPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 } { -ICLASS: VPTESTNMB +ICLASS: VUNPCKLPD CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 -IFORM: VPTESTNMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x14 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VUNPCKLPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 } -# EMITTING VPTESTNMB (VPTESTNMB-512-1) +# EMITTING VUNPCKLPD (VUNPCKLPD-256-1) { -ICLASS: VPTESTNMB +ICLASS: VUNPCKLPD CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 -IFORM: VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 +PATTERN: EVV 0x14 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 } { -ICLASS: VPTESTNMB +ICLASS: VUNPCKLPD CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 -IFORM: VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x14 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VUNPCKLPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 } -# EMITTING VPTESTNMD (VPTESTNMD-128-1) +# EMITTING VUNPCKLPS (VUNPCKLPS-128-1) { -ICLASS: VPTESTNMD +ICLASS: VUNPCKLPS CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 -IFORM: VPTESTNMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512 +PATTERN: EVV 0x14 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VUNPCKLPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 } { -ICLASS: VPTESTNMD +ICLASS: VUNPCKLPS CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPTESTNMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x14 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VUNPCKLPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 } -# EMITTING VPTESTNMD (VPTESTNMD-256-1) +# EMITTING VUNPCKLPS (VUNPCKLPS-256-1) { -ICLASS: VPTESTNMD +ICLASS: VUNPCKLPS CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 -IFORM: VPTESTNMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512 +PATTERN: EVV 0x14 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VUNPCKLPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 } { -ICLASS: VPTESTNMD +ICLASS: VUNPCKLPS CPL: 3 -CATEGORY: LOGICAL +CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPTESTNMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x14 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VUNPCKLPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 } -# EMITTING VPTESTNMQ (VPTESTNMQ-128-1) +# EMITTING VXORPD (VXORPD-128-1) { -ICLASS: VPTESTNMQ +ICLASS: VXORPD CPL: 3 -CATEGORY: LOGICAL +CATEGORY: LOGICAL_FP EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512DQ_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 -IFORM: VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512 +PATTERN: EVV 0x57 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VXORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 } { -ICLASS: VPTESTNMQ +ICLASS: VXORPD CPL: 3 -CATEGORY: LOGICAL +CATEGORY: LOGICAL_FP EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512DQ_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512 +PATTERN: EVV 0x57 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VXORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 } -# EMITTING VPTESTNMQ (VPTESTNMQ-256-1) +# EMITTING VXORPD (VXORPD-256-1) { -ICLASS: VPTESTNMQ +ICLASS: VXORPD CPL: 3 -CATEGORY: LOGICAL +CATEGORY: LOGICAL_FP EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 +ISA_SET: AVX512DQ_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 -IFORM: VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512 +PATTERN: EVV 0x57 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VXORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 } { -ICLASS: VPTESTNMQ +ICLASS: VXORPD CPL: 3 -CATEGORY: LOGICAL +CATEGORY: LOGICAL_FP EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 +ISA_SET: AVX512DQ_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512 +PATTERN: EVV 0x57 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VXORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 } -# EMITTING VPTESTNMW (VPTESTNMW-128-1) +# EMITTING VXORPD (VXORPD-512-1) { -ICLASS: VPTESTNMW +ICLASS: VXORPD CPL: 3 -CATEGORY: LOGICAL +CATEGORY: LOGICAL_FP EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 +ISA_SET: AVX512DQ_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 -IFORM: VPTESTNMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 +PATTERN: EVV 0x57 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VXORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 } { -ICLASS: VPTESTNMW +ICLASS: VXORPD CPL: 3 -CATEGORY: LOGICAL +CATEGORY: LOGICAL_FP EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 +ISA_SET: AVX512DQ_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 -IFORM: VPTESTNMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x57 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VXORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 } -# EMITTING VPTESTNMW (VPTESTNMW-256-1) +# EMITTING VXORPS (VXORPS-128-1) { -ICLASS: VPTESTNMW +ICLASS: VXORPS CPL: 3 -CATEGORY: LOGICAL +CATEGORY: LOGICAL_FP EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 +ISA_SET: AVX512DQ_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 -IFORM: VPTESTNMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 +PATTERN: EVV 0x57 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VXORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 } { -ICLASS: VPTESTNMW +ICLASS: VXORPS CPL: 3 -CATEGORY: LOGICAL +CATEGORY: LOGICAL_FP EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 +ISA_SET: AVX512DQ_128 EXCEPTIONS: AVX512-E4 -REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 -IFORM: VPTESTNMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x57 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VXORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 } -# EMITTING VPTESTNMW (VPTESTNMW-512-1) +# EMITTING VXORPS (VXORPS-256-1) { -ICLASS: VPTESTNMW +ICLASS: VXORPS CPL: 3 -CATEGORY: LOGICAL +CATEGORY: LOGICAL_FP EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 +ISA_SET: AVX512DQ_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 -IFORM: VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 +PATTERN: EVV 0x57 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VXORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 } { -ICLASS: VPTESTNMW +ICLASS: VXORPS CPL: 3 -CATEGORY: LOGICAL +CATEGORY: LOGICAL_FP EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 +ISA_SET: AVX512DQ_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 -IFORM: VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x57 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VXORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 } -# EMITTING VPUNPCKHBW (VPUNPCKHBW-128-1) +# EMITTING VXORPS (VXORPS-512-1) { -ICLASS: VPUNPCKHBW +ICLASS: VXORPS CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL_FP EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x68 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 -OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 -IFORM: VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +PATTERN: EVV 0x57 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VXORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 } { -ICLASS: VPUNPCKHBW +ICLASS: VXORPS CPL: 3 -CATEGORY: AVX512 +CATEGORY: LOGICAL_FP EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x68 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 -IFORM: VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x57 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VXORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 } -# EMITTING VPUNPCKHBW (VPUNPCKHBW-256-1) +AVX_INSTRUCTIONS():: +# EMITTING KADDB (KADDB-256-1) { -ICLASS: VPUNPCKHBW +ICLASS: KADDB CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4NF +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x68 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 -OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 -IFORM: VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +ATTRIBUTES: KMASK +PATTERN: VV1 0x4A V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KADDB_MASKmskw_MASKmskw_MASKmskw_AVX512 } + +# EMITTING KADDD (KADDD-256-1) { -ICLASS: VPUNPCKHBW +ICLASS: KADDD CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4NF +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x68 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 -IFORM: VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +ATTRIBUTES: KMASK +PATTERN: VV1 0x4A V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KADDD_MASKmskw_MASKmskw_MASKmskw_AVX512 } -# EMITTING VPUNPCKHBW (VPUNPCKHBW-512-1) +# EMITTING KADDQ (KADDQ-256-1) { -ICLASS: VPUNPCKHBW +ICLASS: KADDQ CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4NF +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x68 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 -OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 -IFORM: VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +ATTRIBUTES: KMASK +PATTERN: VV1 0x4A VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KADDQ_MASKmskw_MASKmskw_MASKmskw_AVX512 } + +# EMITTING KADDW (KADDW-256-1) { -ICLASS: VPUNPCKHBW +ICLASS: KADDW CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4NF +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x68 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 -IFORM: VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +ATTRIBUTES: KMASK +PATTERN: VV1 0x4A VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KADDW_MASKmskw_MASKmskw_MASKmskw_AVX512 } -# EMITTING VPUNPCKHDQ (VPUNPCKHDQ-128-1) +# EMITTING KANDB (KANDB-256-1) { -ICLASS: VPUNPCKHDQ +ICLASS: KANDB CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x6A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 -IFORM: VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +ATTRIBUTES: KMASK +PATTERN: VV1 0x41 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KANDB_MASKmskw_MASKmskw_MASKmskw_AVX512 } + +# EMITTING KANDD (KANDD-256-1) { -ICLASS: VPUNPCKHDQ +ICLASS: KANDD CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x6A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +ATTRIBUTES: KMASK +PATTERN: VV1 0x41 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KANDD_MASKmskw_MASKmskw_MASKmskw_AVX512 } -# EMITTING VPUNPCKHDQ (VPUNPCKHDQ-256-1) +# EMITTING KANDNB (KANDNB-256-1) { -ICLASS: VPUNPCKHDQ +ICLASS: KANDNB CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x6A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 -IFORM: VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +ATTRIBUTES: KMASK +PATTERN: VV1 0x42 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KANDNB_MASKmskw_MASKmskw_MASKmskw_AVX512 } + +# EMITTING KANDND (KANDND-256-1) { -ICLASS: VPUNPCKHDQ +ICLASS: KANDND CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x6A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +ATTRIBUTES: KMASK +PATTERN: VV1 0x42 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KANDND_MASKmskw_MASKmskw_MASKmskw_AVX512 } -# EMITTING VPUNPCKHQDQ (VPUNPCKHQDQ-128-1) +# EMITTING KANDNQ (KANDNQ-256-1) { -ICLASS: VPUNPCKHQDQ +ICLASS: KANDNQ CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x6D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 -IFORM: VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +ATTRIBUTES: KMASK +PATTERN: VV1 0x42 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KANDNQ_MASKmskw_MASKmskw_MASKmskw_AVX512 } + +# EMITTING KANDQ (KANDQ-256-1) { -ICLASS: VPUNPCKHQDQ +ICLASS: KANDQ CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x6D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +ATTRIBUTES: KMASK +PATTERN: VV1 0x41 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KANDQ_MASKmskw_MASKmskw_MASKmskw_AVX512 } -# EMITTING VPUNPCKHQDQ (VPUNPCKHQDQ-256-1) +# EMITTING KMOVB (KMOVB-128-1) { -ICLASS: VPUNPCKHQDQ +ICLASS: KMOVB CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K21 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x6D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 -IFORM: VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +ATTRIBUTES: KMASK +PATTERN: VV1 0x90 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw:u8 +IFORM: KMOVB_MASKmskw_MASKu8_AVX512 } { -ICLASS: VPUNPCKHQDQ +ICLASS: KMOVB CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K21 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x6D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +ATTRIBUTES: KMASK +PATTERN: VV1 0x90 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL=0 W0 NOVSR +OPERANDS: REG0=MASK_R():w:mskw MEM0:r:b:u8 +IFORM: KMOVB_MASKmskw_MEMu8_AVX512 } -# EMITTING VPUNPCKHWD (VPUNPCKHWD-128-1) +# EMITTING KMOVB (KMOVB-128-2) { -ICLASS: VPUNPCKHWD +ICLASS: KMOVB CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4NF +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K21 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x69 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 -OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 -IFORM: VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +ATTRIBUTES: KMASK +PATTERN: VV1 0x91 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL=0 W0 NOVSR +OPERANDS: MEM0:w:b:u8 REG0=MASK_R():r:mskw +IFORM: KMOVB_MEMu8_MASKmskw_AVX512 } + +# EMITTING KMOVB (KMOVB-128-3) { -ICLASS: VPUNPCKHWD +ICLASS: KMOVB CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4NF +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x69 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 -IFORM: VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +ATTRIBUTES: KMASK +PATTERN: VV1 0x92 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR +OPERANDS: REG0=MASK_R():w:mskw REG1=GPR32_B():r:d:u32 +IFORM: KMOVB_MASKmskw_GPR32u32_AVX512 } -# EMITTING VPUNPCKHWD (VPUNPCKHWD-256-1) +# EMITTING KMOVB (KMOVB-128-4) { -ICLASS: VPUNPCKHWD +ICLASS: KMOVB CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4NF +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x69 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 -OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 -IFORM: VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +ATTRIBUTES: KMASK +PATTERN: VV1 0x93 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR +OPERANDS: REG0=GPR32_R():w:d:u32 REG1=MASK_B():r:mskw +IFORM: KMOVB_GPR32u32_MASKmskw_AVX512 } + +# EMITTING KMOVD (KMOVD-128-1) { -ICLASS: VPUNPCKHWD +ICLASS: KMOVD CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4NF +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K21 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x69 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 -IFORM: VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +ATTRIBUTES: KMASK +PATTERN: VV1 0x90 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw:u32 +IFORM: KMOVD_MASKmskw_MASKu32_AVX512 } - -# EMITTING VPUNPCKHWD (VPUNPCKHWD-512-1) { -ICLASS: VPUNPCKHWD +ICLASS: KMOVD CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4NF +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K21 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x69 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 -OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 -IFORM: VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +ATTRIBUTES: KMASK +PATTERN: VV1 0x90 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL=0 W1 NOVSR +OPERANDS: REG0=MASK_R():w:mskw MEM0:r:d:u32 +IFORM: KMOVD_MASKmskw_MEMu32_AVX512 } + +# EMITTING KMOVD (KMOVD-128-2) { -ICLASS: VPUNPCKHWD +ICLASS: KMOVD CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4NF +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K21 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x69 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 -IFORM: VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +ATTRIBUTES: KMASK +PATTERN: VV1 0x91 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL=0 W1 NOVSR +OPERANDS: MEM0:w:d:u32 REG0=MASK_R():r:mskw +IFORM: KMOVD_MEMu32_MASKmskw_AVX512 } -# EMITTING VPUNPCKLBW (VPUNPCKLBW-128-1) +# EMITTING KMOVD (KMOVD-128-3) { -ICLASS: VPUNPCKLBW +ICLASS: KMOVD CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4NF +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x60 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 -OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 -IFORM: VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +ATTRIBUTES: KMASK +COMMENT: KMOVQ aliases to KMOVD in 32b mode due to W bit being ignored. +PATTERN: VV1 0x92 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 mode64 NOVSR +OPERANDS: REG0=MASK_R():w:mskw REG1=GPR32_B():r:d:u32 +IFORM: KMOVD_MASKmskw_GPR32u32_AVX512 + +PATTERN: VV1 0x92 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 not64 NOVSR +OPERANDS: REG0=MASK_R():w:mskw REG1=GPR32_B():r:d:u32 +IFORM: KMOVD_MASKmskw_GPR32u32_AVX512 } + +# EMITTING KMOVD (KMOVD-128-4) { -ICLASS: VPUNPCKLBW +ICLASS: KMOVD CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4NF +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x60 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 -IFORM: VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +ATTRIBUTES: KMASK +COMMENT: KMOVQ aliases to KMOVD in 32b mode due to W bit being ignored. +PATTERN: VV1 0x93 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 mode64 NOVSR +OPERANDS: REG0=GPR32_R():w:d:u32 REG1=MASK_B():r:mskw +IFORM: KMOVD_GPR32u32_MASKmskw_AVX512 + +PATTERN: VV1 0x93 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 not64 NOVSR +OPERANDS: REG0=GPR32_R():w:d:u32 REG1=MASK_B():r:mskw +IFORM: KMOVD_GPR32u32_MASKmskw_AVX512 } -# EMITTING VPUNPCKLBW (VPUNPCKLBW-256-1) +# EMITTING KMOVQ (KMOVQ-128-1) { -ICLASS: VPUNPCKLBW +ICLASS: KMOVQ CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4NF +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K21 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x60 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 -OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 -IFORM: VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +ATTRIBUTES: KMASK +PATTERN: VV1 0x90 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw:u64 +IFORM: KMOVQ_MASKmskw_MASKu64_AVX512 } { -ICLASS: VPUNPCKLBW +ICLASS: KMOVQ CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4NF +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K21 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x60 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 -IFORM: VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +ATTRIBUTES: KMASK +PATTERN: VV1 0x90 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL=0 W1 NOVSR +OPERANDS: REG0=MASK_R():w:mskw MEM0:r:q:u64 +IFORM: KMOVQ_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING KMOVQ (KMOVQ-128-2) +{ +ICLASS: KMOVQ +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K21 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x91 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL=0 W1 NOVSR +OPERANDS: MEM0:w:q:u64 REG0=MASK_R():r:mskw +IFORM: KMOVQ_MEMu64_MASKmskw_AVX512 } -# EMITTING VPUNPCKLBW (VPUNPCKLBW-512-1) +# EMITTING KMOVQ (KMOVQ-128-3) { -ICLASS: VPUNPCKLBW +ICLASS: KMOVQ CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4NF +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x60 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 -OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 -IFORM: VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +ATTRIBUTES: KMASK +PATTERN: VV1 0x92 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 mode64 NOVSR +OPERANDS: REG0=MASK_R():w:mskw REG1=GPR64_B():r:q:u64 +IFORM: KMOVQ_MASKmskw_GPR64u64_AVX512 } + +# EMITTING KMOVQ (KMOVQ-128-4) { -ICLASS: VPUNPCKLBW +ICLASS: KMOVQ CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4NF +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x60 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 -IFORM: VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +ATTRIBUTES: KMASK +PATTERN: VV1 0x93 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 mode64 NOVSR +OPERANDS: REG0=GPR64_R():w:q:u64 REG1=MASK_B():r:mskw +IFORM: KMOVQ_GPR64u64_MASKmskw_AVX512 } -# EMITTING VPUNPCKLDQ (VPUNPCKLDQ-128-1) +# EMITTING KNOTB (KNOTB-128-1) { -ICLASS: VPUNPCKLDQ +ICLASS: KNOTB CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x62 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 -IFORM: VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +ATTRIBUTES: KMASK +PATTERN: VV1 0x44 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw +IFORM: KNOTB_MASKmskw_MASKmskw_AVX512 } + +# EMITTING KNOTD (KNOTD-128-1) { -ICLASS: VPUNPCKLDQ +ICLASS: KNOTD CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x62 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +ATTRIBUTES: KMASK +PATTERN: VV1 0x44 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw +IFORM: KNOTD_MASKmskw_MASKmskw_AVX512 } -# EMITTING VPUNPCKLDQ (VPUNPCKLDQ-256-1) +# EMITTING KNOTQ (KNOTQ-128-1) { -ICLASS: VPUNPCKLDQ +ICLASS: KNOTQ CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x62 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 -IFORM: VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +ATTRIBUTES: KMASK +PATTERN: VV1 0x44 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw +IFORM: KNOTQ_MASKmskw_MASKmskw_AVX512 } + +# EMITTING KORB (KORB-256-1) { -ICLASS: VPUNPCKLDQ +ICLASS: KORB CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x62 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +ATTRIBUTES: KMASK +PATTERN: VV1 0x45 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KORB_MASKmskw_MASKmskw_MASKmskw_AVX512 } -# EMITTING VPUNPCKLQDQ (VPUNPCKLQDQ-128-1) +# EMITTING KORD (KORD-256-1) { -ICLASS: VPUNPCKLQDQ +ICLASS: KORD CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x6C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 -IFORM: VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +ATTRIBUTES: KMASK +PATTERN: VV1 0x45 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KORD_MASKmskw_MASKmskw_MASKmskw_AVX512 } + +# EMITTING KORQ (KORQ-256-1) { -ICLASS: VPUNPCKLQDQ +ICLASS: KORQ CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x6C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +ATTRIBUTES: KMASK +PATTERN: VV1 0x45 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 } -# EMITTING VPUNPCKLQDQ (VPUNPCKLQDQ-256-1) +# EMITTING KORTESTB (KORTESTB-128-1) { -ICLASS: VPUNPCKLQDQ +ICLASS: KORTESTB CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x6C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 -IFORM: VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] +ATTRIBUTES: KMASK +PATTERN: VV1 0x98 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR +OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw +IFORM: KORTESTB_MASKmskw_MASKmskw_AVX512 } + +# EMITTING KORTESTD (KORTESTD-128-1) { -ICLASS: VPUNPCKLQDQ +ICLASS: KORTESTD CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x6C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] +ATTRIBUTES: KMASK +PATTERN: VV1 0x98 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR +OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw +IFORM: KORTESTD_MASKmskw_MASKmskw_AVX512 } -# EMITTING VPUNPCKLWD (VPUNPCKLWD-128-1) +# EMITTING KORTESTQ (KORTESTQ-128-1) { -ICLASS: VPUNPCKLWD +ICLASS: KORTESTQ CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4NF +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x61 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 -OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 -IFORM: VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] +ATTRIBUTES: KMASK +PATTERN: VV1 0x98 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR +OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw +IFORM: KORTESTQ_MASKmskw_MASKmskw_AVX512 } + +# EMITTING KSHIFTLB (KSHIFTLB-128-1) { -ICLASS: VPUNPCKLWD +ICLASS: KSHIFTLB CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_128 -EXCEPTIONS: AVX512-E4NF +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x61 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 -IFORM: VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +ATTRIBUTES: KMASK +PATTERN: VV1 0x32 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b +IFORM: KSHIFTLB_MASKmskw_MASKmskw_IMM8_AVX512 } -# EMITTING VPUNPCKLWD (VPUNPCKLWD-256-1) +# EMITTING KSHIFTLD (KSHIFTLD-128-1) { -ICLASS: VPUNPCKLWD +ICLASS: KSHIFTLD CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4NF +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x61 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 -OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 -IFORM: VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +ATTRIBUTES: KMASK +PATTERN: VV1 0x33 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b +IFORM: KSHIFTLD_MASKmskw_MASKmskw_IMM8_AVX512 } + +# EMITTING KSHIFTLQ (KSHIFTLQ-128-1) { -ICLASS: VPUNPCKLWD +ICLASS: KSHIFTLQ CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_256 -EXCEPTIONS: AVX512-E4NF +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x61 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 -IFORM: VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +ATTRIBUTES: KMASK +PATTERN: VV1 0x33 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b +IFORM: KSHIFTLQ_MASKmskw_MASKmskw_IMM8_AVX512 } -# EMITTING VPUNPCKLWD (VPUNPCKLWD-512-1) +# EMITTING KSHIFTRB (KSHIFTRB-128-1) { -ICLASS: VPUNPCKLWD +ICLASS: KSHIFTRB CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4NF +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x61 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 -OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 -IFORM: VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +ATTRIBUTES: KMASK +PATTERN: VV1 0x30 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b +IFORM: KSHIFTRB_MASKmskw_MASKmskw_IMM8_AVX512 } + +# EMITTING KSHIFTRD (KSHIFTRD-128-1) { -ICLASS: VPUNPCKLWD +ICLASS: KSHIFTRD CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512BW_512 -EXCEPTIONS: AVX512-E4NF +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x61 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 -IFORM: VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +ATTRIBUTES: KMASK +PATTERN: VV1 0x31 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b +IFORM: KSHIFTRD_MASKmskw_MASKmskw_IMM8_AVX512 } -# EMITTING VPXORD (VPXORD-128-1) +# EMITTING KSHIFTRQ (KSHIFTRQ-128-1) { -ICLASS: VPXORD +ICLASS: KSHIFTRQ CPL: 3 -CATEGORY: LOGICAL -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 -IFORM: VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +ATTRIBUTES: KMASK +PATTERN: VV1 0x31 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b +IFORM: KSHIFTRQ_MASKmskw_MASKmskw_IMM8_AVX512 } + +# EMITTING KTESTB (KTESTB-128-1) { -ICLASS: VPXORD +ICLASS: KTESTB CPL: 3 -CATEGORY: LOGICAL -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPXORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] +ATTRIBUTES: KMASK +PATTERN: VV1 0x99 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR +OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw +IFORM: KTESTB_MASKmskw_MASKmskw_AVX512 } -# EMITTING VPXORD (VPXORD-256-1) +# EMITTING KTESTD (KTESTD-128-1) { -ICLASS: VPXORD +ICLASS: KTESTD CPL: 3 -CATEGORY: LOGICAL -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 -IFORM: VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] +ATTRIBUTES: KMASK +PATTERN: VV1 0x99 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR +OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw +IFORM: KTESTD_MASKmskw_MASKmskw_AVX512 } + +# EMITTING KTESTQ (KTESTQ-128-1) { -ICLASS: VPXORD +ICLASS: KTESTQ CPL: 3 -CATEGORY: LOGICAL -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR -IFORM: VPXORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] +ATTRIBUTES: KMASK +PATTERN: VV1 0x99 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR +OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw +IFORM: KTESTQ_MASKmskw_MASKmskw_AVX512 } -# EMITTING VPXORQ (VPXORQ-128-1) +# EMITTING KTESTW (KTESTW-128-1) { -ICLASS: VPXORQ +ICLASS: KTESTW CPL: 3 -CATEGORY: LOGICAL -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 -IFORM: VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] +ATTRIBUTES: KMASK +PATTERN: VV1 0x99 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR +OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw +IFORM: KTESTW_MASKmskw_MASKmskw_AVX512 } + +# EMITTING KUNPCKDQ (KUNPCKDQ-256-1) { -ICLASS: VPXORQ +ICLASS: KUNPCKDQ CPL: 3 -CATEGORY: LOGICAL -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPXORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +ATTRIBUTES: KMASK +PATTERN: VV1 0x4B VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KUNPCKDQ_MASKmskw_MASKmskw_MASKmskw_AVX512 } -# EMITTING VPXORQ (VPXORQ-256-1) +# EMITTING KUNPCKWD (KUNPCKWD-256-1) { -ICLASS: VPXORQ +ICLASS: KUNPCKWD CPL: 3 -CATEGORY: LOGICAL -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 -IFORM: VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +ATTRIBUTES: KMASK +PATTERN: VV1 0x4B VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KUNPCKWD_MASKmskw_MASKmskw_MASKmskw_AVX512 } + +# EMITTING KXNORB (KXNORB-256-1) { -ICLASS: VPXORQ +ICLASS: KXNORB CPL: 3 -CATEGORY: LOGICAL -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPXORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +ATTRIBUTES: KMASK +PATTERN: VV1 0x46 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KXNORB_MASKmskw_MASKmskw_MASKmskw_AVX512 } -# EMITTING VRANGEPD (VRANGEPD-128-1) +# EMITTING KXNORD (KXNORD-256-1) { -ICLASS: VRANGEPD +ICLASS: KXNORD CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128 -EXCEPTIONS: AVX512-E2 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b -IFORM: VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +ATTRIBUTES: KMASK +PATTERN: VV1 0x46 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KXNORD_MASKmskw_MASKmskw_MASKmskw_AVX512 } + +# EMITTING KXNORQ (KXNORQ-256-1) { -ICLASS: VRANGEPD +ICLASS: KXNORQ CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128 -EXCEPTIONS: AVX512-E2 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b -IFORM: VRANGEPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 +ATTRIBUTES: KMASK +PATTERN: VV1 0x46 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KXNORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 } -# EMITTING VRANGEPD (VRANGEPD-256-1) +# EMITTING KXORB (KXORB-256-1) { -ICLASS: VRANGEPD +ICLASS: KXORB CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 -EXCEPTIONS: AVX512-E2 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 IMM0:r:b -IFORM: VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 +ATTRIBUTES: KMASK +PATTERN: VV1 0x47 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KXORB_MASKmskw_MASKmskw_MASKmskw_AVX512 } + +# EMITTING KXORD (KXORD-256-1) { -ICLASS: VRANGEPD +ICLASS: KXORD CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 -EXCEPTIONS: AVX512-E2 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b -IFORM: VRANGEPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 +ATTRIBUTES: KMASK +PATTERN: VV1 0x47 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KXORD_MASKmskw_MASKmskw_MASKmskw_AVX512 } -# EMITTING VRANGEPD (VRANGEPD-512-1) +# EMITTING KXORQ (KXORQ-256-1) { -ICLASS: VRANGEPD +ICLASS: KXORQ CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E2 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b -IFORM: VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 +ATTRIBUTES: KMASK +PATTERN: VV1 0x47 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KXORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 } + + + +###FILE: ../xed/datafiles/avx512ifma/ifma-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2018 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING VPMADD52HUQ (VPMADD52HUQ-128-1) { -ICLASS: VRANGEPD +ICLASS: VPMADD52HUQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: IFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512_IFMA_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 UIMM8() -OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b -IFORM: VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xB5 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 } { -ICLASS: VRANGEPD +ICLASS: VPMADD52HUQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: IFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512_IFMA_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b -IFORM: VRANGEPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xB5 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 } -# EMITTING VRANGEPS (VRANGEPS-128-1) +# EMITTING VPMADD52HUQ (VPMADD52HUQ-256-1) { -ICLASS: VRANGEPS +ICLASS: VPMADD52HUQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: IFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512_IFMA_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b -IFORM: VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xB5 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 } { -ICLASS: VRANGEPS +ICLASS: VPMADD52HUQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: IFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512_IFMA_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b -IFORM: VRANGEPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xB5 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 } -# EMITTING VRANGEPS (VRANGEPS-256-1) +# EMITTING VPMADD52HUQ (VPMADD52HUQ-512-1) { -ICLASS: VRANGEPS +ICLASS: VPMADD52HUQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: IFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512_IFMA_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 IMM0:r:b -IFORM: VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xB5 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 } { -ICLASS: VRANGEPS +ICLASS: VPMADD52HUQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: IFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512_IFMA_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b -IFORM: VRANGEPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xB5 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 } -# EMITTING VRANGEPS (VRANGEPS-512-1) +# EMITTING VPMADD52LUQ (VPMADD52LUQ-128-1) { -ICLASS: VRANGEPS +ICLASS: VPMADD52LUQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: IFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512_IFMA_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b -IFORM: VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xB4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 } { -ICLASS: VRANGEPS +ICLASS: VPMADD52LUQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: IFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512_IFMA_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 UIMM8() -OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b -IFORM: VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xB4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 } + +# EMITTING VPMADD52LUQ (VPMADD52LUQ-256-1) { -ICLASS: VRANGEPS +ICLASS: VPMADD52LUQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: IFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512_IFMA_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b -IFORM: VRANGEPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xB4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 } - -# EMITTING VRANGESD (VRANGESD-128-1) { -ICLASS: VRANGESD +ICLASS: VPMADD52LUQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: IFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512_IFMA_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x51 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 UIMM8() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b -IFORM: VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xB4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 } + +# EMITTING VPMADD52LUQ (VPMADD52LUQ-512-1) { -ICLASS: VRANGESD +ICLASS: VPMADD52LUQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: IFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512_IFMA_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x51 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 UIMM8() -OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b -IFORM: VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xB4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 } { -ICLASS: VRANGESD +ICLASS: VPMADD52LUQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: IFMA EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512_IFMA_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0x51 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b -IFORM: VRANGESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xB4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 } -# EMITTING VRANGESS (VRANGESS-128-1) -{ -ICLASS: VRANGESS -CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_SCALAR -EXCEPTIONS: AVX512-E3 -REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x51 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 UIMM8() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b -IFORM: VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 -} + +###FILE: ../xed/datafiles/avx512vbmi/vbmi-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2018 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING VPERMB (VPERMB-128-1) { -ICLASS: VRANGESS +ICLASS: VPERMB CPL: 3 -CATEGORY: AVX512 +CATEGORY: AVX512_VBMI EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512_VBMI_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x51 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8() -OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b -IFORM: VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPERMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 } { -ICLASS: VRANGESS +ICLASS: VPERMB CPL: 3 -CATEGORY: AVX512 +CATEGORY: AVX512_VBMI EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512_VBMI_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0x51 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b -IFORM: VRANGESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPERMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 } -# EMITTING VRCP14PD (VRCP14PD-128-1) +# EMITTING VPERMB (VPERMB-256-1) { -ICLASS: VRCP14PD +ICLASS: VPERMB CPL: 3 -CATEGORY: AVX512 +CATEGORY: AVX512_VBMI EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512_VBMI_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 -IFORM: VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPERMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 } { -ICLASS: VRCP14PD +ICLASS: VPERMB CPL: 3 -CATEGORY: AVX512 +CATEGORY: AVX512_VBMI EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512_VBMI_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VRCP14PD_XMMf64_MASKmskw_MEMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPERMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 } -# EMITTING VRCP14PD (VRCP14PD-256-1) +# EMITTING VPERMB (VPERMB-512-1) { -ICLASS: VRCP14PD +ICLASS: VPERMB CPL: 3 -CATEGORY: AVX512 +CATEGORY: AVX512_VBMI EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512_VBMI_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 -IFORM: VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPERMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 } { -ICLASS: VRCP14PD +ICLASS: VPERMB CPL: 3 -CATEGORY: AVX512 +CATEGORY: AVX512_VBMI EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512_VBMI_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VRCP14PD_YMMf64_MASKmskw_MEMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPERMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 } -# EMITTING VRCP14PS (VRCP14PS-128-1) +# EMITTING VPERMI2B (VPERMI2B-128-1) { -ICLASS: VRCP14PS +ICLASS: VPERMI2B CPL: 3 -CATEGORY: AVX512 +CATEGORY: AVX512_VBMI EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512_VBMI_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 -IFORM: VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPERMI2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 } { -ICLASS: VRCP14PS +ICLASS: VPERMI2B CPL: 3 -CATEGORY: AVX512 +CATEGORY: AVX512_VBMI EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512_VBMI_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VRCP14PS_XMMf32_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():rw:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPERMI2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 } -# EMITTING VRCP14PS (VRCP14PS-256-1) +# EMITTING VPERMI2B (VPERMI2B-256-1) { -ICLASS: VRCP14PS +ICLASS: VPERMI2B CPL: 3 -CATEGORY: AVX512 +CATEGORY: AVX512_VBMI EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512_VBMI_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 -IFORM: VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPERMI2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 } { -ICLASS: VRCP14PS +ICLASS: VPERMI2B CPL: 3 -CATEGORY: AVX512 +CATEGORY: AVX512_VBMI EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4 +ISA_SET: AVX512_VBMI_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VRCP14PS_YMMf32_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():rw:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPERMI2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 } -# EMITTING VREDUCEPD (VREDUCEPD-128-1) +# EMITTING VPERMI2B (VPERMI2B-512-1) { -ICLASS: VREDUCEPD +ICLASS: VPERMI2B CPL: 3 -CATEGORY: AVX512 +CATEGORY: AVX512_VBMI EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512_VBMI_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR UIMM8() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 IMM0:r:b -IFORM: VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPERMI2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 } { -ICLASS: VREDUCEPD +ICLASS: VPERMI2B CPL: 3 -CATEGORY: AVX512 +CATEGORY: AVX512_VBMI EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512_VBMI_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b -IFORM: VREDUCEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():rw:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPERMI2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 } -# EMITTING VREDUCEPD (VREDUCEPD-256-1) +# EMITTING VPERMT2B (VPERMT2B-128-1) { -ICLASS: VREDUCEPD +ICLASS: VPERMT2B CPL: 3 -CATEGORY: AVX512 +CATEGORY: AVX512_VBMI EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512_VBMI_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 IMM0:r:b -IFORM: VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPERMT2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 } { -ICLASS: VREDUCEPD +ICLASS: VPERMT2B CPL: 3 -CATEGORY: AVX512 +CATEGORY: AVX512_VBMI EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512_VBMI_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b -IFORM: VREDUCEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():rw:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPERMT2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 } -# EMITTING VREDUCEPD (VREDUCEPD-512-1) +# EMITTING VPERMT2B (VPERMT2B-256-1) { -ICLASS: VREDUCEPD +ICLASS: VPERMT2B CPL: 3 -CATEGORY: AVX512 +CATEGORY: AVX512_VBMI EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512_VBMI_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b -IFORM: VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPERMT2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 } { -ICLASS: VREDUCEPD +ICLASS: VPERMT2B CPL: 3 -CATEGORY: AVX512 +CATEGORY: AVX512_VBMI EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512_VBMI_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR UIMM8() -OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b -IFORM: VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():rw:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPERMT2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 } + +# EMITTING VPERMT2B (VPERMT2B-512-1) { -ICLASS: VREDUCEPD +ICLASS: VPERMT2B CPL: 3 -CATEGORY: AVX512 +CATEGORY: AVX512_VBMI EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512_VBMI_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b -IFORM: VREDUCEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPERMT2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPERMT2B +CPL: 3 +CATEGORY: AVX512_VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():rw:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPERMT2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 } -# EMITTING VREDUCEPS (VREDUCEPS-128-1) +# EMITTING VPMULTISHIFTQB (VPMULTISHIFTQB-128-1) { -ICLASS: VREDUCEPS +ICLASS: VPMULTISHIFTQB CPL: 3 -CATEGORY: AVX512 +CATEGORY: AVX512_VBMI EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512_VBMI_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 IMM0:r:b -IFORM: VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x83 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u64 +IFORM: VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_XMMu64_AVX512 } { -ICLASS: VREDUCEPS +ICLASS: VPMULTISHIFTQB CPL: 3 -CATEGORY: AVX512 +CATEGORY: AVX512_VBMI EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512_VBMI_128 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b -IFORM: VREDUCEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x83 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_MEMu64_AVX512 } -# EMITTING VREDUCEPS (VREDUCEPS-256-1) +# EMITTING VPMULTISHIFTQB (VPMULTISHIFTQB-256-1) { -ICLASS: VREDUCEPS +ICLASS: VPMULTISHIFTQB CPL: 3 -CATEGORY: AVX512 +CATEGORY: AVX512_VBMI EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512_VBMI_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 IMM0:r:b -IFORM: VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x83 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u64 +IFORM: VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_YMMu64_AVX512 } { -ICLASS: VREDUCEPS +ICLASS: VPMULTISHIFTQB CPL: 3 -CATEGORY: AVX512 +CATEGORY: AVX512_VBMI EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512_VBMI_256 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b -IFORM: VREDUCEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x83 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_MEMu64_AVX512 } -# EMITTING VREDUCEPS (VREDUCEPS-512-1) +# EMITTING VPMULTISHIFTQB (VPMULTISHIFTQB-512-1) { -ICLASS: VREDUCEPS +ICLASS: VPMULTISHIFTQB CPL: 3 -CATEGORY: AVX512 +CATEGORY: AVX512_VBMI EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512_VBMI_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b -IFORM: VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x83 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu64 +IFORM: VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_AVX512 } { -ICLASS: VREDUCEPS +ICLASS: VPMULTISHIFTQB CPL: 3 -CATEGORY: AVX512 +CATEGORY: AVX512_VBMI EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512_VBMI_512 +EXCEPTIONS: AVX512-E4NF REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8() -OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b -IFORM: VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x83 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_AVX512 } + + + +###FILE: ../xed/datafiles/wbnoinvd/wbnoinvd-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2018 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +INSTRUCTIONS():: { -ICLASS: VREDUCEPS -CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 -EXCEPTIONS: AVX512-E2 +ICLASS : WBINVD +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I486REAL +ATTRIBUTES : RING0 NOTSX +PATTERN : 0x0F 0x09 WBNOINVD=0 +OPERANDS : +PATTERN : 0x0F 0x09 WBNOINVD=1 REP!=3 +OPERANDS : +VERSION : 2 +} + +{ +ICLASS : WBNOINVD +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : WBNOINVD +ISA_SET : WBNOINVD +ATTRIBUTES : RING0 NOTSX +PATTERN : 0x0F 0x09 WBNOINVD=1 f3_refining_prefix +OPERANDS : +} + + +###FILE: ../xed/datafiles/pconfig/pconfig-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2018 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +INSTRUCTIONS():: +# EMITTING PCONFIG (PCONFIG-N/A-1) +{ +ICLASS: PCONFIG +CPL: 0 +CATEGORY: PCONFIG +EXTENSION: PCONFIG +ISA_SET: PCONFIG REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b -IFORM: VREDUCEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 +FLAGS: MUST [ zf-mod cf-0 pf-0 of-0 sf-0 af-0 ] +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b101] no_refining_prefix +OPERANDS: REG0=XED_REG_EAX:rw:SUPP:d:u32 REG1=XED_REG_EBX:crw:SUPP:d:u32 REG2=XED_REG_ECX:crw:SUPP:d:u32 REG3=XED_REG_EDX:crw:SUPP:d:u32 +IFORM: PCONFIG } -# EMITTING VREDUCESD (VREDUCESD-128-1) + + +###FILE: ../xed/datafiles/bitalg/bitalg-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2018 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING VPOPCNTB (VPOPCNTB-128-1) { -ICLASS: VREDUCESD +ICLASS: VPOPCNTB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512_BITALG_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x57 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 UIMM8() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b -IFORM: VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x54 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u8 +IFORM: VPOPCNTB_XMMu8_MASKmskw_XMMu8_AVX512 } { -ICLASS: VREDUCESD +ICLASS: VPOPCNTB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512_BITALG_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x57 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 UIMM8() -OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b -IFORM: VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x54 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u8 +IFORM: VPOPCNTB_XMMu8_MASKmskw_MEMu8_AVX512 } + +# EMITTING VPOPCNTB (VPOPCNTB-256-1) { -ICLASS: VREDUCESD +ICLASS: VPOPCNTB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512_BITALG_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0x57 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b -IFORM: VREDUCESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x54 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u8 +IFORM: VPOPCNTB_YMMu8_MASKmskw_YMMu8_AVX512 } - -# EMITTING VREDUCESS (VREDUCESS-128-1) { -ICLASS: VREDUCESS +ICLASS: VPOPCNTB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512_BITALG_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x57 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 UIMM8() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b -IFORM: VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x54 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u8 +IFORM: VPOPCNTB_YMMu8_MASKmskw_MEMu8_AVX512 } + +# EMITTING VPOPCNTB (VPOPCNTB-512-1) { -ICLASS: VREDUCESS +ICLASS: VPOPCNTB CPL: 3 -CATEGORY: AVX512 +CATEGORY: AVX512_BITALG EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512_BITALG_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX -PATTERN: EVV 0x57 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8() -OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b -IFORM: VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x54 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu8 +IFORM: VPOPCNTB_ZMMu8_MASKmskw_ZMMu8_AVX512 } { -ICLASS: VREDUCESS +ICLASS: VPOPCNTB CPL: 3 -CATEGORY: AVX512 +CATEGORY: AVX512_BITALG EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_SCALAR -EXCEPTIONS: AVX512-E3 +ISA_SET: AVX512_BITALG_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR -PATTERN: EVV 0x57 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b -IFORM: VREDUCESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x54 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u8 +IFORM: VPOPCNTB_ZMMu8_MASKmskw_MEMu8_AVX512 } -# EMITTING VRNDSCALEPD (VRNDSCALEPD-128-1) +# EMITTING VPOPCNTW (VPOPCNTW-128-1) { -ICLASS: VRNDSCALEPD +ICLASS: VPOPCNTW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512_BITALG_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x09 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR UIMM8() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 IMM0:r:b -IFORM: VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x54 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 +IFORM: VPOPCNTW_XMMu16_MASKmskw_XMMu16_AVX512 } { -ICLASS: VRNDSCALEPD +ICLASS: VPOPCNTW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512_BITALG_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x09 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b -IFORM: VRNDSCALEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x54 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 +IFORM: VPOPCNTW_XMMu16_MASKmskw_MEMu16_AVX512 } -# EMITTING VRNDSCALEPD (VRNDSCALEPD-256-1) +# EMITTING VPOPCNTW (VPOPCNTW-256-1) { -ICLASS: VRNDSCALEPD +ICLASS: VPOPCNTW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512_BITALG_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x09 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 IMM0:r:b -IFORM: VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x54 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 +IFORM: VPOPCNTW_YMMu16_MASKmskw_YMMu16_AVX512 } { -ICLASS: VRNDSCALEPD +ICLASS: VPOPCNTW CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512_BITALG_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x09 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b -IFORM: VRNDSCALEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x54 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 +IFORM: VPOPCNTW_YMMu16_MASKmskw_MEMu16_AVX512 } -# EMITTING VRNDSCALEPS (VRNDSCALEPS-128-1) +# EMITTING VPOPCNTW (VPOPCNTW-512-1) { -ICLASS: VRNDSCALEPS +ICLASS: VPOPCNTW CPL: 3 -CATEGORY: AVX512 +CATEGORY: AVX512_BITALG EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512_BITALG_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x08 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 IMM0:r:b -IFORM: VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x54 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 +IFORM: VPOPCNTW_ZMMu16_MASKmskw_ZMMu16_AVX512 } { -ICLASS: VRNDSCALEPS +ICLASS: VPOPCNTW CPL: 3 -CATEGORY: AVX512 +CATEGORY: AVX512_BITALG EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512_BITALG_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x08 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b -IFORM: VRNDSCALEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x54 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 +IFORM: VPOPCNTW_ZMMu16_MASKmskw_MEMu16_AVX512 } -# EMITTING VRNDSCALEPS (VRNDSCALEPS-256-1) +# EMITTING VPSHUFBITQMB (VPSHUFBITQMB-128-1) { -ICLASS: VRNDSCALEPS +ICLASS: VPSHUFBITQMB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512_BITALG_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x08 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 IMM0:r:b -IFORM: VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u8 +IFORM: VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_XMMu8_AVX512 } { -ICLASS: VRNDSCALEPS +ICLASS: VPSHUFBITQMB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512_BITALG_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x08 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b -IFORM: VRNDSCALEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x8F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 MEM0:r:dq:u8 +IFORM: VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_MEMu8_AVX512 } -# EMITTING VRSQRT14PD (VRSQRT14PD-128-1) +# EMITTING VPSHUFBITQMB (VPSHUFBITQMB-256-1) { -ICLASS: VRSQRT14PD +ICLASS: VPSHUFBITQMB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512_BITALG_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 -IFORM: VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u8 +IFORM: VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_YMMu8_AVX512 } { -ICLASS: VRSQRT14PD +ICLASS: VPSHUFBITQMB CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512_BITALG_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VRSQRT14PD_XMMf64_MASKmskw_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x8F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 MEM0:r:qq:u8 +IFORM: VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_MEMu8_AVX512 } -# EMITTING VRSQRT14PD (VRSQRT14PD-256-1) +# EMITTING VPSHUFBITQMB (VPSHUFBITQMB-512-1) { -ICLASS: VRSQRT14PD +ICLASS: VPSHUFBITQMB CPL: 3 -CATEGORY: AVX512 +CATEGORY: AVX512_BITALG EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 +ISA_SET: AVX512_BITALG_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 -IFORM: VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu8 +IFORM: VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_ZMMu8_AVX512 } { -ICLASS: VRSQRT14PD +ICLASS: VPSHUFBITQMB CPL: 3 -CATEGORY: AVX512 +CATEGORY: AVX512_BITALG EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 +ISA_SET: AVX512_BITALG_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VRSQRT14PD_YMMf64_MASKmskw_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x8F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 MEM0:r:zd:u8 +IFORM: VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_MEMu8_AVX512 } -# EMITTING VRSQRT14PS (VRSQRT14PS-128-1) + + +###FILE: ../xed/datafiles/vbmi2/vbmi2-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2018 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING VPCOMPRESSB (VPCOMPRESSB-128-1) { -ICLASS: VRSQRT14PS +ICLASS: VPCOMPRESSB CPL: 3 -CATEGORY: AVX512 +CATEGORY: COMPRESS EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512_VBMI2_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 -IFORM: VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x63 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:dq:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u8 +IFORM: VPCOMPRESSB_MEMu8_MASKmskw_XMMu8_AVX512 } + +# EMITTING VPCOMPRESSB (VPCOMPRESSB-128-2) { -ICLASS: VRSQRT14PS +ICLASS: VPCOMPRESSB CPL: 3 -CATEGORY: AVX512 +CATEGORY: COMPRESS EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 +ISA_SET: AVX512_VBMI2_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VRSQRT14PS_XMMf32_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u8 +IFORM: VPCOMPRESSB_XMMu8_MASKmskw_XMMu8_AVX512 } -# EMITTING VRSQRT14PS (VRSQRT14PS-256-1) +# EMITTING VPCOMPRESSB (VPCOMPRESSB-256-1) { -ICLASS: VRSQRT14PS +ICLASS: VPCOMPRESSB CPL: 3 -CATEGORY: AVX512 +CATEGORY: COMPRESS EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 +ISA_SET: AVX512_VBMI2_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 -IFORM: VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x63 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:qq:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u8 +IFORM: VPCOMPRESSB_MEMu8_MASKmskw_YMMu8_AVX512 } + +# EMITTING VPCOMPRESSB (VPCOMPRESSB-256-2) { -ICLASS: VRSQRT14PS +ICLASS: VPCOMPRESSB CPL: 3 -CATEGORY: AVX512 +CATEGORY: COMPRESS EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 +ISA_SET: AVX512_VBMI2_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u8 +IFORM: VPCOMPRESSB_YMMu8_MASKmskw_YMMu8_AVX512 } -# EMITTING VSCALEFPD (VSCALEFPD-128-1) -{ -ICLASS: VSCALEFPD -CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 -REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 -} - +# EMITTING VPCOMPRESSB (VPCOMPRESSB-512-1) { -ICLASS: VSCALEFPD +ICLASS: VPCOMPRESSB CPL: 3 -CATEGORY: AVX512 +CATEGORY: COMPRESS EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VSCALEFPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x63 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:zd:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu8 +IFORM: VPCOMPRESSB_MEMu8_MASKmskw_ZMMu8_AVX512 } -# EMITTING VSCALEFPD (VSCALEFPD-256-1) +# EMITTING VPCOMPRESSB (VPCOMPRESSB-512-2) { -ICLASS: VSCALEFPD +ICLASS: VPCOMPRESSB CPL: 3 -CATEGORY: AVX512 +CATEGORY: COMPRESS EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 -IFORM: VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu8 +IFORM: VPCOMPRESSB_ZMMu8_MASKmskw_ZMMu8_AVX512 } + +# EMITTING VPCOMPRESSW (VPCOMPRESSW-128-1) { -ICLASS: VSCALEFPD +ICLASS: VPCOMPRESSW CPL: 3 -CATEGORY: AVX512 +CATEGORY: COMPRESS EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VSCALEFPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x63 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:dq:u16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u16 +IFORM: VPCOMPRESSW_MEMu16_MASKmskw_XMMu16_AVX512 } -# EMITTING VSCALEFPS (VSCALEFPS-128-1) +# EMITTING VPCOMPRESSW (VPCOMPRESSW-128-2) { -ICLASS: VSCALEFPS +ICLASS: VPCOMPRESSW CPL: 3 -CATEGORY: AVX512 +CATEGORY: COMPRESS EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u16 +IFORM: VPCOMPRESSW_XMMu16_MASKmskw_XMMu16_AVX512 } + +# EMITTING VPCOMPRESSW (VPCOMPRESSW-256-1) { -ICLASS: VSCALEFPS +ICLASS: VPCOMPRESSW CPL: 3 -CATEGORY: AVX512 +CATEGORY: COMPRESS EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VSCALEFPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x63 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:qq:u16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u16 +IFORM: VPCOMPRESSW_MEMu16_MASKmskw_YMMu16_AVX512 } -# EMITTING VSCALEFPS (VSCALEFPS-256-1) +# EMITTING VPCOMPRESSW (VPCOMPRESSW-256-2) { -ICLASS: VSCALEFPS +ICLASS: VPCOMPRESSW CPL: 3 -CATEGORY: AVX512 +CATEGORY: COMPRESS EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 -IFORM: VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u16 +IFORM: VPCOMPRESSW_YMMu16_MASKmskw_YMMu16_AVX512 } + +# EMITTING VPCOMPRESSW (VPCOMPRESSW-512-1) { -ICLASS: VSCALEFPS +ICLASS: VPCOMPRESSW CPL: 3 -CATEGORY: AVX512 +CATEGORY: COMPRESS EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VSCALEFPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x63 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:zd:u16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu16 +IFORM: VPCOMPRESSW_MEMu16_MASKmskw_ZMMu16_AVX512 } -# EMITTING VSCATTERDPD (VSCATTERDPD-128-1) +# EMITTING VPCOMPRESSW (VPCOMPRESSW-512-2) { -ICLASS: VSCATTERDPD +ICLASS: VPCOMPRESSW CPL: 3 -CATEGORY: SCATTER +CATEGORY: COMPRESS EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E12 +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W1 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() -OPERANDS: MEM0:w:dq:f64 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:f64 -IFORM: VSCATTERDPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu16 +IFORM: VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512 } -# EMITTING VSCATTERDPD (VSCATTERDPD-256-1) +# EMITTING VPEXPANDB (VPEXPANDB-128-1) { -ICLASS: VSCATTERDPD +ICLASS: VPEXPANDB CPL: 3 -CATEGORY: SCATTER +CATEGORY: EXPAND EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E12 +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W1 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() -OPERANDS: MEM0:w:qq:f64 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:f64 -IFORM: VSCATTERDPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x62 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_8_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u8 +IFORM: VPEXPANDB_XMMu8_MASKmskw_MEMu8_AVX512 } -# EMITTING VSCATTERDPS (VSCATTERDPS-128-1) +# EMITTING VPEXPANDB (VPEXPANDB-128-2) { -ICLASS: VSCATTERDPS +ICLASS: VPEXPANDB CPL: 3 -CATEGORY: SCATTER +CATEGORY: EXPAND EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E12 +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W0 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() -OPERANDS: MEM0:w:dq:f32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:f32 -IFORM: VSCATTERDPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x62 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u8 +IFORM: VPEXPANDB_XMMu8_MASKmskw_XMMu8_AVX512 } -# EMITTING VSCATTERDPS (VSCATTERDPS-256-1) +# EMITTING VPEXPANDB (VPEXPANDB-256-1) { -ICLASS: VSCATTERDPS +ICLASS: VPEXPANDB CPL: 3 -CATEGORY: SCATTER +CATEGORY: EXPAND EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E12 +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W0 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() -OPERANDS: MEM0:w:qq:f32 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:f32 -IFORM: VSCATTERDPS_MEMf32_MASKmskw_YMMf32_AVX512_VL256 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x62 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_8_BITS() NELEM_GSCAT() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u8 +IFORM: VPEXPANDB_YMMu8_MASKmskw_MEMu8_AVX512 } -# EMITTING VSCATTERQPD (VSCATTERQPD-128-1) +# EMITTING VPEXPANDB (VPEXPANDB-256-2) { -ICLASS: VSCATTERQPD +ICLASS: VPEXPANDB CPL: 3 -CATEGORY: SCATTER +CATEGORY: EXPAND EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E12 +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W1 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() -OPERANDS: MEM0:w:dq:f64 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:f64 -IFORM: VSCATTERQPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x62 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u8 +IFORM: VPEXPANDB_YMMu8_MASKmskw_YMMu8_AVX512 } -# EMITTING VSCATTERQPD (VSCATTERQPD-256-1) +# EMITTING VPEXPANDB (VPEXPANDB-512-1) { -ICLASS: VSCATTERQPD +ICLASS: VPEXPANDB CPL: 3 -CATEGORY: SCATTER +CATEGORY: EXPAND EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E12 +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() -OPERANDS: MEM0:w:qq:f64 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:f64 -IFORM: VSCATTERQPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x62 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_8_BITS() NELEM_GSCAT() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u8 +IFORM: VPEXPANDB_ZMMu8_MASKmskw_MEMu8_AVX512 } -# EMITTING VSCATTERQPS (VSCATTERQPS-128-1) +# EMITTING VPEXPANDB (VPEXPANDB-512-2) { -ICLASS: VSCATTERQPS +ICLASS: VPEXPANDB CPL: 3 -CATEGORY: SCATTER +CATEGORY: EXPAND EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E12 +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W0 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() -OPERANDS: MEM0:w:q:f32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:f32 -IFORM: VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x62 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu8 +IFORM: VPEXPANDB_ZMMu8_MASKmskw_ZMMu8_AVX512 } -# EMITTING VSCATTERQPS (VSCATTERQPS-256-1) +# EMITTING VPEXPANDW (VPEXPANDW-128-1) { -ICLASS: VSCATTERQPS +ICLASS: VPEXPANDW CPL: 3 -CATEGORY: SCATTER +CATEGORY: EXPAND EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E12 +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT -PATTERN: EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W0 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() -OPERANDS: MEM0:w:dq:f32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:f32 -IFORM: VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL256 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x62 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_16_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 +IFORM: VPEXPANDW_XMMu16_MASKmskw_MEMu16_AVX512 } -# EMITTING VSHUFF32X4 (VSHUFF32X4-256-1) +# EMITTING VPEXPANDW (VPEXPANDW-128-2) { -ICLASS: VSHUFF32X4 +ICLASS: VPEXPANDW CPL: 3 -CATEGORY: AVX512 +CATEGORY: EXPAND EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x23 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 IMM0:r:b -IFORM: VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 +PATTERN: EVV 0x62 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 +IFORM: VPEXPANDW_XMMu16_MASKmskw_XMMu16_AVX512 } + +# EMITTING VPEXPANDW (VPEXPANDW-256-1) { -ICLASS: VSHUFF32X4 +ICLASS: VPEXPANDW CPL: 3 -CATEGORY: AVX512 +CATEGORY: EXPAND EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x23 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b -IFORM: VSHUFF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x62 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_16_BITS() NELEM_GSCAT() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 +IFORM: VPEXPANDW_YMMu16_MASKmskw_MEMu16_AVX512 } -# EMITTING VSHUFF64X2 (VSHUFF64X2-256-1) +# EMITTING VPEXPANDW (VPEXPANDW-256-2) { -ICLASS: VSHUFF64X2 +ICLASS: VPEXPANDW CPL: 3 -CATEGORY: AVX512 +CATEGORY: EXPAND EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x23 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 IMM0:r:b -IFORM: VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 +PATTERN: EVV 0x62 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 +IFORM: VPEXPANDW_YMMu16_MASKmskw_YMMu16_AVX512 } + +# EMITTING VPEXPANDW (VPEXPANDW-512-1) { -ICLASS: VSHUFF64X2 +ICLASS: VPEXPANDW CPL: 3 -CATEGORY: AVX512 +CATEGORY: EXPAND EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x23 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b -IFORM: VSHUFF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x62 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_16_BITS() NELEM_GSCAT() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 +IFORM: VPEXPANDW_ZMMu16_MASKmskw_MEMu16_AVX512 } -# EMITTING VSHUFI32X4 (VSHUFI32X4-256-1) +# EMITTING VPEXPANDW (VPEXPANDW-512-2) { -ICLASS: VSHUFI32X4 +ICLASS: VPEXPANDW CPL: 3 -CATEGORY: AVX512 +CATEGORY: EXPAND EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x43 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 IMM0:r:b -IFORM: VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 -} - -{ -ICLASS: VSHUFI32X4 -CPL: 3 -CATEGORY: AVX512 -EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF -REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x43 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b -IFORM: VSHUFI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 +PATTERN: EVV 0x62 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 +IFORM: VPEXPANDW_ZMMu16_MASKmskw_ZMMu16_AVX512 } -# EMITTING VSHUFI64X2 (VSHUFI64X2-256-1) +# EMITTING VPSHLDD (VPSHLDD-128-1) { -ICLASS: VSHUFI64X2 +ICLASS: VPSHLDD CPL: 3 -CATEGORY: AVX512 +CATEGORY: VBMI2 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x43 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 IMM0:r:b -IFORM: VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 +PATTERN: EVV 0x71 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 IMM0:r:b +IFORM: VPSHLDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 } { -ICLASS: VSHUFI64X2 +ICLASS: VPSHLDD CPL: 3 -CATEGORY: AVX512 +CATEGORY: VBMI2 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x43 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b -IFORM: VSHUFI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSHLDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 } -# EMITTING VSHUFPD (VSHUFPD-128-1) +# EMITTING VPSHLDD (VPSHLDD-256-1) { -ICLASS: VSHUFPD +ICLASS: VPSHLDD CPL: 3 -CATEGORY: AVX512 +CATEGORY: VBMI2 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xC6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b -IFORM: VSHUFPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +PATTERN: EVV 0x71 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 IMM0:r:b +IFORM: VPSHLDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 } { -ICLASS: VSHUFPD +ICLASS: VPSHLDD CPL: 3 -CATEGORY: AVX512 +CATEGORY: VBMI2 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xC6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b -IFORM: VSHUFPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSHLDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 } -# EMITTING VSHUFPD (VSHUFPD-256-1) +# EMITTING VPSHLDD (VPSHLDD-512-1) { -ICLASS: VSHUFPD +ICLASS: VPSHLDD CPL: 3 -CATEGORY: AVX512 +CATEGORY: VBMI2 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xC6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 IMM0:r:b -IFORM: VSHUFPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 +PATTERN: EVV 0x71 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 IMM0:r:b +IFORM: VPSHLDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 } { -ICLASS: VSHUFPD +ICLASS: VPSHLDD CPL: 3 -CATEGORY: AVX512 +CATEGORY: VBMI2 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xC6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b -IFORM: VSHUFPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSHLDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 } -# EMITTING VSHUFPS (VSHUFPS-128-1) +# EMITTING VPSHLDQ (VPSHLDQ-128-1) { -ICLASS: VSHUFPS +ICLASS: VPSHLDQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: VBMI2 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xC6 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b -IFORM: VSHUFPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +PATTERN: EVV 0x71 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 IMM0:r:b +IFORM: VPSHLDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 } { -ICLASS: VSHUFPS +ICLASS: VPSHLDQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: VBMI2 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xC6 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b -IFORM: VSHUFPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPSHLDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 } -# EMITTING VSHUFPS (VSHUFPS-256-1) +# EMITTING VPSHLDQ (VPSHLDQ-256-1) { -ICLASS: VSHUFPS +ICLASS: VPSHLDQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: VBMI2 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xC6 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 IMM0:r:b -IFORM: VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 +PATTERN: EVV 0x71 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VPSHLDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 } { -ICLASS: VSHUFPS +ICLASS: VPSHLDQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: VBMI2 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xC6 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b -IFORM: VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPSHLDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 } -# EMITTING VSQRTPD (VSQRTPD-128-1) +# EMITTING VPSHLDQ (VPSHLDQ-512-1) { -ICLASS: VSQRTPD +ICLASS: VPSHLDQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: VBMI2 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x51 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 -IFORM: VSQRTPD_XMMf64_MASKmskw_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 IMM0:r:b +IFORM: VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 } { -ICLASS: VSQRTPD +ICLASS: VPSHLDQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: VBMI2 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x51 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VSQRTPD_XMMf64_MASKmskw_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 } -# EMITTING VSQRTPD (VSQRTPD-256-1) +# EMITTING VPSHLDVD (VPSHLDVD-128-1) { -ICLASS: VSQRTPD +ICLASS: VPSHLDVD CPL: 3 -CATEGORY: AVX512 +CATEGORY: VBMI2 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x51 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 -IFORM: VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSHLDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 } { -ICLASS: VSQRTPD +ICLASS: VPSHLDVD CPL: 3 -CATEGORY: AVX512 +CATEGORY: VBMI2 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x51 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VSQRTPD_YMMf64_MASKmskw_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSHLDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 } -# EMITTING VSQRTPS (VSQRTPS-128-1) +# EMITTING VPSHLDVD (VPSHLDVD-256-1) { -ICLASS: VSQRTPS +ICLASS: VPSHLDVD CPL: 3 -CATEGORY: AVX512 +CATEGORY: VBMI2 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x51 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 -IFORM: VSQRTPS_XMMf32_MASKmskw_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPSHLDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 } { -ICLASS: VSQRTPS +ICLASS: VPSHLDVD CPL: 3 -CATEGORY: AVX512 +CATEGORY: VBMI2 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x51 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VSQRTPS_XMMf32_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSHLDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 } -# EMITTING VSQRTPS (VSQRTPS-256-1) +# EMITTING VPSHLDVD (VPSHLDVD-512-1) { -ICLASS: VSQRTPS +ICLASS: VPSHLDVD CPL: 3 -CATEGORY: AVX512 +CATEGORY: VBMI2 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x51 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 -IFORM: VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 } { -ICLASS: VSQRTPS +ICLASS: VPSHLDVD CPL: 3 -CATEGORY: AVX512 +CATEGORY: VBMI2 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x51 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VSQRTPS_YMMf32_MASKmskw_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 } -# EMITTING VSUBPD (VSUBPD-128-1) +# EMITTING VPSHLDVQ (VPSHLDVQ-128-1) { -ICLASS: VSUBPD +ICLASS: VPSHLDVQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: VBMI2 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VSUBPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSHLDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 } { -ICLASS: VSUBPD +ICLASS: VPSHLDVQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: VBMI2 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x5C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VSUBPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSHLDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 } -# EMITTING VSUBPD (VSUBPD-256-1) +# EMITTING VPSHLDVQ (VPSHLDVQ-256-1) { -ICLASS: VSUBPD +ICLASS: VPSHLDVQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: VBMI2 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 -IFORM: VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPSHLDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 } { -ICLASS: VSUBPD +ICLASS: VPSHLDVQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: VBMI2 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x5C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VSUBPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSHLDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 } -# EMITTING VSUBPS (VSUBPS-128-1) +# EMITTING VPSHLDVQ (VPSHLDVQ-512-1) { -ICLASS: VSUBPS +ICLASS: VPSHLDVQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: VBMI2 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5C VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VSUBPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 } { -ICLASS: VSUBPS +ICLASS: VPSHLDVQ CPL: 3 -CATEGORY: AVX512 +CATEGORY: VBMI2 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x5C VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VSUBPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 } -# EMITTING VSUBPS (VSUBPS-256-1) +# EMITTING VPSHLDVW (VPSHLDVW-128-1) { -ICLASS: VSUBPS +ICLASS: VPSHLDVW CPL: 3 -CATEGORY: AVX512 +CATEGORY: VBMI2 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MASKOP_EVEX -PATTERN: EVV 0x5C VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 -IFORM: VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x70 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSHLDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 } { -ICLASS: VSUBPS +ICLASS: VPSHLDVW CPL: 3 -CATEGORY: AVX512 +CATEGORY: VBMI2 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E2 +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x5C VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VSUBPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x70 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPSHLDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 } -# EMITTING VUNPCKHPD (VUNPCKHPD-128-1) +# EMITTING VPSHLDVW (VPSHLDVW-256-1) { -ICLASS: VUNPCKHPD +ICLASS: VPSHLDVW CPL: 3 -CATEGORY: AVX512 +CATEGORY: VBMI2 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x15 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VUNPCKHPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +PATTERN: EVV 0x70 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPSHLDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 } { -ICLASS: VUNPCKHPD +ICLASS: VPSHLDVW CPL: 3 -CATEGORY: AVX512 +CATEGORY: VBMI2 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x15 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VUNPCKHPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x70 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPSHLDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 } -# EMITTING VUNPCKHPD (VUNPCKHPD-256-1) +# EMITTING VPSHLDVW (VPSHLDVW-512-1) { -ICLASS: VUNPCKHPD +ICLASS: VPSHLDVW CPL: 3 -CATEGORY: AVX512 +CATEGORY: VBMI2 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x15 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 -IFORM: VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +PATTERN: EVV 0x70 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 } { -ICLASS: VUNPCKHPD +ICLASS: VPSHLDVW CPL: 3 -CATEGORY: AVX512 +CATEGORY: VBMI2 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x15 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VUNPCKHPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x70 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 } -# EMITTING VUNPCKHPS (VUNPCKHPS-128-1) +# EMITTING VPSHLDW (VPSHLDW-128-1) { -ICLASS: VUNPCKHPS +ICLASS: VPSHLDW CPL: 3 -CATEGORY: AVX512 +CATEGORY: VBMI2 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x15 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VUNPCKHPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +PATTERN: EVV 0x70 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 IMM0:r:b +IFORM: VPSHLDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512 } { -ICLASS: VUNPCKHPS +ICLASS: VPSHLDW CPL: 3 -CATEGORY: AVX512 +CATEGORY: VBMI2 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x15 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VUNPCKHPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x70 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 IMM0:r:b +IFORM: VPSHLDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512 } -# EMITTING VUNPCKHPS (VUNPCKHPS-256-1) +# EMITTING VPSHLDW (VPSHLDW-256-1) { -ICLASS: VUNPCKHPS +ICLASS: VPSHLDW CPL: 3 -CATEGORY: AVX512 +CATEGORY: VBMI2 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x15 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 -IFORM: VUNPCKHPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +PATTERN: EVV 0x70 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 IMM0:r:b +IFORM: VPSHLDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512 } { -ICLASS: VUNPCKHPS +ICLASS: VPSHLDW CPL: 3 -CATEGORY: AVX512 +CATEGORY: VBMI2 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x15 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VUNPCKHPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x70 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 IMM0:r:b +IFORM: VPSHLDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512 } -# EMITTING VUNPCKLPD (VUNPCKLPD-128-1) +# EMITTING VPSHLDW (VPSHLDW-512-1) { -ICLASS: VUNPCKLPD +ICLASS: VPSHLDW CPL: 3 -CATEGORY: AVX512 +CATEGORY: VBMI2 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x14 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VUNPCKLPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +PATTERN: EVV 0x70 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 IMM0:r:b +IFORM: VPSHLDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512 } { -ICLASS: VUNPCKLPD +ICLASS: VPSHLDW CPL: 3 -CATEGORY: AVX512 +CATEGORY: VBMI2 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x14 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VUNPCKLPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x70 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 IMM0:r:b +IFORM: VPSHLDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512 } -# EMITTING VUNPCKLPD (VUNPCKLPD-256-1) +# EMITTING VPSHRDD (VPSHRDD-128-1) { -ICLASS: VUNPCKLPD +ICLASS: VPSHRDD CPL: 3 -CATEGORY: AVX512 +CATEGORY: VBMI2 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x14 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 -IFORM: VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +PATTERN: EVV 0x73 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 IMM0:r:b +IFORM: VPSHRDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 } { -ICLASS: VUNPCKLPD +ICLASS: VPSHRDD CPL: 3 -CATEGORY: AVX512 +CATEGORY: VBMI2 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x14 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VUNPCKLPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSHRDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 } -# EMITTING VUNPCKLPS (VUNPCKLPS-128-1) +# EMITTING VPSHRDD (VPSHRDD-256-1) { -ICLASS: VUNPCKLPS +ICLASS: VPSHRDD CPL: 3 -CATEGORY: AVX512 +CATEGORY: VBMI2 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x14 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VUNPCKLPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +PATTERN: EVV 0x73 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 IMM0:r:b +IFORM: VPSHRDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 } { -ICLASS: VUNPCKLPS +ICLASS: VPSHRDD CPL: 3 -CATEGORY: AVX512 +CATEGORY: VBMI2 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x14 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VUNPCKLPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSHRDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 } -# EMITTING VUNPCKLPS (VUNPCKLPS-256-1) +# EMITTING VPSHRDD (VPSHRDD-512-1) { -ICLASS: VUNPCKLPS +ICLASS: VPSHRDD CPL: 3 -CATEGORY: AVX512 +CATEGORY: VBMI2 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x14 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 -IFORM: VUNPCKLPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +PATTERN: EVV 0x73 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 IMM0:r:b +IFORM: VPSHRDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 } { -ICLASS: VUNPCKLPS +ICLASS: VPSHRDD CPL: 3 -CATEGORY: AVX512 +CATEGORY: VBMI2 EXTENSION: AVX512EVEX -ISA_SET: AVX512F_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x14 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VUNPCKLPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSHRDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 } -# EMITTING VXORPD (VXORPD-128-1) +# EMITTING VPSHRDQ (VPSHRDQ-128-1) { -ICLASS: VXORPD +ICLASS: VPSHRDQ CPL: 3 -CATEGORY: LOGICAL_FP +CATEGORY: VBMI2 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128 +ISA_SET: AVX512_VBMI2_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x57 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VXORPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +PATTERN: EVV 0x73 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 IMM0:r:b +IFORM: VPSHRDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 } { -ICLASS: VXORPD +ICLASS: VPSHRDQ CPL: 3 -CATEGORY: LOGICAL_FP +CATEGORY: VBMI2 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128 +ISA_SET: AVX512_VBMI2_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x57 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VXORPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +PATTERN: EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPSHRDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 } -# EMITTING VXORPD (VXORPD-256-1) +# EMITTING VPSHRDQ (VPSHRDQ-256-1) { -ICLASS: VXORPD +ICLASS: VPSHRDQ CPL: 3 -CATEGORY: LOGICAL_FP +CATEGORY: VBMI2 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 +ISA_SET: AVX512_VBMI2_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x57 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 -IFORM: VXORPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +PATTERN: EVV 0x73 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VPSHRDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 } { -ICLASS: VXORPD +ICLASS: VPSHRDQ CPL: 3 -CATEGORY: LOGICAL_FP +CATEGORY: VBMI2 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 +ISA_SET: AVX512_VBMI2_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x57 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VXORPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +PATTERN: EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPSHRDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 } -# EMITTING VXORPD (VXORPD-512-1) +# EMITTING VPSHRDQ (VPSHRDQ-512-1) { -ICLASS: VXORPD +ICLASS: VPSHRDQ CPL: 3 -CATEGORY: LOGICAL_FP +CATEGORY: VBMI2 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 +ISA_SET: AVX512_VBMI2_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x57 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VXORPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +PATTERN: EVV 0x73 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 IMM0:r:b +IFORM: VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 } { -ICLASS: VXORPD +ICLASS: VPSHRDQ CPL: 3 -CATEGORY: LOGICAL_FP +CATEGORY: VBMI2 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 +ISA_SET: AVX512_VBMI2_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x57 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VXORPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +PATTERN: EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 } -# EMITTING VXORPS (VXORPS-128-1) +# EMITTING VPSHRDVD (VPSHRDVD-128-1) { -ICLASS: VXORPS +ICLASS: VPSHRDVD CPL: 3 -CATEGORY: LOGICAL_FP +CATEGORY: VBMI2 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128 +ISA_SET: AVX512_VBMI2_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x57 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VXORPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +PATTERN: EVV 0x73 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSHRDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 } { -ICLASS: VXORPS +ICLASS: VPSHRDVD CPL: 3 -CATEGORY: LOGICAL_FP +CATEGORY: VBMI2 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_128 +ISA_SET: AVX512_VBMI2_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x57 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VXORPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +PATTERN: EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSHRDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 } -# EMITTING VXORPS (VXORPS-256-1) +# EMITTING VPSHRDVD (VPSHRDVD-256-1) { -ICLASS: VXORPS +ICLASS: VPSHRDVD CPL: 3 -CATEGORY: LOGICAL_FP +CATEGORY: VBMI2 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 +ISA_SET: AVX512_VBMI2_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x57 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 -IFORM: VXORPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +PATTERN: EVV 0x73 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPSHRDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 } { -ICLASS: VXORPS +ICLASS: VPSHRDVD CPL: 3 -CATEGORY: LOGICAL_FP +CATEGORY: VBMI2 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_256 +ISA_SET: AVX512_VBMI2_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x57 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VXORPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +PATTERN: EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSHRDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 } -# EMITTING VXORPS (VXORPS-512-1) +# EMITTING VPSHRDVD (VPSHRDVD-512-1) { -ICLASS: VXORPS +ICLASS: VPSHRDVD CPL: 3 -CATEGORY: LOGICAL_FP +CATEGORY: VBMI2 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 +ISA_SET: AVX512_VBMI2_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x57 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VXORPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +PATTERN: EVV 0x73 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 } { -ICLASS: VXORPS +ICLASS: VPSHRDVD CPL: 3 -CATEGORY: LOGICAL_FP +CATEGORY: VBMI2 EXTENSION: AVX512EVEX -ISA_SET: AVX512DQ_512 +ISA_SET: AVX512_VBMI2_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x57 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VXORPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +PATTERN: EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 } -AVX_INSTRUCTIONS():: -# EMITTING KADDB (KADDB-256-1) +# EMITTING VPSHRDVQ (VPSHRDVQ-128-1) { -ICLASS: KADDB +ICLASS: VPSHRDVQ CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512DQ_KOP -EXCEPTIONS: AVX512-K20 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x4A V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw -IFORM: KADDB_MASKmskw_MASKmskw_MASKmskw_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x73 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSHRDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 } - -# EMITTING KADDD (KADDD-256-1) { -ICLASS: KADDD +ICLASS: VPSHRDVQ CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512BW_KOP -EXCEPTIONS: AVX512-K20 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x4A V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw -IFORM: KADDD_MASKmskw_MASKmskw_MASKmskw_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSHRDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 } -# EMITTING KADDQ (KADDQ-256-1) +# EMITTING VPSHRDVQ (VPSHRDVQ-256-1) { -ICLASS: KADDQ +ICLASS: VPSHRDVQ CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512BW_KOP -EXCEPTIONS: AVX512-K20 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x4A VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw -IFORM: KADDQ_MASKmskw_MASKmskw_MASKmskw_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x73 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPSHRDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 } - -# EMITTING KADDW (KADDW-256-1) { -ICLASS: KADDW +ICLASS: VPSHRDVQ CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512DQ_KOP -EXCEPTIONS: AVX512-K20 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x4A VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw -IFORM: KADDW_MASKmskw_MASKmskw_MASKmskw_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSHRDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 } -# EMITTING KANDB (KANDB-256-1) +# EMITTING VPSHRDVQ (VPSHRDVQ-512-1) { -ICLASS: KANDB +ICLASS: VPSHRDVQ CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512DQ_KOP -EXCEPTIONS: AVX512-K20 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x41 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw -IFORM: KANDB_MASKmskw_MASKmskw_MASKmskw_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x73 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 } - -# EMITTING KANDD (KANDD-256-1) { -ICLASS: KANDD +ICLASS: VPSHRDVQ CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512BW_KOP -EXCEPTIONS: AVX512-K20 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x41 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw -IFORM: KANDD_MASKmskw_MASKmskw_MASKmskw_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 } -# EMITTING KANDNB (KANDNB-256-1) +# EMITTING VPSHRDVW (VPSHRDVW-128-1) { -ICLASS: KANDNB +ICLASS: VPSHRDVW CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512DQ_KOP -EXCEPTIONS: AVX512-K20 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x42 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw -IFORM: KANDNB_MASKmskw_MASKmskw_MASKmskw_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSHRDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 } - -# EMITTING KANDND (KANDND-256-1) { -ICLASS: KANDND +ICLASS: VPSHRDVW CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512BW_KOP -EXCEPTIONS: AVX512-K20 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x42 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw -IFORM: KANDND_MASKmskw_MASKmskw_MASKmskw_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x72 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPSHRDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 } -# EMITTING KANDNQ (KANDNQ-256-1) +# EMITTING VPSHRDVW (VPSHRDVW-256-1) { -ICLASS: KANDNQ +ICLASS: VPSHRDVW CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512BW_KOP -EXCEPTIONS: AVX512-K20 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x42 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw -IFORM: KANDNQ_MASKmskw_MASKmskw_MASKmskw_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPSHRDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 } - -# EMITTING KANDQ (KANDQ-256-1) { -ICLASS: KANDQ +ICLASS: VPSHRDVW CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512BW_KOP -EXCEPTIONS: AVX512-K20 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x41 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw -IFORM: KANDQ_MASKmskw_MASKmskw_MASKmskw_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x72 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPSHRDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 } -# EMITTING KMOVB (KMOVB-128-1) +# EMITTING VPSHRDVW (VPSHRDVW-512-1) { -ICLASS: KMOVB +ICLASS: VPSHRDVW CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512DQ_KOP -EXCEPTIONS: AVX512-K21 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x90 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw:u8 -IFORM: KMOVB_MASKmskw_MASKu8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 } { -ICLASS: KMOVB +ICLASS: VPSHRDVW CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512DQ_KOP -EXCEPTIONS: AVX512-K21 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x90 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL=0 W0 NOVSR -OPERANDS: REG0=MASK_R():w:mskw MEM0:r:b:u8 -IFORM: KMOVB_MASKmskw_MEMu8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x72 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 } -# EMITTING KMOVB (KMOVB-128-2) +# EMITTING VPSHRDW (VPSHRDW-128-1) { -ICLASS: KMOVB +ICLASS: VPSHRDW CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512DQ_KOP -EXCEPTIONS: AVX512-K21 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x91 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL=0 W0 NOVSR -OPERANDS: MEM0:w:b:u8 REG0=MASK_R():r:mskw -IFORM: KMOVB_MEMu8_MASKmskw_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 IMM0:r:b +IFORM: VPSHRDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512 } - -# EMITTING KMOVB (KMOVB-128-3) { -ICLASS: KMOVB +ICLASS: VPSHRDW CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512DQ_KOP -EXCEPTIONS: AVX512-K20 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x92 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR -OPERANDS: REG0=MASK_R():w:mskw REG1=GPR32_B():r:d:u32 -IFORM: KMOVB_MASKmskw_GPR32u32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x72 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 IMM0:r:b +IFORM: VPSHRDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSHRDW (VPSHRDW-256-1) +{ +ICLASS: VPSHRDW +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 IMM0:r:b +IFORM: VPSHRDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512 } - -# EMITTING KMOVB (KMOVB-128-4) { -ICLASS: KMOVB +ICLASS: VPSHRDW CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512DQ_KOP -EXCEPTIONS: AVX512-K20 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x93 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR -OPERANDS: REG0=GPR32_R():w:d:u32 REG1=MASK_B():r:mskw -IFORM: KMOVB_GPR32u32_MASKmskw_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x72 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 IMM0:r:b +IFORM: VPSHRDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512 } -# EMITTING KMOVD (KMOVD-128-1) +# EMITTING VPSHRDW (VPSHRDW-512-1) { -ICLASS: KMOVD +ICLASS: VPSHRDW CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512BW_KOP -EXCEPTIONS: AVX512-K21 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x90 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw:u32 -IFORM: KMOVD_MASKmskw_MASKu32_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 IMM0:r:b +IFORM: VPSHRDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512 } { -ICLASS: KMOVD +ICLASS: VPSHRDW CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512BW_KOP -EXCEPTIONS: AVX512-K21 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x90 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL=0 W1 NOVSR -OPERANDS: REG0=MASK_R():w:mskw MEM0:r:d:u32 -IFORM: KMOVD_MASKmskw_MEMu32_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x72 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 IMM0:r:b +IFORM: VPSHRDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512 } -# EMITTING KMOVD (KMOVD-128-2) + + +###FILE: ../xed/datafiles/gfni-vaes-vpcl/gfni-sse-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2018 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +INSTRUCTIONS():: +# EMITTING GF2P8AFFINEINVQB (GF2P8AFFINEINVQB-N/A-1) { -ICLASS: KMOVD +ICLASS: GF2P8AFFINEINVQB CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512BW_KOP -EXCEPTIONS: AVX512-K21 +CATEGORY: GFNI +EXTENSION: GFNI +ISA_SET: GFNI +EXCEPTIONS: SSE_TYPE_4 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x91 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL=0 W1 NOVSR -OPERANDS: MEM0:w:d:u32 REG0=MASK_R():r:mskw -IFORM: KMOVD_MEMu32_MASKmskw_AVX512 +PATTERN: 0x0F 0x3A 0xCF MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix UIMM8() +OPERANDS: REG0=XMM_R():rw:dq:u8 REG1=XMM_B():r:dq:u64 IMM0:r:b +IFORM: GF2P8AFFINEINVQB_XMMu8_XMMu64_IMM8 } - -# EMITTING KMOVD (KMOVD-128-3) { -ICLASS: KMOVD +ICLASS: GF2P8AFFINEINVQB CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512BW_KOP -EXCEPTIONS: AVX512-K20 +CATEGORY: GFNI +EXTENSION: GFNI +ISA_SET: GFNI +EXCEPTIONS: SSE_TYPE_4 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x92 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR -OPERANDS: REG0=MASK_R():w:mskw REG1=GPR32_B():r:d:u32 -IFORM: KMOVD_MASKmskw_GPR32u32_AVX512 +ATTRIBUTES: REQUIRES_ALIGNMENT +PATTERN: 0x0F 0x3A 0xCF MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix UIMM8() +OPERANDS: REG0=XMM_R():rw:dq:u8 MEM0:r:dq:u64 IMM0:r:b +IFORM: GF2P8AFFINEINVQB_XMMu8_MEMu64_IMM8 } -# EMITTING KMOVD (KMOVD-128-4) +# EMITTING GF2P8AFFINEQB (GF2P8AFFINEQB-N/A-1) { -ICLASS: KMOVD +ICLASS: GF2P8AFFINEQB CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512BW_KOP -EXCEPTIONS: AVX512-K20 +CATEGORY: GFNI +EXTENSION: GFNI +ISA_SET: GFNI +EXCEPTIONS: SSE_TYPE_4 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x93 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR -OPERANDS: REG0=GPR32_R():w:d:u32 REG1=MASK_B():r:mskw -IFORM: KMOVD_GPR32u32_MASKmskw_AVX512 +PATTERN: 0x0F 0x3A 0xCE MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix UIMM8() +OPERANDS: REG0=XMM_R():rw:dq:u8 REG1=XMM_B():r:dq:u64 IMM0:r:b +IFORM: GF2P8AFFINEQB_XMMu8_XMMu64_IMM8 } +{ +ICLASS: GF2P8AFFINEQB +CPL: 3 +CATEGORY: GFNI +EXTENSION: GFNI +ISA_SET: GFNI +EXCEPTIONS: SSE_TYPE_4 +REAL_OPCODE: Y +ATTRIBUTES: REQUIRES_ALIGNMENT +PATTERN: 0x0F 0x3A 0xCE MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix UIMM8() +OPERANDS: REG0=XMM_R():rw:dq:u8 MEM0:r:dq:u64 IMM0:r:b +IFORM: GF2P8AFFINEQB_XMMu8_MEMu64_IMM8 +} -# EMITTING KMOVQ (KMOVQ-128-1) + +# EMITTING GF2P8MULB (GF2P8MULB-N/A-1) { -ICLASS: KMOVQ +ICLASS: GF2P8MULB CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512BW_KOP -EXCEPTIONS: AVX512-K21 +CATEGORY: GFNI +EXTENSION: GFNI +ISA_SET: GFNI +EXCEPTIONS: SSE_TYPE_4 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x90 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw:u64 -IFORM: KMOVQ_MASKmskw_MASKu64_AVX512 +PATTERN: 0x0F 0x38 0xCF MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix +OPERANDS: REG0=XMM_R():rw:dq:u8 REG1=XMM_B():r:dq:u8 +IFORM: GF2P8MULB_XMMu8_XMMu8 } { -ICLASS: KMOVQ +ICLASS: GF2P8MULB CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512BW_KOP -EXCEPTIONS: AVX512-K21 +CATEGORY: GFNI +EXTENSION: GFNI +ISA_SET: GFNI +EXCEPTIONS: SSE_TYPE_4 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x90 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL=0 W1 NOVSR -OPERANDS: REG0=MASK_R():w:mskw MEM0:r:q:u64 -IFORM: KMOVQ_MASKmskw_MEMu64_AVX512 +ATTRIBUTES: REQUIRES_ALIGNMENT +PATTERN: 0x0F 0x38 0xCF MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix +OPERANDS: REG0=XMM_R():rw:dq:u8 MEM0:r:dq:u8 +IFORM: GF2P8MULB_XMMu8_MEMu8 } -# EMITTING KMOVQ (KMOVQ-128-2) + + +###FILE: ../xed/datafiles/gfni-vaes-vpcl/gfni-evex-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2018 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING VGF2P8AFFINEINVQB (VGF2P8AFFINEINVQB-128-1) { -ICLASS: KMOVQ +ICLASS: VGF2P8AFFINEINVQB CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512BW_KOP -EXCEPTIONS: AVX512-K21 +CATEGORY: GFNI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_GFNI_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x91 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL=0 W1 NOVSR -OPERANDS: MEM0:w:q:u64 REG0=MASK_R():r:mskw -IFORM: KMOVQ_MEMu64_MASKmskw_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xCF V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u64 IMM0:r:b +IFORM: VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512 } - -# EMITTING KMOVQ (KMOVQ-128-3) { -ICLASS: KMOVQ +ICLASS: VGF2P8AFFINEINVQB CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512BW_KOP -EXCEPTIONS: AVX512-K20 +CATEGORY: GFNI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_GFNI_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x92 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 mode64 NOVSR -OPERANDS: REG0=MASK_R():w:mskw REG1=GPR64_B():r:q:u64 -IFORM: KMOVQ_MASKmskw_GPR64u64_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xCF V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512 } -# EMITTING KMOVQ (KMOVQ-128-4) +# EMITTING VGF2P8AFFINEINVQB (VGF2P8AFFINEINVQB-256-1) { -ICLASS: KMOVQ +ICLASS: VGF2P8AFFINEINVQB CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512BW_KOP -EXCEPTIONS: AVX512-K20 +CATEGORY: GFNI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_GFNI_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x93 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 mode64 NOVSR -OPERANDS: REG0=GPR64_R():w:q:u64 REG1=MASK_B():r:mskw -IFORM: KMOVQ_GPR64u64_MASKmskw_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xCF V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512 } - -# EMITTING KNOTB (KNOTB-128-1) { -ICLASS: KNOTB +ICLASS: VGF2P8AFFINEINVQB CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512DQ_KOP -EXCEPTIONS: AVX512-K20 +CATEGORY: GFNI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_GFNI_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x44 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw -IFORM: KNOTB_MASKmskw_MASKmskw_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xCF V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512 } -# EMITTING KNOTD (KNOTD-128-1) +# EMITTING VGF2P8AFFINEINVQB (VGF2P8AFFINEINVQB-512-1) { -ICLASS: KNOTD +ICLASS: VGF2P8AFFINEINVQB CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512BW_KOP -EXCEPTIONS: AVX512-K20 +CATEGORY: GFNI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_GFNI_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x44 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw -IFORM: KNOTD_MASKmskw_MASKmskw_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xCF V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu64 IMM0:r:b +IFORM: VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512 } - -# EMITTING KNOTQ (KNOTQ-128-1) { -ICLASS: KNOTQ +ICLASS: VGF2P8AFFINEINVQB CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512BW_KOP -EXCEPTIONS: AVX512-K20 +CATEGORY: GFNI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_GFNI_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x44 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw -IFORM: KNOTQ_MASKmskw_MASKmskw_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xCF V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512 } -# EMITTING KORB (KORB-256-1) +# EMITTING VGF2P8AFFINEQB (VGF2P8AFFINEQB-128-1) { -ICLASS: KORB +ICLASS: VGF2P8AFFINEQB CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512DQ_KOP -EXCEPTIONS: AVX512-K20 +CATEGORY: GFNI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_GFNI_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x45 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw -IFORM: KORB_MASKmskw_MASKmskw_MASKmskw_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xCE V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u64 IMM0:r:b +IFORM: VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512 } - -# EMITTING KORD (KORD-256-1) { -ICLASS: KORD +ICLASS: VGF2P8AFFINEQB CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512BW_KOP -EXCEPTIONS: AVX512-K20 +CATEGORY: GFNI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_GFNI_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x45 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw -IFORM: KORD_MASKmskw_MASKmskw_MASKmskw_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xCE V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512 } -# EMITTING KORQ (KORQ-256-1) +# EMITTING VGF2P8AFFINEQB (VGF2P8AFFINEQB-256-1) { -ICLASS: KORQ +ICLASS: VGF2P8AFFINEQB CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512BW_KOP -EXCEPTIONS: AVX512-K20 +CATEGORY: GFNI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_GFNI_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x45 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw -IFORM: KORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xCE V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512 } - -# EMITTING KORTESTB (KORTESTB-128-1) { -ICLASS: KORTESTB +ICLASS: VGF2P8AFFINEQB CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512DQ_KOP -EXCEPTIONS: AVX512-K20 +CATEGORY: GFNI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_GFNI_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] -ATTRIBUTES: KMASK -PATTERN: VV1 0x98 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR -OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw -IFORM: KORTESTB_MASKmskw_MASKmskw_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xCE V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512 } -# EMITTING KORTESTD (KORTESTD-128-1) +# EMITTING VGF2P8AFFINEQB (VGF2P8AFFINEQB-512-1) { -ICLASS: KORTESTD +ICLASS: VGF2P8AFFINEQB CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512BW_KOP -EXCEPTIONS: AVX512-K20 +CATEGORY: GFNI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_GFNI_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] -ATTRIBUTES: KMASK -PATTERN: VV1 0x98 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR -OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw -IFORM: KORTESTD_MASKmskw_MASKmskw_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xCE V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu64 IMM0:r:b +IFORM: VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512 } - -# EMITTING KORTESTQ (KORTESTQ-128-1) { -ICLASS: KORTESTQ +ICLASS: VGF2P8AFFINEQB CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512BW_KOP -EXCEPTIONS: AVX512-K20 +CATEGORY: GFNI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_GFNI_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] -ATTRIBUTES: KMASK -PATTERN: VV1 0x98 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR -OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw -IFORM: KORTESTQ_MASKmskw_MASKmskw_AVX512 +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xCE V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512 } -# EMITTING KSHIFTLB (KSHIFTLB-128-1) +# EMITTING VGF2P8MULB (VGF2P8MULB-128-1) { -ICLASS: KSHIFTLB +ICLASS: VGF2P8MULB CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512DQ_KOP -EXCEPTIONS: AVX512-K20 +CATEGORY: GFNI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_GFNI_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x32 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR UIMM8() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b -IFORM: KSHIFTLB_MASKmskw_MASKmskw_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xCF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VGF2P8MULB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 } - -# EMITTING KSHIFTLD (KSHIFTLD-128-1) { -ICLASS: KSHIFTLD +ICLASS: VGF2P8MULB CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512BW_KOP -EXCEPTIONS: AVX512-K20 +CATEGORY: GFNI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_GFNI_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x33 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR UIMM8() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b -IFORM: KSHIFTLD_MASKmskw_MASKmskw_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xCF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VGF2P8MULB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 } -# EMITTING KSHIFTLQ (KSHIFTLQ-128-1) +# EMITTING VGF2P8MULB (VGF2P8MULB-256-1) { -ICLASS: KSHIFTLQ +ICLASS: VGF2P8MULB CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512BW_KOP -EXCEPTIONS: AVX512-K20 +CATEGORY: GFNI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_GFNI_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x33 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR UIMM8() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b -IFORM: KSHIFTLQ_MASKmskw_MASKmskw_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xCF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VGF2P8MULB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 } - -# EMITTING KSHIFTRB (KSHIFTRB-128-1) { -ICLASS: KSHIFTRB +ICLASS: VGF2P8MULB CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512DQ_KOP -EXCEPTIONS: AVX512-K20 +CATEGORY: GFNI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_GFNI_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x30 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR UIMM8() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b -IFORM: KSHIFTRB_MASKmskw_MASKmskw_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xCF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VGF2P8MULB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 } -# EMITTING KSHIFTRD (KSHIFTRD-128-1) +# EMITTING VGF2P8MULB (VGF2P8MULB-512-1) { -ICLASS: KSHIFTRD +ICLASS: VGF2P8MULB CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512BW_KOP -EXCEPTIONS: AVX512-K20 +CATEGORY: GFNI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_GFNI_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x31 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR UIMM8() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b -IFORM: KSHIFTRD_MASKmskw_MASKmskw_IMM8_AVX512 +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xCF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 } - -# EMITTING KSHIFTRQ (KSHIFTRQ-128-1) { -ICLASS: KSHIFTRQ +ICLASS: VGF2P8MULB CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512BW_KOP -EXCEPTIONS: AVX512-K20 +CATEGORY: GFNI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_GFNI_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x31 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR UIMM8() -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b -IFORM: KSHIFTRQ_MASKmskw_MASKmskw_IMM8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xCF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 } -# EMITTING KTESTB (KTESTB-128-1) + + +###FILE: ../xed/datafiles/gfni-vaes-vpcl/gfni-vex-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2018 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +AVX_INSTRUCTIONS():: +# EMITTING VGF2P8AFFINEINVQB (VGF2P8AFFINEINVQB-128-2) { -ICLASS: KTESTB +ICLASS: VGF2P8AFFINEINVQB CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512DQ_KOP -EXCEPTIONS: AVX512-K20 +CATEGORY: GFNI +EXTENSION: GFNI +ISA_SET: AVX_GFNI +EXCEPTIONS: avx-type-4 REAL_OPCODE: Y -FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] -ATTRIBUTES: KMASK -PATTERN: VV1 0x99 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR -OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw -IFORM: KTESTB_MASKmskw_MASKmskw_AVX512 +PATTERN: VV1 0xCF V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u64 IMM0:r:b +IFORM: VGF2P8AFFINEINVQB_XMMu8_XMMu8_XMMu64_IMM8 } - -# EMITTING KTESTD (KTESTD-128-1) { -ICLASS: KTESTD +ICLASS: VGF2P8AFFINEINVQB CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512BW_KOP -EXCEPTIONS: AVX512-K20 +CATEGORY: GFNI +EXTENSION: GFNI +ISA_SET: AVX_GFNI +EXCEPTIONS: avx-type-4 REAL_OPCODE: Y -FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] -ATTRIBUTES: KMASK -PATTERN: VV1 0x99 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR -OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw -IFORM: KTESTD_MASKmskw_MASKmskw_AVX512 +PATTERN: VV1 0xCF V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u64 IMM0:r:b +IFORM: VGF2P8AFFINEINVQB_XMMu8_XMMu8_MEMu64_IMM8 } -# EMITTING KTESTQ (KTESTQ-128-1) +# EMITTING VGF2P8AFFINEINVQB (VGF2P8AFFINEINVQB-256-2) { -ICLASS: KTESTQ +ICLASS: VGF2P8AFFINEINVQB CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512BW_KOP -EXCEPTIONS: AVX512-K20 +CATEGORY: GFNI +EXTENSION: GFNI +ISA_SET: AVX_GFNI +EXCEPTIONS: avx-type-4 REAL_OPCODE: Y -FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] -ATTRIBUTES: KMASK -PATTERN: VV1 0x99 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR -OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw -IFORM: KTESTQ_MASKmskw_MASKmskw_AVX512 +PATTERN: VV1 0xCF V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u64 IMM0:r:b +IFORM: VGF2P8AFFINEINVQB_YMMu8_YMMu8_YMMu64_IMM8 } - -# EMITTING KTESTW (KTESTW-128-1) { -ICLASS: KTESTW +ICLASS: VGF2P8AFFINEINVQB CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512DQ_KOP -EXCEPTIONS: AVX512-K20 +CATEGORY: GFNI +EXTENSION: GFNI +ISA_SET: AVX_GFNI +EXCEPTIONS: avx-type-4 REAL_OPCODE: Y -FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] -ATTRIBUTES: KMASK -PATTERN: VV1 0x99 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR -OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw -IFORM: KTESTW_MASKmskw_MASKmskw_AVX512 +PATTERN: VV1 0xCF V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u64 IMM0:r:b +IFORM: VGF2P8AFFINEINVQB_YMMu8_YMMu8_MEMu64_IMM8 } -# EMITTING KUNPCKDQ (KUNPCKDQ-256-1) +# EMITTING VGF2P8AFFINEQB (VGF2P8AFFINEQB-128-2) { -ICLASS: KUNPCKDQ +ICLASS: VGF2P8AFFINEQB CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512BW_KOP -EXCEPTIONS: AVX512-K20 +CATEGORY: GFNI +EXTENSION: GFNI +ISA_SET: AVX_GFNI +EXCEPTIONS: avx-type-4 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x4B VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw -IFORM: KUNPCKDQ_MASKmskw_MASKmskw_MASKmskw_AVX512 +PATTERN: VV1 0xCE V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u64 IMM0:r:b +IFORM: VGF2P8AFFINEQB_XMMu8_XMMu8_XMMu64_IMM8 } - -# EMITTING KUNPCKWD (KUNPCKWD-256-1) { -ICLASS: KUNPCKWD +ICLASS: VGF2P8AFFINEQB CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512BW_KOP -EXCEPTIONS: AVX512-K20 +CATEGORY: GFNI +EXTENSION: GFNI +ISA_SET: AVX_GFNI +EXCEPTIONS: avx-type-4 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x4B VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw -IFORM: KUNPCKWD_MASKmskw_MASKmskw_MASKmskw_AVX512 +PATTERN: VV1 0xCE V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u64 IMM0:r:b +IFORM: VGF2P8AFFINEQB_XMMu8_XMMu8_MEMu64_IMM8 } -# EMITTING KXNORB (KXNORB-256-1) +# EMITTING VGF2P8AFFINEQB (VGF2P8AFFINEQB-256-2) { -ICLASS: KXNORB +ICLASS: VGF2P8AFFINEQB CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512DQ_KOP -EXCEPTIONS: AVX512-K20 +CATEGORY: GFNI +EXTENSION: GFNI +ISA_SET: AVX_GFNI +EXCEPTIONS: avx-type-4 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x46 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw -IFORM: KXNORB_MASKmskw_MASKmskw_MASKmskw_AVX512 +PATTERN: VV1 0xCE V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u64 IMM0:r:b +IFORM: VGF2P8AFFINEQB_YMMu8_YMMu8_YMMu64_IMM8 } - -# EMITTING KXNORD (KXNORD-256-1) { -ICLASS: KXNORD +ICLASS: VGF2P8AFFINEQB CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512BW_KOP -EXCEPTIONS: AVX512-K20 +CATEGORY: GFNI +EXTENSION: GFNI +ISA_SET: AVX_GFNI +EXCEPTIONS: avx-type-4 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x46 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw -IFORM: KXNORD_MASKmskw_MASKmskw_MASKmskw_AVX512 +PATTERN: VV1 0xCE V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u64 IMM0:r:b +IFORM: VGF2P8AFFINEQB_YMMu8_YMMu8_MEMu64_IMM8 } -# EMITTING KXNORQ (KXNORQ-256-1) +# EMITTING VGF2P8MULB (VGF2P8MULB-128-2) { -ICLASS: KXNORQ +ICLASS: VGF2P8MULB CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512BW_KOP -EXCEPTIONS: AVX512-K20 +CATEGORY: GFNI +EXTENSION: GFNI +ISA_SET: AVX_GFNI +EXCEPTIONS: avx-type-4 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x46 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw -IFORM: KXNORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 +PATTERN: VV1 0xCF V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 +IFORM: VGF2P8MULB_XMMu8_XMMu8_XMMu8 } - -# EMITTING KXORB (KXORB-256-1) { -ICLASS: KXORB +ICLASS: VGF2P8MULB CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512DQ_KOP -EXCEPTIONS: AVX512-K20 +CATEGORY: GFNI +EXTENSION: GFNI +ISA_SET: AVX_GFNI +EXCEPTIONS: avx-type-4 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x47 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw -IFORM: KXORB_MASKmskw_MASKmskw_MASKmskw_AVX512 +PATTERN: VV1 0xCF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 +OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 +IFORM: VGF2P8MULB_XMMu8_XMMu8_MEMu8 } -# EMITTING KXORD (KXORD-256-1) +# EMITTING VGF2P8MULB (VGF2P8MULB-256-2) { -ICLASS: KXORD +ICLASS: VGF2P8MULB CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512BW_KOP -EXCEPTIONS: AVX512-K20 +CATEGORY: GFNI +EXTENSION: GFNI +ISA_SET: AVX_GFNI +EXCEPTIONS: avx-type-4 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x47 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw -IFORM: KXORD_MASKmskw_MASKmskw_MASKmskw_AVX512 +PATTERN: VV1 0xCF V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 +IFORM: VGF2P8MULB_YMMu8_YMMu8_YMMu8 } - -# EMITTING KXORQ (KXORQ-256-1) { -ICLASS: KXORQ +ICLASS: VGF2P8MULB CPL: 3 -CATEGORY: KMASK -EXTENSION: AVX512VEX -ISA_SET: AVX512BW_KOP -EXCEPTIONS: AVX512-K20 +CATEGORY: GFNI +EXTENSION: GFNI +ISA_SET: AVX_GFNI +EXCEPTIONS: avx-type-4 REAL_OPCODE: Y -ATTRIBUTES: KMASK -PATTERN: VV1 0x47 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 -OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw -IFORM: KXORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 +PATTERN: VV1 0xCF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 +OPERANDS: REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 +IFORM: VGF2P8MULB_YMMu8_YMMu8_MEMu8 } -###FILE: ../xed/datafiles/avx512ifma/ifma-isa.xed.txt +###FILE: ../xed/datafiles/gfni-vaes-vpcl/vaes-evex-isa.xed.txt #BEGIN_LEGAL # -#Copyright (c) 2016 Intel Corporation +#Copyright (c) 2018 Intel Corporation # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -70036,574 +75134,760 @@ IFORM: KXORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 # # EVEX_INSTRUCTIONS():: -# EMITTING VPMADD52HUQ (VPMADD52HUQ-128-1) +# EMITTING VAESDEC (VAESDEC-128-1) { -ICLASS: VPMADD52HUQ +ICLASS: VAESDEC CPL: 3 -CATEGORY: IFMA +CATEGORY: VAES EXTENSION: AVX512EVEX -ISA_SET: AVX512IFMA_128 +ISA_SET: AVX512_VAES_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xB5 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 -IFORM: VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +PATTERN: EVV 0xDE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 REG2=XMM_B3():r:dq:u128 +IFORM: VAESDEC_XMMu128_XMMu128_XMMu128_AVX512 } { -ICLASS: VPMADD52HUQ +ICLASS: VAESDEC CPL: 3 -CATEGORY: IFMA +CATEGORY: VAES EXTENSION: AVX512EVEX -ISA_SET: AVX512IFMA_128 +ISA_SET: AVX512_VAES_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xB5 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0xDE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 MEM0:r:dq:u128 +IFORM: VAESDEC_XMMu128_XMMu128_MEMu128_AVX512 } -# EMITTING VPMADD52HUQ (VPMADD52HUQ-256-1) +# EMITTING VAESDEC (VAESDEC-256-1) { -ICLASS: VPMADD52HUQ +ICLASS: VAESDEC CPL: 3 -CATEGORY: IFMA +CATEGORY: VAES EXTENSION: AVX512EVEX -ISA_SET: AVX512IFMA_256 +ISA_SET: AVX512_VAES_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xB5 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 -IFORM: VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +PATTERN: EVV 0xDE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 MASK=0 +OPERANDS: REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 REG2=YMM_B3():r:qq:u128 +IFORM: VAESDEC_YMMu128_YMMu128_YMMu128_AVX512 } { -ICLASS: VPMADD52HUQ +ICLASS: VAESDEC CPL: 3 -CATEGORY: IFMA +CATEGORY: VAES EXTENSION: AVX512EVEX -ISA_SET: AVX512IFMA_256 +ISA_SET: AVX512_VAES_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xB5 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0xDE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 MEM0:r:qq:u128 +IFORM: VAESDEC_YMMu128_YMMu128_MEMu128_AVX512 } -# EMITTING VPMADD52HUQ (VPMADD52HUQ-512-1) +# EMITTING VAESDEC (VAESDEC-512-1) { -ICLASS: VPMADD52HUQ +ICLASS: VAESDEC CPL: 3 -CATEGORY: IFMA +CATEGORY: VAES EXTENSION: AVX512EVEX -ISA_SET: AVX512IFMA_512 +ISA_SET: AVX512_VAES_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xB5 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 -IFORM: VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +PATTERN: EVV 0xDE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 MASK=0 +OPERANDS: REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 REG2=ZMM_B3():r:zu128 +IFORM: VAESDEC_ZMMu128_ZMMu128_ZMMu128_AVX512 } { -ICLASS: VPMADD52HUQ +ICLASS: VAESDEC CPL: 3 -CATEGORY: IFMA +CATEGORY: VAES EXTENSION: AVX512EVEX -ISA_SET: AVX512IFMA_512 +ISA_SET: AVX512_VAES_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xB5 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0xDE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 MEM0:r:zd:u128 +IFORM: VAESDEC_ZMMu128_ZMMu128_MEMu128_AVX512 } -# EMITTING VPMADD52LUQ (VPMADD52LUQ-128-1) +# EMITTING VAESDECLAST (VAESDECLAST-128-1) { -ICLASS: VPMADD52LUQ +ICLASS: VAESDECLAST CPL: 3 -CATEGORY: IFMA +CATEGORY: VAES EXTENSION: AVX512EVEX -ISA_SET: AVX512IFMA_128 +ISA_SET: AVX512_VAES_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xB4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 -IFORM: VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +PATTERN: EVV 0xDF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 REG2=XMM_B3():r:dq:u128 +IFORM: VAESDECLAST_XMMu128_XMMu128_XMMu128_AVX512 } { -ICLASS: VPMADD52LUQ +ICLASS: VAESDECLAST CPL: 3 -CATEGORY: IFMA +CATEGORY: VAES EXTENSION: AVX512EVEX -ISA_SET: AVX512IFMA_128 +ISA_SET: AVX512_VAES_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xB4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0xDF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 MEM0:r:dq:u128 +IFORM: VAESDECLAST_XMMu128_XMMu128_MEMu128_AVX512 } -# EMITTING VPMADD52LUQ (VPMADD52LUQ-256-1) +# EMITTING VAESDECLAST (VAESDECLAST-256-1) { -ICLASS: VPMADD52LUQ +ICLASS: VAESDECLAST CPL: 3 -CATEGORY: IFMA +CATEGORY: VAES EXTENSION: AVX512EVEX -ISA_SET: AVX512IFMA_256 +ISA_SET: AVX512_VAES_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xB4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 -IFORM: VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +PATTERN: EVV 0xDF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 MASK=0 +OPERANDS: REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 REG2=YMM_B3():r:qq:u128 +IFORM: VAESDECLAST_YMMu128_YMMu128_YMMu128_AVX512 } { -ICLASS: VPMADD52LUQ +ICLASS: VAESDECLAST CPL: 3 -CATEGORY: IFMA +CATEGORY: VAES EXTENSION: AVX512EVEX -ISA_SET: AVX512IFMA_256 +ISA_SET: AVX512_VAES_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xB4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0xDF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 MEM0:r:qq:u128 +IFORM: VAESDECLAST_YMMu128_YMMu128_MEMu128_AVX512 } -# EMITTING VPMADD52LUQ (VPMADD52LUQ-512-1) +# EMITTING VAESDECLAST (VAESDECLAST-512-1) { -ICLASS: VPMADD52LUQ +ICLASS: VAESDECLAST CPL: 3 -CATEGORY: IFMA +CATEGORY: VAES EXTENSION: AVX512EVEX -ISA_SET: AVX512IFMA_512 +ISA_SET: AVX512_VAES_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0xB4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 -IFORM: VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +PATTERN: EVV 0xDF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 MASK=0 +OPERANDS: REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 REG2=ZMM_B3():r:zu128 +IFORM: VAESDECLAST_ZMMu128_ZMMu128_ZMMu128_AVX512 } { -ICLASS: VPMADD52LUQ +ICLASS: VAESDECLAST CPL: 3 -CATEGORY: IFMA +CATEGORY: VAES EXTENSION: AVX512EVEX -ISA_SET: AVX512IFMA_512 +ISA_SET: AVX512_VAES_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0xB4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0xDF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 MEM0:r:zd:u128 +IFORM: VAESDECLAST_ZMMu128_ZMMu128_MEMu128_AVX512 } +# EMITTING VAESENC (VAESENC-128-1) +{ +ICLASS: VAESENC +CPL: 3 +CATEGORY: VAES +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VAES_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +PATTERN: EVV 0xDC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 REG2=XMM_B3():r:dq:u128 +IFORM: VAESENC_XMMu128_XMMu128_XMMu128_AVX512 +} +{ +ICLASS: VAESENC +CPL: 3 +CATEGORY: VAES +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VAES_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0xDC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 MEM0:r:dq:u128 +IFORM: VAESENC_XMMu128_XMMu128_MEMu128_AVX512 +} -###FILE: ../xed/datafiles/avx512vbmi/vbmi-isa.xed.txt -#BEGIN_LEGAL -# -#Copyright (c) 2016 Intel Corporation -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -#END_LEGAL -# -# -# -# ***** GENERATED FILE -- DO NOT EDIT! ***** -# ***** GENERATED FILE -- DO NOT EDIT! ***** -# ***** GENERATED FILE -- DO NOT EDIT! ***** -# -# -# -EVEX_INSTRUCTIONS():: -# EMITTING VPERMB (VPERMB-128-1) +# EMITTING VAESENC (VAESENC-256-1) { -ICLASS: VPERMB +ICLASS: VAESENC CPL: 3 -CATEGORY: AVX512VBMI +CATEGORY: VAES EXTENSION: AVX512EVEX -ISA_SET: AVX512VBMI_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512_VAES_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 -IFORM: VPERMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +PATTERN: EVV 0xDC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 MASK=0 +OPERANDS: REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 REG2=YMM_B3():r:qq:u128 +IFORM: VAESENC_YMMu128_YMMu128_YMMu128_AVX512 } { -ICLASS: VPERMB +ICLASS: VAESENC CPL: 3 -CATEGORY: AVX512VBMI +CATEGORY: VAES EXTENSION: AVX512EVEX -ISA_SET: AVX512VBMI_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512_VAES_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 -IFORM: VPERMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0xDC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 MEM0:r:qq:u128 +IFORM: VAESENC_YMMu128_YMMu128_MEMu128_AVX512 } -# EMITTING VPERMB (VPERMB-256-1) +# EMITTING VAESENC (VAESENC-512-1) { -ICLASS: VPERMB +ICLASS: VAESENC CPL: 3 -CATEGORY: AVX512VBMI +CATEGORY: VAES EXTENSION: AVX512EVEX -ISA_SET: AVX512VBMI_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512_VAES_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 -IFORM: VPERMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +PATTERN: EVV 0xDC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 MASK=0 +OPERANDS: REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 REG2=ZMM_B3():r:zu128 +IFORM: VAESENC_ZMMu128_ZMMu128_ZMMu128_AVX512 } { -ICLASS: VPERMB +ICLASS: VAESENC CPL: 3 -CATEGORY: AVX512VBMI +CATEGORY: VAES EXTENSION: AVX512EVEX -ISA_SET: AVX512VBMI_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512_VAES_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 -IFORM: VPERMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0xDC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 MEM0:r:zd:u128 +IFORM: VAESENC_ZMMu128_ZMMu128_MEMu128_AVX512 } -# EMITTING VPERMB (VPERMB-512-1) +# EMITTING VAESENCLAST (VAESENCLAST-128-1) { -ICLASS: VPERMB +ICLASS: VAESENCLAST CPL: 3 -CATEGORY: AVX512VBMI +CATEGORY: VAES EXTENSION: AVX512EVEX -ISA_SET: AVX512VBMI_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512_VAES_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 -IFORM: VPERMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +PATTERN: EVV 0xDD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 REG2=XMM_B3():r:dq:u128 +IFORM: VAESENCLAST_XMMu128_XMMu128_XMMu128_AVX512 } { -ICLASS: VPERMB +ICLASS: VAESENCLAST CPL: 3 -CATEGORY: AVX512VBMI +CATEGORY: VAES EXTENSION: AVX512EVEX -ISA_SET: AVX512VBMI_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512_VAES_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 -IFORM: VPERMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0xDD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 MEM0:r:dq:u128 +IFORM: VAESENCLAST_XMMu128_XMMu128_MEMu128_AVX512 } -# EMITTING VPERMI2B (VPERMI2B-128-1) +# EMITTING VAESENCLAST (VAESENCLAST-256-1) { -ICLASS: VPERMI2B +ICLASS: VAESENCLAST CPL: 3 -CATEGORY: AVX512VBMI +CATEGORY: VAES EXTENSION: AVX512EVEX -ISA_SET: AVX512VBMI_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512_VAES_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():rw:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 -IFORM: VPERMI2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +PATTERN: EVV 0xDD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 MASK=0 +OPERANDS: REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 REG2=YMM_B3():r:qq:u128 +IFORM: VAESENCLAST_YMMu128_YMMu128_YMMu128_AVX512 } { -ICLASS: VPERMI2B +ICLASS: VAESENCLAST CPL: 3 -CATEGORY: AVX512VBMI +CATEGORY: VAES EXTENSION: AVX512EVEX -ISA_SET: AVX512VBMI_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512_VAES_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():rw:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 -IFORM: VPERMI2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0xDD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 MEM0:r:qq:u128 +IFORM: VAESENCLAST_YMMu128_YMMu128_MEMu128_AVX512 } -# EMITTING VPERMI2B (VPERMI2B-256-1) +# EMITTING VAESENCLAST (VAESENCLAST-512-1) { -ICLASS: VPERMI2B +ICLASS: VAESENCLAST CPL: 3 -CATEGORY: AVX512VBMI +CATEGORY: VAES EXTENSION: AVX512EVEX -ISA_SET: AVX512VBMI_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512_VAES_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():rw:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 -IFORM: VPERMI2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +PATTERN: EVV 0xDD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 MASK=0 +OPERANDS: REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 REG2=ZMM_B3():r:zu128 +IFORM: VAESENCLAST_ZMMu128_ZMMu128_ZMMu128_AVX512 } { -ICLASS: VPERMI2B +ICLASS: VAESENCLAST CPL: 3 -CATEGORY: AVX512VBMI +CATEGORY: VAES EXTENSION: AVX512EVEX -ISA_SET: AVX512VBMI_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512_VAES_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():rw:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 -IFORM: VPERMI2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0xDD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 MEM0:r:zd:u128 +IFORM: VAESENCLAST_ZMMu128_ZMMu128_MEMu128_AVX512 } -# EMITTING VPERMI2B (VPERMI2B-512-1) +# EMITTING VPCLMULQDQ (VPCLMULQDQ-128-1) { -ICLASS: VPERMI2B +ICLASS: VPCLMULQDQ CPL: 3 -CATEGORY: AVX512VBMI +CATEGORY: VPCLMULQDQ EXTENSION: AVX512EVEX -ISA_SET: AVX512VBMI_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512_VPCLMULQDQ_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():rw:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 -IFORM: VPERMI2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +PATTERN: EVV 0x44 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u64 REG2=XMM_B3():r:dq:u64 IMM0:r:b +IFORM: VPCLMULQDQ_XMMu128_XMMu64_XMMu64_IMM8_AVX512 } { -ICLASS: VPERMI2B +ICLASS: VPCLMULQDQ CPL: 3 -CATEGORY: AVX512VBMI +CATEGORY: VPCLMULQDQ EXTENSION: AVX512EVEX -ISA_SET: AVX512VBMI_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512_VPCLMULQDQ_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():rw:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 -IFORM: VPERMI2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0x44 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u64 MEM0:r:dq:u64 IMM0:r:b +IFORM: VPCLMULQDQ_XMMu128_XMMu64_MEMu64_IMM8_AVX512 } -# EMITTING VPERMT2B (VPERMT2B-128-1) +# EMITTING VPCLMULQDQ (VPCLMULQDQ-256-1) { -ICLASS: VPERMT2B +ICLASS: VPCLMULQDQ CPL: 3 -CATEGORY: AVX512VBMI +CATEGORY: VPCLMULQDQ EXTENSION: AVX512EVEX -ISA_SET: AVX512VBMI_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512_VPCLMULQDQ_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():rw:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 -IFORM: VPERMT2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +PATTERN: EVV 0x44 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u64 REG2=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_AVX512 } { -ICLASS: VPERMT2B +ICLASS: VPCLMULQDQ CPL: 3 -CATEGORY: AVX512VBMI +CATEGORY: VPCLMULQDQ EXTENSION: AVX512EVEX -ISA_SET: AVX512VBMI_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512_VPCLMULQDQ_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=XMM_R3():rw:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 -IFORM: VPERMT2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0x44 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 UIMM8() ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u64 MEM0:r:qq:u64 IMM0:r:b +IFORM: VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8_AVX512 } -# EMITTING VPERMT2B (VPERMT2B-256-1) +# EMITTING VPCLMULQDQ (VPCLMULQDQ-512-1) { -ICLASS: VPERMT2B +ICLASS: VPCLMULQDQ CPL: 3 -CATEGORY: AVX512VBMI +CATEGORY: VPCLMULQDQ EXTENSION: AVX512EVEX -ISA_SET: AVX512VBMI_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512_VPCLMULQDQ_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():rw:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 -IFORM: VPERMT2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +PATTERN: EVV 0x44 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu64 REG2=ZMM_B3():r:zu64 IMM0:r:b +IFORM: VPCLMULQDQ_ZMMu128_ZMMu64_ZMMu64_IMM8_AVX512 } { -ICLASS: VPERMT2B +ICLASS: VPCLMULQDQ CPL: 3 -CATEGORY: AVX512VBMI +CATEGORY: VPCLMULQDQ EXTENSION: AVX512EVEX -ISA_SET: AVX512VBMI_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512_VPCLMULQDQ_512 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=YMM_R3():rw:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 -IFORM: VPERMT2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0x44 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 UIMM8() ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu64 MEM0:r:zd:u64 IMM0:r:b +IFORM: VPCLMULQDQ_ZMMu128_ZMMu64_MEMu64_IMM8_AVX512 } -# EMITTING VPERMT2B (VPERMT2B-512-1) + + +###FILE: ../xed/datafiles/gfni-vaes-vpcl/vaes-vex-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2018 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +AVX_INSTRUCTIONS():: +# EMITTING VAESDEC (VAESDEC-256-2) { -ICLASS: VPERMT2B +ICLASS: VAESDEC +CPL: 3 +CATEGORY: VAES +EXTENSION: VAES +ISA_SET: VAES +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xDE V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 REG2=YMM_B():r:qq:u128 +IFORM: VAESDEC_YMMu128_YMMu128_YMMu128 +} + +{ +ICLASS: VAESDEC +CPL: 3 +CATEGORY: VAES +EXTENSION: VAES +ISA_SET: VAES +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xDE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 +OPERANDS: REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 MEM0:r:qq:u128 +IFORM: VAESDEC_YMMu128_YMMu128_MEMu128 +} + + +# EMITTING VAESDECLAST (VAESDECLAST-256-2) +{ +ICLASS: VAESDECLAST +CPL: 3 +CATEGORY: VAES +EXTENSION: VAES +ISA_SET: VAES +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xDF V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 REG2=YMM_B():r:qq:u128 +IFORM: VAESDECLAST_YMMu128_YMMu128_YMMu128 +} + +{ +ICLASS: VAESDECLAST +CPL: 3 +CATEGORY: VAES +EXTENSION: VAES +ISA_SET: VAES +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xDF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 +OPERANDS: REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 MEM0:r:qq:u128 +IFORM: VAESDECLAST_YMMu128_YMMu128_MEMu128 +} + + +# EMITTING VAESENC (VAESENC-256-2) +{ +ICLASS: VAESENC +CPL: 3 +CATEGORY: VAES +EXTENSION: VAES +ISA_SET: VAES +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xDC V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 REG2=YMM_B():r:qq:u128 +IFORM: VAESENC_YMMu128_YMMu128_YMMu128 +} + +{ +ICLASS: VAESENC +CPL: 3 +CATEGORY: VAES +EXTENSION: VAES +ISA_SET: VAES +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xDC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 +OPERANDS: REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 MEM0:r:qq:u128 +IFORM: VAESENC_YMMu128_YMMu128_MEMu128 +} + + +# EMITTING VAESENCLAST (VAESENCLAST-256-2) +{ +ICLASS: VAESENCLAST +CPL: 3 +CATEGORY: VAES +EXTENSION: VAES +ISA_SET: VAES +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xDD V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 REG2=YMM_B():r:qq:u128 +IFORM: VAESENCLAST_YMMu128_YMMu128_YMMu128 +} + +{ +ICLASS: VAESENCLAST CPL: 3 -CATEGORY: AVX512VBMI +CATEGORY: VAES +EXTENSION: VAES +ISA_SET: VAES +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xDD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 +OPERANDS: REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 MEM0:r:qq:u128 +IFORM: VAESENCLAST_YMMu128_YMMu128_MEMu128 +} + + +# EMITTING VPCLMULQDQ (VPCLMULQDQ-256-2) +{ +ICLASS: VPCLMULQDQ +CPL: 3 +CATEGORY: VPCLMULQDQ +EXTENSION: VPCLMULQDQ +ISA_SET: VPCLMULQDQ +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x44 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 UIMM8() +OPERANDS: REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 IMM0:r:b +IFORM: VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8 +} + +{ +ICLASS: VPCLMULQDQ +CPL: 3 +CATEGORY: VPCLMULQDQ +EXTENSION: VPCLMULQDQ +ISA_SET: VPCLMULQDQ +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x44 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 UIMM8() +OPERANDS: REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 IMM0:r:b +IFORM: VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8 +} + + + + +###FILE: ../xed/datafiles/vpopcntdq-vl/vpopcntdq-vl-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2018 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING VPOPCNTD (VPOPCNTD-128-1) +{ +ICLASS: VPOPCNTD +CPL: 3 +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512VBMI_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512_VPOPCNTDQ_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():rw:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 -IFORM: VPERMT2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +PATTERN: EVV 0x55 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 +IFORM: VPOPCNTD_XMMu32_MASKmskw_XMMu32_AVX512 } { -ICLASS: VPERMT2B +ICLASS: VPOPCNTD CPL: 3 -CATEGORY: AVX512VBMI +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512VBMI_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512_VPOPCNTDQ_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM -PATTERN: EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_8_BITS() NELEM_FULLMEM() -OPERANDS: REG0=ZMM_R3():rw:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 -IFORM: VPERMT2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPOPCNTD_XMMu32_MASKmskw_MEMu32_AVX512 } -# EMITTING VPMULTISHIFTQB (VPMULTISHIFTQB-128-1) +# EMITTING VPOPCNTD (VPOPCNTD-256-1) { -ICLASS: VPMULTISHIFTQB +ICLASS: VPOPCNTD CPL: 3 -CATEGORY: AVX512VBMI +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512VBMI_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512_VPOPCNTDQ_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x83 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u64 -IFORM: VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_XMMu64_AVX512 +PATTERN: EVV 0x55 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 +IFORM: VPOPCNTD_YMMu32_MASKmskw_YMMu32_AVX512 } { -ICLASS: VPMULTISHIFTQB +ICLASS: VPOPCNTD CPL: 3 -CATEGORY: AVX512VBMI +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512VBMI_128 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512_VPOPCNTDQ_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x83 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPOPCNTD_YMMu32_MASKmskw_MEMu32_AVX512 } -# EMITTING VPMULTISHIFTQB (VPMULTISHIFTQB-256-1) +# EMITTING VPOPCNTQ (VPOPCNTQ-128-1) { -ICLASS: VPMULTISHIFTQB +ICLASS: VPOPCNTQ CPL: 3 -CATEGORY: AVX512VBMI +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512VBMI_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512_VPOPCNTDQ_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x83 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u64 -IFORM: VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_YMMu64_AVX512 +PATTERN: EVV 0x55 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 +IFORM: VPOPCNTQ_XMMu64_MASKmskw_XMMu64_AVX512 } { -ICLASS: VPMULTISHIFTQB +ICLASS: VPOPCNTQ CPL: 3 -CATEGORY: AVX512VBMI +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512VBMI_256 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512_VPOPCNTDQ_128 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x83 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPOPCNTQ_XMMu64_MASKmskw_MEMu64_AVX512 } -# EMITTING VPMULTISHIFTQB (VPMULTISHIFTQB-512-1) +# EMITTING VPOPCNTQ (VPOPCNTQ-256-1) { -ICLASS: VPMULTISHIFTQB +ICLASS: VPOPCNTQ CPL: 3 -CATEGORY: AVX512VBMI +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512VBMI_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512_VPOPCNTDQ_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x83 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu64 -IFORM: VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_AVX512 +PATTERN: EVV 0x55 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 +IFORM: VPOPCNTQ_YMMu64_MASKmskw_YMMu64_AVX512 } { -ICLASS: VPMULTISHIFTQB +ICLASS: VPOPCNTQ CPL: 3 -CATEGORY: AVX512VBMI +CATEGORY: AVX512 EXTENSION: AVX512EVEX -ISA_SET: AVX512VBMI_512 -EXCEPTIONS: AVX512-E4NF +ISA_SET: AVX512_VPOPCNTDQ_256 +EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y -ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED -PATTERN: EVV 0x83 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:vv:u64:TXT=BCASTSTR -IFORM: VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_AVX512 +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPOPCNTQ_YMMu64_MASKmskw_MEMu64_AVX512 } diff --git a/pkg/ifuzz/gen/gen.go b/pkg/ifuzz/gen/gen.go index 80caf1bb5..86c04617d 100644 --- a/pkg/ifuzz/gen/gen.go +++ b/pkg/ifuzz/gen/gen.go @@ -362,6 +362,9 @@ func parsePattern(insn *ifuzz.Insn, vals []string) error { insn.No66Prefix = true case v == "no66_prefix", v == "eosz32", v == "eosz64": insn.No66Prefix = true + case v == "eosz16", v == "eosznot64", v == "REP!=3": + // TODO(dvyukov): this may have some effect on REP/66 prefixes, + // but this wasn't checked. These are just added here to unbreak build. case v == "f2_refining_prefix", v == "refining_f2", v == "repne", v == "REP=2": insn.Prefix = append(insn.Prefix, 0xF2) insn.NoRepPrefix = true @@ -416,6 +419,7 @@ func parsePattern(insn *ifuzz.Insn, vals []string) error { v == "ESIZE_16_BITS()", v == "ESIZE_32_BITS()", v == "ESIZE_64_BITS()", + v == "ESIZE_128_BITS()", v == "NELEM_GPR_WRITER_STORE()", v == "NELEM_GPR_WRITER_STORE_BYTE()", v == "NELEM_GPR_WRITER_STORE_WORD()", @@ -452,6 +456,13 @@ func parsePattern(insn *ifuzz.Insn, vals []string) error { v == "SAE()", v == "VL512", // VL=2 v == "not_refining_f3", + v == "EVEXRR_ONE", + v == "CET=0", + v == "CET=1", + v == "WBNOINVD=0", + v == "WBNOINVD=1", + v == "CLDEMOTE=0", + v == "CLDEMOTE=1", strings.HasPrefix(v, "MODEP5="): default: return errSkip(fmt.Sprintf("unknown pattern %v", v)) diff --git a/pkg/ifuzz/generated/insns.go b/pkg/ifuzz/generated/insns.go index f72d1c349..f63233a9a 100644 --- a/pkg/ifuzz/generated/insns.go +++ b/pkg/ifuzz/generated/insns.go @@ -284,9 +284,9 @@ var insns = []*Insn{ {Name: "INC", Extension: "BASE", Mode: 15, Opcode: []uint8{255}, Modrm: true, Mod: -1, Rm: -1, VexP: -1}, {Name: "DEC_LOCK", Extension: "BASE", Mode: 15, Opcode: []uint8{255}, Prefix: []uint8{240}, Modrm: true, Mod: -3, Reg: 1, Rm: -1, VexP: -1}, {Name: "DEC", Extension: "BASE", Mode: 15, Opcode: []uint8{255}, Modrm: true, Mod: -1, Reg: 1, Rm: -1, VexP: -1}, + {Name: "CALL_NEAR", Extension: "BASE", Mode: 15, Opcode: []uint8{255}, Modrm: true, Mod: -1, Reg: 2, Rm: -1, VexP: -1}, {Name: "CALL_NEAR", Extension: "BASE", Mode: 14, Opcode: []uint8{232}, Mod: -100, Reg: -100, Rm: -100, Imm: -1, VexP: -1}, {Name: "CALL_NEAR", Extension: "BASE", Mode: 1, Opcode: []uint8{232}, Mod: -100, Reg: -100, Rm: -100, Imm: 4, VexP: -1}, - {Name: "CALL_NEAR", Extension: "BASE", Mode: 15, Opcode: []uint8{255}, Modrm: true, Mod: -1, Reg: 2, Rm: -1, VexP: -1}, {Name: "JMP", Extension: "BASE", Mode: 15, Opcode: []uint8{255}, Modrm: true, Mod: -1, Reg: 4, Rm: -1, VexP: -1}, {Name: "JMP_FAR", Extension: "BASE", Mode: 15, Opcode: []uint8{255}, Modrm: true, Mod: -3, Reg: 5, Rm: -1, VexP: -1}, {Name: "PUSH", Extension: "BASE", Mode: 15, Opcode: []uint8{255}, Modrm: true, Mod: -1, Reg: 6, Rm: -1, VexP: -1}, @@ -307,10 +307,10 @@ var insns = []*Insn{ {Name: "BTR", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 186}, Modrm: true, Mod: -1, Reg: 6, Rm: -1, Imm: 1, VexP: -1}, {Name: "BTC_LOCK", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 186}, Prefix: []uint8{240}, Modrm: true, Mod: -3, Reg: 7, Rm: -1, Imm: 1, VexP: -1}, {Name: "BTC", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 186}, Modrm: true, Mod: -1, Reg: 7, Rm: -1, Imm: 1, VexP: -1}, - {Name: "VMCLEAR", Extension: "VTX", Mode: 15, Opcode: []uint8{15, 199}, Prefix: []uint8{102}, Modrm: true, Mod: -3, Reg: 6, Rm: -1, NoRepPrefix: true, VexP: -1}, - {Name: "VMPTRLD", Extension: "VTX", Mode: 15, Opcode: []uint8{15, 199}, Modrm: true, Mod: -3, Reg: 6, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1}, - {Name: "VMPTRST", Extension: "VTX", Mode: 15, Opcode: []uint8{15, 199}, Modrm: true, Mod: -3, Reg: 7, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1}, - {Name: "VMXON", Extension: "VTX", Mode: 15, Opcode: []uint8{15, 199}, Prefix: []uint8{243}, Modrm: true, Mod: -3, Reg: 6, Rm: -1, NoRepPrefix: true, VexP: -1}, + {Name: "VMCLEAR", Extension: "VTX", Mode: 15, Priv: true, Opcode: []uint8{15, 199}, Prefix: []uint8{102}, Modrm: true, Mod: -3, Reg: 6, Rm: -1, NoRepPrefix: true, VexP: -1}, + {Name: "VMPTRLD", Extension: "VTX", Mode: 15, Priv: true, Opcode: []uint8{15, 199}, Modrm: true, Mod: -3, Reg: 6, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1}, + {Name: "VMPTRST", Extension: "VTX", Mode: 15, Priv: true, Opcode: []uint8{15, 199}, Modrm: true, Mod: -3, Reg: 7, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1}, + {Name: "VMXON", Extension: "VTX", Mode: 15, Priv: true, Opcode: []uint8{15, 199}, Prefix: []uint8{243}, Modrm: true, Mod: -3, Reg: 6, Rm: -1, NoRepPrefix: true, VexP: -1}, {Name: "CMPXCHG8B_LOCK", Extension: "BASE", Mode: 14, Opcode: []uint8{15, 199}, Prefix: []uint8{240}, Modrm: true, Mod: -3, Reg: 1, Rm: -1, VexP: -1}, {Name: "CMPXCHG8B_LOCK", Extension: "BASE", Mode: 1, Opcode: []uint8{15, 199}, Prefix: []uint8{240}, Modrm: true, Mod: -3, Reg: 1, Rm: -1, Rexw: -1, VexP: -1}, {Name: "CMPXCHG8B", Extension: "BASE", Mode: 14, Opcode: []uint8{15, 199}, Modrm: true, Mod: -3, Reg: 1, Rm: -1, VexP: -1}, @@ -362,16 +362,17 @@ var insns = []*Insn{ {Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 29}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1}, {Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 30}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1}, {Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 31}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1}, - {Name: "VMCALL", Extension: "VTX", Mode: 15, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Rm: 1, VexP: -1}, - {Name: "VMLAUNCH", Extension: "VTX", Mode: 15, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Rm: 2, VexP: -1}, - {Name: "VMRESUME", Extension: "VTX", Mode: 15, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Rm: 3, VexP: -1}, - {Name: "VMXOFF", Extension: "VTX", Mode: 15, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Rm: 4, VexP: -1}, + {Name: "VMCALL", Extension: "VTX", Mode: 15, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Rm: 1, NoRepPrefix: true, No66Prefix: true, VexP: -1}, + {Name: "VMLAUNCH", Extension: "VTX", Mode: 15, Priv: true, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Rm: 2, NoRepPrefix: true, No66Prefix: true, VexP: -1}, + {Name: "VMRESUME", Extension: "VTX", Mode: 15, Priv: true, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Rm: 3, NoRepPrefix: true, No66Prefix: true, VexP: -1}, + {Name: "VMXOFF", Extension: "VTX", Mode: 15, Priv: true, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Rm: 4, NoRepPrefix: true, No66Prefix: true, VexP: -1}, {Name: "SGDT", Extension: "BASE", Mode: 1, Opcode: []uint8{15, 1}, Modrm: true, Mod: -3, Rm: -1, VexP: -1}, {Name: "SGDT", Extension: "BASE", Mode: 14, Opcode: []uint8{15, 1}, Modrm: true, Mod: -3, Rm: -1, VexP: -1}, {Name: "LIDT", Extension: "BASE", Mode: 1, Priv: true, Opcode: []uint8{15, 1}, Modrm: true, Mod: -3, Reg: 3, Rm: -1, VexP: -1}, {Name: "LIDT", Extension: "BASE", Mode: 14, Priv: true, Opcode: []uint8{15, 1}, Modrm: true, Mod: -3, Reg: 3, Rm: -1, VexP: -1}, - {Name: "MONITOR", Extension: "SSE3", Mode: 15, Priv: true, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Reg: 1, VexP: -1}, - {Name: "MWAIT", Extension: "SSE3", Mode: 15, Priv: true, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Reg: 1, Rm: 1, VexP: -1}, + {Name: "MONITOR", Extension: "MONITOR", Mode: 14, Priv: true, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Reg: 1, NoRepPrefix: true, No66Prefix: true, VexP: -1}, + {Name: "MONITOR", Extension: "MONITOR", Mode: 1, Priv: true, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Reg: 1, NoRepPrefix: true, No66Prefix: true, VexP: -1}, + {Name: "MWAIT", Extension: "MONITOR", Mode: 15, Priv: true, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Reg: 1, Rm: 1, NoRepPrefix: true, No66Prefix: true, VexP: -1}, {Name: "SIDT", Extension: "BASE", Mode: 14, Opcode: []uint8{15, 1}, Modrm: true, Mod: -3, Reg: 1, Rm: -1, VexP: -1}, {Name: "SIDT", Extension: "BASE", Mode: 1, Opcode: []uint8{15, 1}, Modrm: true, Mod: -3, Reg: 1, Rm: -1, VexP: -1}, {Name: "INVLPG", Extension: "BASE", Mode: 15, Priv: true, Opcode: []uint8{15, 1}, Modrm: true, Mod: -3, Reg: 7, Rm: -1, VexP: -1}, @@ -466,8 +467,8 @@ var insns = []*Insn{ {Name: "PUSHAD", Extension: "BASE", Mode: 14, Opcode: []uint8{96}, Mod: -100, Reg: -100, Rm: -100, VexP: -1}, {Name: "POPA", Extension: "BASE", Mode: 14, Opcode: []uint8{97}, Mod: -100, Reg: -100, Rm: -100, VexP: -1}, {Name: "POPAD", Extension: "BASE", Mode: 14, Opcode: []uint8{97}, Mod: -100, Reg: -100, Rm: -100, VexP: -1}, - {Name: "BOUND", Extension: "BASE", Mode: 12, Opcode: []uint8{98}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, VexP: -1}, - {Name: "BOUND", Extension: "BASE", Mode: 2, Opcode: []uint8{98}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, VexP: -1}, + {Name: "BOUND", Extension: "BASE", Mode: 14, Opcode: []uint8{98}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, VexP: -1}, + {Name: "BOUND", Extension: "BASE", Mode: 14, Opcode: []uint8{98}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, No66Prefix: true, VexP: -1}, {Name: "ARPL", Extension: "BASE", Mode: 14, Opcode: []uint8{99}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1}, {Name: "MOVSXD", Extension: "LONGMODE", Mode: 1, Opcode: []uint8{99}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1}, {Name: "PUSH", Extension: "BASE", Mode: 15, Opcode: []uint8{104}, Mod: -100, Reg: -100, Rm: -100, Imm: -1, VexP: -1}, @@ -536,7 +537,7 @@ var insns = []*Insn{ {Name: "MOV", Extension: "BASE", Mode: 15, Opcode: []uint8{139}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1}, {Name: "MOV", Extension: "BASE", Mode: 15, Opcode: []uint8{140}, Modrm: true, Mod: -1, Reg: -6, Rm: -1, VexP: -1}, {Name: "LEA", Extension: "BASE", Mode: 15, Opcode: []uint8{141}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, VexP: -1}, - {Name: "MOV", Extension: "BASE", Mode: 15, Opcode: []uint8{142}, Modrm: true, Mod: -1, Reg: -6, Rm: -1, VexP: -1}, + {Name: "MOV", Extension: "BASE", Mode: 15, Opcode: []uint8{142}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1}, {Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{144}, Mod: -100, Reg: -100, Srm: true, VexP: -1}, {Name: "PAUSE", Extension: "PAUSE", Mode: 15, Opcode: []uint8{144}, Prefix: []uint8{243}, Mod: -100, Reg: -100, Srm: true, NoRepPrefix: true, VexP: -1}, {Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{144}, Prefix: []uint8{243}, Mod: -100, Reg: -100, Srm: true, NoRepPrefix: true, VexP: -1}, @@ -654,7 +655,8 @@ var insns = []*Insn{ {Name: "LOOPE", Extension: "BASE", Mode: 15, Opcode: []uint8{224}, Prefix: []uint8{243}, Mod: -100, Reg: -100, Rm: -100, Imm: 1, NoRepPrefix: true, VexP: -1}, {Name: "LOOP", Extension: "BASE", Mode: 15, Opcode: []uint8{226}, Mod: -100, Reg: -100, Rm: -100, Imm: 1, VexP: -1}, {Name: "JCXZ", Extension: "BASE", Mode: 15, Opcode: []uint8{227}, Mod: -100, Reg: -100, Rm: -100, Imm: 1, VexP: -1}, - {Name: "JECXZ", Extension: "BASE", Mode: 15, Opcode: []uint8{227}, Mod: -100, Reg: -100, Rm: -100, Imm: 1, VexP: -1}, + {Name: "JECXZ", Extension: "BASE", Mode: 14, Opcode: []uint8{227}, Mod: -100, Reg: -100, Rm: -100, Imm: 1, VexP: -1}, + {Name: "JECXZ", Extension: "BASE", Mode: 1, Opcode: []uint8{227}, Mod: -100, Reg: -100, Rm: -100, Imm: 1, VexP: -1}, {Name: "JRCXZ", Extension: "BASE", Mode: 15, Opcode: []uint8{227}, Mod: -100, Reg: -100, Rm: -100, Imm: 1, VexP: -1}, {Name: "IN", Extension: "BASE", Mode: 15, Opcode: []uint8{228}, Mod: -100, Reg: -100, Rm: -100, Imm: 1, VexP: -1}, {Name: "IN", Extension: "BASE", Mode: 15, Opcode: []uint8{229}, Mod: -100, Reg: -100, Rm: -100, Imm: 1, VexP: -1}, @@ -663,7 +665,8 @@ var insns = []*Insn{ {Name: "JMP", Extension: "BASE", Mode: 14, Opcode: []uint8{233}, Mod: -100, Reg: -100, Rm: -100, Imm: -1, VexP: -1}, {Name: "JMP", Extension: "BASE", Mode: 1, Opcode: []uint8{233}, Mod: -100, Reg: -100, Rm: -100, Imm: 4, VexP: -1}, {Name: "JMP_FAR", Extension: "BASE", Mode: 14, Opcode: []uint8{234}, Mod: -100, Reg: -100, Rm: -100, Imm: -1, Imm2: 2, VexP: -1}, - {Name: "JMP", Extension: "BASE", Mode: 15, Opcode: []uint8{235}, Mod: -100, Reg: -100, Rm: -100, Imm: 1, VexP: -1}, + {Name: "JMP", Extension: "BASE", Mode: 14, Opcode: []uint8{235}, Mod: -100, Reg: -100, Rm: -100, Imm: 1, VexP: -1}, + {Name: "JMP", Extension: "BASE", Mode: 1, Opcode: []uint8{235}, Mod: -100, Reg: -100, Rm: -100, Imm: 1, VexP: -1}, {Name: "IN", Extension: "BASE", Mode: 15, Opcode: []uint8{236}, Mod: -100, Reg: -100, Rm: -100, VexP: -1}, {Name: "IN", Extension: "BASE", Mode: 15, Opcode: []uint8{237}, Mod: -100, Reg: -100, Rm: -100, VexP: -1}, {Name: "OUT", Extension: "BASE", Mode: 15, Opcode: []uint8{238}, Mod: -100, Reg: -100, Rm: -100, VexP: -1}, @@ -682,6 +685,7 @@ var insns = []*Insn{ {Name: "SYSCALL", Extension: "LONGMODE", Mode: 1, Opcode: []uint8{15, 5}, Mod: -100, Reg: -100, Rm: -100, VexP: -1}, {Name: "CLTS", Extension: "BASE", Mode: 15, Priv: true, Opcode: []uint8{15, 6}, Mod: -100, Reg: -100, Rm: -100, VexP: -1}, {Name: "SYSRET", Extension: "LONGMODE", Mode: 1, Priv: true, Opcode: []uint8{15, 7}, Mod: -100, Reg: -100, Rm: -100, No66Prefix: true, VexP: -1}, + {Name: "SYSRET", Extension: "LONGMODE", Mode: 1, Priv: true, Opcode: []uint8{15, 7}, Mod: -100, Reg: -100, Rm: -100, VexP: -1}, {Name: "MOVUPS", Extension: "SSE", Mode: 15, Opcode: []uint8{15, 16}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1}, {Name: "MOVUPS", Extension: "SSE", Mode: 15, Opcode: []uint8{15, 17}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1}, {Name: "MOVLPS", Extension: "SSE", Mode: 15, Opcode: []uint8{15, 19}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1}, @@ -715,8 +719,10 @@ var insns = []*Insn{ {Name: "RDTSC", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 49}, Mod: -100, Reg: -100, Rm: -100, VexP: -1}, {Name: "RDMSR", Extension: "BASE", Mode: 15, Priv: true, Opcode: []uint8{15, 50}, Mod: -100, Reg: -100, Rm: -100, VexP: -1}, {Name: "RDPMC", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 51}, Mod: -100, Reg: -100, Rm: -100, VexP: -1}, - {Name: "SYSENTER", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 52}, Mod: -100, Reg: -100, Rm: -100, VexP: -1}, - {Name: "SYSEXIT", Extension: "BASE", Mode: 15, Priv: true, Opcode: []uint8{15, 53}, Mod: -100, Reg: -100, Rm: -100, VexP: -1}, + {Name: "SYSENTER", Extension: "BASE", Mode: 14, Opcode: []uint8{15, 52}, Mod: -100, Reg: -100, Rm: -100, VexP: -1}, + {Name: "SYSENTER", Extension: "BASE", Mode: 1, Opcode: []uint8{15, 52}, Mod: -100, Reg: -100, Rm: -100, VexP: -1}, + {Name: "SYSEXIT", Extension: "BASE", Mode: 14, Priv: true, Opcode: []uint8{15, 53}, Mod: -100, Reg: -100, Rm: -100, VexP: -1}, + {Name: "SYSEXIT", Extension: "BASE", Mode: 1, Priv: true, Opcode: []uint8{15, 53}, Mod: -100, Reg: -100, Rm: -100, VexP: -1}, {Name: "CMOVO", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 64}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1}, {Name: "CMOVNO", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 65}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1}, {Name: "CMOVB", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 66}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1}, @@ -874,6 +880,8 @@ var insns = []*Insn{ {Name: "LDDQU", Extension: "SSE3", Mode: 15, Opcode: []uint8{15, 240}, Prefix: []uint8{242}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1}, {Name: "INVD", Extension: "BASE", Mode: 15, Priv: true, Opcode: []uint8{15, 8}, Mod: -100, Reg: -100, Rm: -100, VexP: -1}, {Name: "WBINVD", Extension: "BASE", Mode: 15, Priv: true, Opcode: []uint8{15, 9}, Mod: -100, Reg: -100, Rm: -100, VexP: -1}, + {Name: "UD0", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 255}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1}, + {Name: "UD1", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 185}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1}, {Name: "UD2", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 11}, Mod: -100, Reg: -100, Rm: -100, VexP: -1}, {Name: "MOVAPS", Extension: "SSE", Mode: 15, Opcode: []uint8{15, 40}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1}, {Name: "MOVAPS", Extension: "SSE", Mode: 15, Opcode: []uint8{15, 41}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1}, @@ -970,10 +978,10 @@ var insns = []*Insn{ {Name: "PUNPCKHQDQ", Extension: "SSE2", Mode: 15, Opcode: []uint8{15, 109}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1}, {Name: "MOVDQU", Extension: "SSE2", Mode: 15, Opcode: []uint8{15, 111}, Prefix: []uint8{243}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1}, {Name: "MOVDQU", Extension: "SSE2", Mode: 15, Opcode: []uint8{15, 127}, Prefix: []uint8{243}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1}, - {Name: "VMREAD", Extension: "VTX", Mode: 1, Opcode: []uint8{15, 120}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1}, - {Name: "VMREAD", Extension: "VTX", Mode: 14, Opcode: []uint8{15, 120}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1}, - {Name: "VMWRITE", Extension: "VTX", Mode: 1, Opcode: []uint8{15, 121}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1}, - {Name: "VMWRITE", Extension: "VTX", Mode: 14, Opcode: []uint8{15, 121}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1}, + {Name: "VMREAD", Extension: "VTX", Mode: 1, Priv: true, Opcode: []uint8{15, 120}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1}, + {Name: "VMREAD", Extension: "VTX", Mode: 14, Priv: true, Opcode: []uint8{15, 120}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1}, + {Name: "VMWRITE", Extension: "VTX", Mode: 1, Priv: true, Opcode: []uint8{15, 121}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1}, + {Name: "VMWRITE", Extension: "VTX", Mode: 14, Priv: true, Opcode: []uint8{15, 121}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1}, {Name: "HADDPD", Extension: "SSE3", Mode: 15, Opcode: []uint8{15, 124}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1}, {Name: "HSUBPD", Extension: "SSE3", Mode: 15, Opcode: []uint8{15, 125}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1}, {Name: "MOVDQA", Extension: "SSE2", Mode: 15, Opcode: []uint8{15, 127}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1}, @@ -1152,12 +1160,9 @@ var insns = []*Insn{ {Name: "PMOVZXWD", Extension: "SSE4", Mode: 15, Opcode: []uint8{15, 56, 51}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1}, {Name: "PMOVZXWQ", Extension: "SSE4", Mode: 15, Opcode: []uint8{15, 56, 52}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1}, {Name: "PMOVZXDQ", Extension: "SSE4", Mode: 15, Opcode: []uint8{15, 56, 53}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1}, - {Name: "PCMPESTRI", Extension: "SSE4", Mode: 15, Opcode: []uint8{15, 58, 97}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, NoRepPrefix: true, Rexw: -1, VexP: -1}, - {Name: "PCMPESTRI", Extension: "SSE4", Mode: 15, Opcode: []uint8{15, 58, 97}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, NoRepPrefix: true, Rexw: 1, VexP: -1}, - {Name: "PCMPISTRI", Extension: "SSE4", Mode: 15, Opcode: []uint8{15, 58, 99}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, NoRepPrefix: true, Rexw: -1, VexP: -1}, - {Name: "PCMPISTRI", Extension: "SSE4", Mode: 15, Opcode: []uint8{15, 58, 99}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, NoRepPrefix: true, Rexw: 1, VexP: -1}, - {Name: "PCMPESTRM", Extension: "SSE4", Mode: 15, Opcode: []uint8{15, 58, 96}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, NoRepPrefix: true, Rexw: -1, VexP: -1}, - {Name: "PCMPESTRM", Extension: "SSE4", Mode: 15, Opcode: []uint8{15, 58, 96}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, NoRepPrefix: true, Rexw: 1, VexP: -1}, + {Name: "PCMPESTRI", Extension: "SSE4", Mode: 15, Opcode: []uint8{15, 58, 97}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, NoRepPrefix: true, VexP: -1}, + {Name: "PCMPISTRI", Extension: "SSE4", Mode: 15, Opcode: []uint8{15, 58, 99}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, NoRepPrefix: true, VexP: -1}, + {Name: "PCMPESTRM", Extension: "SSE4", Mode: 15, Opcode: []uint8{15, 58, 96}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, NoRepPrefix: true, VexP: -1}, {Name: "PCMPISTRM", Extension: "SSE4", Mode: 15, Opcode: []uint8{15, 58, 98}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, NoRepPrefix: true, VexP: -1}, {Name: "XGETBV", Extension: "XSAVE", Mode: 15, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Reg: 2, NoRepPrefix: true, No66Prefix: true, VexP: -1}, {Name: "XSETBV", Extension: "XSAVE", Mode: 15, Priv: true, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Reg: 2, Rm: 1, NoRepPrefix: true, No66Prefix: true, VexP: -1}, @@ -1167,7 +1172,7 @@ var insns = []*Insn{ {Name: "XRSTOR64", Extension: "XSAVE", Mode: 15, Opcode: []uint8{15, 174}, Modrm: true, Mod: -3, Reg: 5, Rm: -1, NoRepPrefix: true, No66Prefix: true, Rexw: 1, VexP: -1}, {Name: "MOVBE", Extension: "MOVBE", Mode: 15, Opcode: []uint8{15, 56, 240}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1}, {Name: "MOVBE", Extension: "MOVBE", Mode: 15, Opcode: []uint8{15, 56, 241}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1}, - {Name: "GETSEC", Extension: "SMX", Mode: 15, Opcode: []uint8{15, 55}, Mod: -100, Reg: -100, Rm: -100, VexP: -1}, + {Name: "GETSEC", Extension: "SMX", Mode: 15, Opcode: []uint8{15, 55}, Mod: -100, Reg: -100, Rm: -100, NoRepPrefix: true, No66Prefix: true, VexP: -1}, {Name: "AESKEYGENASSIST", Extension: "AES", Mode: 15, Opcode: []uint8{15, 58, 223}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, NoRepPrefix: true, VexP: -1}, {Name: "AESENC", Extension: "AES", Mode: 15, Opcode: []uint8{15, 56, 220}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1}, {Name: "AESENCLAST", Extension: "AES", Mode: 15, Opcode: []uint8{15, 56, 221}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1}, @@ -1176,9 +1181,9 @@ var insns = []*Insn{ {Name: "AESIMC", Extension: "AES", Mode: 15, Opcode: []uint8{15, 56, 219}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1}, {Name: "PCLMULQDQ", Extension: "PCLMULQDQ", Mode: 15, Opcode: []uint8{15, 58, 68}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, NoRepPrefix: true, VexP: -1}, {Name: "INVEPT", Extension: "VTX", Mode: 1, Priv: true, Opcode: []uint8{15, 56, 128}, Prefix: []uint8{102}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1}, - {Name: "INVEPT", Extension: "VTX", Mode: 2, Priv: true, Opcode: []uint8{15, 56, 128}, Prefix: []uint8{102}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1}, + {Name: "INVEPT", Extension: "VTX", Mode: 14, Priv: true, Opcode: []uint8{15, 56, 128}, Prefix: []uint8{102}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1}, {Name: "INVVPID", Extension: "VTX", Mode: 1, Priv: true, Opcode: []uint8{15, 56, 129}, Prefix: []uint8{102}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1}, - {Name: "INVVPID", Extension: "VTX", Mode: 2, Priv: true, Opcode: []uint8{15, 56, 129}, Prefix: []uint8{102}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1}, + {Name: "INVVPID", Extension: "VTX", Mode: 14, Priv: true, Opcode: []uint8{15, 56, 129}, Prefix: []uint8{102}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1}, {Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 13}, Modrm: true, Mod: 3, Reg: -1, Rm: -1, VexP: -1}, {Name: "PREFETCH_EXCLUSIVE", Extension: "3DNOW", Mode: 15, Opcode: []uint8{15, 13}, Modrm: true, Mod: -3, Rm: -1, VexP: -1}, {Name: "PREFETCHW", Extension: "3DNOW", Mode: 15, Opcode: []uint8{15, 13}, Modrm: true, Mod: -3, Reg: 1, Rm: -1, VexP: -1}, @@ -1191,6 +1196,16 @@ var insns = []*Insn{ {Name: "NOP2", Extension: "BASE", Mode: 15, Opcode: []uint8{102, 144}, Mod: -100, Reg: -100, Rm: -100, VexP: -1}, {Name: "NOP3", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 31, 0}, Mod: -100, Reg: -100, Rm: -100, VexP: -1}, {Name: "NOP4", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 31, 64, 0}, Mod: -100, Reg: -100, Rm: -100, VexP: -1}, + {Name: "XSTORE", Extension: "VIA_PADLOCK_RNG", Mode: 15, Opcode: []uint8{15, 167}, Modrm: true, Mod: 3, NoRepPrefix: true, VexP: -1}, + {Name: "REP_XSTORE", Extension: "VIA_PADLOCK_RNG", Mode: 15, Opcode: []uint8{15, 167}, Prefix: []uint8{243}, Modrm: true, Mod: 3, NoRepPrefix: true, VexP: -1}, + {Name: "REP_XCRYPTECB", Extension: "VIA_PADLOCK_AES", Mode: 15, Opcode: []uint8{15, 167}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 1, NoRepPrefix: true, VexP: -1}, + {Name: "REP_XCRYPTCBC", Extension: "VIA_PADLOCK_AES", Mode: 15, Opcode: []uint8{15, 167}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 2, NoRepPrefix: true, VexP: -1}, + {Name: "REP_XCRYPTCTR", Extension: "VIA_PADLOCK_AES", Mode: 15, Opcode: []uint8{15, 167}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 3, NoRepPrefix: true, VexP: -1}, + {Name: "REP_XCRYPTCFB", Extension: "VIA_PADLOCK_AES", Mode: 15, Opcode: []uint8{15, 167}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 4, NoRepPrefix: true, VexP: -1}, + {Name: "REP_XCRYPTOFB", Extension: "VIA_PADLOCK_AES", Mode: 15, Opcode: []uint8{15, 167}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 5, NoRepPrefix: true, VexP: -1}, + {Name: "REP_XSHA1", Extension: "VIA_PADLOCK_SHA", Mode: 15, Opcode: []uint8{15, 166}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 1, NoRepPrefix: true, VexP: -1}, + {Name: "REP_XSHA256", Extension: "VIA_PADLOCK_SHA", Mode: 15, Opcode: []uint8{15, 166}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 2, NoRepPrefix: true, VexP: -1}, + {Name: "REP_MONTMUL", Extension: "VIA_PADLOCK_MONTMUL", Mode: 15, Opcode: []uint8{15, 166}, Prefix: []uint8{243}, Modrm: true, Mod: 3, NoRepPrefix: true, VexP: -1}, {Name: "FEMMS", Extension: "3DNOW", Mode: 15, Opcode: []uint8{15, 14}, Mod: -100, Reg: -100, Rm: -100, VexP: -1}, {Name: "PI2FW", Extension: "3DNOW", Mode: 15, Opcode: []uint8{15, 15}, Suffix: []uint8{12}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1}, {Name: "PI2FD", Extension: "3DNOW", Mode: 15, Opcode: []uint8{15, 15}, Suffix: []uint8{13}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1}, @@ -1201,12 +1216,12 @@ var insns = []*Insn{ {Name: "PFCMPGE", Extension: "3DNOW", Mode: 15, Opcode: []uint8{15, 15}, Suffix: []uint8{144}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1}, {Name: "PFMIN", Extension: "3DNOW", Mode: 15, Opcode: []uint8{15, 15}, Suffix: []uint8{148}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1}, {Name: "PFRCP", Extension: "3DNOW", Mode: 15, Opcode: []uint8{15, 15}, Suffix: []uint8{150}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1}, - {Name: "PFSQRT", Extension: "3DNOW", Mode: 15, Opcode: []uint8{15, 15}, Suffix: []uint8{151}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1}, + {Name: "PFRSQRT", Extension: "3DNOW", Mode: 15, Opcode: []uint8{15, 15}, Suffix: []uint8{151}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1}, {Name: "PFSUB", Extension: "3DNOW", Mode: 15, Opcode: []uint8{15, 15}, Suffix: []uint8{154}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1}, {Name: "PFADD", Extension: "3DNOW", Mode: 15, Opcode: []uint8{15, 15}, Suffix: []uint8{158}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1}, {Name: "PFCMPGT", Extension: "3DNOW", Mode: 15, Opcode: []uint8{15, 15}, Suffix: []uint8{160}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1}, {Name: "PFMAX", Extension: "3DNOW", Mode: 15, Opcode: []uint8{15, 15}, Suffix: []uint8{164}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1}, - {Name: "PFCPIT1", Extension: "3DNOW", Mode: 15, Opcode: []uint8{15, 15}, Suffix: []uint8{166}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1}, + {Name: "PFRCPIT1", Extension: "3DNOW", Mode: 15, Opcode: []uint8{15, 15}, Suffix: []uint8{166}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1}, {Name: "PFRSQIT1", Extension: "3DNOW", Mode: 15, Opcode: []uint8{15, 15}, Suffix: []uint8{167}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1}, {Name: "PFSUBR", Extension: "3DNOW", Mode: 15, Opcode: []uint8{15, 15}, Suffix: []uint8{170}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1}, {Name: "PFACC", Extension: "3DNOW", Mode: 15, Opcode: []uint8{15, 15}, Suffix: []uint8{174}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, VexP: -1}, @@ -1234,6 +1249,9 @@ var insns = []*Insn{ {Name: "MOVNTSS", Extension: "SSE4a", Mode: 15, Opcode: []uint8{15, 43}, Prefix: []uint8{243}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1}, {Name: "LZCNT", Extension: "AMD", Mode: 15, Opcode: []uint8{15, 189}, Prefix: []uint8{243}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1}, {Name: "CLZERO", Extension: "CLZERO", Mode: 15, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Reg: 7, Rm: 4, VexP: -1}, + {Name: "MONITORX", Extension: "MONITORX", Mode: 14, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Reg: 7, Rm: 2, NoRepPrefix: true, No66Prefix: true, VexP: -1}, + {Name: "MONITORX", Extension: "MONITORX", Mode: 1, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Reg: 7, Rm: 2, NoRepPrefix: true, No66Prefix: true, VexP: -1}, + {Name: "MWAITX", Extension: "MONITORX", Mode: 15, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Reg: 7, Rm: 3, NoRepPrefix: true, No66Prefix: true, VexP: -1}, {Name: "VPMACSSWW", Extension: "XOP", Mode: 3, Opcode: []uint8{133}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: -1, Vex: 143, VexMap: 8, VexL: -1}, {Name: "VPMACSSWD", Extension: "XOP", Mode: 3, Opcode: []uint8{134}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: -1, Vex: 143, VexMap: 8, VexL: -1}, {Name: "VPMACSSDQL", Extension: "XOP", Mode: 3, Opcode: []uint8{135}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: -1, Vex: 143, VexMap: 8, VexL: -1}, @@ -1309,20 +1327,30 @@ var insns = []*Insn{ {Name: "VPSHAQ", Extension: "XOP", Mode: 3, Opcode: []uint8{155}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 143, VexMap: 9, VexL: -1}, {Name: "VPHADDDQ", Extension: "XOP", Mode: 3, Opcode: []uint8{203}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 143, VexMap: 9, VexL: -1, VexNoR: true}, {Name: "VPHADDUDQ", Extension: "XOP", Mode: 3, Opcode: []uint8{219}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 143, VexMap: 9, VexL: -1, VexNoR: true}, - {Name: "BEXTR_XOP", Extension: "TBM", Mode: 7, Opcode: []uint8{16}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 4, Rexw: -1, Vex: 143, VexMap: 10, VexL: -1, VexNoR: true}, - {Name: "BLCFILL", Extension: "TBM", Mode: 7, Opcode: []uint8{1}, Modrm: true, Mod: -1, Reg: 1, Rm: -1, Rexw: -1, Vex: 143, VexMap: 9, VexL: -1}, - {Name: "BLSFILL", Extension: "TBM", Mode: 7, Opcode: []uint8{1}, Modrm: true, Mod: -1, Reg: 2, Rm: -1, Rexw: -1, Vex: 143, VexMap: 9, VexL: -1}, - {Name: "BLCS", Extension: "TBM", Mode: 7, Opcode: []uint8{1}, Modrm: true, Mod: -1, Reg: 3, Rm: -1, Rexw: -1, Vex: 143, VexMap: 9, VexL: -1}, - {Name: "TZMSK", Extension: "TBM", Mode: 7, Opcode: []uint8{1}, Modrm: true, Mod: -1, Reg: 4, Rm: -1, Rexw: -1, Vex: 143, VexMap: 9, VexL: -1}, - {Name: "BLCIC", Extension: "TBM", Mode: 7, Opcode: []uint8{1}, Modrm: true, Mod: -1, Reg: 5, Rm: -1, Rexw: -1, Vex: 143, VexMap: 9, VexL: -1}, - {Name: "BLSIC", Extension: "TBM", Mode: 7, Opcode: []uint8{1}, Modrm: true, Mod: -1, Reg: 6, Rm: -1, Rexw: -1, Vex: 143, VexMap: 9, VexL: -1}, - {Name: "T1MSKC", Extension: "TBM", Mode: 7, Opcode: []uint8{1}, Modrm: true, Mod: -1, Reg: 7, Rm: -1, Rexw: -1, Vex: 143, VexMap: 9, VexL: -1}, - {Name: "BLCMSK", Extension: "TBM", Mode: 7, Opcode: []uint8{2}, Modrm: true, Mod: -1, Reg: 1, Rm: -1, Rexw: -1, Vex: 143, VexMap: 9, VexL: -1}, - {Name: "BLCI", Extension: "TBM", Mode: 7, Opcode: []uint8{2}, Modrm: true, Mod: -1, Reg: 6, Rm: -1, Rexw: -1, Vex: 143, VexMap: 9, VexL: -1}, - {Name: "LLWPCB", Extension: "XOP", Mode: 3, Opcode: []uint8{18}, Modrm: true, Mod: 3, Rm: -1, Rexw: -1, Vex: 143, VexMap: 9, VexL: -1, VexNoR: true}, - {Name: "SLWPCB", Extension: "XOP", Mode: 3, Opcode: []uint8{18}, Modrm: true, Mod: 3, Reg: 1, Rm: -1, Rexw: -1, Vex: 143, VexMap: 9, VexL: -1, VexNoR: true}, - {Name: "LWPINS", Extension: "XOP", Mode: 3, Opcode: []uint8{18}, Modrm: true, Mod: -1, Rm: -1, Imm: 4, Rexw: -1, Vex: 143, VexMap: 10, VexL: -1}, - {Name: "LWPVAL", Extension: "XOP", Mode: 3, Opcode: []uint8{18}, Modrm: true, Mod: -1, Reg: 1, Rm: -1, Imm: 4, Rexw: -1, Vex: 143, VexMap: 10, VexL: -1}, + {Name: "BEXTR_XOP", Extension: "TBM", Mode: 6, Opcode: []uint8{16}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 4, Vex: 143, VexMap: 10, VexL: -1, VexNoR: true}, + {Name: "BEXTR_XOP", Extension: "TBM", Mode: 1, Opcode: []uint8{16}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 4, Vex: 143, VexMap: 10, VexL: -1, VexNoR: true}, + {Name: "BLCFILL", Extension: "TBM", Mode: 6, Opcode: []uint8{1}, Modrm: true, Mod: -1, Reg: 1, Rm: -1, Vex: 143, VexMap: 9, VexL: -1}, + {Name: "BLCFILL", Extension: "TBM", Mode: 1, Opcode: []uint8{1}, Modrm: true, Mod: -1, Reg: 1, Rm: -1, Vex: 143, VexMap: 9, VexL: -1}, + {Name: "BLSFILL", Extension: "TBM", Mode: 6, Opcode: []uint8{1}, Modrm: true, Mod: -1, Reg: 2, Rm: -1, Vex: 143, VexMap: 9, VexL: -1}, + {Name: "BLSFILL", Extension: "TBM", Mode: 1, Opcode: []uint8{1}, Modrm: true, Mod: -1, Reg: 2, Rm: -1, Vex: 143, VexMap: 9, VexL: -1}, + {Name: "BLCS", Extension: "TBM", Mode: 6, Opcode: []uint8{1}, Modrm: true, Mod: -1, Reg: 3, Rm: -1, Vex: 143, VexMap: 9, VexL: -1}, + {Name: "BLCS", Extension: "TBM", Mode: 1, Opcode: []uint8{1}, Modrm: true, Mod: -1, Reg: 3, Rm: -1, Vex: 143, VexMap: 9, VexL: -1}, + {Name: "TZMSK", Extension: "TBM", Mode: 6, Opcode: []uint8{1}, Modrm: true, Mod: -1, Reg: 4, Rm: -1, Vex: 143, VexMap: 9, VexL: -1}, + {Name: "TZMSK", Extension: "TBM", Mode: 1, Opcode: []uint8{1}, Modrm: true, Mod: -1, Reg: 4, Rm: -1, Vex: 143, VexMap: 9, VexL: -1}, + {Name: "BLCIC", Extension: "TBM", Mode: 6, Opcode: []uint8{1}, Modrm: true, Mod: -1, Reg: 5, Rm: -1, Vex: 143, VexMap: 9, VexL: -1}, + {Name: "BLCIC", Extension: "TBM", Mode: 1, Opcode: []uint8{1}, Modrm: true, Mod: -1, Reg: 5, Rm: -1, Vex: 143, VexMap: 9, VexL: -1}, + {Name: "BLSIC", Extension: "TBM", Mode: 6, Opcode: []uint8{1}, Modrm: true, Mod: -1, Reg: 6, Rm: -1, Vex: 143, VexMap: 9, VexL: -1}, + {Name: "BLSIC", Extension: "TBM", Mode: 1, Opcode: []uint8{1}, Modrm: true, Mod: -1, Reg: 6, Rm: -1, Vex: 143, VexMap: 9, VexL: -1}, + {Name: "T1MSKC", Extension: "TBM", Mode: 6, Opcode: []uint8{1}, Modrm: true, Mod: -1, Reg: 7, Rm: -1, Vex: 143, VexMap: 9, VexL: -1}, + {Name: "T1MSKC", Extension: "TBM", Mode: 1, Opcode: []uint8{1}, Modrm: true, Mod: -1, Reg: 7, Rm: -1, Vex: 143, VexMap: 9, VexL: -1}, + {Name: "BLCMSK", Extension: "TBM", Mode: 6, Opcode: []uint8{2}, Modrm: true, Mod: -1, Reg: 1, Rm: -1, Vex: 143, VexMap: 9, VexL: -1}, + {Name: "BLCMSK", Extension: "TBM", Mode: 1, Opcode: []uint8{2}, Modrm: true, Mod: -1, Reg: 1, Rm: -1, Vex: 143, VexMap: 9, VexL: -1}, + {Name: "BLCI", Extension: "TBM", Mode: 6, Opcode: []uint8{2}, Modrm: true, Mod: -1, Reg: 6, Rm: -1, Vex: 143, VexMap: 9, VexL: -1}, + {Name: "BLCI", Extension: "TBM", Mode: 1, Opcode: []uint8{2}, Modrm: true, Mod: -1, Reg: 6, Rm: -1, Vex: 143, VexMap: 9, VexL: -1}, + {Name: "LLWPCB", Extension: "XOP", Mode: 3, Opcode: []uint8{18}, Modrm: true, Mod: 3, Rm: -1, Vex: 143, VexMap: 9, VexL: -1, VexNoR: true}, + {Name: "SLWPCB", Extension: "XOP", Mode: 3, Opcode: []uint8{18}, Modrm: true, Mod: 3, Reg: 1, Rm: -1, Vex: 143, VexMap: 9, VexL: -1, VexNoR: true}, + {Name: "LWPINS", Extension: "XOP", Mode: 3, Opcode: []uint8{18}, Modrm: true, Mod: -1, Rm: -1, Imm: 4, Vex: 143, VexMap: 10, VexL: -1}, + {Name: "LWPVAL", Extension: "XOP", Mode: 3, Opcode: []uint8{18}, Modrm: true, Mod: -1, Reg: 1, Rm: -1, Imm: 4, Vex: 143, VexMap: 10, VexL: -1}, {Name: "VFMADDSUBPS", Extension: "FMA4", Mode: 3, Opcode: []uint8{92}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: -1, Vex: 196, VexMap: 3, VexL: -1, VexP: 1}, {Name: "VFMADDSUBPS", Extension: "FMA4", Mode: 3, Opcode: []uint8{92}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: 1, Vex: 196, VexMap: 3, VexL: -1, VexP: 1}, {Name: "VFMADDSUBPS", Extension: "FMA4", Mode: 3, Opcode: []uint8{92}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: -1, Vex: 196, VexMap: 3, VexL: 1, VexP: 1}, @@ -1395,8 +1423,6 @@ var insns = []*Insn{ {Name: "VPERMIL2PD", Extension: "XOP", Mode: 3, Opcode: []uint8{73}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: -1, Vex: 196, VexMap: 3, VexL: 1, VexP: 1}, {Name: "VPERMIL2PD", Extension: "XOP", Mode: 3, Opcode: []uint8{73}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: 1, Vex: 196, VexMap: 3, VexL: -1, VexP: 1}, {Name: "VPERMIL2PD", Extension: "XOP", Mode: 3, Opcode: []uint8{73}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: 1, Vex: 196, VexMap: 3, VexL: 1, VexP: 1}, - {Name: "XSAVEOPT", Extension: "XSAVEOPT", Mode: 15, Opcode: []uint8{15, 174}, Modrm: true, Mod: -3, Reg: 6, Rm: -1, NoRepPrefix: true, No66Prefix: true, Rexw: -1, VexP: -1}, - {Name: "XSAVEOPT64", Extension: "XSAVEOPT", Mode: 15, Opcode: []uint8{15, 174}, Modrm: true, Mod: -3, Reg: 6, Rm: -1, NoRepPrefix: true, No66Prefix: true, Rexw: 1, VexP: -1}, {Name: "BNDMK", Extension: "MPX", Mode: 15, Opcode: []uint8{15, 27}, Prefix: []uint8{243}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1}, {Name: "BNDCL", Extension: "MPX", Mode: 15, Opcode: []uint8{15, 26}, Prefix: []uint8{243}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1}, {Name: "BNDCL", Extension: "MPX", Mode: 1, Opcode: []uint8{15, 26}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1}, @@ -1426,6 +1452,40 @@ var insns = []*Insn{ {Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 26}, Modrm: true, Mod: 3, Reg: -1, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1}, {Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 27}, Modrm: true, Mod: 3, Reg: -1, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1}, {Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 27}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1}, + {Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 30}, Modrm: true, Mod: 3, Reg: -1, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1}, + {Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 30}, Prefix: []uint8{242}, Modrm: true, Mod: 3, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1}, + {Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 30}, Prefix: []uint8{102}, Modrm: true, Mod: 3, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1}, + {Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 30}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Rm: -1, NoRepPrefix: true, VexP: -1}, + {Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 30}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 2, Rm: -1, NoRepPrefix: true, VexP: -1}, + {Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 30}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 3, Rm: -1, NoRepPrefix: true, VexP: -1}, + {Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 30}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 4, Rm: -1, NoRepPrefix: true, VexP: -1}, + {Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 30}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 5, Rm: -1, NoRepPrefix: true, VexP: -1}, + {Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 30}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 6, Rm: -1, NoRepPrefix: true, VexP: -1}, + {Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 30}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 7, NoRepPrefix: true, VexP: -1}, + {Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 30}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 7, Rm: 1, NoRepPrefix: true, VexP: -1}, + {Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 30}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 7, Rm: 4, NoRepPrefix: true, VexP: -1}, + {Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 30}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 7, Rm: 5, NoRepPrefix: true, VexP: -1}, + {Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 30}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 7, Rm: 6, NoRepPrefix: true, VexP: -1}, + {Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 30}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 7, Rm: 7, NoRepPrefix: true, VexP: -1}, + {Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 30}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 7, Rm: 2, NoRepPrefix: true, VexP: -1}, + {Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 30}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 7, Rm: 3, NoRepPrefix: true, VexP: -1}, + {Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 30}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 1, Rm: -1, NoRepPrefix: true, Rexw: -1, VexP: -1}, + {Name: "NOP", Extension: "BASE", Mode: 1, Opcode: []uint8{15, 30}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 1, Rm: -1, NoRepPrefix: true, Rexw: 1, VexP: -1}, + {Name: "CLRSSBSY", Extension: "CET", Mode: 15, Opcode: []uint8{15, 174}, Prefix: []uint8{243}, Modrm: true, Mod: -3, Reg: 6, Rm: -1, NoRepPrefix: true, VexP: -1}, + {Name: "ENDBR32", Extension: "CET", Mode: 15, Opcode: []uint8{15, 30}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 7, Rm: 3, NoRepPrefix: true, VexP: -1}, + {Name: "ENDBR64", Extension: "CET", Mode: 15, Opcode: []uint8{15, 30}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 7, Rm: 2, NoRepPrefix: true, VexP: -1}, + {Name: "INCSSPD", Extension: "CET", Mode: 15, Opcode: []uint8{15, 174}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 5, Rm: -1, NoRepPrefix: true, Rexw: -1, VexP: -1}, + {Name: "INCSSPQ", Extension: "CET", Mode: 1, Opcode: []uint8{15, 174}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 5, Rm: -1, NoRepPrefix: true, Rexw: 1, VexP: -1}, + {Name: "RDSSPD", Extension: "CET", Mode: 15, Opcode: []uint8{15, 30}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 1, Rm: -1, NoRepPrefix: true, Rexw: -1, VexP: -1}, + {Name: "RDSSPQ", Extension: "CET", Mode: 1, Opcode: []uint8{15, 30}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 1, Rm: -1, NoRepPrefix: true, Rexw: 1, VexP: -1}, + {Name: "RSTORSSP", Extension: "CET", Mode: 15, Opcode: []uint8{15, 1}, Prefix: []uint8{243}, Modrm: true, Mod: -3, Reg: 5, Rm: -1, NoRepPrefix: true, VexP: -1}, + {Name: "SAVEPREVSSP", Extension: "CET", Mode: 15, Opcode: []uint8{15, 1}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 5, Rm: 2, NoRepPrefix: true, VexP: -1}, + {Name: "SETSSBSY", Extension: "CET", Mode: 15, Opcode: []uint8{15, 1}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 5, NoRepPrefix: true, VexP: -1}, + {Name: "WRSSD", Extension: "CET", Mode: 15, Opcode: []uint8{15, 56, 246}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, NoRepPrefix: true, No66Prefix: true, Rexw: -1, VexP: -1}, + {Name: "WRSSQ", Extension: "CET", Mode: 1, Opcode: []uint8{15, 56, 246}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, NoRepPrefix: true, No66Prefix: true, Rexw: 1, VexP: -1}, + {Name: "WRUSSD", Extension: "CET", Mode: 15, Opcode: []uint8{15, 56, 245}, Prefix: []uint8{102}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, NoRepPrefix: true, Rexw: -1, VexP: -1}, + {Name: "WRUSSQ", Extension: "CET", Mode: 1, Opcode: []uint8{15, 56, 245}, Prefix: []uint8{102}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, NoRepPrefix: true, Rexw: 1, VexP: -1}, + {Name: "RDRAND", Extension: "RDRAND", Mode: 15, Opcode: []uint8{15, 199}, Modrm: true, Mod: 3, Reg: 6, Rm: -1, NoRepPrefix: true, VexP: -1}, {Name: "SHA1MSG1", Extension: "SHA", Mode: 15, Opcode: []uint8{15, 56, 201}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1}, {Name: "SHA1MSG2", Extension: "SHA", Mode: 15, Opcode: []uint8{15, 56, 202}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1}, {Name: "SHA1NEXTE", Extension: "SHA", Mode: 15, Opcode: []uint8{15, 56, 200}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1}, @@ -1433,17 +1493,49 @@ var insns = []*Insn{ {Name: "SHA256MSG1", Extension: "SHA", Mode: 15, Opcode: []uint8{15, 56, 204}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1}, {Name: "SHA256MSG2", Extension: "SHA", Mode: 15, Opcode: []uint8{15, 56, 205}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1}, {Name: "SHA256RNDS2", Extension: "SHA", Mode: 15, Opcode: []uint8{15, 56, 203}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1}, - {Name: "RDRAND", Extension: "RDRAND", Mode: 15, Opcode: []uint8{15, 199}, Modrm: true, Mod: 3, Reg: 6, Rm: -1, NoRepPrefix: true, VexP: -1}, - {Name: "RDFSBASE", Extension: "RDWRFSGS", Mode: 1, Opcode: []uint8{15, 174}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1}, - {Name: "RDGSBASE", Extension: "RDWRFSGS", Mode: 1, Opcode: []uint8{15, 174}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 1, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1}, - {Name: "WRFSBASE", Extension: "RDWRFSGS", Mode: 1, Opcode: []uint8{15, 174}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 2, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1}, - {Name: "WRGSBASE", Extension: "RDWRFSGS", Mode: 1, Opcode: []uint8{15, 174}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 3, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1}, + {Name: "XSAVEOPT", Extension: "XSAVEOPT", Mode: 15, Opcode: []uint8{15, 174}, Modrm: true, Mod: -3, Reg: 6, Rm: -1, NoRepPrefix: true, No66Prefix: true, Rexw: -1, VexP: -1}, + {Name: "XSAVEOPT64", Extension: "XSAVEOPT", Mode: 15, Opcode: []uint8{15, 174}, Modrm: true, Mod: -3, Reg: 6, Rm: -1, NoRepPrefix: true, No66Prefix: true, Rexw: 1, VexP: -1}, {Name: "XSAVES", Extension: "XSAVES", Mode: 15, Priv: true, Opcode: []uint8{15, 199}, Modrm: true, Mod: -3, Reg: 5, Rm: -1, NoRepPrefix: true, No66Prefix: true, Rexw: -1, VexP: -1}, {Name: "XSAVES64", Extension: "XSAVES", Mode: 15, Priv: true, Opcode: []uint8{15, 199}, Modrm: true, Mod: -3, Reg: 5, Rm: -1, NoRepPrefix: true, No66Prefix: true, Rexw: 1, VexP: -1}, {Name: "XRSTORS", Extension: "XSAVES", Mode: 15, Priv: true, Opcode: []uint8{15, 199}, Modrm: true, Mod: -3, Reg: 3, Rm: -1, NoRepPrefix: true, No66Prefix: true, Rexw: -1, VexP: -1}, {Name: "XRSTORS64", Extension: "XSAVES", Mode: 15, Priv: true, Opcode: []uint8{15, 199}, Modrm: true, Mod: -3, Reg: 3, Rm: -1, NoRepPrefix: true, No66Prefix: true, Rexw: 1, VexP: -1}, {Name: "XSAVEC", Extension: "XSAVEC", Mode: 15, Opcode: []uint8{15, 199}, Modrm: true, Mod: -3, Reg: 4, Rm: -1, NoRepPrefix: true, No66Prefix: true, Rexw: -1, VexP: -1}, {Name: "XSAVEC64", Extension: "XSAVEC", Mode: 15, Opcode: []uint8{15, 199}, Modrm: true, Mod: -3, Reg: 4, Rm: -1, NoRepPrefix: true, No66Prefix: true, Rexw: 1, VexP: -1}, + {Name: "CLFLUSHOPT", Extension: "CLFLUSHOPT", Mode: 15, Opcode: []uint8{15, 174}, Prefix: []uint8{102}, Modrm: true, Mod: -3, Reg: 7, Rm: -1, NoRepPrefix: true, VexP: -1}, + {Name: "RDSEED", Extension: "RDSEED", Mode: 15, Opcode: []uint8{15, 199}, Modrm: true, Mod: 3, Reg: 7, Rm: -1, NoRepPrefix: true, VexP: -1}, + {Name: "RDFSBASE", Extension: "RDWRFSGS", Mode: 1, Opcode: []uint8{15, 174}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Rm: -1, NoRepPrefix: true, VexP: -1}, + {Name: "RDGSBASE", Extension: "RDWRFSGS", Mode: 1, Opcode: []uint8{15, 174}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 1, Rm: -1, NoRepPrefix: true, VexP: -1}, + {Name: "WRFSBASE", Extension: "RDWRFSGS", Mode: 1, Opcode: []uint8{15, 174}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 2, Rm: -1, NoRepPrefix: true, VexP: -1}, + {Name: "WRGSBASE", Extension: "RDWRFSGS", Mode: 1, Opcode: []uint8{15, 174}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 3, Rm: -1, NoRepPrefix: true, VexP: -1}, + {Name: "CLAC", Extension: "SMAP", Mode: 15, Priv: true, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Reg: 1, Rm: 2, NoRepPrefix: true, No66Prefix: true, VexP: -1}, + {Name: "STAC", Extension: "SMAP", Mode: 15, Priv: true, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Reg: 1, Rm: 3, NoRepPrefix: true, No66Prefix: true, VexP: -1}, + {Name: "ENCLU", Extension: "SGX", Mode: 15, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Reg: 2, Rm: 7, NoRepPrefix: true, No66Prefix: true, VexP: -1}, + {Name: "ENCLS", Extension: "SGX", Mode: 15, Priv: true, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Reg: 1, Rm: 7, NoRepPrefix: true, No66Prefix: true, VexP: -1}, + {Name: "RDPID", Extension: "RDPID", Mode: 14, Opcode: []uint8{15, 199}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 7, Rm: -1, NoRepPrefix: true, VexP: -1}, + {Name: "RDPID", Extension: "RDPID", Mode: 1, Opcode: []uint8{15, 199}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 7, Rm: -1, NoRepPrefix: true, VexP: -1}, + {Name: "PTWRITE", Extension: "PT", Mode: 15, Opcode: []uint8{15, 174}, Prefix: []uint8{243}, Modrm: true, Mod: -1, Reg: 4, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1}, + {Name: "MOVDIR64B", Extension: "MOVDIR", Mode: 14, Opcode: []uint8{15, 56, 248}, Prefix: []uint8{102}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1}, + {Name: "MOVDIR64B", Extension: "MOVDIR", Mode: 1, Opcode: []uint8{15, 56, 248}, Prefix: []uint8{102}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1}, + {Name: "MOVDIRI", Extension: "MOVDIR", Mode: 15, Opcode: []uint8{15, 56, 249}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, NoRepPrefix: true, No66Prefix: true, Rexw: -1, VexP: -1}, + {Name: "MOVDIRI", Extension: "MOVDIR", Mode: 1, Opcode: []uint8{15, 56, 249}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, NoRepPrefix: true, No66Prefix: true, Rexw: 1, VexP: -1}, + {Name: "TPAUSE", Extension: "WAITPKG", Mode: 15, Opcode: []uint8{15, 174}, Prefix: []uint8{102}, Modrm: true, Mod: 3, Reg: 6, Rm: -1, NoRepPrefix: true, Rexw: -1, VexP: -1}, + {Name: "TPAUSE", Extension: "WAITPKG", Mode: 1, Opcode: []uint8{15, 174}, Prefix: []uint8{102}, Modrm: true, Mod: 3, Reg: 6, Rm: -1, NoRepPrefix: true, Rexw: 1, VexP: -1}, + {Name: "UMONITOR", Extension: "WAITPKG", Mode: 15, Opcode: []uint8{15, 174}, Prefix: []uint8{243}, Modrm: true, Mod: 3, Reg: 6, Rm: -1, NoRepPrefix: true, VexP: -1}, + {Name: "UMWAIT", Extension: "WAITPKG", Mode: 15, Opcode: []uint8{15, 174}, Prefix: []uint8{242}, Modrm: true, Mod: 3, Reg: 6, Rm: -1, NoRepPrefix: true, Rexw: -1, VexP: -1}, + {Name: "UMWAIT", Extension: "WAITPKG", Mode: 1, Opcode: []uint8{15, 174}, Prefix: []uint8{242}, Modrm: true, Mod: 3, Reg: 6, Rm: -1, NoRepPrefix: true, Rexw: 1, VexP: -1}, + {Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 28}, Prefix: []uint8{242}, Modrm: true, Mod: -3, Rm: -1, NoRepPrefix: true, VexP: -1}, + {Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 28}, Prefix: []uint8{243}, Modrm: true, Mod: -3, Rm: -1, NoRepPrefix: true, VexP: -1}, + {Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 28}, Prefix: []uint8{102}, Modrm: true, Mod: -3, Rm: -1, NoRepPrefix: true, VexP: -1}, + {Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 28}, Modrm: true, Mod: -3, Reg: 1, Rm: -1, VexP: -1}, + {Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 28}, Modrm: true, Mod: -3, Reg: 2, Rm: -1, VexP: -1}, + {Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 28}, Modrm: true, Mod: -3, Reg: 3, Rm: -1, VexP: -1}, + {Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 28}, Modrm: true, Mod: -3, Reg: 4, Rm: -1, VexP: -1}, + {Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 28}, Modrm: true, Mod: -3, Reg: 5, Rm: -1, VexP: -1}, + {Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 28}, Modrm: true, Mod: -3, Reg: 6, Rm: -1, VexP: -1}, + {Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 28}, Modrm: true, Mod: -3, Reg: 7, Rm: -1, VexP: -1}, + {Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 28}, Modrm: true, Mod: -3, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1}, + {Name: "CLDEMOTE", Extension: "CLDEMOTE", Mode: 15, Opcode: []uint8{15, 28}, Modrm: true, Mod: -3, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1}, + {Name: "ENCLV", Extension: "SGX_ENCLV", Mode: 15, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, NoRepPrefix: true, No66Prefix: true, VexP: -1}, {Name: "VADDPD", Extension: "AVX", Mode: 3, Opcode: []uint8{88}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 1, VexL: -1, VexP: 1}, {Name: "VADDPD", Extension: "AVX", Mode: 3, Opcode: []uint8{88}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 1, VexL: 1, VexP: 1}, {Name: "VADDPS", Extension: "AVX", Mode: 3, Opcode: []uint8{88}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 1, VexL: -1}, @@ -1471,7 +1563,7 @@ var insns = []*Insn{ {Name: "VCMPPS", Extension: "AVX", Mode: 3, Opcode: []uint8{194}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Vex: 196, VexMap: 1, VexL: -1}, {Name: "VCMPPS", Extension: "AVX", Mode: 3, Opcode: []uint8{194}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Vex: 196, VexMap: 1, VexL: 1}, {Name: "VCMPSD", Extension: "AVX", Mode: 3, Opcode: []uint8{194}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Vex: 196, VexMap: 1, VexP: 3}, - {Name: "VCMPSS", Extension: "AVX", Mode: 3, Opcode: []uint8{194}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Vex: 196, VexMap: 1, VexL: -1, VexP: 2}, + {Name: "VCMPSS", Extension: "AVX", Mode: 3, Opcode: []uint8{194}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Vex: 196, VexMap: 1, VexP: 2}, {Name: "VCOMISD", Extension: "AVX", Mode: 3, Opcode: []uint8{47}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 1, VexNoR: true, VexP: 1}, {Name: "VCOMISS", Extension: "AVX", Mode: 3, Opcode: []uint8{47}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 1, VexNoR: true}, {Name: "VCVTDQ2PD", Extension: "AVX", Mode: 3, Opcode: []uint8{230}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 1, VexL: -1, VexNoR: true, VexP: 2}, @@ -1490,18 +1582,18 @@ var insns = []*Insn{ {Name: "VCVTTPS2DQ", Extension: "AVX", Mode: 3, Opcode: []uint8{91}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 1, VexL: 1, VexNoR: true, VexP: 2}, {Name: "VCVTPS2PD", Extension: "AVX", Mode: 3, Opcode: []uint8{90}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 1, VexL: -1, VexNoR: true}, {Name: "VCVTPS2PD", Extension: "AVX", Mode: 3, Opcode: []uint8{90}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 1, VexL: 1, VexNoR: true}, - {Name: "VCVTSD2SI", Extension: "AVX", Mode: 2, Opcode: []uint8{45}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 1, VexL: -1, VexNoR: true, VexP: 3}, - {Name: "VCVTSD2SI", Extension: "AVX", Mode: 1, Opcode: []uint8{45}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 1, VexL: -1, VexNoR: true, VexP: 3}, - {Name: "VCVTSD2SI", Extension: "AVX", Mode: 1, Opcode: []uint8{45}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 1, VexL: -1, VexNoR: true, VexP: 3}, - {Name: "VCVTTSD2SI", Extension: "AVX", Mode: 2, Opcode: []uint8{44}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 1, VexL: -1, VexNoR: true, VexP: 3}, - {Name: "VCVTTSD2SI", Extension: "AVX", Mode: 1, Opcode: []uint8{44}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 1, VexL: -1, VexNoR: true, VexP: 3}, - {Name: "VCVTTSD2SI", Extension: "AVX", Mode: 1, Opcode: []uint8{44}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 1, VexL: -1, VexNoR: true, VexP: 3}, - {Name: "VCVTSS2SI", Extension: "AVX", Mode: 2, Opcode: []uint8{45}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 1, VexL: -1, VexNoR: true, VexP: 2}, - {Name: "VCVTSS2SI", Extension: "AVX", Mode: 1, Opcode: []uint8{45}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 1, VexL: -1, VexNoR: true, VexP: 2}, - {Name: "VCVTSS2SI", Extension: "AVX", Mode: 1, Opcode: []uint8{45}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 1, VexL: -1, VexNoR: true, VexP: 2}, - {Name: "VCVTTSS2SI", Extension: "AVX", Mode: 2, Opcode: []uint8{44}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 1, VexL: -1, VexNoR: true, VexP: 2}, - {Name: "VCVTTSS2SI", Extension: "AVX", Mode: 1, Opcode: []uint8{44}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 1, VexL: -1, VexNoR: true, VexP: 2}, - {Name: "VCVTTSS2SI", Extension: "AVX", Mode: 1, Opcode: []uint8{44}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 1, VexL: -1, VexNoR: true, VexP: 2}, + {Name: "VCVTSD2SI", Extension: "AVX", Mode: 2, Opcode: []uint8{45}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 1, VexNoR: true, VexP: 3}, + {Name: "VCVTSD2SI", Extension: "AVX", Mode: 1, Opcode: []uint8{45}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 1, VexNoR: true, VexP: 3}, + {Name: "VCVTSD2SI", Extension: "AVX", Mode: 1, Opcode: []uint8{45}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 1, VexNoR: true, VexP: 3}, + {Name: "VCVTTSD2SI", Extension: "AVX", Mode: 2, Opcode: []uint8{44}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 1, VexNoR: true, VexP: 3}, + {Name: "VCVTTSD2SI", Extension: "AVX", Mode: 1, Opcode: []uint8{44}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 1, VexNoR: true, VexP: 3}, + {Name: "VCVTTSD2SI", Extension: "AVX", Mode: 1, Opcode: []uint8{44}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 1, VexNoR: true, VexP: 3}, + {Name: "VCVTSS2SI", Extension: "AVX", Mode: 2, Opcode: []uint8{45}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 1, VexNoR: true, VexP: 2}, + {Name: "VCVTSS2SI", Extension: "AVX", Mode: 1, Opcode: []uint8{45}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 1, VexNoR: true, VexP: 2}, + {Name: "VCVTSS2SI", Extension: "AVX", Mode: 1, Opcode: []uint8{45}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 1, VexNoR: true, VexP: 2}, + {Name: "VCVTTSS2SI", Extension: "AVX", Mode: 2, Opcode: []uint8{44}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 1, VexNoR: true, VexP: 2}, + {Name: "VCVTTSS2SI", Extension: "AVX", Mode: 1, Opcode: []uint8{44}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 1, VexNoR: true, VexP: 2}, + {Name: "VCVTTSS2SI", Extension: "AVX", Mode: 1, Opcode: []uint8{44}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 1, VexNoR: true, VexP: 2}, {Name: "VCVTSD2SS", Extension: "AVX", Mode: 3, Opcode: []uint8{90}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 1, VexP: 3}, {Name: "VCVTSI2SD", Extension: "AVX", Mode: 2, Opcode: []uint8{42}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 1, VexP: 3}, {Name: "VCVTSI2SD", Extension: "AVX", Mode: 1, Opcode: []uint8{42}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 1, VexP: 3}, @@ -1805,24 +1897,23 @@ var insns = []*Insn{ {Name: "VPEXTRW", Extension: "AVX", Mode: 3, Opcode: []uint8{21}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Vex: 196, VexMap: 3, VexL: -1, VexNoR: true, VexP: 1}, {Name: "VPEXTRW", Extension: "AVX", Mode: 3, Opcode: []uint8{197}, Modrm: true, Mod: 3, Reg: -1, Rm: -1, Imm: 1, Vex: 196, VexMap: 1, VexL: -1, VexNoR: true, VexP: 1}, {Name: "VPEXTRQ", Extension: "AVX", Mode: 1, Opcode: []uint8{22}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: 1, Vex: 196, VexMap: 3, VexL: -1, VexNoR: true, VexP: 1}, - {Name: "VPEXTRD", Extension: "AVX", Mode: 3, Opcode: []uint8{22}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: -1, Vex: 196, VexMap: 3, VexL: -1, VexNoR: true, VexP: 1}, + {Name: "VPEXTRD", Extension: "AVX", Mode: 1, Opcode: []uint8{22}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: -1, Vex: 196, VexMap: 3, VexL: -1, VexNoR: true, VexP: 1}, + {Name: "VPEXTRD", Extension: "AVX", Mode: 2, Opcode: []uint8{22}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Vex: 196, VexMap: 3, VexL: -1, VexNoR: true, VexP: 1}, {Name: "VPINSRB", Extension: "AVX", Mode: 3, Opcode: []uint8{32}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Vex: 196, VexMap: 3, VexL: -1, VexP: 1}, {Name: "VPINSRW", Extension: "AVX", Mode: 3, Opcode: []uint8{196}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Vex: 196, VexMap: 1, VexL: -1, VexP: 1}, - {Name: "VPINSRD", Extension: "AVX", Mode: 3, Opcode: []uint8{34}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: -1, Vex: 196, VexMap: 3, VexL: -1, VexP: 1}, + {Name: "VPINSRD", Extension: "AVX", Mode: 1, Opcode: []uint8{34}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: -1, Vex: 196, VexMap: 3, VexL: -1, VexP: 1}, + {Name: "VPINSRD", Extension: "AVX", Mode: 2, Opcode: []uint8{34}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Vex: 196, VexMap: 3, VexL: -1, VexP: 1}, {Name: "VPINSRQ", Extension: "AVX", Mode: 1, Opcode: []uint8{34}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: 1, Vex: 196, VexMap: 3, VexL: -1, VexP: 1}, {Name: "VPCMPESTRI", Extension: "AVX", Mode: 2, Opcode: []uint8{97}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Vex: 196, VexMap: 3, VexL: -1, VexNoR: true, VexP: 1}, - {Name: "VPCMPESTRI", Extension: "AVX", Mode: 1, Opcode: []uint8{97}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: -1, Vex: 196, VexMap: 3, VexL: -1, VexNoR: true, VexP: 1}, - {Name: "VPCMPESTRI", Extension: "AVX", Mode: 1, Opcode: []uint8{97}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: 1, Vex: 196, VexMap: 3, VexL: -1, VexNoR: true, VexP: 1}, + {Name: "VPCMPESTRI", Extension: "AVX", Mode: 1, Opcode: []uint8{97}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Vex: 196, VexMap: 3, VexL: -1, VexNoR: true, VexP: 1}, {Name: "VPCMPISTRI", Extension: "AVX", Mode: 2, Opcode: []uint8{99}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Vex: 196, VexMap: 3, VexL: -1, VexNoR: true, VexP: 1}, - {Name: "VPCMPISTRI", Extension: "AVX", Mode: 1, Opcode: []uint8{99}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: -1, Vex: 196, VexMap: 3, VexL: -1, VexNoR: true, VexP: 1}, - {Name: "VPCMPISTRI", Extension: "AVX", Mode: 1, Opcode: []uint8{99}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: 1, Vex: 196, VexMap: 3, VexL: -1, VexNoR: true, VexP: 1}, + {Name: "VPCMPISTRI", Extension: "AVX", Mode: 1, Opcode: []uint8{99}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Vex: 196, VexMap: 3, VexL: -1, VexNoR: true, VexP: 1}, {Name: "VPCMPESTRM", Extension: "AVX", Mode: 2, Opcode: []uint8{96}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Vex: 196, VexMap: 3, VexL: -1, VexNoR: true, VexP: 1}, - {Name: "VPCMPESTRM", Extension: "AVX", Mode: 1, Opcode: []uint8{96}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: -1, Vex: 196, VexMap: 3, VexL: -1, VexNoR: true, VexP: 1}, - {Name: "VPCMPESTRM", Extension: "AVX", Mode: 1, Opcode: []uint8{96}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: 1, Vex: 196, VexMap: 3, VexL: -1, VexNoR: true, VexP: 1}, + {Name: "VPCMPESTRM", Extension: "AVX", Mode: 1, Opcode: []uint8{96}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Vex: 196, VexMap: 3, VexL: -1, VexNoR: true, VexP: 1}, {Name: "VPCMPISTRM", Extension: "AVX", Mode: 3, Opcode: []uint8{98}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Vex: 196, VexMap: 3, VexL: -1, VexNoR: true, VexP: 1}, {Name: "VMASKMOVDQU", Extension: "AVX", Mode: 3, Opcode: []uint8{247}, Modrm: true, Mod: 3, Reg: -1, Rm: -1, Vex: 196, VexMap: 1, VexL: -1, VexNoR: true, VexP: 1}, - {Name: "VLDMXCSR", Extension: "AVX", Mode: 3, Opcode: []uint8{174}, Modrm: true, Mod: -3, Reg: 2, Rm: -1, NoRepPrefix: true, No66Prefix: true, Vex: 196, VexMap: 1, VexL: -1, VexNoR: true}, - {Name: "VSTMXCSR", Extension: "AVX", Mode: 3, Opcode: []uint8{174}, Modrm: true, Mod: -3, Reg: 3, Rm: -1, NoRepPrefix: true, No66Prefix: true, Vex: 196, VexMap: 1, VexL: -1, VexNoR: true}, + {Name: "VLDMXCSR", Extension: "AVX", Mode: 3, Opcode: []uint8{174}, Modrm: true, Mod: -3, Reg: 2, Rm: -1, Vex: 196, VexMap: 1, VexL: -1, VexNoR: true}, + {Name: "VSTMXCSR", Extension: "AVX", Mode: 3, Opcode: []uint8{174}, Modrm: true, Mod: -3, Reg: 3, Rm: -1, Vex: 196, VexMap: 1, VexL: -1, VexNoR: true}, {Name: "VPBLENDVB", Extension: "AVX", Mode: 3, Opcode: []uint8{76}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: -1, Vex: 196, VexMap: 3, VexL: -1, VexP: 1}, {Name: "VBLENDVPD", Extension: "AVX", Mode: 3, Opcode: []uint8{75}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: -1, Vex: 196, VexMap: 3, VexL: -1, VexP: 1}, {Name: "VBLENDVPD", Extension: "AVX", Mode: 3, Opcode: []uint8{75}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: -1, Vex: 196, VexMap: 3, VexL: 1, VexP: 1}, @@ -1846,6 +1937,102 @@ var insns = []*Insn{ {Name: "VCVTPH2PS", Extension: "F16C", Mode: 3, Opcode: []uint8{19}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexNoR: true, VexP: 1}, {Name: "VCVTPS2PH", Extension: "F16C", Mode: 3, Opcode: []uint8{29}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: -1, Vex: 196, VexMap: 3, VexL: -1, VexNoR: true, VexP: 1}, {Name: "VCVTPS2PH", Extension: "F16C", Mode: 3, Opcode: []uint8{29}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: -1, Vex: 196, VexMap: 3, VexL: 1, VexNoR: true, VexP: 1}, + {Name: "VFMADD132PD", Extension: "FMA", Mode: 3, Opcode: []uint8{152}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, + {Name: "VFMADD132PD", Extension: "FMA", Mode: 3, Opcode: []uint8{152}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, + {Name: "VFMADD132PS", Extension: "FMA", Mode: 3, Opcode: []uint8{152}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, + {Name: "VFMADD132PS", Extension: "FMA", Mode: 3, Opcode: []uint8{152}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, + {Name: "VFMADD132SD", Extension: "FMA", Mode: 3, Opcode: []uint8{153}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexP: 1}, + {Name: "VFMADD132SS", Extension: "FMA", Mode: 3, Opcode: []uint8{153}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexP: 1}, + {Name: "VFMADD213PD", Extension: "FMA", Mode: 3, Opcode: []uint8{168}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, + {Name: "VFMADD213PD", Extension: "FMA", Mode: 3, Opcode: []uint8{168}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, + {Name: "VFMADD213PS", Extension: "FMA", Mode: 3, Opcode: []uint8{168}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, + {Name: "VFMADD213PS", Extension: "FMA", Mode: 3, Opcode: []uint8{168}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, + {Name: "VFMADD213SD", Extension: "FMA", Mode: 3, Opcode: []uint8{169}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexP: 1}, + {Name: "VFMADD213SS", Extension: "FMA", Mode: 3, Opcode: []uint8{169}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexP: 1}, + {Name: "VFMADD231PD", Extension: "FMA", Mode: 3, Opcode: []uint8{184}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, + {Name: "VFMADD231PD", Extension: "FMA", Mode: 3, Opcode: []uint8{184}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, + {Name: "VFMADD231PS", Extension: "FMA", Mode: 3, Opcode: []uint8{184}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, + {Name: "VFMADD231PS", Extension: "FMA", Mode: 3, Opcode: []uint8{184}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, + {Name: "VFMADD231SD", Extension: "FMA", Mode: 3, Opcode: []uint8{185}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexP: 1}, + {Name: "VFMADD231SS", Extension: "FMA", Mode: 3, Opcode: []uint8{185}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexP: 1}, + {Name: "VFMADDSUB132PD", Extension: "FMA", Mode: 3, Opcode: []uint8{150}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, + {Name: "VFMADDSUB132PD", Extension: "FMA", Mode: 3, Opcode: []uint8{150}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, + {Name: "VFMADDSUB213PD", Extension: "FMA", Mode: 3, Opcode: []uint8{166}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, + {Name: "VFMADDSUB213PD", Extension: "FMA", Mode: 3, Opcode: []uint8{166}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, + {Name: "VFMADDSUB231PD", Extension: "FMA", Mode: 3, Opcode: []uint8{182}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, + {Name: "VFMADDSUB231PD", Extension: "FMA", Mode: 3, Opcode: []uint8{182}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, + {Name: "VFMADDSUB132PS", Extension: "FMA", Mode: 3, Opcode: []uint8{150}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, + {Name: "VFMADDSUB132PS", Extension: "FMA", Mode: 3, Opcode: []uint8{150}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, + {Name: "VFMADDSUB213PS", Extension: "FMA", Mode: 3, Opcode: []uint8{166}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, + {Name: "VFMADDSUB213PS", Extension: "FMA", Mode: 3, Opcode: []uint8{166}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, + {Name: "VFMADDSUB231PS", Extension: "FMA", Mode: 3, Opcode: []uint8{182}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, + {Name: "VFMADDSUB231PS", Extension: "FMA", Mode: 3, Opcode: []uint8{182}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, + {Name: "VFMSUBADD132PD", Extension: "FMA", Mode: 3, Opcode: []uint8{151}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, + {Name: "VFMSUBADD132PD", Extension: "FMA", Mode: 3, Opcode: []uint8{151}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, + {Name: "VFMSUBADD213PD", Extension: "FMA", Mode: 3, Opcode: []uint8{167}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, + {Name: "VFMSUBADD213PD", Extension: "FMA", Mode: 3, Opcode: []uint8{167}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, + {Name: "VFMSUBADD231PD", Extension: "FMA", Mode: 3, Opcode: []uint8{183}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, + {Name: "VFMSUBADD231PD", Extension: "FMA", Mode: 3, Opcode: []uint8{183}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, + {Name: "VFMSUBADD132PS", Extension: "FMA", Mode: 3, Opcode: []uint8{151}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, + {Name: "VFMSUBADD132PS", Extension: "FMA", Mode: 3, Opcode: []uint8{151}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, + {Name: "VFMSUBADD213PS", Extension: "FMA", Mode: 3, Opcode: []uint8{167}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, + {Name: "VFMSUBADD213PS", Extension: "FMA", Mode: 3, Opcode: []uint8{167}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, + {Name: "VFMSUBADD231PS", Extension: "FMA", Mode: 3, Opcode: []uint8{183}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, + {Name: "VFMSUBADD231PS", Extension: "FMA", Mode: 3, Opcode: []uint8{183}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, + {Name: "VFMSUB132PD", Extension: "FMA", Mode: 3, Opcode: []uint8{154}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, + {Name: "VFMSUB132PD", Extension: "FMA", Mode: 3, Opcode: []uint8{154}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, + {Name: "VFMSUB132PS", Extension: "FMA", Mode: 3, Opcode: []uint8{154}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, + {Name: "VFMSUB132PS", Extension: "FMA", Mode: 3, Opcode: []uint8{154}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, + {Name: "VFMSUB132SD", Extension: "FMA", Mode: 3, Opcode: []uint8{155}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexP: 1}, + {Name: "VFMSUB132SS", Extension: "FMA", Mode: 3, Opcode: []uint8{155}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexP: 1}, + {Name: "VFMSUB213PD", Extension: "FMA", Mode: 3, Opcode: []uint8{170}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, + {Name: "VFMSUB213PD", Extension: "FMA", Mode: 3, Opcode: []uint8{170}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, + {Name: "VFMSUB213PS", Extension: "FMA", Mode: 3, Opcode: []uint8{170}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, + {Name: "VFMSUB213PS", Extension: "FMA", Mode: 3, Opcode: []uint8{170}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, + {Name: "VFMSUB213SD", Extension: "FMA", Mode: 3, Opcode: []uint8{171}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexP: 1}, + {Name: "VFMSUB213SS", Extension: "FMA", Mode: 3, Opcode: []uint8{171}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexP: 1}, + {Name: "VFMSUB231PD", Extension: "FMA", Mode: 3, Opcode: []uint8{186}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, + {Name: "VFMSUB231PD", Extension: "FMA", Mode: 3, Opcode: []uint8{186}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, + {Name: "VFMSUB231PS", Extension: "FMA", Mode: 3, Opcode: []uint8{186}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, + {Name: "VFMSUB231PS", Extension: "FMA", Mode: 3, Opcode: []uint8{186}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, + {Name: "VFMSUB231SD", Extension: "FMA", Mode: 3, Opcode: []uint8{187}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexP: 1}, + {Name: "VFMSUB231SS", Extension: "FMA", Mode: 3, Opcode: []uint8{187}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexP: 1}, + {Name: "VFNMADD132PD", Extension: "FMA", Mode: 3, Opcode: []uint8{156}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, + {Name: "VFNMADD132PD", Extension: "FMA", Mode: 3, Opcode: []uint8{156}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, + {Name: "VFNMADD132PS", Extension: "FMA", Mode: 3, Opcode: []uint8{156}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, + {Name: "VFNMADD132PS", Extension: "FMA", Mode: 3, Opcode: []uint8{156}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, + {Name: "VFNMADD132SD", Extension: "FMA", Mode: 3, Opcode: []uint8{157}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexP: 1}, + {Name: "VFNMADD132SS", Extension: "FMA", Mode: 3, Opcode: []uint8{157}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexP: 1}, + {Name: "VFNMADD213PD", Extension: "FMA", Mode: 3, Opcode: []uint8{172}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, + {Name: "VFNMADD213PD", Extension: "FMA", Mode: 3, Opcode: []uint8{172}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, + {Name: "VFNMADD213PS", Extension: "FMA", Mode: 3, Opcode: []uint8{172}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, + {Name: "VFNMADD213PS", Extension: "FMA", Mode: 3, Opcode: []uint8{172}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, + {Name: "VFNMADD213SD", Extension: "FMA", Mode: 3, Opcode: []uint8{173}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexP: 1}, + {Name: "VFNMADD213SS", Extension: "FMA", Mode: 3, Opcode: []uint8{173}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexP: 1}, + {Name: "VFNMADD231PD", Extension: "FMA", Mode: 3, Opcode: []uint8{188}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, + {Name: "VFNMADD231PD", Extension: "FMA", Mode: 3, Opcode: []uint8{188}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, + {Name: "VFNMADD231PS", Extension: "FMA", Mode: 3, Opcode: []uint8{188}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, + {Name: "VFNMADD231PS", Extension: "FMA", Mode: 3, Opcode: []uint8{188}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, + {Name: "VFNMADD231SD", Extension: "FMA", Mode: 3, Opcode: []uint8{189}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexP: 1}, + {Name: "VFNMADD231SS", Extension: "FMA", Mode: 3, Opcode: []uint8{189}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexP: 1}, + {Name: "VFNMSUB132PD", Extension: "FMA", Mode: 3, Opcode: []uint8{158}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, + {Name: "VFNMSUB132PD", Extension: "FMA", Mode: 3, Opcode: []uint8{158}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, + {Name: "VFNMSUB132PS", Extension: "FMA", Mode: 3, Opcode: []uint8{158}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, + {Name: "VFNMSUB132PS", Extension: "FMA", Mode: 3, Opcode: []uint8{158}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, + {Name: "VFNMSUB132SD", Extension: "FMA", Mode: 3, Opcode: []uint8{159}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexP: 1}, + {Name: "VFNMSUB132SS", Extension: "FMA", Mode: 3, Opcode: []uint8{159}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexP: 1}, + {Name: "VFNMSUB213PD", Extension: "FMA", Mode: 3, Opcode: []uint8{174}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, + {Name: "VFNMSUB213PD", Extension: "FMA", Mode: 3, Opcode: []uint8{174}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, + {Name: "VFNMSUB213PS", Extension: "FMA", Mode: 3, Opcode: []uint8{174}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, + {Name: "VFNMSUB213PS", Extension: "FMA", Mode: 3, Opcode: []uint8{174}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, + {Name: "VFNMSUB213SD", Extension: "FMA", Mode: 3, Opcode: []uint8{175}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexP: 1}, + {Name: "VFNMSUB213SS", Extension: "FMA", Mode: 3, Opcode: []uint8{175}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexP: 1}, + {Name: "VFNMSUB231PD", Extension: "FMA", Mode: 3, Opcode: []uint8{190}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, + {Name: "VFNMSUB231PD", Extension: "FMA", Mode: 3, Opcode: []uint8{190}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, + {Name: "VFNMSUB231PS", Extension: "FMA", Mode: 3, Opcode: []uint8{190}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, + {Name: "VFNMSUB231PS", Extension: "FMA", Mode: 3, Opcode: []uint8{190}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, + {Name: "VFNMSUB231SD", Extension: "FMA", Mode: 3, Opcode: []uint8{191}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexP: 1}, + {Name: "VFNMSUB231SS", Extension: "FMA", Mode: 3, Opcode: []uint8{191}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexP: 1}, {Name: "VGATHERDPD", Extension: "AVX2GATHER", Mode: 3, Opcode: []uint8{146}, Modrm: true, Mod: -3, Reg: -1, Rm: 4, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1, Avx2Gather: true}, {Name: "VGATHERDPD", Extension: "AVX2GATHER", Mode: 3, Opcode: []uint8{146}, Modrm: true, Mod: -3, Reg: -1, Rm: 4, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1, Avx2Gather: true}, {Name: "VGATHERDPS", Extension: "AVX2GATHER", Mode: 3, Opcode: []uint8{146}, Modrm: true, Mod: -3, Reg: -1, Rm: 4, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1, Avx2Gather: true}, @@ -1865,7 +2052,6 @@ var insns = []*Insn{ {Name: "VPABSB", Extension: "AVX2", Mode: 3, Opcode: []uint8{28}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 2, VexL: 1, VexNoR: true, VexP: 1}, {Name: "VPABSW", Extension: "AVX2", Mode: 3, Opcode: []uint8{29}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 2, VexL: 1, VexNoR: true, VexP: 1}, {Name: "VPABSD", Extension: "AVX2", Mode: 3, Opcode: []uint8{30}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 2, VexL: 1, VexNoR: true, VexP: 1}, - {Name: "VPHMINPOSUW", Extension: "AVX2", Mode: 3, Opcode: []uint8{65}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 2, VexL: 1, VexNoR: true, VexP: 1}, {Name: "VPACKSSWB", Extension: "AVX2", Mode: 3, Opcode: []uint8{99}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 1, VexL: 1, VexP: 1}, {Name: "VPACKSSDW", Extension: "AVX2", Mode: 3, Opcode: []uint8{107}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 1, VexL: 1, VexP: 1}, {Name: "VPACKUSWB", Extension: "AVX2", Mode: 3, Opcode: []uint8{103}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 1, VexL: 1, VexP: 1}, @@ -2007,12 +2193,17 @@ var insns = []*Insn{ {Name: "VBROADCASTSS", Extension: "AVX2", Mode: 3, Opcode: []uint8{24}, Modrm: true, Mod: 3, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexNoR: true, VexP: 1}, {Name: "VBROADCASTSD", Extension: "AVX2", Mode: 3, Opcode: []uint8{25}, Modrm: true, Mod: 3, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexNoR: true, VexP: 1}, {Name: "VBROADCASTI128", Extension: "AVX2", Mode: 3, Opcode: []uint8{90}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexNoR: true, VexP: 1}, - {Name: "TZCNT", Extension: "BMI1", Mode: 3, Opcode: []uint8{15, 188}, Prefix: []uint8{243}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1}, - {Name: "BSF", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 188}, Prefix: []uint8{243}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1}, - {Name: "INVPCID", Extension: "INVPCID", Mode: 1, Priv: true, Opcode: []uint8{15, 56, 130}, Prefix: []uint8{102}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1}, - {Name: "INVPCID", Extension: "INVPCID", Mode: 2, Priv: true, Opcode: []uint8{15, 56, 130}, Prefix: []uint8{102}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1}, - {Name: "LZCNT", Extension: "LZCNT", Mode: 15, Opcode: []uint8{15, 189}, Prefix: []uint8{243}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1}, - {Name: "BSR", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 189}, Prefix: []uint8{243}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1}, + {Name: "VPSLLVD", Extension: "AVX2", Mode: 3, Opcode: []uint8{71}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, + {Name: "VPSLLVD", Extension: "AVX2", Mode: 3, Opcode: []uint8{71}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, + {Name: "VPSLLVQ", Extension: "AVX2", Mode: 3, Opcode: []uint8{71}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, + {Name: "VPSLLVQ", Extension: "AVX2", Mode: 3, Opcode: []uint8{71}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, + {Name: "VPSRLVD", Extension: "AVX2", Mode: 3, Opcode: []uint8{69}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, + {Name: "VPSRLVD", Extension: "AVX2", Mode: 3, Opcode: []uint8{69}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, + {Name: "VPSRLVQ", Extension: "AVX2", Mode: 3, Opcode: []uint8{69}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, + {Name: "VPSRLVQ", Extension: "AVX2", Mode: 3, Opcode: []uint8{69}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, + {Name: "VPSRAVD", Extension: "AVX2", Mode: 3, Opcode: []uint8{70}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, + {Name: "VPSRAVD", Extension: "AVX2", Mode: 3, Opcode: []uint8{70}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, + {Name: "VMOVNTDQA", Extension: "AVX2", Mode: 3, Opcode: []uint8{42}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, Vex: 196, VexMap: 2, VexL: 1, VexNoR: true, VexP: 1}, {Name: "PDEP", Extension: "BMI2", Mode: 2, Opcode: []uint8{245}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 3}, {Name: "PDEP", Extension: "BMI2", Mode: 1, Opcode: []uint8{245}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 3}, {Name: "PDEP", Extension: "BMI2", Mode: 1, Opcode: []uint8{245}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 3}, @@ -2052,131 +2243,39 @@ var insns = []*Insn{ {Name: "RORX", Extension: "BMI2", Mode: 2, Opcode: []uint8{240}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Vex: 196, VexMap: 3, VexL: -1, VexNoR: true, VexP: 3}, {Name: "RORX", Extension: "BMI2", Mode: 1, Opcode: []uint8{240}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: -1, Vex: 196, VexMap: 3, VexL: -1, VexNoR: true, VexP: 3}, {Name: "RORX", Extension: "BMI2", Mode: 1, Opcode: []uint8{240}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: 1, Vex: 196, VexMap: 3, VexL: -1, VexNoR: true, VexP: 3}, - {Name: "VPSLLVD", Extension: "AVX2", Mode: 3, Opcode: []uint8{71}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, - {Name: "VPSLLVD", Extension: "AVX2", Mode: 3, Opcode: []uint8{71}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, - {Name: "VPSLLVQ", Extension: "AVX2", Mode: 3, Opcode: []uint8{71}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, - {Name: "VPSLLVQ", Extension: "AVX2", Mode: 3, Opcode: []uint8{71}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, - {Name: "VPSRLVD", Extension: "AVX2", Mode: 3, Opcode: []uint8{69}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, - {Name: "VPSRLVD", Extension: "AVX2", Mode: 3, Opcode: []uint8{69}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, - {Name: "VPSRLVQ", Extension: "AVX2", Mode: 3, Opcode: []uint8{69}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, - {Name: "VPSRLVQ", Extension: "AVX2", Mode: 3, Opcode: []uint8{69}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, - {Name: "VPSRAVD", Extension: "AVX2", Mode: 3, Opcode: []uint8{70}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, - {Name: "VPSRAVD", Extension: "AVX2", Mode: 3, Opcode: []uint8{70}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, - {Name: "VMOVNTDQA", Extension: "AVX2", Mode: 3, Opcode: []uint8{42}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, Vex: 196, VexMap: 2, VexL: 1, VexNoR: true, VexP: 1}, + {Name: "TZCNT", Extension: "BMI1", Mode: 3, Opcode: []uint8{15, 188}, Prefix: []uint8{243}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1}, + {Name: "BSF", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 188}, Prefix: []uint8{243}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1}, {Name: "VMFUNC", Extension: "VMFUNC", Mode: 15, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Reg: 2, Rm: 4, NoRepPrefix: true, No66Prefix: true, VexP: -1}, + {Name: "INVPCID", Extension: "INVPCID", Mode: 1, Priv: true, Opcode: []uint8{15, 56, 130}, Prefix: []uint8{102}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1}, + {Name: "INVPCID", Extension: "INVPCID", Mode: 14, Priv: true, Opcode: []uint8{15, 56, 130}, Prefix: []uint8{102}, Modrm: true, Mod: -3, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1}, + {Name: "LZCNT", Extension: "LZCNT", Mode: 15, Opcode: []uint8{15, 189}, Prefix: []uint8{243}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1}, + {Name: "BSR", Extension: "BASE", Mode: 15, Opcode: []uint8{15, 189}, Prefix: []uint8{243}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1}, {Name: "XBEGIN", Extension: "RTM", Mode: 15, Opcode: []uint8{199}, Modrm: true, Mod: 3, Reg: 7, Imm: -1, VexP: -1}, {Name: "XEND", Extension: "RTM", Mode: 15, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Reg: 2, Rm: 5, NoRepPrefix: true, No66Prefix: true, VexP: -1}, {Name: "XABORT", Extension: "RTM", Mode: 15, Opcode: []uint8{198}, Modrm: true, Mod: 3, Reg: 7, Imm: 1, VexP: -1}, {Name: "XTEST", Extension: "RTM", Mode: 15, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Reg: 2, Rm: 6, NoRepPrefix: true, No66Prefix: true, VexP: -1}, - {Name: "VFMADD132PD", Extension: "FMA", Mode: 3, Opcode: []uint8{152}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, - {Name: "VFMADD132PD", Extension: "FMA", Mode: 3, Opcode: []uint8{152}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, - {Name: "VFMADD132PS", Extension: "FMA", Mode: 3, Opcode: []uint8{152}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, - {Name: "VFMADD132PS", Extension: "FMA", Mode: 3, Opcode: []uint8{152}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, - {Name: "VFMADD132SD", Extension: "FMA", Mode: 3, Opcode: []uint8{153}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexP: 1}, - {Name: "VFMADD132SS", Extension: "FMA", Mode: 3, Opcode: []uint8{153}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexP: 1}, - {Name: "VFMADD213PD", Extension: "FMA", Mode: 3, Opcode: []uint8{168}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, - {Name: "VFMADD213PD", Extension: "FMA", Mode: 3, Opcode: []uint8{168}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, - {Name: "VFMADD213PS", Extension: "FMA", Mode: 3, Opcode: []uint8{168}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, - {Name: "VFMADD213PS", Extension: "FMA", Mode: 3, Opcode: []uint8{168}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, - {Name: "VFMADD213SD", Extension: "FMA", Mode: 3, Opcode: []uint8{169}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexP: 1}, - {Name: "VFMADD213SS", Extension: "FMA", Mode: 3, Opcode: []uint8{169}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexP: 1}, - {Name: "VFMADD231PD", Extension: "FMA", Mode: 3, Opcode: []uint8{184}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, - {Name: "VFMADD231PD", Extension: "FMA", Mode: 3, Opcode: []uint8{184}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, - {Name: "VFMADD231PS", Extension: "FMA", Mode: 3, Opcode: []uint8{184}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, - {Name: "VFMADD231PS", Extension: "FMA", Mode: 3, Opcode: []uint8{184}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, - {Name: "VFMADD231SD", Extension: "FMA", Mode: 3, Opcode: []uint8{185}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexP: 1}, - {Name: "VFMADD231SS", Extension: "FMA", Mode: 3, Opcode: []uint8{185}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexP: 1}, - {Name: "VFMADDSUB132PD", Extension: "FMA", Mode: 3, Opcode: []uint8{150}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, - {Name: "VFMADDSUB132PD", Extension: "FMA", Mode: 3, Opcode: []uint8{150}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, - {Name: "VFMADDSUB213PD", Extension: "FMA", Mode: 3, Opcode: []uint8{166}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, - {Name: "VFMADDSUB213PD", Extension: "FMA", Mode: 3, Opcode: []uint8{166}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, - {Name: "VFMADDSUB231PD", Extension: "FMA", Mode: 3, Opcode: []uint8{182}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, - {Name: "VFMADDSUB231PD", Extension: "FMA", Mode: 3, Opcode: []uint8{182}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, - {Name: "VFMADDSUB132PS", Extension: "FMA", Mode: 3, Opcode: []uint8{150}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, - {Name: "VFMADDSUB132PS", Extension: "FMA", Mode: 3, Opcode: []uint8{150}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, - {Name: "VFMADDSUB213PS", Extension: "FMA", Mode: 3, Opcode: []uint8{166}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, - {Name: "VFMADDSUB213PS", Extension: "FMA", Mode: 3, Opcode: []uint8{166}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, - {Name: "VFMADDSUB231PS", Extension: "FMA", Mode: 3, Opcode: []uint8{182}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, - {Name: "VFMADDSUB231PS", Extension: "FMA", Mode: 3, Opcode: []uint8{182}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, - {Name: "VFMSUBADD132PD", Extension: "FMA", Mode: 3, Opcode: []uint8{151}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, - {Name: "VFMSUBADD132PD", Extension: "FMA", Mode: 3, Opcode: []uint8{151}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, - {Name: "VFMSUBADD213PD", Extension: "FMA", Mode: 3, Opcode: []uint8{167}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, - {Name: "VFMSUBADD213PD", Extension: "FMA", Mode: 3, Opcode: []uint8{167}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, - {Name: "VFMSUBADD231PD", Extension: "FMA", Mode: 3, Opcode: []uint8{183}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, - {Name: "VFMSUBADD231PD", Extension: "FMA", Mode: 3, Opcode: []uint8{183}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, - {Name: "VFMSUBADD132PS", Extension: "FMA", Mode: 3, Opcode: []uint8{151}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, - {Name: "VFMSUBADD132PS", Extension: "FMA", Mode: 3, Opcode: []uint8{151}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, - {Name: "VFMSUBADD213PS", Extension: "FMA", Mode: 3, Opcode: []uint8{167}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, - {Name: "VFMSUBADD213PS", Extension: "FMA", Mode: 3, Opcode: []uint8{167}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, - {Name: "VFMSUBADD231PS", Extension: "FMA", Mode: 3, Opcode: []uint8{183}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, - {Name: "VFMSUBADD231PS", Extension: "FMA", Mode: 3, Opcode: []uint8{183}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, - {Name: "VFMSUB132PD", Extension: "FMA", Mode: 3, Opcode: []uint8{154}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, - {Name: "VFMSUB132PD", Extension: "FMA", Mode: 3, Opcode: []uint8{154}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, - {Name: "VFMSUB132PS", Extension: "FMA", Mode: 3, Opcode: []uint8{154}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, - {Name: "VFMSUB132PS", Extension: "FMA", Mode: 3, Opcode: []uint8{154}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, - {Name: "VFMSUB132SD", Extension: "FMA", Mode: 3, Opcode: []uint8{155}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexP: 1}, - {Name: "VFMSUB132SS", Extension: "FMA", Mode: 3, Opcode: []uint8{155}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexP: 1}, - {Name: "VFMSUB213PD", Extension: "FMA", Mode: 3, Opcode: []uint8{170}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, - {Name: "VFMSUB213PD", Extension: "FMA", Mode: 3, Opcode: []uint8{170}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, - {Name: "VFMSUB213PS", Extension: "FMA", Mode: 3, Opcode: []uint8{170}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, - {Name: "VFMSUB213PS", Extension: "FMA", Mode: 3, Opcode: []uint8{170}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, - {Name: "VFMSUB213SD", Extension: "FMA", Mode: 3, Opcode: []uint8{171}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexP: 1}, - {Name: "VFMSUB213SS", Extension: "FMA", Mode: 3, Opcode: []uint8{171}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexP: 1}, - {Name: "VFMSUB231PD", Extension: "FMA", Mode: 3, Opcode: []uint8{186}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, - {Name: "VFMSUB231PD", Extension: "FMA", Mode: 3, Opcode: []uint8{186}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, - {Name: "VFMSUB231PS", Extension: "FMA", Mode: 3, Opcode: []uint8{186}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, - {Name: "VFMSUB231PS", Extension: "FMA", Mode: 3, Opcode: []uint8{186}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, - {Name: "VFMSUB231SD", Extension: "FMA", Mode: 3, Opcode: []uint8{187}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexP: 1}, - {Name: "VFMSUB231SS", Extension: "FMA", Mode: 3, Opcode: []uint8{187}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexP: 1}, - {Name: "VFNMADD132PD", Extension: "FMA", Mode: 3, Opcode: []uint8{156}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, - {Name: "VFNMADD132PD", Extension: "FMA", Mode: 3, Opcode: []uint8{156}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, - {Name: "VFNMADD132PS", Extension: "FMA", Mode: 3, Opcode: []uint8{156}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, - {Name: "VFNMADD132PS", Extension: "FMA", Mode: 3, Opcode: []uint8{156}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, - {Name: "VFNMADD132SD", Extension: "FMA", Mode: 3, Opcode: []uint8{157}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexP: 1}, - {Name: "VFNMADD132SS", Extension: "FMA", Mode: 3, Opcode: []uint8{157}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexP: 1}, - {Name: "VFNMADD213PD", Extension: "FMA", Mode: 3, Opcode: []uint8{172}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, - {Name: "VFNMADD213PD", Extension: "FMA", Mode: 3, Opcode: []uint8{172}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, - {Name: "VFNMADD213PS", Extension: "FMA", Mode: 3, Opcode: []uint8{172}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, - {Name: "VFNMADD213PS", Extension: "FMA", Mode: 3, Opcode: []uint8{172}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, - {Name: "VFNMADD213SD", Extension: "FMA", Mode: 3, Opcode: []uint8{173}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexP: 1}, - {Name: "VFNMADD213SS", Extension: "FMA", Mode: 3, Opcode: []uint8{173}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexP: 1}, - {Name: "VFNMADD231PD", Extension: "FMA", Mode: 3, Opcode: []uint8{188}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, - {Name: "VFNMADD231PD", Extension: "FMA", Mode: 3, Opcode: []uint8{188}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, - {Name: "VFNMADD231PS", Extension: "FMA", Mode: 3, Opcode: []uint8{188}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, - {Name: "VFNMADD231PS", Extension: "FMA", Mode: 3, Opcode: []uint8{188}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, - {Name: "VFNMADD231SD", Extension: "FMA", Mode: 3, Opcode: []uint8{189}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexP: 1}, - {Name: "VFNMADD231SS", Extension: "FMA", Mode: 3, Opcode: []uint8{189}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexP: 1}, - {Name: "VFNMSUB132PD", Extension: "FMA", Mode: 3, Opcode: []uint8{158}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, - {Name: "VFNMSUB132PD", Extension: "FMA", Mode: 3, Opcode: []uint8{158}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, - {Name: "VFNMSUB132PS", Extension: "FMA", Mode: 3, Opcode: []uint8{158}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, - {Name: "VFNMSUB132PS", Extension: "FMA", Mode: 3, Opcode: []uint8{158}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, - {Name: "VFNMSUB132SD", Extension: "FMA", Mode: 3, Opcode: []uint8{159}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexP: 1}, - {Name: "VFNMSUB132SS", Extension: "FMA", Mode: 3, Opcode: []uint8{159}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexP: 1}, - {Name: "VFNMSUB213PD", Extension: "FMA", Mode: 3, Opcode: []uint8{174}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, - {Name: "VFNMSUB213PD", Extension: "FMA", Mode: 3, Opcode: []uint8{174}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, - {Name: "VFNMSUB213PS", Extension: "FMA", Mode: 3, Opcode: []uint8{174}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, - {Name: "VFNMSUB213PS", Extension: "FMA", Mode: 3, Opcode: []uint8{174}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, - {Name: "VFNMSUB213SD", Extension: "FMA", Mode: 3, Opcode: []uint8{175}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexP: 1}, - {Name: "VFNMSUB213SS", Extension: "FMA", Mode: 3, Opcode: []uint8{175}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexP: 1}, - {Name: "VFNMSUB231PD", Extension: "FMA", Mode: 3, Opcode: []uint8{190}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, - {Name: "VFNMSUB231PD", Extension: "FMA", Mode: 3, Opcode: []uint8{190}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, - {Name: "VFNMSUB231PS", Extension: "FMA", Mode: 3, Opcode: []uint8{190}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, - {Name: "VFNMSUB231PS", Extension: "FMA", Mode: 3, Opcode: []uint8{190}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, - {Name: "VFNMSUB231SD", Extension: "FMA", Mode: 3, Opcode: []uint8{191}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: 1, Vex: 196, VexMap: 2, VexP: 1}, - {Name: "VFNMSUB231SS", Extension: "FMA", Mode: 3, Opcode: []uint8{191}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexP: 1}, - {Name: "ADCX", Extension: "BDW", Mode: 15, Opcode: []uint8{15, 56, 246}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, Rexw: -1, VexP: -1}, - {Name: "ADCX", Extension: "BDW", Mode: 15, Opcode: []uint8{15, 56, 246}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, Rexw: 1, VexP: -1}, - {Name: "ADOX", Extension: "BDW", Mode: 15, Opcode: []uint8{15, 56, 246}, Prefix: []uint8{243}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, Rexw: -1, VexP: -1}, - {Name: "ADOX", Extension: "BDW", Mode: 15, Opcode: []uint8{15, 56, 246}, Prefix: []uint8{243}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, Rexw: 1, VexP: -1}, - {Name: "RDSEED", Extension: "RDSEED", Mode: 15, Opcode: []uint8{15, 199}, Modrm: true, Mod: 3, Reg: 7, Rm: -1, NoRepPrefix: true, VexP: -1}, - {Name: "CLAC", Extension: "SMAP", Mode: 15, Priv: true, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Reg: 1, Rm: 2, NoRepPrefix: true, No66Prefix: true, VexP: -1}, - {Name: "STAC", Extension: "SMAP", Mode: 15, Priv: true, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Reg: 1, Rm: 3, NoRepPrefix: true, No66Prefix: true, VexP: -1}, - {Name: "ENCLU", Extension: "SGX", Mode: 15, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Reg: 2, Rm: 7, NoRepPrefix: true, No66Prefix: true, VexP: -1}, - {Name: "ENCLS", Extension: "SGX", Mode: 15, Priv: true, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Reg: 1, Rm: 7, NoRepPrefix: true, No66Prefix: true, VexP: -1}, - {Name: "RDPKRU", Extension: "PKU", Mode: 15, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Reg: 5, Rm: 6, VexP: -1}, - {Name: "WRPKRU", Extension: "PKU", Mode: 15, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Reg: 5, Rm: 7, VexP: -1}, + {Name: "ADCX", Extension: "ADOX_ADCX", Mode: 15, Opcode: []uint8{15, 56, 246}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, Rexw: -1, VexP: -1}, + {Name: "ADCX", Extension: "ADOX_ADCX", Mode: 15, Opcode: []uint8{15, 56, 246}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, Rexw: 1, VexP: -1}, + {Name: "ADOX", Extension: "ADOX_ADCX", Mode: 15, Opcode: []uint8{15, 56, 246}, Prefix: []uint8{243}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, Rexw: -1, VexP: -1}, + {Name: "ADOX", Extension: "ADOX_ADCX", Mode: 15, Opcode: []uint8{15, 56, 246}, Prefix: []uint8{243}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, Rexw: 1, VexP: -1}, + {Name: "RDPKRU", Extension: "PKU", Mode: 15, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Reg: 5, Rm: 6, NoRepPrefix: true, No66Prefix: true, VexP: -1}, + {Name: "WRPKRU", Extension: "PKU", Mode: 15, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Reg: 5, Rm: 7, NoRepPrefix: true, No66Prefix: true, VexP: -1}, {Name: "CLWB", Extension: "CLWB", Mode: 15, Opcode: []uint8{15, 174}, Prefix: []uint8{102}, Modrm: true, Mod: -3, Reg: 6, Rm: -1, NoRepPrefix: true, VexP: -1}, - {Name: "CLFLUSHOPT", Extension: "CLFLUSHOPT", Mode: 15, Opcode: []uint8{15, 174}, Prefix: []uint8{102}, Modrm: true, Mod: -3, Reg: 7, Rm: -1, NoRepPrefix: true, VexP: -1}, - {Name: "PTWRITE", Extension: "PT", Mode: 15, Opcode: []uint8{15, 174}, Prefix: []uint8{243}, Modrm: true, Mod: -1, Reg: 4, Rm: -1, NoRepPrefix: true, No66Prefix: true, VexP: -1}, {Name: "PREFETCHWT1", Extension: "PREFETCHWT1", Mode: 15, Opcode: []uint8{15, 13}, Modrm: true, Mod: -3, Reg: 2, Rm: -1, VexP: -1}, + {Name: "WBNOINVD", Extension: "WBNOINVD", Mode: 15, Priv: true, Opcode: []uint8{15, 9}, Prefix: []uint8{243}, Mod: -100, Reg: -100, Rm: -100, NoRepPrefix: true, VexP: -1}, + {Name: "PCONFIG", Extension: "PCONFIG", Mode: 15, Priv: true, Opcode: []uint8{15, 1}, Modrm: true, Mod: 3, Rm: 5, NoRepPrefix: true, No66Prefix: true, VexP: -1}, + {Name: "GF2P8AFFINEINVQB", Extension: "GFNI", Mode: 15, Opcode: []uint8{15, 58, 207}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, NoRepPrefix: true, VexP: -1}, + {Name: "GF2P8AFFINEQB", Extension: "GFNI", Mode: 15, Opcode: []uint8{15, 58, 206}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, NoRepPrefix: true, VexP: -1}, + {Name: "GF2P8MULB", Extension: "GFNI", Mode: 15, Opcode: []uint8{15, 56, 207}, Prefix: []uint8{102}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, NoRepPrefix: true, VexP: -1}, + {Name: "VGF2P8AFFINEINVQB", Extension: "GFNI", Mode: 15, Opcode: []uint8{207}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: 1, Vex: 196, VexMap: 3, VexL: -1, VexP: 1}, + {Name: "VGF2P8AFFINEINVQB", Extension: "GFNI", Mode: 15, Opcode: []uint8{207}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: 1, Vex: 196, VexMap: 3, VexL: 1, VexP: 1}, + {Name: "VGF2P8AFFINEQB", Extension: "GFNI", Mode: 15, Opcode: []uint8{206}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: 1, Vex: 196, VexMap: 3, VexL: -1, VexP: 1}, + {Name: "VGF2P8AFFINEQB", Extension: "GFNI", Mode: 15, Opcode: []uint8{206}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Rexw: 1, Vex: 196, VexMap: 3, VexL: 1, VexP: 1}, + {Name: "VGF2P8MULB", Extension: "GFNI", Mode: 15, Opcode: []uint8{207}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: -1, VexP: 1}, + {Name: "VGF2P8MULB", Extension: "GFNI", Mode: 15, Opcode: []uint8{207}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Rexw: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, + {Name: "VAESDEC", Extension: "VAES", Mode: 15, Opcode: []uint8{222}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, + {Name: "VAESDECLAST", Extension: "VAES", Mode: 15, Opcode: []uint8{223}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, + {Name: "VAESENC", Extension: "VAES", Mode: 15, Opcode: []uint8{220}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, + {Name: "VAESENCLAST", Extension: "VAES", Mode: 15, Opcode: []uint8{221}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Vex: 196, VexMap: 2, VexL: 1, VexP: 1}, + {Name: "VPCLMULQDQ", Extension: "VPCLMULQDQ", Mode: 15, Opcode: []uint8{68}, Modrm: true, Mod: -1, Reg: -1, Rm: -1, Imm: 1, Vex: 196, VexMap: 3, VexL: 1, VexP: 1}, } -- cgit mrf-deployment