From 3e755bb1827a63c161ea1c17dadbe08cbd2fb019 Mon Sep 17 00:00:00 2001 From: Alexey Kardashevskiy Date: Mon, 25 Oct 2021 20:24:04 +1100 Subject: pkg/ifuzz/powerpc: correct instructions The existing instruction list is generated by a script which parsed the output of pdftotext which produced less than a perfect result. There is ongoing effort to have the instruction set specification in a machine readable format (latex) which this uses to fix errors. As the new spec is a newer PowerISA 3.1 (POWER10) which removed transactional memory instructions and added some new instructions, this change is reflected here. This fixes randomization of paired paramemers (pair of registers for quadword instructions) to not generate odd (==incorrect) numbers. This includes the new conversion script. Signed-off-by: Alexey Kardashevskiy --- pkg/ifuzz/powerpc/powerpc.go | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'pkg/ifuzz/powerpc/powerpc.go') diff --git a/pkg/ifuzz/powerpc/powerpc.go b/pkg/ifuzz/powerpc/powerpc.go index e6f58642b..83c948815 100644 --- a/pkg/ifuzz/powerpc/powerpc.go +++ b/pkg/ifuzz/powerpc/powerpc.go @@ -103,6 +103,10 @@ func (insn Insn) encodeOpcode(cfg *iset.Config, r *rand.Rand, opcode, mask uint3 } for _, f := range f { field := uint(r.Intn(1 << 16)) + if f.Name == "Ap" || f.Name == "FRAp" || f.Name == "FRBp" || f.Name == "FRTp" || f.Name == "FRSp" { + // These are pairs and have to be even numbers. + field &^= 1 + } insn32 |= encodeBits(field, f.Bits) if len(cfg.MemRegions) != 0 && (f.Name == "RA" || f.Name == "RB" || f.Name == "RS") { val := iset.GenerateInt(cfg, r, 8) -- cgit mrf-deployment