pkg/ifuzz/arm64: add arm64 support

This patch adds instruction generator for ARM64 based on the descriptions
provided as part of Go's arm64asm package. It also implements support for
pseudo-instructions for calling ARM64 hypercalls.

14 files changed, 8766 insertions, 1 deletions

diff --git a/pkg/ifuzz/arm64/arm64.go b/pkg/ifuzz/arm64/arm64.go
new file mode 100644
index 000000000..3b835566f
--- /dev/null
+++ b/pkg/ifuzz/arm64/arm64.go
@@ -0,0 +1,116 @@
+// Copyright 2024 syzkaller project authors. All rights reserved.
+// Use of this source code is governed by Apache 2 LICENSE that can be found in the LICENSE file.
+
+//go:generate bash -c "go run gen/gen.go gen/json/arm64.json | gofmt > generated/insns.go"
+
+// Package arm64 allows to generate and mutate arm64 machine code.
+package arm64
+
+import (
+	"encoding/binary"
+	"fmt"
+	"math/rand"
+
+	"github.com/google/syzkaller/pkg/ifuzz/iset"
+)
+
+type InsnField struct {
+	Name   string
+	Start  uint // Little endian bit order.
+	Length uint
+}
+
+type Insn struct {
+	Name       string
+	OpcodeMask uint32
+	Opcode     uint32
+	Fields     []InsnField
+	AsUInt32   uint32
+	Operands   []uint32
+	Pseudo     bool
+	Priv       bool
+	Generator  func(cfg *iset.Config, r *rand.Rand) []byte // for pseudo instructions
+}
+
+type InsnSet struct {
+	modeInsns iset.ModeInsns
+	Insns     []*Insn
+}
+
+func Register(insns []*Insn) {
+	if len(insns) == 0 {
+		panic("no instructions")
+	}
+	insnset := &InsnSet{
+		Insns: append(insns, pseudo...),
+	}
+	for _, insn := range insnset.Insns {
+		insnset.modeInsns.Add(insn)
+	}
+	iset.Arches[iset.ArchArm64] = insnset
+	templates = insns
+}
+
+func (insnset *InsnSet) GetInsns(mode iset.Mode, typ iset.Type) []iset.Insn {
+	return insnset.modeInsns[mode][typ]
+}
+
+func (insn *Insn) Info() (string, iset.Mode, bool, bool) {
+	return insn.Name, 1 << iset.ModeLong64, insn.Pseudo, insn.Priv
+}
+
+func (insn *Insn) Encode(cfg *iset.Config, r *rand.Rand) []byte {
+	if insn.Pseudo {
+		return insn.Generator(cfg, r)
+	}
+	ret := make([]byte, 4)
+	binary.LittleEndian.PutUint32(ret, insn.AsUInt32)
+	return ret
+}
+
+func (insnset *InsnSet) Decode(mode iset.Mode, text []byte) (int, error) {
+	if len(text) < 4 {
+		return 0, fmt.Errorf("must be at least 4 bytes")
+	}
+	opcode := binary.LittleEndian.Uint32(text[:4])
+	_, err := ParseInsn(opcode)
+	if err != nil {
+		return 0, fmt.Errorf("failed to decode %x", opcode)
+	}
+	return 4, nil
+}
+
+func (insnset *InsnSet) DecodeExt(mode iset.Mode, text []byte) (int, error) {
+	return 0, fmt.Errorf("no external decoder")
+}
+
+var templates []*Insn
+
+func (insn *Insn) initFromValue(val uint32) {
+	operands := []uint32{}
+	for _, field := range insn.Fields {
+		extracted := extractBits(val, field.Start, field.Length)
+		operands = append(operands, extracted)
+	}
+	insn.Operands = operands
+	insn.AsUInt32 = val
+}
+
+func (insn *Insn) matchesValue(val uint32) bool {
+	opcode := val & insn.OpcodeMask
+	return opcode == insn.Opcode
+}
+
+func ParseInsn(val uint32) (Insn, error) {
+	for _, tmpl := range templates {
+		if tmpl.matchesValue(val) {
+			newInsn := *tmpl
+			newInsn.initFromValue(val)
+			return newInsn, nil
+		}
+	}
+	unknown := Insn{
+		Name: "unknown",
+	}
+	return unknown, fmt.Errorf("unrecognized instruction: %08x", val)
+}
diff --git a/pkg/ifuzz/arm64/gen/gen.go b/pkg/ifuzz/arm64/gen/gen.go
new file mode 100644
index 000000000..659fea202
--- /dev/null
+++ b/pkg/ifuzz/arm64/gen/gen.go
@@ -0,0 +1,133 @@
+// Copyright 2024 syzkaller project authors. All rights reserved.
+// Use of this source code is governed by Apache 2 LICENSE that can be found in the LICENSE file.
+
+// gen generates instruction tables (ifuzz_types/insns.go) from ARM64 JSON.
+package main
+
+import (
+	"encoding/json"
+	"fmt"
+	"os"
+	"strconv"
+	"strings"
+
+	"github.com/google/syzkaller/pkg/ifuzz/arm64"
+	"github.com/google/syzkaller/pkg/serializer"
+	"github.com/google/syzkaller/pkg/tool"
+)
+
+func main() {
+	if len(os.Args) != 2 {
+		tool.Failf("usage: gen arm64.json")
+	}
+	jsonStr, err := os.ReadFile(os.Args[1])
+	if err != nil {
+		tool.Failf("failed to open input file: %v", err)
+	}
+	insns := JSONToInsns(jsonStr)
+
+	fmt.Printf(`// Code generated by pkg/ifuzz/gen. DO NOT EDIT.
+
+// go:build !codeanalysis
+
+package generated
+
+import (
+	. "github.com/google/syzkaller/pkg/ifuzz/arm64"
+)
+
+func init() {
+	Register(insns_arm64)
+}
+
+var insns_arm64 = 
+`)
+	serializer.Write(os.Stdout, insns)
+
+	fmt.Fprintf(os.Stderr, "handled %v\n", len(insns))
+}
+
+type insnDesc struct {
+	Name   string
+	Bits   string
+	Arch   string
+	Syntax string
+	Code   string
+	Alias  string
+}
+
+func isPrivateInsn(insn arm64.Insn) bool {
+	switch insn.Name {
+	case "AT", "DC", "IC", "SYS", "SYSL", "TLBI":
+		return true
+	}
+	return false
+}
+
+func JSONToInsns(jsonStr []byte) []*arm64.Insn {
+	var insnDescriptions []insnDesc
+	err := json.Unmarshal(jsonStr, &insnDescriptions)
+	if err != nil {
+		return nil
+	}
+	ret := []*arm64.Insn{}
+	for _, desc := range insnDescriptions {
+		mask := uint32(0)
+		opcode := uint32(0)
+		curBit := uint(31)
+		fields := []arm64.InsnField{}
+		pieces := strings.Split(desc.Bits, "|")
+		for _, piece := range pieces {
+			size := uint(1)
+			pair := strings.Split(piece, ":")
+			var pattern = piece
+			if len(pair) == 2 {
+				size64, err := strconv.ParseUint(pair[1], 10, 0)
+				if err != nil {
+					return nil
+				}
+				size = uint(size64)
+				pattern = pair[0]
+			}
+			updateOpcode := true
+			opPart := uint32(0)
+			maskPart := uint32(0)
+			if pattern[0:1] != "(" {
+				number, err := strconv.ParseUint(pattern, 2, 32)
+				if err != nil {
+					// This is a named region.
+					field := arm64.InsnField{
+						Name:   pattern,
+						Start:  curBit,
+						Length: size,
+					}
+					fields = append(fields, field)
+					updateOpcode = false
+				} else {
+					// This is a binary mask.
+					opPart = uint32(number)
+					maskPart = ((1 << size) - 1)
+				}
+			}
+			opcode <<= size
+			mask <<= size
+			curBit -= size
+			if updateOpcode {
+				opcode |= opPart
+				mask |= maskPart
+			}
+		}
+		templ := arm64.Insn{
+			Name:       desc.Name,
+			OpcodeMask: mask,
+			Opcode:     opcode,
+			Fields:     fields,
+			AsUInt32:   opcode,
+		}
+		templ.Priv = isPrivateInsn(templ)
+		insn := new(arm64.Insn)
+		*insn = templ
+		ret = append(ret, insn)
+	}
+	return ret
+}
diff --git a/pkg/ifuzz/arm64/gen/json/LICENSE b/pkg/ifuzz/arm64/gen/json/LICENSE
new file mode 100644
index 000000000..931520b99
--- /dev/null
+++ b/pkg/ifuzz/arm64/gen/json/LICENSE
@@ -0,0 +1,28 @@
+Copyright (c) 2015 The Go Authors. All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are
+met:
+
+   * Redistributions of source code must retain the above copyright
+notice, this list of conditions and the following disclaimer.
+   * Redistributions in binary form must reproduce the above
+copyright notice, this list of conditions and the following disclaimer
+in the documentation and/or other materials provided with the
+distribution.
+   * Neither the name of Google Inc. nor the names of its
+contributors may be used to endorse or promote products derived from
+this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
diff --git a/pkg/ifuzz/arm64/gen/json/README.md b/pkg/ifuzz/arm64/gen/json/README.md
new file mode 100644
index 000000000..4f44ea79f
--- /dev/null
+++ b/pkg/ifuzz/arm64/gen/json/README.md
@@ -0,0 +1,5 @@
+arm64.json is taken from the Go Language repository:
+https://tip.golang.org/src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/inst.json
+
+Please see the LICENSE file (taken from https://tip.golang.org/src/cmd/vendor/golang.org/x/arch/LICENSE)
+for the relevant copyright notice and disclaimers.
diff --git a/pkg/ifuzz/arm64/gen/json/arm64.json b/pkg/ifuzz/arm64/gen/json/arm64.json
new file mode 100644
index 000000000..2d25c944a
--- /dev/null
+++ b/pkg/ifuzz/arm64/gen/json/arm64.json
@@ -0,0 +1,1219 @@
+[{"Name":"ADC","Bits":"0|0|0|1|1|0|1|0|0|0|0|Rm:5|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ADC <Wd>, <Wn>, <Wm>","Code":"","Alias":""},
+{"Name":"ADC","Bits":"1|0|0|1|1|0|1|0|0|0|0|Rm:5|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ADC <Xd>, <Xn>, <Xm>","Code":"","Alias":""},
+{"Name":"ADCS","Bits":"0|0|1|1|1|0|1|0|0|0|0|Rm:5|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ADCS <Wd>, <Wn>, <Wm>","Code":"","Alias":""},
+{"Name":"ADCS","Bits":"1|0|1|1|1|0|1|0|0|0|0|Rm:5|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ADCS <Xd>, <Xn>, <Xm>","Code":"","Alias":""},
+{"Name":"ADD (extended register)","Bits":"0|0|0|0|1|0|1|1|0|0|1|Rm:5|option:3|imm3:3|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ADD <Wd|WSP>, <Wn|WSP>, <Wm>{, <extend> {#<amount>}}","Code":"","Alias":""},
+{"Name":"ADD (extended register)","Bits":"1|0|0|0|1|0|1|1|0|0|1|Rm:5|option:3|imm3:3|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ADD <Xd|SP>, <Xn|SP>, <R><m>{, <extend> {#<amount>}}","Code":"","Alias":""},
+{"Name":"ADD (immediate)","Bits":"0|0|0|1|0|0|0|1|shift:2|imm12:12|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ADD <Wd|WSP>, <Wn|WSP>, #<imm>{, <shift>}","Code":"","Alias":"This instruction is used by the alias MOV (to/from SP)."},
+{"Name":"ADD (immediate)","Bits":"1|0|0|1|0|0|0|1|shift:2|imm12:12|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ADD <Xd|SP>, <Xn|SP>, #<imm>{, <shift>}","Code":"","Alias":"This instruction is used by the alias MOV (to/from SP)."},
+{"Name":"ADD (shifted register)","Bits":"0|0|0|0|1|0|1|1|shift:2|0|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ADD <Wd>, <Wn>, <Wm>{, <shift> #<amount>}","Code":"","Alias":""},
+{"Name":"ADD (shifted register)","Bits":"1|0|0|0|1|0|1|1|shift:2|0|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ADD <Xd>, <Xn>, <Xm>{, <shift> #<amount>}","Code":"","Alias":""},
+{"Name":"ADDS (extended register)","Bits":"0|0|1|0|1|0|1|1|0|0|1|Rm:5|option:3|imm3:3|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ADDS <Wd>, <Wn|WSP>, <Wm>{, <extend> {#<amount>}}","Code":"","Alias":"This instruction is used by the alias CMN (extended register)."},
+{"Name":"ADDS (extended register)","Bits":"1|0|1|0|1|0|1|1|0|0|1|Rm:5|option:3|imm3:3|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ADDS <Xd>, <Xn|SP>, <R><m>{, <extend> {#<amount>}}","Code":"","Alias":"This instruction is used by the alias CMN (extended register)."},
+{"Name":"ADDS (immediate)","Bits":"0|0|1|1|0|0|0|1|shift:2|imm12:12|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ADDS <Wd>, <Wn|WSP>, #<imm>{, <shift>}","Code":"","Alias":"This instruction is used by the alias CMN (immediate)."},
+{"Name":"ADDS (immediate)","Bits":"1|0|1|1|0|0|0|1|shift:2|imm12:12|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ADDS <Xd>, <Xn|SP>, #<imm>{, <shift>}","Code":"","Alias":"This instruction is used by the alias CMN (immediate)."},
+{"Name":"ADDS (shifted register)","Bits":"0|0|1|0|1|0|1|1|shift:2|0|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ADDS <Wd>, <Wn>, <Wm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is used by the alias CMN (shifted register)."},
+{"Name":"ADDS (shifted register)","Bits":"1|0|1|0|1|0|1|1|shift:2|0|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ADDS <Xd>, <Xn>, <Xm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is used by the alias CMN (shifted register)."},
+{"Name":"ADR","Bits":"0|immlo:2|1|0|0|0|0|immhi:19|Rd:5","Arch":"Literal variant","Syntax":"ADR <Xd>, <label>","Code":"","Alias":""},
+{"Name":"ADRP","Bits":"1|immlo:2|1|0|0|0|0|immhi:19|Rd:5","Arch":"Literal variant","Syntax":"ADRP <Xd>, <label>","Code":"","Alias":""},
+{"Name":"AND (immediate)","Bits":"0|0|0|1|0|0|1|0|0|0|immr:6|imms:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"AND <Wd|WSP>, <Wn>, #<imm>","Code":"","Alias":""},
+{"Name":"AND (immediate)","Bits":"1|0|0|1|0|0|1|0|0|N|immr:6|imms:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"AND <Xd|SP>, <Xn>, #<imm>","Code":"","Alias":""},
+{"Name":"AND (shifted register)","Bits":"0|0|0|0|1|0|1|0|shift:2|0|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"AND <Wd>, <Wn>, <Wm>{, <shift> #<amount>}","Code":"","Alias":""},
+{"Name":"AND (shifted register)","Bits":"1|0|0|0|1|0|1|0|shift:2|0|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"AND <Xd>, <Xn>, <Xm>{, <shift> #<amount>}","Code":"","Alias":""},
+{"Name":"ANDS (immediate)","Bits":"0|1|1|1|0|0|1|0|0|0|immr:6|imms:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ANDS <Wd>, <Wn>, #<imm>","Code":"","Alias":"This instruction is used by the alias TST (immediate)."},
+{"Name":"ANDS (immediate)","Bits":"1|1|1|1|0|0|1|0|0|N|immr:6|imms:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ANDS <Xd>, <Xn>, #<imm>","Code":"","Alias":"This instruction is used by the alias TST (immediate)."},
+{"Name":"ANDS (shifted register)","Bits":"0|1|1|0|1|0|1|0|shift:2|0|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ANDS <Wd>, <Wn>, <Wm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is used by the alias TST (shifted register)."},
+{"Name":"ANDS (shifted register)","Bits":"1|1|1|0|1|0|1|0|shift:2|0|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ANDS <Xd>, <Xn>, <Xm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is used by the alias TST (shifted register)."},
+{"Name":"ASR (register)","Bits":"0|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|1|0|1|0|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ASR <Wd>, <Wn>, <Wm>","Code":"","Alias":"This instruction is an alias of the ASRV instruction."},
+{"Name":"ASR (register)","Bits":"1|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|1|0|1|0|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ASR <Xd>, <Xn>, <Xm>","Code":"","Alias":"This instruction is an alias of the ASRV instruction."},
+{"Name":"ASR (immediate)","Bits":"0|0|0|1|0|0|1|1|0|0|immr:6|011111:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ASR <Wd>, <Wn>, #<shift>","Code":"","Alias":"This instruction is an alias of the SBFM instruction."},
+{"Name":"ASR (immediate)","Bits":"1|0|0|1|0|0|1|1|0|1|immr:6|111111:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ASR <Xd>, <Xn>, #<shift>","Code":"","Alias":"This instruction is an alias of the SBFM instruction."},
+{"Name":"ASRV","Bits":"0|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|1|0|1|0|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ASRV <Wd>, <Wn>, <Wm>","Code":"","Alias":"This instruction is used by the alias ASR (register)."},
+{"Name":"ASRV","Bits":"1|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|1|0|1|0|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ASRV <Xd>, <Xn>, <Xm>","Code":"","Alias":"This instruction is used by the alias ASR (register)."},
+{"Name":"AT","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|1|op1:3|0|1|1|1|CRm:4|op2:3|Rt:5","Arch":"System variant","Syntax":"AT <at_op>, <Xt>","Code":"","Alias":"This instruction is an alias of the SYS instruction."},
+{"Name":"B.cond","Bits":"0|1|0|1|0|1|0|0|imm19:19|0|cond:4","Arch":"19-bit signed PC-relative branch offset variant","Syntax":"B.<cond> <label>","Code":"","Alias":""},
+{"Name":"B","Bits":"0|0|0|1|0|1|imm26:26","Arch":"26-bit signed PC-relative branch offset variant","Syntax":"B <label>","Code":"","Alias":""},
+{"Name":"BFI","Bits":"0|0|1|1|0|0|1|1|0|0|immr:6|imms:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"BFI <Wd>, <Wn>, #<lsb>, #<width>","Code":"","Alias":"This instruction is an alias of the BFM instruction."},
+{"Name":"BFI","Bits":"1|0|1|1|0|0|1|1|0|1|immr:6|imms:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"BFI <Xd>, <Xn>, #<lsb>, #<width>","Code":"","Alias":"This instruction is an alias of the BFM instruction."},
+{"Name":"BFM","Bits":"0|0|1|1|0|0|1|1|0|0|immr:6|imms:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"BFM <Wd>, <Wn>, #<immr>, #<imms>","Code":"","Alias":"This instruction is used by the aliases BFI and BFXIL."},
+{"Name":"BFM","Bits":"1|0|1|1|0|0|1|1|0|1|immr:6|imms:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"BFM <Xd>, <Xn>, #<immr>, #<imms>","Code":"","Alias":"This instruction is used by the aliases BFI and BFXIL."},
+{"Name":"BFXIL","Bits":"0|0|1|1|0|0|1|1|0|0|immr:6|imms:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"BFXIL <Wd>, <Wn>, #<lsb>, #<width>","Code":"","Alias":"This instruction is an alias of the BFM instruction."},
+{"Name":"BFXIL","Bits":"1|0|1|1|0|0|1|1|0|1|immr:6|imms:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"BFXIL <Xd>, <Xn>, #<lsb>, #<width>","Code":"","Alias":"This instruction is an alias of the BFM instruction."},
+{"Name":"BIC (shifted register)","Bits":"0|0|0|0|1|0|1|0|shift:2|1|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"BIC <Wd>, <Wn>, <Wm>{, <shift> #<amount>}","Code":"","Alias":""},
+{"Name":"BIC (shifted register)","Bits":"1|0|0|0|1|0|1|0|shift:2|1|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"BIC <Xd>, <Xn>, <Xm>{, <shift> #<amount>}","Code":"","Alias":""},
+{"Name":"BICS (shifted register)","Bits":"0|1|1|0|1|0|1|0|shift:2|1|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"BICS <Wd>, <Wn>, <Wm>{, <shift> #<amount>}","Code":"","Alias":""},
+{"Name":"BICS (shifted register)","Bits":"1|1|1|0|1|0|1|0|shift:2|1|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"BICS <Xd>, <Xn>, <Xm>{, <shift> #<amount>}","Code":"","Alias":""},
+{"Name":"BL","Bits":"1|0|0|1|0|1|imm26:26","Arch":"26-bit signed PC-relative branch offset variant","Syntax":"BL <label>","Code":"","Alias":""},
+{"Name":"BLR","Bits":"1|1|0|1|0|1|1|0|0|0|1|1|1|1|1|1|0|0|0|0|0|0|Rn:5|0|0|0|0|0","Arch":"Integer variant","Syntax":"BLR <Xn>","Code":"","Alias":""},
+{"Name":"BR","Bits":"1|1|0|1|0|1|1|0|0|0|0|1|1|1|1|1|0|0|0|0|0|0|Rn:5|0|0|0|0|0","Arch":"Integer variant","Syntax":"BR <Xn>","Code":"","Alias":""},
+{"Name":"BRK","Bits":"1|1|0|1|0|1|0|0|0|0|1|imm16:16|0|0|0|0|0","Arch":"System variant","Syntax":"BRK #<imm>","Code":"","Alias":""},
+{"Name":"CBNZ","Bits":"0|0|1|1|0|1|0|1|imm19:19|Rt:5","Arch":"32-bit variant","Syntax":"CBNZ <Wt>, <label>","Code":"","Alias":""},
+{"Name":"CBNZ","Bits":"1|0|1|1|0|1|0|1|imm19:19|Rt:5","Arch":"64-bit variant","Syntax":"CBNZ <Xt>, <label>","Code":"","Alias":""},
+{"Name":"CBZ","Bits":"0|0|1|1|0|1|0|0|imm19:19|Rt:5","Arch":"32-bit variant","Syntax":"CBZ <Wt>, <label>","Code":"","Alias":""},
+{"Name":"CBZ","Bits":"1|0|1|1|0|1|0|0|imm19:19|Rt:5","Arch":"64-bit variant","Syntax":"CBZ <Xt>, <label>","Code":"","Alias":""},
+{"Name":"CCMN (immediate)","Bits":"0|0|1|1|1|0|1|0|0|1|0|imm5:5|cond:4|1|0|Rn:5|0|nzcv:4","Arch":"32-bit variant","Syntax":"CCMN <Wn>, #<imm>, #<nzcv>, <cond>","Code":"","Alias":""},
+{"Name":"CCMN (immediate)","Bits":"1|0|1|1|1|0|1|0|0|1|0|imm5:5|cond:4|1|0|Rn:5|0|nzcv:4","Arch":"64-bit variant","Syntax":"CCMN <Xn>, #<imm>, #<nzcv>, <cond>","Code":"","Alias":""},
+{"Name":"CCMN (register)","Bits":"0|0|1|1|1|0|1|0|0|1|0|Rm:5|cond:4|0|0|Rn:5|0|nzcv:4","Arch":"32-bit variant","Syntax":"CCMN <Wn>, <Wm>, #<nzcv>, <cond>","Code":"","Alias":""},
+{"Name":"CCMN (register)","Bits":"1|0|1|1|1|0|1|0|0|1|0|Rm:5|cond:4|0|0|Rn:5|0|nzcv:4","Arch":"64-bit variant","Syntax":"CCMN <Xn>, <Xm>, #<nzcv>, <cond>","Code":"","Alias":""},
+{"Name":"CCMP (immediate)","Bits":"0|1|1|1|1|0|1|0|0|1|0|imm5:5|cond:4|1|0|Rn:5|0|nzcv:4","Arch":"32-bit variant","Syntax":"CCMP <Wn>, #<imm>, #<nzcv>, <cond>","Code":"","Alias":""},
+{"Name":"CCMP (immediate)","Bits":"1|1|1|1|1|0|1|0|0|1|0|imm5:5|cond:4|1|0|Rn:5|0|nzcv:4","Arch":"64-bit variant","Syntax":"CCMP <Xn>, #<imm>, #<nzcv>, <cond>","Code":"","Alias":""},
+{"Name":"CCMP (register)","Bits":"0|1|1|1|1|0|1|0|0|1|0|Rm:5|cond:4|0|0|Rn:5|0|nzcv:4","Arch":"32-bit variant","Syntax":"CCMP <Wn>, <Wm>, #<nzcv>, <cond>","Code":"","Alias":""},
+{"Name":"CCMP (register)","Bits":"1|1|1|1|1|0|1|0|0|1|0|Rm:5|cond:4|0|0|Rn:5|0|nzcv:4","Arch":"64-bit variant","Syntax":"CCMP <Xn>, <Xm>, #<nzcv>, <cond>","Code":"","Alias":""},
+{"Name":"CINC","Bits":"0|0|0|1|1|0|1|0|1|0|0|Rm:5|cond:4|0|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"CINC <Wd>, <Wn>, <cond>","Code":"","Alias":"This instruction is an alias of the CSINC instruction."},
+{"Name":"CINC","Bits":"1|0|0|1|1|0|1|0|1|0|0|Rm:5|cond:4|0|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"CINC <Xd>, <Xn>, <cond>","Code":"","Alias":"This instruction is an alias of the CSINC instruction."},
+{"Name":"CINV","Bits":"0|1|0|1|1|0|1|0|1|0|0|Rm:5|cond:4|0|0|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"CINV <Wd>, <Wn>, <cond>","Code":"","Alias":"This instruction is an alias of the CSINV instruction."},
+{"Name":"CINV","Bits":"1|1|0|1|1|0|1|0|1|0|0|Rm:5|cond:4|0|0|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"CINV <Xd>, <Xn>, <cond>","Code":"","Alias":"This instruction is an alias of the CSINV instruction."},
+{"Name":"CLREX","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|0|0|1|1|0|0|1|1|CRm:4|0|1|0|1|1|1|1|1","Arch":"System variant","Syntax":"CLREX {#<imm>}","Code":"","Alias":""},
+{"Name":"CLS","Bits":"0|1|0|1|1|0|1|0|1|1|0|0|0|0|0|0|0|0|0|1|0|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"CLS <Wd>, <Wn>","Code":"","Alias":""},
+{"Name":"CLS","Bits":"1|1|0|1|1|0|1|0|1|1|0|0|0|0|0|0|0|0|0|1|0|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"CLS <Xd>, <Xn>","Code":"","Alias":""},
+{"Name":"CLZ","Bits":"0|1|0|1|1|0|1|0|1|1|0|0|0|0|0|0|0|0|0|1|0|0|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"CLZ <Wd>, <Wn>","Code":"","Alias":""},
+{"Name":"CLZ","Bits":"1|1|0|1|1|0|1|0|1|1|0|0|0|0|0|0|0|0|0|1|0|0|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"CLZ <Xd>, <Xn>","Code":"","Alias":""},
+{"Name":"CMN (extended register)","Bits":"0|0|1|0|1|0|1|1|0|0|1|Rm:5|option:3|imm3:3|Rn:5|1|1|1|1|1","Arch":"32-bit variant","Syntax":"CMN <Wn|WSP>, <Wm>{, <extend> {#<amount>}}","Code":"","Alias":"This instruction is an alias of the ADDS (extended register) instruction."},
+{"Name":"CMN (extended register)","Bits":"1|0|1|0|1|0|1|1|0|0|1|Rm:5|option:3|imm3:3|Rn:5|1|1|1|1|1","Arch":"64-bit variant","Syntax":"CMN <Xn|SP>, <R><m>{, <extend> {#<amount>}}","Code":"","Alias":"This instruction is an alias of the ADDS (extended register) instruction."},
+{"Name":"CMN (immediate)","Bits":"0|0|1|1|0|0|0|1|shift:2|imm12:12|Rn:5|1|1|1|1|1","Arch":"32-bit variant","Syntax":"CMN <Wn|WSP>, #<imm>{, <shift>}","Code":"","Alias":"This instruction is an alias of the ADDS (immediate) instruction."},
+{"Name":"CMN (immediate)","Bits":"1|0|1|1|0|0|0|1|shift:2|imm12:12|Rn:5|1|1|1|1|1","Arch":"64-bit variant","Syntax":"CMN <Xn|SP>, #<imm>{, <shift>}","Code":"","Alias":"This instruction is an alias of the ADDS (immediate) instruction."},
+{"Name":"CMN (shifted register)","Bits":"0|0|1|0|1|0|1|1|shift:2|0|Rm:5|imm6:6|Rn:5|1|1|1|1|1","Arch":"32-bit variant","Syntax":"CMN <Wn>, <Wm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is an alias of the ADDS (shifted register) instruction."},
+{"Name":"CMN (shifted register)","Bits":"1|0|1|0|1|0|1|1|shift:2|0|Rm:5|imm6:6|Rn:5|1|1|1|1|1","Arch":"64-bit variant","Syntax":"CMN <Xn>, <Xm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is an alias of the ADDS (shifted register) instruction."},
+{"Name":"CMP (extended register)","Bits":"0|1|1|0|1|0|1|1|0|0|1|Rm:5|option:3|imm3:3|Rn:5|1|1|1|1|1","Arch":"32-bit variant","Syntax":"CMP <Wn|WSP>, <Wm>{, <extend> {#<amount>}}","Code":"","Alias":"This instruction is an alias of the SUBS (extended register) instruction."},
+{"Name":"CMP (extended register)","Bits":"1|1|1|0|1|0|1|1|0|0|1|Rm:5|option:3|imm3:3|Rn:5|1|1|1|1|1","Arch":"64-bit variant","Syntax":"CMP <Xn|SP>, <R><m>{, <extend> {#<amount>}}","Code":"","Alias":"This instruction is an alias of the SUBS (extended register) instruction."},
+{"Name":"CMP (immediate)","Bits":"0|1|1|1|0|0|0|1|shift:2|imm12:12|Rn:5|1|1|1|1|1","Arch":"32-bit variant","Syntax":"CMP <Wn|WSP>, #<imm>{, <shift>}","Code":"","Alias":"This instruction is an alias of the SUBS (immediate) instruction."},
+{"Name":"CMP (immediate)","Bits":"1|1|1|1|0|0|0|1|shift:2|imm12:12|Rn:5|1|1|1|1|1","Arch":"64-bit variant","Syntax":"CMP <Xn|SP>, #<imm>{, <shift>}","Code":"","Alias":"This instruction is an alias of the SUBS (immediate) instruction."},
+{"Name":"CMP (shifted register)","Bits":"0|1|1|0|1|0|1|1|shift:2|0|Rm:5|imm6:6|Rn:5|1|1|1|1|1","Arch":"32-bit variant","Syntax":"CMP <Wn>, <Wm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is an alias of the SUBS (shifted register) instruction."},
+{"Name":"CMP (shifted register)","Bits":"1|1|1|0|1|0|1|1|shift:2|0|Rm:5|imm6:6|Rn:5|1|1|1|1|1","Arch":"64-bit variant","Syntax":"CMP <Xn>, <Xm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is an alias of the SUBS (shifted register) instruction."},
+{"Name":"CNEG","Bits":"0|1|0|1|1|0|1|0|1|0|0|Rm:5|cond:4|0|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"CNEG <Wd>, <Wn>, <cond>","Code":"","Alias":"This instruction is an alias of the CSNEG instruction."},
+{"Name":"CNEG","Bits":"1|1|0|1|1|0|1|0|1|0|0|Rm:5|cond:4|0|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"CNEG <Xd>, <Xn>, <cond>","Code":"","Alias":"This instruction is an alias of the CSNEG instruction."},
+{"Name":"CRC32B, CRC32H, CRC32W, CRC32X","Bits":"0|0|0|1|1|0|1|0|1|1|0|Rm:5|0|1|0|0|00:2|Rn:5|Rd:5","Arch":"CRC32B variant","Syntax":"CRC32B <Wd>, <Wn>, <Wm>","Code":"","Alias":""},
+{"Name":"CRC32B, CRC32H, CRC32W, CRC32X","Bits":"0|0|0|1|1|0|1|0|1|1|0|Rm:5|0|1|0|0|01:2|Rn:5|Rd:5","Arch":"CRC32H variant","Syntax":"CRC32H <Wd>, <Wn>, <Wm>","Code":"","Alias":""},
+{"Name":"CRC32B, CRC32H, CRC32W, CRC32X","Bits":"0|0|0|1|1|0|1|0|1|1|0|Rm:5|0|1|0|0|10:2|Rn:5|Rd:5","Arch":"CRC32W variant","Syntax":"CRC32W <Wd>, <Wn>, <Wm>","Code":"","Alias":""},
+{"Name":"CRC32B, CRC32H, CRC32W, CRC32X","Bits":"1|0|0|1|1|0|1|0|1|1|0|Rm:5|0|1|0|0|11:2|Rn:5|Rd:5","Arch":"CRC32X variant","Syntax":"CRC32X <Wd>, <Wn>, <Xm>","Code":"","Alias":""},
+{"Name":"CRC32CB, CRC32CH, CRC32CW, CRC32CX","Bits":"0|0|0|1|1|0|1|0|1|1|0|Rm:5|0|1|0|1|00:2|Rn:5|Rd:5","Arch":"CRC32CB variant","Syntax":"CRC32CB <Wd>, <Wn>, <Wm>","Code":"","Alias":""},
+{"Name":"CRC32CB, CRC32CH, CRC32CW, CRC32CX","Bits":"0|0|0|1|1|0|1|0|1|1|0|Rm:5|0|1|0|1|01:2|Rn:5|Rd:5","Arch":"CRC32CH variant","Syntax":"CRC32CH <Wd>, <Wn>, <Wm>","Code":"","Alias":""},
+{"Name":"CRC32CB, CRC32CH, CRC32CW, CRC32CX","Bits":"0|0|0|1|1|0|1|0|1|1|0|Rm:5|0|1|0|1|10:2|Rn:5|Rd:5","Arch":"CRC32CW variant","Syntax":"CRC32CW <Wd>, <Wn>, <Wm>","Code":"","Alias":""},
+{"Name":"CRC32CB, CRC32CH, CRC32CW, CRC32CX","Bits":"1|0|0|1|1|0|1|0|1|1|0|Rm:5|0|1|0|1|11:2|Rn:5|Rd:5","Arch":"CRC32CX variant","Syntax":"CRC32CX <Wd>, <Wn>, <Xm>","Code":"","Alias":""},
+{"Name":"CSEL","Bits":"0|0|0|1|1|0|1|0|1|0|0|Rm:5|cond:4|0|0|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"CSEL <Wd>, <Wn>, <Wm>, <cond>","Code":"","Alias":""},
+{"Name":"CSEL","Bits":"1|0|0|1|1|0|1|0|1|0|0|Rm:5|cond:4|0|0|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"CSEL <Xd>, <Xn>, <Xm>, <cond>","Code":"","Alias":""},
+{"Name":"CSET","Bits":"0|0|0|1|1|0|1|0|1|0|0|1|1|1|1|1|cond:4|0|1|1|1|1|1|1|Rd:5","Arch":"32-bit variant","Syntax":"CSET <Wd>, <cond>","Code":"","Alias":"This instruction is an alias of the CSINC instruction."},
+{"Name":"CSET","Bits":"1|0|0|1|1|0|1|0|1|0|0|1|1|1|1|1|cond:4|0|1|1|1|1|1|1|Rd:5","Arch":"64-bit variant","Syntax":"CSET <Xd>, <cond>","Code":"","Alias":"This instruction is an alias of the CSINC instruction."},
+{"Name":"CSETM","Bits":"0|1|0|1|1|0|1|0|1|0|0|1|1|1|1|1|cond:4|0|0|1|1|1|1|1|Rd:5","Arch":"32-bit variant","Syntax":"CSETM <Wd>, <cond>","Code":"","Alias":"This instruction is an alias of the CSINV instruction."},
+{"Name":"CSETM","Bits":"1|1|0|1|1|0|1|0|1|0|0|1|1|1|1|1|cond:4|0|0|1|1|1|1|1|Rd:5","Arch":"64-bit variant","Syntax":"CSETM <Xd>, <cond>","Code":"","Alias":"This instruction is an alias of the CSINV instruction."},
+{"Name":"CSINC","Bits":"0|0|0|1|1|0|1|0|1|0|0|Rm:5|cond:4|0|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"CSINC <Wd>, <Wn>, <Wm>, <cond>","Code":"","Alias":"This instruction is used by the aliases CINC and CSET."},
+{"Name":"CSINC","Bits":"1|0|0|1|1|0|1|0|1|0|0|Rm:5|cond:4|0|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"CSINC <Xd>, <Xn>, <Xm>, <cond>","Code":"","Alias":"This instruction is used by the aliases CINC and CSET."},
+{"Name":"CSINV","Bits":"0|1|0|1|1|0|1|0|1|0|0|Rm:5|cond:4|0|0|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"CSINV <Wd>, <Wn>, <Wm>, <cond>","Code":"","Alias":"This instruction is used by the aliases CINV and CSETM."},
+{"Name":"CSINV","Bits":"1|1|0|1|1|0|1|0|1|0|0|Rm:5|cond:4|0|0|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"CSINV <Xd>, <Xn>, <Xm>, <cond>","Code":"","Alias":"This instruction is used by the aliases CINV and CSETM."},
+{"Name":"CSNEG","Bits":"0|1|0|1|1|0|1|0|1|0|0|Rm:5|cond:4|0|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"CSNEG <Wd>, <Wn>, <Wm>, <cond>","Code":"","Alias":"This instruction is used by the alias CNEG."},
+{"Name":"CSNEG","Bits":"1|1|0|1|1|0|1|0|1|0|0|Rm:5|cond:4|0|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"CSNEG <Xd>, <Xn>, <Xm>, <cond>","Code":"","Alias":"This instruction is used by the alias CNEG."},
+{"Name":"DC","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|1|op1:3|0|1|1|1|CRm:4|op2:3|Rt:5","Arch":"System variant","Syntax":"DC <dc_op>, <Xt>","Code":"","Alias":"This instruction is an alias of the SYS instruction."},
+{"Name":"DCPS1","Bits":"1|1|0|1|0|1|0|0|1|0|1|imm16:16|0|0|0|0|1","Arch":"System variant","Syntax":"DCPS1 {#<imm>}","Code":"","Alias":""},
+{"Name":"DCPS2","Bits":"1|1|0|1|0|1|0|0|1|0|1|imm16:16|0|0|0|1|0","Arch":"System variant","Syntax":"DCPS2 {#<imm>}","Code":"","Alias":""},
+{"Name":"DCPS3","Bits":"1|1|0|1|0|1|0|0|1|0|1|imm16:16|0|0|0|1|1","Arch":"System variant","Syntax":"DCPS3 {#<imm>}","Code":"","Alias":""},
+{"Name":"DMB","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|0|0|1|1|0|0|1|1|CRm:4|1|0|1|1|1|1|1|1","Arch":"System variant","Syntax":"DMB <option>|#<imm>","Code":"","Alias":""},
+{"Name":"DRPS","Bits":"1|1|0|1|0|1|1|0|1|0|1|1|1|1|1|1|0|0|0|0|0|0|1|1|1|1|1|0|0|0|0|0","Arch":"System variant","Syntax":"DRPS","Code":"","Alias":""},
+{"Name":"DSB","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|0|0|1|1|0|0|1|1|CRm:4|1|0|0|1|1|1|1|1","Arch":"System variant","Syntax":"DSB <option>|#<imm>","Code":"","Alias":""},
+{"Name":"EON (shifted register)","Bits":"0|1|0|0|1|0|1|0|shift:2|1|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"EON <Wd>, <Wn>, <Wm>{, <shift> #<amount>}","Code":"","Alias":""},
+{"Name":"EON (shifted register)","Bits":"1|1|0|0|1|0|1|0|shift:2|1|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"EON <Xd>, <Xn>, <Xm>{, <shift> #<amount>}","Code":"","Alias":""},
+{"Name":"EOR (immediate)","Bits":"0|1|0|1|0|0|1|0|0|0|immr:6|imms:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"EOR <Wd|WSP>, <Wn>, #<imm>","Code":"","Alias":""},
+{"Name":"EOR (immediate)","Bits":"1|1|0|1|0|0|1|0|0|N|immr:6|imms:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"EOR <Xd|SP>, <Xn>, #<imm>","Code":"","Alias":""},
+{"Name":"EOR (shifted register)","Bits":"0|1|0|0|1|0|1|0|shift:2|0|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"EOR <Wd>, <Wn>, <Wm>{, <shift> #<amount>}","Code":"","Alias":""},
+{"Name":"EOR (shifted register)","Bits":"1|1|0|0|1|0|1|0|shift:2|0|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"EOR <Xd>, <Xn>, <Xm>{, <shift> #<amount>}","Code":"","Alias":""},
+{"Name":"ERET","Bits":"1|1|0|1|0|1|1|0|1|0|0|1|1|1|1|1|0|0|0|0|0|0|1|1|1|1|1|0|0|0|0|0","Arch":"System variant","Syntax":"ERET","Code":"","Alias":""},
+{"Name":"EXTR","Bits":"0|0|0|1|0|0|1|1|1|0|0|Rm:5|imms:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"EXTR <Wd>, <Wn>, <Wm>, #<lsb>","Code":"","Alias":"This instruction is used by the alias ROR (immediate)."},
+{"Name":"EXTR","Bits":"1|0|0|1|0|0|1|1|1|1|0|Rm:5|imms:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"EXTR <Xd>, <Xn>, <Xm>, #<lsb>","Code":"","Alias":"This instruction is used by the alias ROR (immediate)."},
+{"Name":"HINT","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|0|0|1|1|0|0|1|0|0000:4|op2:3|1|1|1|1|1","Arch":"Hints 6 and 7 variant","Syntax":"HINT #<imm>","Code":"","Alias":""},
+{"Name":"HINT","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|0|0|1|1|0|0|1|0|CRm:4|op2:3|1|1|1|1|1","Arch":"Hints 8 to 127 variant","Syntax":"HINT #<imm>","Code":"","Alias":""},
+{"Name":"HLT","Bits":"1|1|0|1|0|1|0|0|0|1|0|imm16:16|0|0|0|0|0","Arch":"System variant","Syntax":"HLT #<imm>","Code":"","Alias":""},
+{"Name":"HVC","Bits":"1|1|0|1|0|1|0|0|0|0|0|imm16:16|0|0|0|1|0","Arch":"System variant","Syntax":"HVC #<imm>","Code":"","Alias":""},
+{"Name":"IC","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|1|op1:3|0|1|1|1|CRm:4|op2:3|Rt:5","Arch":"System variant","Syntax":"IC <ic_op>{, <Xt>}","Code":"","Alias":"This instruction is an alias of the SYS instruction."},
+{"Name":"ISB","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|0|0|1|1|0|0|1|1|CRm:4|1|1|0|1|1|1|1|1","Arch":"System variant","Syntax":"ISB {<option>|#<imm>}","Code":"","Alias":""},
+{"Name":"LDAR","Bits":"10:2|0|0|1|0|0|0|1|1|0|(1)|(1)|(1)|(1)|(1)|1|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDAR <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"LDAR","Bits":"11:2|0|0|1|0|0|0|1|1|0|(1)|(1)|(1)|(1)|(1)|1|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDAR <Xt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"LDARB","Bits":"0|0|0|0|1|0|0|0|1|1|0|(1)|(1)|(1)|(1)|(1)|1|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"No offset variant","Syntax":"LDARB <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"LDARH","Bits":"0|1|0|0|1|0|0|0|1|1|0|(1)|(1)|(1)|(1)|(1)|1|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"No offset variant","Syntax":"LDARH <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"LDAXP","Bits":"1|0|0|0|1|0|0|0|0|1|1|(1)|(1)|(1)|(1)|(1)|1|Rt2:5|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDAXP <Wt1>, <Wt2>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"LDAXP","Bits":"1|1|0|0|1|0|0|0|0|1|1|(1)|(1)|(1)|(1)|(1)|1|Rt2:5|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDAXP <Xt1>, <Xt2>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"LDAXR","Bits":"10:2|0|0|1|0|0|0|0|1|0|(1)|(1)|(1)|(1)|(1)|1|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDAXR <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"LDAXR","Bits":"11:2|0|0|1|0|0|0|0|1|0|(1)|(1)|(1)|(1)|(1)|1|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDAXR <Xt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"LDAXRB","Bits":"0|0|0|0|1|0|0|0|0|1|0|(1)|(1)|(1)|(1)|(1)|1|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"No offset variant","Syntax":"LDAXRB <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"LDAXRH","Bits":"0|1|0|0|1|0|0|0|0|1|0|(1)|(1)|(1)|(1)|(1)|1|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"No offset variant","Syntax":"LDAXRH <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"LDNP","Bits":"00:2|1|0|1|0|0|0|0|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDNP <Wt1>, <Wt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
+{"Name":"LDNP","Bits":"10:2|1|0|1|0|0|0|0|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDNP <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
+{"Name":"LDP","Bits":"00:2|1|0|1|0|0|0|1|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Post-index 32-bit variant","Syntax":"LDP <Wt1>, <Wt2>, [<Xn|SP>], #<imm>","Code":"","Alias":""},
+{"Name":"LDP","Bits":"10:2|1|0|1|0|0|0|1|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Post-index 64-bit variant","Syntax":"LDP <Xt1>, <Xt2>, [<Xn|SP>], #<imm>","Code":"","Alias":""},
+{"Name":"LDP","Bits":"00:2|1|0|1|0|0|1|1|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Pre-index 32-bit variant","Syntax":"LDP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>]!","Code":"","Alias":""},
+{"Name":"LDP","Bits":"10:2|1|0|1|0|0|1|1|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Pre-index 64-bit variant","Syntax":"LDP <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]!","Code":"","Alias":""},
+{"Name":"LDP","Bits":"00:2|1|0|1|0|0|1|0|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Signed offset 32-bit variant","Syntax":"LDP <Wt1>, <Wt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
+{"Name":"LDP","Bits":"10:2|1|0|1|0|0|1|0|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Signed offset 64-bit variant","Syntax":"LDP <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
+{"Name":"LDPSW","Bits":"0|1|1|0|1|0|0|0|1|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Post-index Post-index variant","Syntax":"LDPSW <Xt1>, <Xt2>, [<Xn|SP>], #<imm>","Code":"","Alias":""},
+{"Name":"LDPSW","Bits":"0|1|1|0|1|0|0|1|1|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Pre-index Pre-index variant","Syntax":"LDPSW <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]!","Code":"","Alias":""},
+{"Name":"LDPSW","Bits":"0|1|1|0|1|0|0|1|0|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Signed offset Signed offset variant","Syntax":"LDPSW <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
+{"Name":"LDR (immediate)","Bits":"10:2|1|1|1|0|0|0|0|1|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 32-bit variant","Syntax":"LDR <Wt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
+{"Name":"LDR (immediate)","Bits":"11:2|1|1|1|0|0|0|0|1|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 64-bit variant","Syntax":"LDR <Xt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
+{"Name":"LDR (immediate)","Bits":"10:2|1|1|1|0|0|0|0|1|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index 32-bit variant","Syntax":"LDR <Wt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
+{"Name":"LDR (immediate)","Bits":"11:2|1|1|1|0|0|0|0|1|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index 64-bit variant","Syntax":"LDR <Xt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
+{"Name":"LDR (immediate)","Bits":"10:2|1|1|1|0|0|1|0|1|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 32-bit variant","Syntax":"LDR <Wt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
+{"Name":"LDR (immediate)","Bits":"11:2|1|1|1|0|0|1|0|1|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 64-bit variant","Syntax":"LDR <Xt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
+{"Name":"LDR (literal)","Bits":"00:2|0|1|1|0|0|0|imm19:19|Rt:5","Arch":"32-bit variant","Syntax":"LDR <Wt>, <label>","Code":"","Alias":""},
+{"Name":"LDR (literal)","Bits":"01:2|0|1|1|0|0|0|imm19:19|Rt:5","Arch":"64-bit variant","Syntax":"LDR <Xt>, <label>","Code":"","Alias":""},
+{"Name":"LDR (register)","Bits":"10:2|1|1|1|0|0|0|0|1|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDR <Wt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]","Code":"","Alias":""},
+{"Name":"LDR (register)","Bits":"11:2|1|1|1|0|0|0|0|1|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDR <Xt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]","Code":"","Alias":""},
+{"Name":"LDRB (immediate)","Bits":"0|0|1|1|1|0|0|0|0|1|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index Post-index variant","Syntax":"LDRB <Wt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
+{"Name":"LDRB (immediate)","Bits":"0|0|1|1|1|0|0|0|0|1|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index Pre-index variant","Syntax":"LDRB <Wt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
+{"Name":"LDRB (immediate)","Bits":"0|0|1|1|1|0|0|1|0|1|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset Unsigned offset variant","Syntax":"LDRB <Wt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
+{"Name":"LDRB (register)","Bits":"0|0|1|1|1|0|0|0|0|1|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"Extended register variant","Syntax":"LDRB <Wt>, [<Xn|SP>, (<Wm>|<Xm>), <extend> {<amount>}]","Code":"","Alias":""},
+{"Name":"LDRB (register)","Bits":"0|0|1|1|1|0|0|0|0|1|1|Rm:5|011:3|S|1|0|Rn:5|Rt:5","Arch":"Shifted register variant","Syntax":"LDRB <Wt>, [<Xn|SP>, <Xm>{, LSL <amount>}]","Code":"","Alias":""},
+{"Name":"LDRH (immediate)","Bits":"0|1|1|1|1|0|0|0|0|1|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index Post-index variant","Syntax":"LDRH <Wt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
+{"Name":"LDRH (immediate)","Bits":"0|1|1|1|1|0|0|0|0|1|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index Pre-index variant","Syntax":"LDRH <Wt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
+{"Name":"LDRH (immediate)","Bits":"0|1|1|1|1|0|0|1|0|1|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset Unsigned offset variant","Syntax":"LDRH <Wt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
+{"Name":"LDRH (register)","Bits":"0|1|1|1|1|0|0|0|0|1|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDRH <Wt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]","Code":"","Alias":""},
+{"Name":"LDRSB (immediate)","Bits":"0|0|1|1|1|0|0|0|11:2|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 32-bit variant","Syntax":"LDRSB <Wt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
+{"Name":"LDRSB (immediate)","Bits":"0|0|1|1|1|0|0|0|10:2|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 64-bit variant","Syntax":"LDRSB <Xt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
+{"Name":"LDRSB (immediate)","Bits":"0|0|1|1|1|0|0|0|11:2|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index 32-bit variant","Syntax":"LDRSB <Wt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
+{"Name":"LDRSB (immediate)","Bits":"0|0|1|1|1|0|0|0|10:2|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index 64-bit variant","Syntax":"LDRSB <Xt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
+{"Name":"LDRSB (immediate)","Bits":"0|0|1|1|1|0|0|1|11:2|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 32-bit variant","Syntax":"LDRSB <Wt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
+{"Name":"LDRSB (immediate)","Bits":"0|0|1|1|1|0|0|1|10:2|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 64-bit variant","Syntax":"LDRSB <Xt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
+{"Name":"LDRSB (register)","Bits":"0|0|1|1|1|0|0|0|11:2|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"32-bit with extended register offset variant","Syntax":"LDRSB <Wt>, [<Xn|SP>, (<Wm>|<Xm>), <extend> {<amount>}]","Code":"","Alias":""},
+{"Name":"LDRSB (register)","Bits":"0|0|1|1|1|0|0|0|11:2|1|Rm:5|011:3|S|1|0|Rn:5|Rt:5","Arch":"32-bit with shifted register offset variant","Syntax":"LDRSB <Wt>, [<Xn|SP>, <Xm>{, LSL <amount>}]","Code":"","Alias":""},
+{"Name":"LDRSB (register)","Bits":"0|0|1|1|1|0|0|0|10:2|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"64-bit with extended register offset variant","Syntax":"LDRSB <Xt>, [<Xn|SP>, (<Wm>|<Xm>), <extend> {<amount>}]","Code":"","Alias":""},
+{"Name":"LDRSB (register)","Bits":"0|0|1|1|1|0|0|0|10:2|1|Rm:5|011:3|S|1|0|Rn:5|Rt:5","Arch":"64-bit with shifted register offset variant","Syntax":"LDRSB <Xt>, [<Xn|SP>, <Xm>{, LSL <amount>}]","Code":"","Alias":""},
+{"Name":"LDRSH (immediate)","Bits":"0|1|1|1|1|0|0|0|11:2|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 32-bit variant","Syntax":"LDRSH <Wt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
+{"Name":"LDRSH (immediate)","Bits":"0|1|1|1|1|0|0|0|10:2|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 64-bit variant","Syntax":"LDRSH <Xt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
+{"Name":"LDRSH (immediate)","Bits":"0|1|1|1|1|0|0|0|11:2|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index 32-bit variant","Syntax":"LDRSH <Wt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
+{"Name":"LDRSH (immediate)","Bits":"0|1|1|1|1|0|0|0|10:2|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index 64-bit variant","Syntax":"LDRSH <Xt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
+{"Name":"LDRSH (immediate)","Bits":"0|1|1|1|1|0|0|1|11:2|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 32-bit variant","Syntax":"LDRSH <Wt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
+{"Name":"LDRSH (immediate)","Bits":"0|1|1|1|1|0|0|1|10:2|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 64-bit variant","Syntax":"LDRSH <Xt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
+{"Name":"LDRSH (register)","Bits":"0|1|1|1|1|0|0|0|11:2|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDRSH <Wt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]","Code":"","Alias":""},
+{"Name":"LDRSH (register)","Bits":"0|1|1|1|1|0|0|0|10:2|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDRSH <Xt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]","Code":"","Alias":""},
+{"Name":"LDRSW (immediate)","Bits":"1|0|1|1|1|0|0|0|1|0|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index Post-index variant","Syntax":"LDRSW <Xt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
+{"Name":"LDRSW (immediate)","Bits":"1|0|1|1|1|0|0|0|1|0|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index Pre-index variant","Syntax":"LDRSW <Xt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
+{"Name":"LDRSW (immediate)","Bits":"1|0|1|1|1|0|0|1|1|0|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset Unsigned offset variant","Syntax":"LDRSW <Xt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
+{"Name":"LDRSW (literal)","Bits":"1|0|0|1|1|0|0|0|imm19:19|Rt:5","Arch":"Literal variant","Syntax":"LDRSW <Xt>, <label>","Code":"","Alias":""},
+{"Name":"LDRSW (register)","Bits":"1|0|1|1|1|0|0|0|1|0|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDRSW <Xt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]","Code":"","Alias":""},
+{"Name":"LDTR","Bits":"10:2|1|1|1|0|0|0|0|1|0|imm9:9|1|0|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDTR <Wt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"LDTR","Bits":"11:2|1|1|1|0|0|0|0|1|0|imm9:9|1|0|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDTR <Xt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"LDTRB","Bits":"0|0|1|1|1|0|0|0|0|1|0|imm9:9|1|0|Rn:5|Rt:5","Arch":"Unscaled offset variant","Syntax":"LDTRB <Wt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"LDTRH","Bits":"0|1|1|1|1|0|0|0|0|1|0|imm9:9|1|0|Rn:5|Rt:5","Arch":"Unscaled offset variant","Syntax":"LDTRH <Wt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"LDTRSB","Bits":"0|0|1|1|1|0|0|0|11:2|0|imm9:9|1|0|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDTRSB <Wt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"LDTRSB","Bits":"0|0|1|1|1|0|0|0|10:2|0|imm9:9|1|0|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDTRSB <Xt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"LDTRSH","Bits":"0|1|1|1|1|0|0|0|11:2|0|imm9:9|1|0|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDTRSH <Wt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"LDTRSH","Bits":"0|1|1|1|1|0|0|0|10:2|0|imm9:9|1|0|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDTRSH <Xt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"LDTRSW","Bits":"1|0|1|1|1|0|0|0|1|0|0|imm9:9|1|0|Rn:5|Rt:5","Arch":"Unscaled offset variant","Syntax":"LDTRSW <Xt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"LDUR","Bits":"10:2|1|1|1|0|0|0|0|1|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDUR <Wt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"LDUR","Bits":"11:2|1|1|1|0|0|0|0|1|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDUR <Xt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"LDURB","Bits":"0|0|1|1|1|0|0|0|0|1|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"Unscaled offset variant","Syntax":"LDURB <Wt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"LDURH","Bits":"0|1|1|1|1|0|0|0|0|1|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"Unscaled offset variant","Syntax":"LDURH <Wt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"LDURSB","Bits":"0|0|1|1|1|0|0|0|11:2|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDURSB <Wt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"LDURSB","Bits":"0|0|1|1|1|0|0|0|10:2|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDURSB <Xt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"LDURSH","Bits":"0|1|1|1|1|0|0|0|11:2|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDURSH <Wt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"LDURSH","Bits":"0|1|1|1|1|0|0|0|10:2|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDURSH <Xt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"LDURSW","Bits":"1|0|1|1|1|0|0|0|1|0|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"Unscaled offset variant","Syntax":"LDURSW <Xt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"LDXP","Bits":"1|0|0|0|1|0|0|0|0|1|1|(1)|(1)|(1)|(1)|(1)|0|Rt2:5|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDXP <Wt1>, <Wt2>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"LDXP","Bits":"1|1|0|0|1|0|0|0|0|1|1|(1)|(1)|(1)|(1)|(1)|0|Rt2:5|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDXP <Xt1>, <Xt2>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"LDXR","Bits":"10:2|0|0|1|0|0|0|0|1|0|(1)|(1)|(1)|(1)|(1)|0|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDXR <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"LDXR","Bits":"11:2|0|0|1|0|0|0|0|1|0|(1)|(1)|(1)|(1)|(1)|0|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDXR <Xt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"LDXRB","Bits":"0|0|0|0|1|0|0|0|0|1|0|(1)|(1)|(1)|(1)|(1)|0|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"No offset variant","Syntax":"LDXRB <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"LDXRH","Bits":"0|1|0|0|1|0|0|0|0|1|0|(1)|(1)|(1)|(1)|(1)|0|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"No offset variant","Syntax":"LDXRH <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"LSL (register)","Bits":"0|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|1|0|0|0|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"LSL <Wd>, <Wn>, <Wm>","Code":"","Alias":"This instruction is an alias of the LSLV instruction."},
+{"Name":"LSL (register)","Bits":"1|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|1|0|0|0|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"LSL <Xd>, <Xn>, <Xm>","Code":"","Alias":"This instruction is an alias of the LSLV instruction."},
+{"Name":"LSL (immediate)","Bits":"0|1|0|1|0|0|1|1|0|0|immr:6|imms:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"LSL <Wd>, <Wn>, #<shift>","Code":"","Alias":"This instruction is an alias of the UBFM instruction."},
+{"Name":"LSL (immediate)","Bits":"1|1|0|1|0|0|1|1|0|1|immr:6|imms:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"LSL <Xd>, <Xn>, #<shift>","Code":"","Alias":"This instruction is an alias of the UBFM instruction."},
+{"Name":"LSLV","Bits":"0|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|1|0|0|0|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"LSLV <Wd>, <Wn>, <Wm>","Code":"","Alias":"This instruction is used by the alias LSL (register)."},
+{"Name":"LSLV","Bits":"1|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|1|0|0|0|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"LSLV <Xd>, <Xn>, <Xm>","Code":"","Alias":"This instruction is used by the alias LSL (register)."},
+{"Name":"LSR (register)","Bits":"0|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|1|0|0|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"LSR <Wd>, <Wn>, <Wm>","Code":"","Alias":"This instruction is an alias of the LSRV instruction."},
+{"Name":"LSR (register)","Bits":"1|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|1|0|0|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"LSR <Xd>, <Xn>, <Xm>","Code":"","Alias":"This instruction is an alias of the LSRV instruction."},
+{"Name":"LSR (immediate)","Bits":"0|1|0|1|0|0|1|1|0|0|immr:6|011111:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"LSR <Wd>, <Wn>, #<shift>","Code":"","Alias":"This instruction is an alias of the UBFM instruction."},
+{"Name":"LSR (immediate)","Bits":"1|1|0|1|0|0|1|1|0|1|immr:6|111111:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"LSR <Xd>, <Xn>, #<shift>","Code":"","Alias":"This instruction is an alias of the UBFM instruction."},
+{"Name":"LSRV","Bits":"0|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|1|0|0|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"LSRV <Wd>, <Wn>, <Wm>","Code":"","Alias":"This instruction is used by the alias LSR (register)."},
+{"Name":"LSRV","Bits":"1|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|1|0|0|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"LSRV <Xd>, <Xn>, <Xm>","Code":"","Alias":"This instruction is used by the alias LSR (register)."},
+{"Name":"MADD","Bits":"0|0|0|1|1|0|1|1|0|0|0|Rm:5|0|Ra:5|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"MADD <Wd>, <Wn>, <Wm>, <Wa>","Code":"","Alias":"This instruction is used by the alias MUL."},
+{"Name":"MADD","Bits":"1|0|0|1|1|0|1|1|0|0|0|Rm:5|0|Ra:5|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"MADD <Xd>, <Xn>, <Xm>, <Xa>","Code":"","Alias":"This instruction is used by the alias MUL."},
+{"Name":"MNEG","Bits":"0|0|0|1|1|0|1|1|0|0|0|Rm:5|1|1|1|1|1|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"MNEG <Wd>, <Wn>, <Wm>","Code":"","Alias":"This instruction is an alias of the MSUB instruction."},
+{"Name":"MNEG","Bits":"1|0|0|1|1|0|1|1|0|0|0|Rm:5|1|1|1|1|1|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"MNEG <Xd>, <Xn>, <Xm>","Code":"","Alias":"This instruction is an alias of the MSUB instruction."},
+{"Name":"MOV (to/from SP)","Bits":"0|0|0|1|0|0|0|1|0|0|0|0|0|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"MOV <Wd|WSP>, <Wn|WSP>","Code":"","Alias":"This instruction is an alias of the ADD (immediate) instruction."},
+{"Name":"MOV (to/from SP)","Bits":"1|0|0|1|0|0|0|1|0|0|0|0|0|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"MOV <Xd|SP>, <Xn|SP>","Code":"","Alias":"This instruction is an alias of the ADD (immediate) instruction."},
+{"Name":"MOV (inverted wide immediate)","Bits":"0|0|0|1|0|0|1|0|1|hw:2|imm16:16|Rd:5","Arch":"32-bit variant","Syntax":"MOV <Wd>, #<imm>","Code":"","Alias":"This instruction is an alias of the MOVN instruction."},
+{"Name":"MOV (inverted wide immediate)","Bits":"1|0|0|1|0|0|1|0|1|hw:2|imm16:16|Rd:5","Arch":"64-bit variant","Syntax":"MOV <Xd>, #<imm>","Code":"","Alias":"This instruction is an alias of the MOVN instruction."},
+{"Name":"MOV (wide immediate)","Bits":"0|1|0|1|0|0|1|0|1|hw:2|imm16:16|Rd:5","Arch":"32-bit variant","Syntax":"MOV <Wd>, #<imm>","Code":"","Alias":"This instruction is an alias of the MOVZ instruction."},
+{"Name":"MOV (wide immediate)","Bits":"1|1|0|1|0|0|1|0|1|hw:2|imm16:16|Rd:5","Arch":"64-bit variant","Syntax":"MOV <Xd>, #<imm>","Code":"","Alias":"This instruction is an alias of the MOVZ instruction."},
+{"Name":"MOV (bitmask immediate)","Bits":"0|0|1|1|0|0|1|0|0|0|immr:6|imms:6|1|1|1|1|1|Rd:5","Arch":"32-bit variant","Syntax":"MOV <Wd|WSP>, #<imm>","Code":"","Alias":"This instruction is an alias of the ORR (immediate) instruction."},
+{"Name":"MOV (bitmask immediate)","Bits":"1|0|1|1|0|0|1|0|0|N|immr:6|imms:6|1|1|1|1|1|Rd:5","Arch":"64-bit variant","Syntax":"MOV <Xd|SP>, #<imm>","Code":"","Alias":"This instruction is an alias of the ORR (immediate) instruction."},
+{"Name":"MOV (register)","Bits":"0|0|1|0|1|0|1|0|0|0|0|Rm:5|0|0|0|0|0|0|1|1|1|1|1|Rd:5","Arch":"32-bit variant","Syntax":"MOV <Wd>, <Wm>","Code":"","Alias":"This instruction is an alias of the ORR (shifted register) instruction."},
+{"Name":"MOV (register)","Bits":"1|0|1|0|1|0|1|0|0|0|0|Rm:5|0|0|0|0|0|0|1|1|1|1|1|Rd:5","Arch":"64-bit variant","Syntax":"MOV <Xd>, <Xm>","Code":"","Alias":"This instruction is an alias of the ORR (shifted register) instruction."},
+{"Name":"MOVK","Bits":"0|1|1|1|0|0|1|0|1|hw:2|imm16:16|Rd:5","Arch":"32-bit variant","Syntax":"MOVK <Wd>, #<imm>{, LSL #<shift>}","Code":"","Alias":""},
+{"Name":"MOVK","Bits":"1|1|1|1|0|0|1|0|1|hw:2|imm16:16|Rd:5","Arch":"64-bit variant","Syntax":"MOVK <Xd>, #<imm>{, LSL #<shift>}","Code":"","Alias":""},
+{"Name":"MOVN","Bits":"0|0|0|1|0|0|1|0|1|hw:2|imm16:16|Rd:5","Arch":"32-bit variant","Syntax":"MOVN <Wd>, #<imm>{, LSL #<shift>}","Code":"","Alias":"This instruction is used by the alias MOV (inverted wide immediate)."},
+{"Name":"MOVN","Bits":"1|0|0|1|0|0|1|0|1|hw:2|imm16:16|Rd:5","Arch":"64-bit variant","Syntax":"MOVN <Xd>, #<imm>{, LSL #<shift>}","Code":"","Alias":"This instruction is used by the alias MOV (inverted wide immediate)."},
+{"Name":"MOVZ","Bits":"0|1|0|1|0|0|1|0|1|hw:2|imm16:16|Rd:5","Arch":"32-bit variant","Syntax":"MOVZ <Wd>, #<imm>{, LSL #<shift>}","Code":"","Alias":"This instruction is used by the alias MOV (wide immediate)."},
+{"Name":"MOVZ","Bits":"1|1|0|1|0|0|1|0|1|hw:2|imm16:16|Rd:5","Arch":"64-bit variant","Syntax":"MOVZ <Xd>, #<imm>{, LSL #<shift>}","Code":"","Alias":"This instruction is used by the alias MOV (wide immediate)."},
+{"Name":"MRS","Bits":"1|1|0|1|0|1|0|1|0|0|1|1|o0|op1:3|CRn:4|CRm:4|op2:3|Rt:5","Arch":"System variant","Syntax":"MRS <Xt>, (<systemreg>|S<op0>_<op1>_<Cn>_<Cm>_<op2>)","Code":"","Alias":""},
+{"Name":"MSR (immediate)","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|0|op1:3|0|1|0|0|CRm:4|op2:3|1|1|1|1|1","Arch":"System variant","Syntax":"MSR <pstatefield>, #<imm>","Code":"","Alias":""},
+{"Name":"MSR (register)","Bits":"1|1|0|1|0|1|0|1|0|0|0|1|o0|op1:3|CRn:4|CRm:4|op2:3|Rt:5","Arch":"System variant","Syntax":"MSR (<systemreg>|S<op0>_<op1>_<Cn>_<Cm>_<op2>), <Xt>","Code":"","Alias":""},
+{"Name":"MSUB","Bits":"0|0|0|1|1|0|1|1|0|0|0|Rm:5|1|Ra:5|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"MSUB <Wd>, <Wn>, <Wm>, <Wa>","Code":"","Alias":"This instruction is used by the alias MNEG."},
+{"Name":"MSUB","Bits":"1|0|0|1|1|0|1|1|0|0|0|Rm:5|1|Ra:5|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"MSUB <Xd>, <Xn>, <Xm>, <Xa>","Code":"","Alias":"This instruction is used by the alias MNEG."},
+{"Name":"MUL","Bits":"0|0|0|1|1|0|1|1|0|0|0|Rm:5|0|1|1|1|1|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"MUL <Wd>, <Wn>, <Wm>","Code":"","Alias":"This instruction is an alias of the MADD instruction."},
+{"Name":"MUL","Bits":"1|0|0|1|1|0|1|1|0|0|0|Rm:5|0|1|1|1|1|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"MUL <Xd>, <Xn>, <Xm>","Code":"","Alias":"This instruction is an alias of the MADD instruction."},
+{"Name":"MVN","Bits":"0|0|1|0|1|0|1|0|shift:2|1|Rm:5|imm6:6|1|1|1|1|1|Rd:5","Arch":"32-bit variant","Syntax":"MVN <Wd>, <Wm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is an alias of the ORN (shifted register) instruction."},
+{"Name":"MVN","Bits":"1|0|1|0|1|0|1|0|shift:2|1|Rm:5|imm6:6|1|1|1|1|1|Rd:5","Arch":"64-bit variant","Syntax":"MVN <Xd>, <Xm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is an alias of the ORN (shifted register) instruction."},
+{"Name":"NEG (shifted register)","Bits":"0|1|0|0|1|0|1|1|shift:2|0|Rm:5|imm6:6|1|1|1|1|1|Rd:5","Arch":"32-bit variant","Syntax":"NEG <Wd>, <Wm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is an alias of the SUB (shifted register) instruction."},
+{"Name":"NEG (shifted register)","Bits":"1|1|0|0|1|0|1|1|shift:2|0|Rm:5|imm6:6|1|1|1|1|1|Rd:5","Arch":"64-bit variant","Syntax":"NEG <Xd>, <Xm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is an alias of the SUB (shifted register) instruction."},
+{"Name":"NEGS","Bits":"0|1|1|0|1|0|1|1|shift:2|0|Rm:5|imm6:6|1|1|1|1|1|Rd:5","Arch":"32-bit variant","Syntax":"NEGS <Wd>, <Wm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is an alias of the SUBS (shifted register) instruction."},
+{"Name":"NEGS","Bits":"1|1|1|0|1|0|1|1|shift:2|0|Rm:5|imm6:6|1|1|1|1|1|Rd:5","Arch":"64-bit variant","Syntax":"NEGS <Xd>, <Xm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is an alias of the SUBS (shifted register) instruction."},
+{"Name":"NGC","Bits":"0|1|0|1|1|0|1|0|0|0|0|Rm:5|0|0|0|0|0|0|1|1|1|1|1|Rd:5","Arch":"32-bit variant","Syntax":"NGC <Wd>, <Wm>","Code":"","Alias":"This instruction is an alias of the SBC instruction."},
+{"Name":"NGC","Bits":"1|1|0|1|1|0|1|0|0|0|0|Rm:5|0|0|0|0|0|0|1|1|1|1|1|Rd:5","Arch":"64-bit variant","Syntax":"NGC <Xd>, <Xm>","Code":"","Alias":"This instruction is an alias of the SBC instruction."},
+{"Name":"NGCS","Bits":"0|1|1|1|1|0|1|0|0|0|0|Rm:5|0|0|0|0|0|0|1|1|1|1|1|Rd:5","Arch":"32-bit variant","Syntax":"NGCS <Wd>, <Wm>","Code":"","Alias":"This instruction is an alias of the SBCS instruction."},
+{"Name":"NGCS","Bits":"1|1|1|1|1|0|1|0|0|0|0|Rm:5|0|0|0|0|0|0|1|1|1|1|1|Rd:5","Arch":"64-bit variant","Syntax":"NGCS <Xd>, <Xm>","Code":"","Alias":"This instruction is an alias of the SBCS instruction."},
+{"Name":"NOP","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|0|0|1|1|0|0|1|0|0|0|0|0|0|0|0|1|1|1|1|1","Arch":"System variant","Syntax":"NOP","Code":"","Alias":""},
+{"Name":"ORN (shifted register)","Bits":"0|0|1|0|1|0|1|0|shift:2|1|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ORN <Wd>, <Wn>, <Wm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is used by the alias MVN."},
+{"Name":"ORN (shifted register)","Bits":"1|0|1|0|1|0|1|0|shift:2|1|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ORN <Xd>, <Xn>, <Xm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is used by the alias MVN."},
+{"Name":"ORR (immediate)","Bits":"0|0|1|1|0|0|1|0|0|0|immr:6|imms:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ORR <Wd|WSP>, <Wn>, #<imm>","Code":"","Alias":"This instruction is used by the alias MOV (bitmask immediate)."},
+{"Name":"ORR (immediate)","Bits":"1|0|1|1|0|0|1|0|0|N|immr:6|imms:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ORR <Xd|SP>, <Xn>, #<imm>","Code":"","Alias":"This instruction is used by the alias MOV (bitmask immediate)."},
+{"Name":"ORR (shifted register)","Bits":"0|0|1|0|1|0|1|0|shift:2|0|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ORR <Wd>, <Wn>, <Wm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is used by the alias MOV (register)."},
+{"Name":"ORR (shifted register)","Bits":"1|0|1|0|1|0|1|0|shift:2|0|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ORR <Xd>, <Xn>, <Xm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is used by the alias MOV (register)."},
+{"Name":"PRFM (immediate)","Bits":"1|1|1|1|1|0|0|1|1|0|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset variant","Syntax":"PRFM (<prfop>|#<imm5>), [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
+{"Name":"PRFM (literal)","Bits":"1|1|0|1|1|0|0|0|imm19:19|Rt:5","Arch":"Literal variant","Syntax":"PRFM (<prfop>|#<imm5>), <label>","Code":"","Alias":""},
+{"Name":"PRFM (register)","Bits":"1|1|1|1|1|0|0|0|1|0|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"Integer variant","Syntax":"PRFM (<prfop>|#<imm5>), [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]","Code":"","Alias":""},
+{"Name":"PRFM (unscaled offset)","Bits":"1|1|1|1|1|0|0|0|1|0|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"Unscaled offset variant","Syntax":"PRFUM (<prfop>|#<imm5>), [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"RBIT","Bits":"0|1|0|1|1|0|1|0|1|1|0|0|0|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"RBIT <Wd>, <Wn>","Code":"","Alias":""},
+{"Name":"RBIT","Bits":"1|1|0|1|1|0|1|0|1|1|0|0|0|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"RBIT <Xd>, <Xn>","Code":"","Alias":""},
+{"Name":"RET","Bits":"1|1|0|1|0|1|1|0|0|1|0|1|1|1|1|1|0|0|0|0|0|0|Rn:5|0|0|0|0|0","Arch":"Integer variant","Syntax":"RET {<Xn>}","Code":"","Alias":""},
+{"Name":"REV","Bits":"0|1|0|1|1|0|1|0|1|1|0|0|0|0|0|0|0|0|0|0|10:2|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"REV <Wd>, <Wn>","Code":"","Alias":""},
+{"Name":"REV","Bits":"1|1|0|1|1|0|1|0|1|1|0|0|0|0|0|0|0|0|0|0|11:2|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"REV <Xd>, <Xn>","Code":"","Alias":""},
+{"Name":"REV16","Bits":"0|1|0|1|1|0|1|0|1|1|0|0|0|0|0|0|0|0|0|0|0|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"REV16 <Wd>, <Wn>","Code":"","Alias":""},
+{"Name":"REV16","Bits":"1|1|0|1|1|0|1|0|1|1|0|0|0|0|0|0|0|0|0|0|0|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"REV16 <Xd>, <Xn>","Code":"","Alias":""},
+{"Name":"REV32","Bits":"1|1|0|1|1|0|1|0|1|1|0|0|0|0|0|0|0|0|0|0|1|0|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"REV32 <Xd>, <Xn>","Code":"","Alias":""},
+{"Name":"REV64","Bits":"1|1|0|1|1|0|1|0|1|1|0|0|0|0|0|0|0|0|0|0|1|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"REV64 <Xd>, <Xn>","Code":"","Alias":""},
+{"Name":"ROR (immediate)","Bits":"0|0|0|1|0|0|1|1|1|0|0|Rm:5|imms:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ROR <Wd>, <Ws>, #<shift>","Code":"","Alias":"This instruction is an alias of the EXTR instruction."},
+{"Name":"ROR (immediate)","Bits":"1|0|0|1|0|0|1|1|1|1|0|Rm:5|imms:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ROR <Xd>, <Xs>, #<shift>","Code":"","Alias":"This instruction is an alias of the EXTR instruction."},
+{"Name":"ROR (register)","Bits":"0|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|1|0|1|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ROR <Wd>, <Wn>, <Wm>","Code":"","Alias":"This instruction is an alias of the RORV instruction."},
+{"Name":"ROR (register)","Bits":"1|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|1|0|1|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ROR <Xd>, <Xn>, <Xm>","Code":"","Alias":"This instruction is an alias of the RORV instruction."},
+{"Name":"RORV","Bits":"0|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|1|0|1|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"RORV <Wd>, <Wn>, <Wm>","Code":"","Alias":"This instruction is used by the alias ROR (register)."},
+{"Name":"RORV","Bits":"1|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|1|0|1|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"RORV <Xd>, <Xn>, <Xm>","Code":"","Alias":"This instruction is used by the alias ROR (register)."},
+{"Name":"SBC","Bits":"0|1|0|1|1|0|1|0|0|0|0|Rm:5|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"SBC <Wd>, <Wn>, <Wm>","Code":"","Alias":"This instruction is used by the alias NGC."},
+{"Name":"SBC","Bits":"1|1|0|1|1|0|1|0|0|0|0|Rm:5|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SBC <Xd>, <Xn>, <Xm>","Code":"","Alias":"This instruction is used by the alias NGC."},
+{"Name":"SBCS","Bits":"0|1|1|1|1|0|1|0|0|0|0|Rm:5|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"SBCS <Wd>, <Wn>, <Wm>","Code":"","Alias":"This instruction is used by the alias NGCS."},
+{"Name":"SBCS","Bits":"1|1|1|1|1|0|1|0|0|0|0|Rm:5|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SBCS <Xd>, <Xn>, <Xm>","Code":"","Alias":"This instruction is used by the alias NGCS."},
+{"Name":"SBFIZ","Bits":"0|0|0|1|0|0|1|1|0|0|immr:6|imms:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"SBFIZ <Wd>, <Wn>, #<lsb>, #<width>","Code":"","Alias":"This instruction is an alias of the SBFM instruction."},
+{"Name":"SBFIZ","Bits":"1|0|0|1|0|0|1|1|0|1|immr:6|imms:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SBFIZ <Xd>, <Xn>, #<lsb>, #<width>","Code":"","Alias":"This instruction is an alias of the SBFM instruction."},
+{"Name":"SBFM","Bits":"0|0|0|1|0|0|1|1|0|0|immr:6|imms:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"SBFM <Wd>, <Wn>, #<immr>, #<imms>","Code":"","Alias":"This instruction is used by the aliases ASR (immediate), SBFIZ, SBFX, SXTB, SXTH, and SXTW."},
+{"Name":"SBFM","Bits":"1|0|0|1|0|0|1|1|0|1|immr:6|imms:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SBFM <Xd>, <Xn>, #<immr>, #<imms>","Code":"","Alias":"This instruction is used by the aliases ASR (immediate), SBFIZ, SBFX, SXTB, SXTH, and SXTW."},
+{"Name":"SBFX","Bits":"0|0|0|1|0|0|1|1|0|0|immr:6|imms:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"SBFX <Wd>, <Wn>, #<lsb>, #<width>","Code":"","Alias":"This instruction is an alias of the SBFM instruction."},
+{"Name":"SBFX","Bits":"1|0|0|1|0|0|1|1|0|1|immr:6|imms:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SBFX <Xd>, <Xn>, #<lsb>, #<width>","Code":"","Alias":"This instruction is an alias of the SBFM instruction."},
+{"Name":"SDIV","Bits":"0|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|0|0|1|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"SDIV <Wd>, <Wn>, <Wm>","Code":"","Alias":""},
+{"Name":"SDIV","Bits":"1|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|0|0|1|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SDIV <Xd>, <Xn>, <Xm>","Code":"","Alias":""},
+{"Name":"SEV","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|0|0|1|1|0|0|1|0|0|0|0|0|1|0|0|1|1|1|1|1","Arch":"System variant","Syntax":"SEV","Code":"","Alias":""},
+{"Name":"SEVL","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|0|0|1|1|0|0|1|0|0|0|0|0|1|0|1|1|1|1|1|1","Arch":"System variant","Syntax":"SEVL","Code":"","Alias":""},
+{"Name":"SMADDL","Bits":"1|0|0|1|1|0|1|1|0|0|1|Rm:5|0|Ra:5|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SMADDL <Xd>, <Wn>, <Wm>, <Xa>","Code":"","Alias":"This instruction is used by the alias SMULL."},
+{"Name":"SMC","Bits":"1|1|0|1|0|1|0|0|0|0|0|imm16:16|0|0|0|1|1","Arch":"System variant","Syntax":"SMC #<imm>","Code":"","Alias":""},
+{"Name":"SMNEGL","Bits":"1|0|0|1|1|0|1|1|0|0|1|Rm:5|1|1|1|1|1|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SMNEGL <Xd>, <Wn>, <Wm>","Code":"","Alias":"This instruction is an alias of the SMSUBL instruction."},
+{"Name":"SMSUBL","Bits":"1|0|0|1|1|0|1|1|0|0|1|Rm:5|1|Ra:5|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SMSUBL <Xd>, <Wn>, <Wm>, <Xa>","Code":"","Alias":"This instruction is used by the alias SMNEGL."},
+{"Name":"SMULH","Bits":"1|0|0|1|1|0|1|1|0|1|0|Rm:5|0|(1)|(1)|(1)|(1)|(1)|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SMULH <Xd>, <Xn>, <Xm>","Code":"","Alias":""},
+{"Name":"SMULL","Bits":"1|0|0|1|1|0|1|1|0|0|1|Rm:5|0|1|1|1|1|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SMULL <Xd>, <Wn>, <Wm>","Code":"","Alias":"This instruction is an alias of the SMADDL instruction."},
+{"Name":"STLR","Bits":"10:2|0|0|1|0|0|0|1|0|0|(1)|(1)|(1)|(1)|(1)|1|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"STLR <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"STLR","Bits":"11:2|0|0|1|0|0|0|1|0|0|(1)|(1)|(1)|(1)|(1)|1|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"STLR <Xt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"STLRB","Bits":"0|0|0|0|1|0|0|0|1|0|0|(1)|(1)|(1)|(1)|(1)|1|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"No offset variant","Syntax":"STLRB <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"STLRH","Bits":"0|1|0|0|1|0|0|0|1|0|0|(1)|(1)|(1)|(1)|(1)|1|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"No offset variant","Syntax":"STLRH <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"STLXP","Bits":"1|0|0|0|1|0|0|0|0|0|1|Rs:5|1|Rt2:5|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"STLXP <Ws>, <Wt1>, <Wt2>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"STLXP","Bits":"1|1|0|0|1|0|0|0|0|0|1|Rs:5|1|Rt2:5|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"STLXP <Ws>, <Xt1>, <Xt2>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"STLXR","Bits":"10:2|0|0|1|0|0|0|0|0|0|Rs:5|1|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"STLXR <Ws>, <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"STLXR","Bits":"11:2|0|0|1|0|0|0|0|0|0|Rs:5|1|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"STLXR <Ws>, <Xt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"STLXRB","Bits":"0|0|0|0|1|0|0|0|0|0|0|Rs:5|1|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"No offset variant","Syntax":"STLXRB <Ws>, <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"STLXRH","Bits":"0|1|0|0|1|0|0|0|0|0|0|Rs:5|1|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"No offset variant","Syntax":"STLXRH <Ws>, <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"STNP","Bits":"00:2|1|0|1|0|0|0|0|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"STNP <Wt1>, <Wt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
+{"Name":"STNP","Bits":"10:2|1|0|1|0|0|0|0|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"STNP <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
+{"Name":"STP","Bits":"00:2|1|0|1|0|0|0|1|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Post-index 32-bit variant","Syntax":"STP <Wt1>, <Wt2>, [<Xn|SP>], #<imm>","Code":"","Alias":""},
+{"Name":"STP","Bits":"10:2|1|0|1|0|0|0|1|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Post-index 64-bit variant","Syntax":"STP <Xt1>, <Xt2>, [<Xn|SP>], #<imm>","Code":"","Alias":""},
+{"Name":"STP","Bits":"00:2|1|0|1|0|0|1|1|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Pre-index 32-bit variant","Syntax":"STP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>]!","Code":"","Alias":""},
+{"Name":"STP","Bits":"10:2|1|0|1|0|0|1|1|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Pre-index 64-bit variant","Syntax":"STP <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]!","Code":"","Alias":""},
+{"Name":"STP","Bits":"00:2|1|0|1|0|0|1|0|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Signed offset 32-bit variant","Syntax":"STP <Wt1>, <Wt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
+{"Name":"STP","Bits":"10:2|1|0|1|0|0|1|0|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Signed offset 64-bit variant","Syntax":"STP <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
+{"Name":"STR (immediate)","Bits":"10:2|1|1|1|0|0|0|0|0|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 32-bit variant","Syntax":"STR <Wt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
+{"Name":"STR (immediate)","Bits":"11:2|1|1|1|0|0|0|0|0|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 64-bit variant","Syntax":"STR <Xt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
+{"Name":"STR (immediate)","Bits":"10:2|1|1|1|0|0|0|0|0|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index 32-bit variant","Syntax":"STR <Wt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
+{"Name":"STR (immediate)","Bits":"11:2|1|1|1|0|0|0|0|0|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index 64-bit variant","Syntax":"STR <Xt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
+{"Name":"STR (immediate)","Bits":"10:2|1|1|1|0|0|1|0|0|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 32-bit variant","Syntax":"STR <Wt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
+{"Name":"STR (immediate)","Bits":"11:2|1|1|1|0|0|1|0|0|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 64-bit variant","Syntax":"STR <Xt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
+{"Name":"STR (register)","Bits":"10:2|1|1|1|0|0|0|0|0|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"STR <Wt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]","Code":"","Alias":""},
+{"Name":"STR (register)","Bits":"11:2|1|1|1|0|0|0|0|0|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"STR <Xt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]","Code":"","Alias":""},
+{"Name":"STRB (immediate)","Bits":"0|0|1|1|1|0|0|0|0|0|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index Post-index variant","Syntax":"STRB <Wt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
+{"Name":"STRB (immediate)","Bits":"0|0|1|1|1|0|0|0|0|0|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index Pre-index variant","Syntax":"STRB <Wt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
+{"Name":"STRB (immediate)","Bits":"0|0|1|1|1|0|0|1|0|0|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset Unsigned offset variant","Syntax":"STRB <Wt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
+{"Name":"STRB (register)","Bits":"0|0|1|1|1|0|0|0|0|0|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"Extended register variant","Syntax":"STRB <Wt>, [<Xn|SP>, (<Wm>|<Xm>), <extend> {<amount>}]","Code":"","Alias":""},
+{"Name":"STRB (register)","Bits":"0|0|1|1|1|0|0|0|0|0|1|Rm:5|011:3|S|1|0|Rn:5|Rt:5","Arch":"Shifted register variant","Syntax":"STRB <Wt>, [<Xn|SP>, <Xm>{, LSL <amount>}]","Code":"","Alias":""},
+{"Name":"STRH (immediate)","Bits":"0|1|1|1|1|0|0|0|0|0|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index Post-index variant","Syntax":"STRH <Wt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
+{"Name":"STRH (immediate)","Bits":"0|1|1|1|1|0|0|0|0|0|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index Pre-index variant","Syntax":"STRH <Wt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
+{"Name":"STRH (immediate)","Bits":"0|1|1|1|1|0|0|1|0|0|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset Unsigned offset variant","Syntax":"STRH <Wt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
+{"Name":"STRH (register)","Bits":"0|1|1|1|1|0|0|0|0|0|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"STRH <Wt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]","Code":"","Alias":""},
+{"Name":"STTR","Bits":"10:2|1|1|1|0|0|0|0|0|0|imm9:9|1|0|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"STTR <Wt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"STTR","Bits":"11:2|1|1|1|0|0|0|0|0|0|imm9:9|1|0|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"STTR <Xt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"STTRB","Bits":"0|0|1|1|1|0|0|0|0|0|0|imm9:9|1|0|Rn:5|Rt:5","Arch":"Unscaled offset variant","Syntax":"STTRB <Wt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"STTRH","Bits":"0|1|1|1|1|0|0|0|0|0|0|imm9:9|1|0|Rn:5|Rt:5","Arch":"Unscaled offset variant","Syntax":"STTRH <Wt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"STUR","Bits":"10:2|1|1|1|0|0|0|0|0|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"STUR <Wt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"STUR","Bits":"11:2|1|1|1|0|0|0|0|0|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"STUR <Xt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"STURB","Bits":"0|0|1|1|1|0|0|0|0|0|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"Unscaled offset variant","Syntax":"STURB <Wt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"STURH","Bits":"0|1|1|1|1|0|0|0|0|0|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"Unscaled offset variant","Syntax":"STURH <Wt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"STXP","Bits":"1|0|0|0|1|0|0|0|0|0|1|Rs:5|0|Rt2:5|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"STXP <Ws>, <Wt1>, <Wt2>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"STXP","Bits":"1|1|0|0|1|0|0|0|0|0|1|Rs:5|0|Rt2:5|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"STXP <Ws>, <Xt1>, <Xt2>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"STXR","Bits":"10:2|0|0|1|0|0|0|0|0|0|Rs:5|0|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"STXR <Ws>, <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"STXR","Bits":"11:2|0|0|1|0|0|0|0|0|0|Rs:5|0|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"STXR <Ws>, <Xt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"STXRB","Bits":"0|0|0|0|1|0|0|0|0|0|0|Rs:5|0|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"No offset variant","Syntax":"STXRB <Ws>, <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"STXRH","Bits":"0|1|0|0|1|0|0|0|0|0|0|Rs:5|0|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"No offset variant","Syntax":"STXRH <Ws>, <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"SUB (extended register)","Bits":"0|1|0|0|1|0|1|1|0|0|1|Rm:5|option:3|imm3:3|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"SUB <Wd|WSP>, <Wn|WSP>, <Wm>{, <extend> {#<amount>}}","Code":"","Alias":""},
+{"Name":"SUB (extended register)","Bits":"1|1|0|0|1|0|1|1|0|0|1|Rm:5|option:3|imm3:3|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SUB <Xd|SP>, <Xn|SP>, <R><m>{, <extend> {#<amount>}}","Code":"","Alias":""},
+{"Name":"SUB (immediate)","Bits":"0|1|0|1|0|0|0|1|shift:2|imm12:12|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"SUB <Wd|WSP>, <Wn|WSP>, #<imm>{, <shift>}","Code":"","Alias":""},
+{"Name":"SUB (immediate)","Bits":"1|1|0|1|0|0|0|1|shift:2|imm12:12|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SUB <Xd|SP>, <Xn|SP>, #<imm>{, <shift>}","Code":"","Alias":""},
+{"Name":"SUB (shifted register)","Bits":"0|1|0|0|1|0|1|1|shift:2|0|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"SUB <Wd>, <Wn>, <Wm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is used by the alias NEG (shifted register)."},
+{"Name":"SUB (shifted register)","Bits":"1|1|0|0|1|0|1|1|shift:2|0|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SUB <Xd>, <Xn>, <Xm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is used by the alias NEG (shifted register)."},
+{"Name":"SUBS (extended register)","Bits":"0|1|1|0|1|0|1|1|0|0|1|Rm:5|option:3|imm3:3|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"SUBS <Wd>, <Wn|WSP>, <Wm>{, <extend> {#<amount>}}","Code":"","Alias":"This instruction is used by the alias CMP (extended register)."},
+{"Name":"SUBS (extended register)","Bits":"1|1|1|0|1|0|1|1|0|0|1|Rm:5|option:3|imm3:3|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SUBS <Xd>, <Xn|SP>, <R><m>{, <extend> {#<amount>}}","Code":"","Alias":"This instruction is used by the alias CMP (extended register)."},
+{"Name":"SUBS (immediate)","Bits":"0|1|1|1|0|0|0|1|shift:2|imm12:12|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"SUBS <Wd>, <Wn|WSP>, #<imm>{, <shift>}","Code":"","Alias":"This instruction is used by the alias CMP (immediate)."},
+{"Name":"SUBS (immediate)","Bits":"1|1|1|1|0|0|0|1|shift:2|imm12:12|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SUBS <Xd>, <Xn|SP>, #<imm>{, <shift>}","Code":"","Alias":"This instruction is used by the alias CMP (immediate)."},
+{"Name":"SUBS (shifted register)","Bits":"0|1|1|0|1|0|1|1|shift:2|0|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"SUBS <Wd>, <Wn>, <Wm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is used by the aliases CMP (shifted register) and NEGS."},
+{"Name":"SUBS (shifted register)","Bits":"1|1|1|0|1|0|1|1|shift:2|0|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SUBS <Xd>, <Xn>, <Xm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is used by the aliases CMP (shifted register) and NEGS."},
+{"Name":"SVC","Bits":"1|1|0|1|0|1|0|0|0|0|0|imm16:16|0|0|0|0|1","Arch":"System variant","Syntax":"SVC #<imm>","Code":"","Alias":""},
+{"Name":"SXTB","Bits":"0|0|0|1|0|0|1|1|0|0|0|0|0|0|0|0|0|0|0|1|1|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"SXTB <Wd>, <Wn>","Code":"","Alias":"This instruction is an alias of the SBFM instruction."},
+{"Name":"SXTB","Bits":"1|0|0|1|0|0|1|1|0|1|0|0|0|0|0|0|0|0|0|1|1|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SXTB <Xd>, <Wn>","Code":"","Alias":"This instruction is an alias of the SBFM instruction."},
+{"Name":"SXTH","Bits":"0|0|0|1|0|0|1|1|0|0|0|0|0|0|0|0|0|0|1|1|1|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"SXTH <Wd>, <Wn>","Code":"","Alias":"This instruction is an alias of the SBFM instruction."},
+{"Name":"SXTH","Bits":"1|0|0|1|0|0|1|1|0|1|0|0|0|0|0|0|0|0|1|1|1|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SXTH <Xd>, <Wn>","Code":"","Alias":"This instruction is an alias of the SBFM instruction."},
+{"Name":"SXTW","Bits":"1|0|0|1|0|0|1|1|0|1|0|0|0|0|0|0|0|1|1|1|1|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SXTW <Xd>, <Wn>","Code":"","Alias":"This instruction is an alias of the SBFM instruction."},
+{"Name":"SYS","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|1|op1:3|CRn:4|CRm:4|op2:3|Rt:5","Arch":"System variant","Syntax":"SYS #<op1>, <Cn>, <Cm>, #<op2>{, <Xt>}","Code":"","Alias":"This instruction is used by the aliases AT, DC, IC, and TLBI."},
+{"Name":"SYSL","Bits":"1|1|0|1|0|1|0|1|0|0|1|0|1|op1:3|CRn:4|CRm:4|op2:3|Rt:5","Arch":"System variant","Syntax":"SYSL <Xt>, #<op1>, <Cn>, <Cm>, #<op2>","Code":"","Alias":""},
+{"Name":"TBNZ","Bits":"b5|0|1|1|0|1|1|1|b40:5|imm14:14|Rt:5","Arch":"14-bit signed PC-relative branch offset variant","Syntax":"TBNZ <R><t>, #<imm>, <label>","Code":"","Alias":""},
+{"Name":"TBZ","Bits":"b5|0|1|1|0|1|1|0|b40:5|imm14:14|Rt:5","Arch":"14-bit signed PC-relative branch offset variant","Syntax":"TBZ <R><t>, #<imm>, <label>","Code":"","Alias":""},
+{"Name":"TLBI","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|1|op1:3|1|0|0|0|CRm:4|op2:3|Rt:5","Arch":"System variant","Syntax":"TLBI <tlbi_op>{, <Xt>}","Code":"","Alias":"This instruction is an alias of the SYS instruction."},
+{"Name":"TST (immediate)","Bits":"0|1|1|1|0|0|1|0|0|0|immr:6|imms:6|Rn:5|1|1|1|1|1","Arch":"32-bit variant","Syntax":"TST <Wn>, #<imm>","Code":"","Alias":"This instruction is an alias of the ANDS (immediate) instruction."},
+{"Name":"TST (immediate)","Bits":"1|1|1|1|0|0|1|0|0|N|immr:6|imms:6|Rn:5|1|1|1|1|1","Arch":"64-bit variant","Syntax":"TST <Xn>, #<imm>","Code":"","Alias":"This instruction is an alias of the ANDS (immediate) instruction."},
+{"Name":"TST (shifted register)","Bits":"0|1|1|0|1|0|1|0|shift:2|0|Rm:5|imm6:6|Rn:5|1|1|1|1|1","Arch":"32-bit variant","Syntax":"TST <Wn>, <Wm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is an alias of the ANDS (shifted register) instruction."},
+{"Name":"TST (shifted register)","Bits":"1|1|1|0|1|0|1|0|shift:2|0|Rm:5|imm6:6|Rn:5|1|1|1|1|1","Arch":"64-bit variant","Syntax":"TST <Xn>, <Xm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is an alias of the ANDS (shifted register) instruction."},
+{"Name":"UBFIZ","Bits":"0|1|0|1|0|0|1|1|0|0|immr:6|imms:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"UBFIZ <Wd>, <Wn>, #<lsb>, #<width>","Code":"","Alias":"This instruction is an alias of the UBFM instruction."},
+{"Name":"UBFIZ","Bits":"1|1|0|1|0|0|1|1|0|1|immr:6|imms:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"UBFIZ <Xd>, <Xn>, #<lsb>, #<width>","Code":"","Alias":"This instruction is an alias of the UBFM instruction."},
+{"Name":"UBFM","Bits":"0|1|0|1|0|0|1|1|0|0|immr:6|imms:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"UBFM <Wd>, <Wn>, #<immr>, #<imms>","Code":"","Alias":"This instruction is used by the aliases LSL (immediate), LSR (immediate), UBFIZ, UBFX, UXTB, and UXTH."},
+{"Name":"UBFM","Bits":"1|1|0|1|0|0|1|1|0|1|immr:6|imms:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"UBFM <Xd>, <Xn>, #<immr>, #<imms>","Code":"","Alias":"This instruction is used by the aliases LSL (immediate), LSR (immediate), UBFIZ, UBFX, UXTB, and UXTH."},
+{"Name":"UBFX","Bits":"0|1|0|1|0|0|1|1|0|0|immr:6|imms:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"UBFX <Wd>, <Wn>, #<lsb>, #<width>","Code":"","Alias":"This instruction is an alias of the UBFM instruction."},
+{"Name":"UBFX","Bits":"1|1|0|1|0|0|1|1|0|1|immr:6|imms:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"UBFX <Xd>, <Xn>, #<lsb>, #<width>","Code":"","Alias":"This instruction is an alias of the UBFM instruction."},
+{"Name":"UDIV","Bits":"0|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|0|0|1|0|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"UDIV <Wd>, <Wn>, <Wm>","Code":"","Alias":""},
+{"Name":"UDIV","Bits":"1|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|0|0|1|0|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"UDIV <Xd>, <Xn>, <Xm>","Code":"","Alias":""},
+{"Name":"UMADDL","Bits":"1|0|0|1|1|0|1|1|1|0|1|Rm:5|0|Ra:5|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"UMADDL <Xd>, <Wn>, <Wm>, <Xa>","Code":"","Alias":"This instruction is used by the alias UMULL."},
+{"Name":"UMNEGL","Bits":"1|0|0|1|1|0|1|1|1|0|1|Rm:5|1|1|1|1|1|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"UMNEGL <Xd>, <Wn>, <Wm>","Code":"","Alias":"This instruction is an alias of the UMSUBL instruction."},
+{"Name":"UMSUBL","Bits":"1|0|0|1|1|0|1|1|1|0|1|Rm:5|1|Ra:5|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"UMSUBL <Xd>, <Wn>, <Wm>, <Xa>","Code":"","Alias":"This instruction is used by the alias UMNEGL."},
+{"Name":"UMULH","Bits":"1|0|0|1|1|0|1|1|1|1|0|Rm:5|0|(1)|(1)|(1)|(1)|(1)|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"UMULH <Xd>, <Xn>, <Xm>","Code":"","Alias":""},
+{"Name":"UMULL","Bits":"1|0|0|1|1|0|1|1|1|0|1|Rm:5|0|1|1|1|1|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"UMULL <Xd>, <Wn>, <Wm>","Code":"","Alias":"This instruction is an alias of the UMADDL instruction."},
+{"Name":"UXTB","Bits":"0|1|0|1|0|0|1|1|0|0|0|0|0|0|0|0|0|0|0|1|1|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"UXTB <Wd>, <Wn>","Code":"","Alias":"This instruction is an alias of the UBFM instruction."},
+{"Name":"UXTH","Bits":"0|1|0|1|0|0|1|1|0|0|0|0|0|0|0|0|0|0|1|1|1|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"UXTH <Wd>, <Wn>","Code":"","Alias":"This instruction is an alias of the UBFM instruction."},
+{"Name":"WFE","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|0|0|1|1|0|0|1|0|0|0|0|0|0|1|0|1|1|1|1|1","Arch":"System variant","Syntax":"WFE","Code":"","Alias":""},
+{"Name":"WFI","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|0|0|1|1|0|0|1|0|0|0|0|0|0|1|1|1|1|1|1|1","Arch":"System variant","Syntax":"WFI","Code":"","Alias":""},
+{"Name":"YIELD","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|0|0|1|1|0|0|1|0|0|0|0|0|0|0|1|1|1|1|1|1","Arch":"System variant","Syntax":"YIELD","Code":"","Alias":""},
+{"Name":"ABS","Bits":"0|1|0|1|1|1|1|0|size:2|1|0|0|0|0|0|1|0|1|1|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"ABS <V><d>, <V><n>","Code":"","Alias":""},
+{"Name":"ABS","Bits":"0|Q|0|0|1|1|1|0|size:2|1|0|0|0|0|0|1|0|1|1|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"ABS <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"ADD (vector)","Bits":"0|1|0|1|1|1|1|0|size:2|1|Rm:5|1|0|0|0|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"ADD <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"ADD (vector)","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|1|0|0|0|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"ADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"ADDHN, ADDHN2","Bits":"0|0|0|0|1|1|1|0|size:2|1|Rm:5|0|1|0|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"ADDHN <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>","Code":"","Alias":""},
+{"Name":"ADDHN, ADDHN2","Bits":"0|1|0|0|1|1|1|0|size:2|1|Rm:5|0|1|0|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"ADDHN2 <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>","Code":"","Alias":""},
+{"Name":"ADDP (scalar)","Bits":"0|1|0|1|1|1|1|0|size:2|1|1|0|0|0|1|1|0|1|1|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"ADDP <V><d>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"ADDP (vector)","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|1|0|1|1|1|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"ADDP <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"ADDV","Bits":"0|Q|0|0|1|1|1|0|size:2|1|1|0|0|0|1|1|0|1|1|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"ADDV <V><d>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"AESD","Bits":"0|1|0|0|1|1|1|0|0|0|1|0|1|0|0|0|0|1|0|1|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"AESD <Vd>.16B, <Vn>.16B","Code":"","Alias":""},
+{"Name":"AESE","Bits":"0|1|0|0|1|1|1|0|0|0|1|0|1|0|0|0|0|1|0|0|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"AESE <Vd>.16B, <Vn>.16B","Code":"","Alias":""},
+{"Name":"AESIMC","Bits":"0|1|0|0|1|1|1|0|0|0|1|0|1|0|0|0|0|1|1|1|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"AESIMC <Vd>.16B, <Vn>.16B","Code":"","Alias":""},
+{"Name":"AESMC","Bits":"0|1|0|0|1|1|1|0|0|0|1|0|1|0|0|0|0|1|1|0|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"AESMC <Vd>.16B, <Vn>.16B","Code":"","Alias":""},
+{"Name":"AND (vector)","Bits":"0|Q|0|0|1|1|1|0|0|0|1|Rm:5|0|0|0|1|1|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"AND <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"BIC (vector, immediate)","Bits":"0|Q|1|0|1|1|1|1|0|0|0|0|0|a|b|c|cmode:4|0|1|d|e|f|g|h|Rd:5","Arch":"16-bit variant","Syntax":"BIC <Vd>.<T>, #<imm8>{, LSL #<amount>}","Code":"","Alias":""},
+{"Name":"BIC (vector, immediate)","Bits":"0|Q|1|0|1|1|1|1|0|0|0|0|0|a|b|c|cmode:4|0|1|d|e|f|g|h|Rd:5","Arch":"32-bit variant","Syntax":"BIC <Vd>.<T>, #<imm8>{, LSL #<amount>}","Code":"","Alias":""},
+{"Name":"BIC (vector, register)","Bits":"0|Q|0|0|1|1|1|0|0|1|1|Rm:5|0|0|0|1|1|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"BIC <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"BIF","Bits":"0|Q|1|0|1|1|1|0|1|1|1|Rm:5|0|0|0|1|1|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"BIF <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"BIT","Bits":"0|Q|1|0|1|1|1|0|1|0|1|Rm:5|0|0|0|1|1|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"BIT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"BSL","Bits":"0|Q|1|0|1|1|1|0|0|1|1|Rm:5|0|0|0|1|1|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"BSL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"CLS (vector)","Bits":"0|Q|0|0|1|1|1|0|size:2|1|0|0|0|0|0|0|1|0|0|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"CLS <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"CLZ (vector)","Bits":"0|Q|1|0|1|1|1|0|size:2|1|0|0|0|0|0|0|1|0|0|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"CLZ <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"CMEQ (register)","Bits":"0|1|1|1|1|1|1|0|size:2|1|Rm:5|1|0|0|0|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"CMEQ <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"CMEQ (register)","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|1|0|0|0|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"CMEQ <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"CMEQ (zero)","Bits":"0|1|0|1|1|1|1|0|size:2|1|0|0|0|0|0|1|0|0|1|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"CMEQ <V><d>, <V><n>, #0","Code":"","Alias":""},
+{"Name":"CMEQ (zero)","Bits":"0|Q|0|0|1|1|1|0|size:2|1|0|0|0|0|0|1|0|0|1|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"CMEQ <Vd>.<T>, <Vn>.<T>, #0","Code":"","Alias":""},
+{"Name":"CMGE (register)","Bits":"0|1|0|1|1|1|1|0|size:2|1|Rm:5|0|0|1|1|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"CMGE <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"CMGE (register)","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|0|0|1|1|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"CMGE <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"CMGE (zero)","Bits":"0|1|1|1|1|1|1|0|size:2|1|0|0|0|0|0|1|0|0|0|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"CMGE <V><d>, <V><n>, #0","Code":"","Alias":""},
+{"Name":"CMGE (zero)","Bits":"0|Q|1|0|1|1|1|0|size:2|1|0|0|0|0|0|1|0|0|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"CMGE <Vd>.<T>, <Vn>.<T>, #0","Code":"","Alias":""},
+{"Name":"CMGT (register)","Bits":"0|1|0|1|1|1|1|0|size:2|1|Rm:5|0|0|1|1|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"CMGT <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"CMGT (register)","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|0|0|1|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"CMGT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"CMGT (zero)","Bits":"0|1|0|1|1|1|1|0|size:2|1|0|0|0|0|0|1|0|0|0|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"CMGT <V><d>, <V><n>, #0","Code":"","Alias":""},
+{"Name":"CMGT (zero)","Bits":"0|Q|0|0|1|1|1|0|size:2|1|0|0|0|0|0|1|0|0|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"CMGT <Vd>.<T>, <Vn>.<T>, #0","Code":"","Alias":""},
+{"Name":"CMHI (register)","Bits":"0|1|1|1|1|1|1|0|size:2|1|Rm:5|0|0|1|1|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"CMHI <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"CMHI (register)","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|0|0|1|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"CMHI <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"CMHS (register)","Bits":"0|1|1|1|1|1|1|0|size:2|1|Rm:5|0|0|1|1|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"CMHS <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"CMHS (register)","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|0|0|1|1|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"CMHS <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"CMLE (zero)","Bits":"0|1|1|1|1|1|1|0|size:2|1|0|0|0|0|0|1|0|0|1|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"CMLE <V><d>, <V><n>, #0","Code":"","Alias":""},
+{"Name":"CMLE (zero)","Bits":"0|Q|1|0|1|1|1|0|size:2|1|0|0|0|0|0|1|0|0|1|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"CMLE <Vd>.<T>, <Vn>.<T>, #0","Code":"","Alias":""},
+{"Name":"CMLT (zero)","Bits":"0|1|0|1|1|1|1|0|size:2|1|0|0|0|0|0|1|0|1|0|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"CMLT <V><d>, <V><n>, #0","Code":"","Alias":""},
+{"Name":"CMLT (zero)","Bits":"0|Q|0|0|1|1|1|0|size:2|1|0|0|0|0|0|1|0|1|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"CMLT <Vd>.<T>, <Vn>.<T>, #0","Code":"","Alias":""},
+{"Name":"CMTST","Bits":"0|1|0|1|1|1|1|0|size:2|1|Rm:5|1|0|0|0|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"CMTST <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"CMTST","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|1|0|0|0|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"CMTST <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"CNT","Bits":"0|Q|0|0|1|1|1|0|size:2|1|0|0|0|0|0|0|1|0|1|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"CNT <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"DUP (element)","Bits":"0|1|0|1|1|1|1|0|0|0|0|imm5:5|0|0|0|0|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"DUP <V><d>, <Vn>.<T>[<index>]","Code":"","Alias":"This instruction is used by the alias MOV (scalar)."},
+{"Name":"DUP (element)","Bits":"0|Q|0|0|1|1|1|0|0|0|0|imm5:5|0|0|0|0|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"DUP <Vd>.<T>, <Vn>.<Ts>[<index>]","Code":"","Alias":"This instruction is used by the alias MOV (scalar)."},
+{"Name":"DUP (general)","Bits":"0|Q|0|0|1|1|1|0|0|0|0|imm5:5|0|0|0|0|1|1|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"DUP <Vd>.<T>, <R><n>","Code":"","Alias":""},
+{"Name":"EOR (vector)","Bits":"0|Q|1|0|1|1|1|0|0|0|1|Rm:5|0|0|0|1|1|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"EOR <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"EXT","Bits":"0|Q|1|0|1|1|1|0|0|0|0|Rm:5|0|imm4:4|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"EXT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>, #<index>","Code":"","Alias":""},
+{"Name":"FABD","Bits":"0|1|1|1|1|1|1|0|1|sz|1|Rm:5|1|1|0|1|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FABD <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"FABD","Bits":"0|Q|1|0|1|1|1|0|1|sz|1|Rm:5|1|1|0|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FABD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"FABS (vector)","Bits":"0|Q|0|0|1|1|1|0|1|sz|1|0|0|0|0|0|1|1|1|1|1|0|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FABS <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
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+{"Name":"FABS (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|0|0|0|1|1|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FABS <Dd>, <Dn>","Code":"","Alias":""},
+{"Name":"FACGE","Bits":"0|1|1|1|1|1|1|0|0|sz|1|Rm:5|1|1|1|0|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FACGE <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"FACGE","Bits":"0|Q|1|0|1|1|1|0|0|sz|1|Rm:5|1|1|1|0|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FACGE <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"FACGT","Bits":"0|1|1|1|1|1|1|0|1|sz|1|Rm:5|1|1|1|0|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FACGT <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"FACGT","Bits":"0|Q|1|0|1|1|1|0|1|sz|1|Rm:5|1|1|1|0|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FACGT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"FADD (vector)","Bits":"0|Q|0|0|1|1|1|0|0|sz|1|Rm:5|1|1|0|1|0|1|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"FADD (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|Rm:5|0|0|1|0|1|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FADD <Sd>, <Sn>, <Sm>","Code":"","Alias":""},
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+{"Name":"FADDP (scalar)","Bits":"0|1|1|1|1|1|1|0|0|sz|1|1|0|0|0|0|1|1|0|1|1|0|Rn:5|Rd:5","Arch":"Single-precision and double-precision variant","Syntax":"FADDP <V><d>, <Vn>.<T>","Code":"","Alias":""},
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+{"Name":"FCCMP","Bits":"0|0|0|1|1|1|1|0|00:2|1|Rm:5|cond:4|0|1|Rn:5|0|nzcv:4","Arch":"Single-precision variant","Syntax":"FCCMP <Sn>, <Sm>, #<nzcv>, <cond>","Code":"","Alias":""},
+{"Name":"FCCMP","Bits":"0|0|0|1|1|1|1|0|01:2|1|Rm:5|cond:4|0|1|Rn:5|0|nzcv:4","Arch":"Double-precision variant","Syntax":"FCCMP <Dn>, <Dm>, #<nzcv>, <cond>","Code":"","Alias":""},
+{"Name":"FCCMPE","Bits":"0|0|0|1|1|1|1|0|00:2|1|Rm:5|cond:4|0|1|Rn:5|1|nzcv:4","Arch":"Single-precision variant","Syntax":"FCCMPE <Sn>, <Sm>, #<nzcv>, <cond>","Code":"","Alias":""},
+{"Name":"FCCMPE","Bits":"0|0|0|1|1|1|1|0|01:2|1|Rm:5|cond:4|0|1|Rn:5|1|nzcv:4","Arch":"Double-precision variant","Syntax":"FCCMPE <Dn>, <Dm>, #<nzcv>, <cond>","Code":"","Alias":""},
+{"Name":"FCMEQ (register)","Bits":"0|1|0|1|1|1|1|0|0|sz|1|Rm:5|1|1|1|0|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCMEQ <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"FCMEQ (register)","Bits":"0|Q|0|0|1|1|1|0|0|sz|1|Rm:5|1|1|1|0|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCMEQ <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"FCMEQ (zero)","Bits":"0|1|0|1|1|1|1|0|1|sz|1|0|0|0|0|0|1|1|0|1|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCMEQ <V><d>, <V><n>, #0.0","Code":"","Alias":""},
+{"Name":"FCMEQ (zero)","Bits":"0|Q|0|0|1|1|1|0|1|sz|1|0|0|0|0|0|1|1|0|1|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCMEQ <Vd>.<T>, <Vn>.<T>, #0.0","Code":"","Alias":""},
+{"Name":"FCMGE (register)","Bits":"0|1|1|1|1|1|1|0|0|sz|1|Rm:5|1|1|1|0|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCMGE <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
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+{"Name":"FCMGE (zero)","Bits":"0|1|1|1|1|1|1|0|1|sz|1|0|0|0|0|0|1|1|0|0|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCMGE <V><d>, <V><n>, #0.0","Code":"","Alias":""},
+{"Name":"FCMGE (zero)","Bits":"0|Q|1|0|1|1|1|0|1|sz|1|0|0|0|0|0|1|1|0|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCMGE <Vd>.<T>, <Vn>.<T>, #0.0","Code":"","Alias":""},
+{"Name":"FCMGT (register)","Bits":"0|1|1|1|1|1|1|0|1|sz|1|Rm:5|1|1|1|0|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCMGT <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
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+{"Name":"FCMGT (zero)","Bits":"0|1|0|1|1|1|1|0|1|sz|1|0|0|0|0|0|1|1|0|0|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCMGT <V><d>, <V><n>, #0.0","Code":"","Alias":""},
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+{"Name":"FCMLE (zero)","Bits":"0|1|1|1|1|1|1|0|1|sz|1|0|0|0|0|0|1|1|0|1|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCMLE <V><d>, <V><n>, #0.0","Code":"","Alias":""},
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+{"Name":"FCMLT (zero)","Bits":"0|1|0|1|1|1|1|0|1|sz|1|0|0|0|0|0|1|1|1|0|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCMLT <V><d>, <V><n>, #0.0","Code":"","Alias":""},
+{"Name":"FCMLT (zero)","Bits":"0|Q|0|0|1|1|1|0|1|sz|1|0|0|0|0|0|1|1|1|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCMLT <Vd>.<T>, <Vn>.<T>, #0.0","Code":"","Alias":""},
+{"Name":"FCMP","Bits":"0|0|0|1|1|1|1|0|00:2|1|Rm:5|0|0|1|0|0|0|Rn:5|00:2|0|0|0","Arch":"Single-precision variant","Syntax":"FCMP <Sn>, <Sm>","Code":"","Alias":""},
+{"Name":"FCMP","Bits":"0|0|0|1|1|1|1|0|00:2|1|(00000):5|0|0|1|0|0|0|Rn:5|01:2|0|0|0","Arch":"Single-precision, zero variant","Syntax":"FCMP <Sn>, #0.0","Code":"","Alias":""},
+{"Name":"FCMP","Bits":"0|0|0|1|1|1|1|0|01:2|1|Rm:5|0|0|1|0|0|0|Rn:5|00:2|0|0|0","Arch":"Double-precision variant","Syntax":"FCMP <Dn>, <Dm>","Code":"","Alias":""},
+{"Name":"FCMP","Bits":"0|0|0|1|1|1|1|0|01:2|1|(00000):5|0|0|1|0|0|0|Rn:5|01:2|0|0|0","Arch":"Double-precision, zero variant","Syntax":"FCMP <Dn>, #0.0","Code":"","Alias":""},
+{"Name":"FCMPE","Bits":"0|0|0|1|1|1|1|0|00:2|1|Rm:5|0|0|1|0|0|0|Rn:5|10:2|0|0|0","Arch":"Single-precision variant","Syntax":"FCMPE <Sn>, <Sm>","Code":"","Alias":""},
+{"Name":"FCMPE","Bits":"0|0|0|1|1|1|1|0|00:2|1|(00000):5|0|0|1|0|0|0|Rn:5|11:2|0|0|0","Arch":"Single-precision, zero variant","Syntax":"FCMPE <Sn>, #0.0","Code":"","Alias":""},
+{"Name":"FCMPE","Bits":"0|0|0|1|1|1|1|0|01:2|1|Rm:5|0|0|1|0|0|0|Rn:5|10:2|0|0|0","Arch":"Double-precision variant","Syntax":"FCMPE <Dn>, <Dm>","Code":"","Alias":""},
+{"Name":"FCMPE","Bits":"0|0|0|1|1|1|1|0|01:2|1|(00000):5|0|0|1|0|0|0|Rn:5|11:2|0|0|0","Arch":"Double-precision, zero variant","Syntax":"FCMPE <Dn>, #0.0","Code":"","Alias":""},
+{"Name":"FCSEL","Bits":"0|0|0|1|1|1|1|0|00:2|1|Rm:5|cond:4|1|1|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FCSEL <Sd>, <Sn>, <Sm>, <cond>","Code":"","Alias":""},
+{"Name":"FCSEL","Bits":"0|0|0|1|1|1|1|0|01:2|1|Rm:5|cond:4|1|1|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FCSEL <Dd>, <Dn>, <Dm>, <cond>","Code":"","Alias":""},
+{"Name":"FCVT","Bits":"0|0|0|1|1|1|1|0|11:2|1|0|0|0|1|00:2|1|0|0|0|0|Rn:5|Rd:5","Arch":"Half-precision to single-precision variant","Syntax":"FCVT <Sd>, <Hn>","Code":"","Alias":""},
+{"Name":"FCVT","Bits":"0|0|0|1|1|1|1|0|11:2|1|0|0|0|1|01:2|1|0|0|0|0|Rn:5|Rd:5","Arch":"Half-precision to double-precision variant","Syntax":"FCVT <Dd>, <Hn>","Code":"","Alias":""},
+{"Name":"FCVT","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|0|0|1|11:2|1|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to half-precision variant","Syntax":"FCVT <Hd>, <Sn>","Code":"","Alias":""},
+{"Name":"FCVT","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|0|0|1|01:2|1|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to double-precision variant","Syntax":"FCVT <Dd>, <Sn>","Code":"","Alias":""},
+{"Name":"FCVT","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|0|1|11:2|1|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to half-precision variant","Syntax":"FCVT <Hd>, <Dn>","Code":"","Alias":""},
+{"Name":"FCVT","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|0|1|00:2|1|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to single-precision variant","Syntax":"FCVT <Sd>, <Dn>","Code":"","Alias":""},
+{"Name":"FCVTAS (vector)","Bits":"0|1|0|1|1|1|1|0|0|sz|1|0|0|0|0|1|1|1|0|0|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCVTAS <V><d>, <V><n>","Code":"","Alias":""},
+{"Name":"FCVTAS (vector)","Bits":"0|Q|0|0|1|1|1|0|0|sz|1|0|0|0|0|1|1|1|0|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCVTAS <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"FCVTAS (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|0|1|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 32-bit variant","Syntax":"FCVTAS <Wd>, <Sn>","Code":"","Alias":""},
+{"Name":"FCVTAS (scalar)","Bits":"1|0|0|1|1|1|1|0|00:2|1|0|0|1|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 64-bit variant","Syntax":"FCVTAS <Xd>, <Sn>","Code":"","Alias":""},
+{"Name":"FCVTAS (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|1|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 32-bit variant","Syntax":"FCVTAS <Wd>, <Dn>","Code":"","Alias":""},
+{"Name":"FCVTAS (scalar)","Bits":"1|0|0|1|1|1|1|0|01:2|1|0|0|1|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 64-bit variant","Syntax":"FCVTAS <Xd>, <Dn>","Code":"","Alias":""},
+{"Name":"FCVTAU (vector)","Bits":"0|1|1|1|1|1|1|0|0|sz|1|0|0|0|0|1|1|1|0|0|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCVTAU <V><d>, <V><n>","Code":"","Alias":""},
+{"Name":"FCVTAU (vector)","Bits":"0|Q|1|0|1|1|1|0|0|sz|1|0|0|0|0|1|1|1|0|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCVTAU <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"FCVTAU (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|0|1|0|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 32-bit variant","Syntax":"FCVTAU <Wd>, <Sn>","Code":"","Alias":""},
+{"Name":"FCVTAU (scalar)","Bits":"1|0|0|1|1|1|1|0|00:2|1|0|0|1|0|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 64-bit variant","Syntax":"FCVTAU <Xd>, <Sn>","Code":"","Alias":""},
+{"Name":"FCVTAU (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|1|0|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 32-bit variant","Syntax":"FCVTAU <Wd>, <Dn>","Code":"","Alias":""},
+{"Name":"FCVTAU (scalar)","Bits":"1|0|0|1|1|1|1|0|01:2|1|0|0|1|0|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 64-bit variant","Syntax":"FCVTAU <Xd>, <Dn>","Code":"","Alias":""},
+{"Name":"FCVTL, FCVTL2","Bits":"0|0|0|0|1|1|1|0|0|sz|1|0|0|0|0|1|0|1|1|1|1|0|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FCVTL <Vd>.<Ta>, <Vn>.<Tb>","Code":"","Alias":""},
+{"Name":"FCVTL, FCVTL2","Bits":"0|1|0|0|1|1|1|0|0|sz|1|0|0|0|0|1|0|1|1|1|1|0|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FCVTL2 <Vd>.<Ta>, <Vn>.<Tb>","Code":"","Alias":""},
+{"Name":"FCVTMS (vector)","Bits":"0|1|0|1|1|1|1|0|0|sz|1|0|0|0|0|1|1|0|1|1|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCVTMS <V><d>, <V><n>","Code":"","Alias":""},
+{"Name":"FCVTMS (vector)","Bits":"0|Q|0|0|1|1|1|0|0|sz|1|0|0|0|0|1|1|0|1|1|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCVTMS <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"FCVTMS (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|1|0|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 32-bit variant","Syntax":"FCVTMS <Wd>, <Sn>","Code":"","Alias":""},
+{"Name":"FCVTMS (scalar)","Bits":"1|0|0|1|1|1|1|0|00:2|1|1|0|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 64-bit variant","Syntax":"FCVTMS <Xd>, <Sn>","Code":"","Alias":""},
+{"Name":"FCVTMS (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|1|0|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 32-bit variant","Syntax":"FCVTMS <Wd>, <Dn>","Code":"","Alias":""},
+{"Name":"FCVTMS (scalar)","Bits":"1|0|0|1|1|1|1|0|01:2|1|1|0|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 64-bit variant","Syntax":"FCVTMS <Xd>, <Dn>","Code":"","Alias":""},
+{"Name":"FCVTMU (vector)","Bits":"0|1|1|1|1|1|1|0|0|sz|1|0|0|0|0|1|1|0|1|1|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCVTMU <V><d>, <V><n>","Code":"","Alias":""},
+{"Name":"FCVTMU (vector)","Bits":"0|Q|1|0|1|1|1|0|0|sz|1|0|0|0|0|1|1|0|1|1|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCVTMU <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"FCVTMU (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|1|0|0|0|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 32-bit variant","Syntax":"FCVTMU <Wd>, <Sn>","Code":"","Alias":""},
+{"Name":"FCVTMU (scalar)","Bits":"1|0|0|1|1|1|1|0|00:2|1|1|0|0|0|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 64-bit variant","Syntax":"FCVTMU <Xd>, <Sn>","Code":"","Alias":""},
+{"Name":"FCVTMU (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|1|0|0|0|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 32-bit variant","Syntax":"FCVTMU <Wd>, <Dn>","Code":"","Alias":""},
+{"Name":"FCVTMU (scalar)","Bits":"1|0|0|1|1|1|1|0|01:2|1|1|0|0|0|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 64-bit variant","Syntax":"FCVTMU <Xd>, <Dn>","Code":"","Alias":""},
+{"Name":"FCVTN, FCVTN2","Bits":"0|0|0|0|1|1|1|0|0|sz|1|0|0|0|0|1|0|1|1|0|1|0|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FCVTN <Vd>.<Tb>, <Vn>.<Ta>","Code":"","Alias":""},
+{"Name":"FCVTN, FCVTN2","Bits":"0|1|0|0|1|1|1|0|0|sz|1|0|0|0|0|1|0|1|1|0|1|0|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FCVTN2 <Vd>.<Tb>, <Vn>.<Ta>","Code":"","Alias":""},
+{"Name":"FCVTNS (vector)","Bits":"0|1|0|1|1|1|1|0|0|sz|1|0|0|0|0|1|1|0|1|0|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCVTNS <V><d>, <V><n>","Code":"","Alias":""},
+{"Name":"FCVTNS (vector)","Bits":"0|Q|0|0|1|1|1|0|0|sz|1|0|0|0|0|1|1|0|1|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCVTNS <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"FCVTNS (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|0|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 32-bit variant","Syntax":"FCVTNS <Wd>, <Sn>","Code":"","Alias":""},
+{"Name":"FCVTNS (scalar)","Bits":"1|0|0|1|1|1|1|0|00:2|1|0|0|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 64-bit variant","Syntax":"FCVTNS <Xd>, <Sn>","Code":"","Alias":""},
+{"Name":"FCVTNS (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 32-bit variant","Syntax":"FCVTNS <Wd>, <Dn>","Code":"","Alias":""},
+{"Name":"FCVTNS (scalar)","Bits":"1|0|0|1|1|1|1|0|01:2|1|0|0|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 64-bit variant","Syntax":"FCVTNS <Xd>, <Dn>","Code":"","Alias":""},
+{"Name":"FCVTNU (vector)","Bits":"0|1|1|1|1|1|1|0|0|sz|1|0|0|0|0|1|1|0|1|0|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCVTNU <V><d>, <V><n>","Code":"","Alias":""},
+{"Name":"FCVTNU (vector)","Bits":"0|Q|1|0|1|1|1|0|0|sz|1|0|0|0|0|1|1|0|1|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCVTNU <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"FCVTNU (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|0|0|0|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 32-bit variant","Syntax":"FCVTNU <Wd>, <Sn>","Code":"","Alias":""},
+{"Name":"FCVTNU (scalar)","Bits":"1|0|0|1|1|1|1|0|00:2|1|0|0|0|0|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 64-bit variant","Syntax":"FCVTNU <Xd>, <Sn>","Code":"","Alias":""},
+{"Name":"FCVTNU (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|0|0|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 32-bit variant","Syntax":"FCVTNU <Wd>, <Dn>","Code":"","Alias":""},
+{"Name":"FCVTNU (scalar)","Bits":"1|0|0|1|1|1|1|0|01:2|1|0|0|0|0|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 64-bit variant","Syntax":"FCVTNU <Xd>, <Dn>","Code":"","Alias":""},
+{"Name":"FCVTPS (vector)","Bits":"0|1|0|1|1|1|1|0|1|sz|1|0|0|0|0|1|1|0|1|0|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCVTPS <V><d>, <V><n>","Code":"","Alias":""},
+{"Name":"FCVTPS (vector)","Bits":"0|Q|0|0|1|1|1|0|1|sz|1|0|0|0|0|1|1|0|1|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCVTPS <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"FCVTPS (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|1|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 32-bit variant","Syntax":"FCVTPS <Wd>, <Sn>","Code":"","Alias":""},
+{"Name":"FCVTPS (scalar)","Bits":"1|0|0|1|1|1|1|0|00:2|1|0|1|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 64-bit variant","Syntax":"FCVTPS <Xd>, <Sn>","Code":"","Alias":""},
+{"Name":"FCVTPS (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|1|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 32-bit variant","Syntax":"FCVTPS <Wd>, <Dn>","Code":"","Alias":""},
+{"Name":"FCVTPS (scalar)","Bits":"1|0|0|1|1|1|1|0|01:2|1|0|1|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 64-bit variant","Syntax":"FCVTPS <Xd>, <Dn>","Code":"","Alias":""},
+{"Name":"FCVTPU (vector)","Bits":"0|1|1|1|1|1|1|0|1|sz|1|0|0|0|0|1|1|0|1|0|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCVTPU <V><d>, <V><n>","Code":"","Alias":""},
+{"Name":"FCVTPU (vector)","Bits":"0|Q|1|0|1|1|1|0|1|sz|1|0|0|0|0|1|1|0|1|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCVTPU <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"FCVTPU (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|1|0|0|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 32-bit variant","Syntax":"FCVTPU <Wd>, <Sn>","Code":"","Alias":""},
+{"Name":"FCVTPU (scalar)","Bits":"1|0|0|1|1|1|1|0|00:2|1|0|1|0|0|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 64-bit variant","Syntax":"FCVTPU <Xd>, <Sn>","Code":"","Alias":""},
+{"Name":"FCVTPU (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|1|0|0|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 32-bit variant","Syntax":"FCVTPU <Wd>, <Dn>","Code":"","Alias":""},
+{"Name":"FCVTPU (scalar)","Bits":"1|0|0|1|1|1|1|0|01:2|1|0|1|0|0|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 64-bit variant","Syntax":"FCVTPU <Xd>, <Dn>","Code":"","Alias":""},
+{"Name":"FCVTXN, FCVTXN2","Bits":"0|1|1|1|1|1|1|0|0|sz|1|0|0|0|0|1|0|1|1|0|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCVTXN <Vb><d>, <Va><n>","Code":"","Alias":""},
+{"Name":"FCVTXN, FCVTXN2","Bits":"0|0|1|0|1|1|1|0|0|sz|1|0|0|0|0|1|0|1|1|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCVTXN <Vd>.<Tb>, <Vn>.<Ta>","Code":"","Alias":""},
+{"Name":"FCVTXN, FCVTXN2","Bits":"0|1|1|0|1|1|1|0|0|sz|1|0|0|0|0|1|0|1|1|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCVTXN2 <Vd>.<Tb>, <Vn>.<Ta>","Code":"","Alias":""},
+{"Name":"FCVTZS (vector, fixed-point)","Bits":"0|1|0|1|1|1|1|1|0|immh:4|immb:3|1|1|1|1|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCVTZS <V><d>, <V><n>, #<fbits>","Code":"","Alias":""},
+{"Name":"FCVTZS (vector, fixed-point)","Bits":"0|Q|0|0|1|1|1|1|0|immh:4|immb:3|1|1|1|1|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCVTZS <Vd>.<T>, <Vn>.<T>, #<fbits>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"FCVTZS (vector, integer)","Bits":"0|1|0|1|1|1|1|0|1|sz|1|0|0|0|0|1|1|0|1|1|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCVTZS <V><d>, <V><n>","Code":"","Alias":""},
+{"Name":"FCVTZS (vector, integer)","Bits":"0|Q|0|0|1|1|1|0|1|sz|1|0|0|0|0|1|1|0|1|1|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCVTZS <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"FCVTZS (scalar, fixed-point)","Bits":"0|0|0|1|1|1|1|0|00:2|0|1|1|0|0|0|scale:6|Rn:5|Rd:5","Arch":"Single-precision to 32-bit variant","Syntax":"FCVTZS <Wd>, <Sn>, #<fbits>","Code":"","Alias":""},
+{"Name":"FCVTZS (scalar, fixed-point)","Bits":"1|0|0|1|1|1|1|0|00:2|0|1|1|0|0|0|scale:6|Rn:5|Rd:5","Arch":"Single-precision to 64-bit variant","Syntax":"FCVTZS <Xd>, <Sn>, #<fbits>","Code":"","Alias":""},
+{"Name":"FCVTZS (scalar, fixed-point)","Bits":"0|0|0|1|1|1|1|0|01:2|0|1|1|0|0|0|scale:6|Rn:5|Rd:5","Arch":"Double-precision to 32-bit variant","Syntax":"FCVTZS <Wd>, <Dn>, #<fbits>","Code":"","Alias":""},
+{"Name":"FCVTZS (scalar, fixed-point)","Bits":"1|0|0|1|1|1|1|0|01:2|0|1|1|0|0|0|scale:6|Rn:5|Rd:5","Arch":"Double-precision to 64-bit variant","Syntax":"FCVTZS <Xd>, <Dn>, #<fbits>","Code":"","Alias":""},
+{"Name":"FCVTZS (scalar, integer)","Bits":"0|0|0|1|1|1|1|0|00:2|1|1|1|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 32-bit variant","Syntax":"FCVTZS <Wd>, <Sn>","Code":"","Alias":""},
+{"Name":"FCVTZS (scalar, integer)","Bits":"1|0|0|1|1|1|1|0|00:2|1|1|1|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 64-bit variant","Syntax":"FCVTZS <Xd>, <Sn>","Code":"","Alias":""},
+{"Name":"FCVTZS (scalar, integer)","Bits":"0|0|0|1|1|1|1|0|01:2|1|1|1|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 32-bit variant","Syntax":"FCVTZS <Wd>, <Dn>","Code":"","Alias":""},
+{"Name":"FCVTZS (scalar, integer)","Bits":"1|0|0|1|1|1|1|0|01:2|1|1|1|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 64-bit variant","Syntax":"FCVTZS <Xd>, <Dn>","Code":"","Alias":""},
+{"Name":"FCVTZU (vector, fixed-point)","Bits":"0|1|1|1|1|1|1|1|0|immh:4|immb:3|1|1|1|1|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCVTZU <V><d>, <V><n>, #<fbits>","Code":"","Alias":""},
+{"Name":"FCVTZU (vector, fixed-point)","Bits":"0|Q|1|0|1|1|1|1|0|immh:4|immb:3|1|1|1|1|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCVTZU <Vd>.<T>, <Vn>.<T>, #<fbits>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"FCVTZU (vector, integer)","Bits":"0|1|1|1|1|1|1|0|1|sz|1|0|0|0|0|1|1|0|1|1|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCVTZU <V><d>, <V><n>","Code":"","Alias":""},
+{"Name":"FCVTZU (vector, integer)","Bits":"0|Q|1|0|1|1|1|0|1|sz|1|0|0|0|0|1|1|0|1|1|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCVTZU <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"FCVTZU (scalar, fixed-point)","Bits":"0|0|0|1|1|1|1|0|00:2|0|1|1|0|0|1|scale:6|Rn:5|Rd:5","Arch":"Single-precision to 32-bit variant","Syntax":"FCVTZU <Wd>, <Sn>, #<fbits>","Code":"","Alias":""},
+{"Name":"FCVTZU (scalar, fixed-point)","Bits":"1|0|0|1|1|1|1|0|00:2|0|1|1|0|0|1|scale:6|Rn:5|Rd:5","Arch":"Single-precision to 64-bit variant","Syntax":"FCVTZU <Xd>, <Sn>, #<fbits>","Code":"","Alias":""},
+{"Name":"FCVTZU (scalar, fixed-point)","Bits":"0|0|0|1|1|1|1|0|01:2|0|1|1|0|0|1|scale:6|Rn:5|Rd:5","Arch":"Double-precision to 32-bit variant","Syntax":"FCVTZU <Wd>, <Dn>, #<fbits>","Code":"","Alias":""},
+{"Name":"FCVTZU (scalar, fixed-point)","Bits":"1|0|0|1|1|1|1|0|01:2|0|1|1|0|0|1|scale:6|Rn:5|Rd:5","Arch":"Double-precision to 64-bit variant","Syntax":"FCVTZU <Xd>, <Dn>, #<fbits>","Code":"","Alias":""},
+{"Name":"FCVTZU (scalar, integer)","Bits":"0|0|0|1|1|1|1|0|00:2|1|1|1|0|0|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 32-bit variant","Syntax":"FCVTZU <Wd>, <Sn>","Code":"","Alias":""},
+{"Name":"FCVTZU (scalar, integer)","Bits":"1|0|0|1|1|1|1|0|00:2|1|1|1|0|0|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 64-bit variant","Syntax":"FCVTZU <Xd>, <Sn>","Code":"","Alias":""},
+{"Name":"FCVTZU (scalar, integer)","Bits":"0|0|0|1|1|1|1|0|01:2|1|1|1|0|0|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 32-bit variant","Syntax":"FCVTZU <Wd>, <Dn>","Code":"","Alias":""},
+{"Name":"FCVTZU (scalar, integer)","Bits":"1|0|0|1|1|1|1|0|01:2|1|1|1|0|0|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 64-bit variant","Syntax":"FCVTZU <Xd>, <Dn>","Code":"","Alias":""},
+{"Name":"FDIV (vector)","Bits":"0|Q|1|0|1|1|1|0|0|sz|1|Rm:5|1|1|1|1|1|1|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FDIV <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"FDIV (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|Rm:5|0|0|0|1|1|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FDIV <Sd>, <Sn>, <Sm>","Code":"","Alias":""},
+{"Name":"FDIV (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|Rm:5|0|0|0|1|1|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FDIV <Dd>, <Dn>, <Dm>","Code":"","Alias":""},
+{"Name":"FMADD","Bits":"0|0|0|1|1|1|1|1|00:2|0|Rm:5|0|Ra:5|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FMADD <Sd>, <Sn>, <Sm>, <Sa>","Code":"","Alias":""},
+{"Name":"FMADD","Bits":"0|0|0|1|1|1|1|1|01:2|0|Rm:5|0|Ra:5|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FMADD <Dd>, <Dn>, <Dm>, <Da>","Code":"","Alias":""},
+{"Name":"FMAX (vector)","Bits":"0|Q|0|0|1|1|1|0|0|sz|1|Rm:5|1|1|1|1|0|1|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FMAX <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"FMAX (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|Rm:5|0|1|0|0|1|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FMAX <Sd>, <Sn>, <Sm>","Code":"","Alias":""},
+{"Name":"FMAX (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|Rm:5|0|1|0|0|1|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FMAX <Dd>, <Dn>, <Dm>","Code":"","Alias":""},
+{"Name":"FMAXNM (vector)","Bits":"0|Q|0|0|1|1|1|0|0|sz|1|Rm:5|1|1|0|0|0|1|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FMAXNM <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"FMAXNM (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|Rm:5|0|1|1|0|1|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FMAXNM <Sd>, <Sn>, <Sm>","Code":"","Alias":""},
+{"Name":"FMAXNM (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|Rm:5|0|1|1|0|1|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FMAXNM <Dd>, <Dn>, <Dm>","Code":"","Alias":""},
+{"Name":"FMAXNMP (scalar)","Bits":"0|1|1|1|1|1|1|0|0|sz|1|1|0|0|0|0|1|1|0|0|1|0|Rn:5|Rd:5","Arch":"Single-precision and double-precision variant","Syntax":"FMAXNMP <V><d>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"FMAXNMP (vector)","Bits":"0|Q|1|0|1|1|1|0|0|sz|1|Rm:5|1|1|0|0|0|1|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FMAXNMP <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"FMAXNMV","Bits":"0|Q|1|0|1|1|1|0|0|sz|1|1|0|0|0|0|1|1|0|0|1|0|Rn:5|Rd:5","Arch":"Single-precision and double-precision variant","Syntax":"FMAXNMV <V><d>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"FMAXP (scalar)","Bits":"0|1|1|1|1|1|1|0|0|sz|1|1|0|0|0|0|1|1|1|1|1|0|Rn:5|Rd:5","Arch":"Single-precision and double-precision variant","Syntax":"FMAXP <V><d>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"FMAXP (vector)","Bits":"0|Q|1|0|1|1|1|0|0|sz|1|Rm:5|1|1|1|1|0|1|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FMAXP <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"FMAXV","Bits":"0|Q|1|0|1|1|1|0|0|sz|1|1|0|0|0|0|1|1|1|1|1|0|Rn:5|Rd:5","Arch":"Single-precision and double-precision variant","Syntax":"FMAXV <V><d>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"FMIN (vector)","Bits":"0|Q|0|0|1|1|1|0|1|sz|1|Rm:5|1|1|1|1|0|1|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FMIN <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"FMIN (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|Rm:5|0|1|0|1|1|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FMIN <Sd>, <Sn>, <Sm>","Code":"","Alias":""},
+{"Name":"FMIN (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|Rm:5|0|1|0|1|1|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FMIN <Dd>, <Dn>, <Dm>","Code":"","Alias":""},
+{"Name":"FMINNM (vector)","Bits":"0|Q|0|0|1|1|1|0|1|sz|1|Rm:5|1|1|0|0|0|1|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FMINNM <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"FMINNM (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|Rm:5|0|1|1|1|1|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FMINNM <Sd>, <Sn>, <Sm>","Code":"","Alias":""},
+{"Name":"FMINNM (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|Rm:5|0|1|1|1|1|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FMINNM <Dd>, <Dn>, <Dm>","Code":"","Alias":""},
+{"Name":"FMINNMP (scalar)","Bits":"0|1|1|1|1|1|1|0|1|sz|1|1|0|0|0|0|1|1|0|0|1|0|Rn:5|Rd:5","Arch":"Single-precision and double-precision variant","Syntax":"FMINNMP <V><d>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"FMINNMP (vector)","Bits":"0|Q|1|0|1|1|1|0|1|sz|1|Rm:5|1|1|0|0|0|1|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FMINNMP <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"FMINNMV","Bits":"0|Q|1|0|1|1|1|0|1|sz|1|1|0|0|0|0|1|1|0|0|1|0|Rn:5|Rd:5","Arch":"Single-precision and double-precision variant","Syntax":"FMINNMV <V><d>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"FMINP (scalar)","Bits":"0|1|1|1|1|1|1|0|1|sz|1|1|0|0|0|0|1|1|1|1|1|0|Rn:5|Rd:5","Arch":"Single-precision and double-precision variant","Syntax":"FMINP <V><d>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"FMINP (vector)","Bits":"0|Q|1|0|1|1|1|0|1|sz|1|Rm:5|1|1|1|1|0|1|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FMINP <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"FMINV","Bits":"0|Q|1|0|1|1|1|0|1|sz|1|1|0|0|0|0|1|1|1|1|1|0|Rn:5|Rd:5","Arch":"Single-precision and double-precision variant","Syntax":"FMINV <V><d>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"FMLA (by element)","Bits":"0|1|0|1|1|1|1|1|1|sz|L|M|Rm:4|0|0|0|1|H|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FMLA <V><d>, <V><n>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"FMLA (by element)","Bits":"0|Q|0|0|1|1|1|1|1|sz|L|M|Rm:4|0|0|0|1|H|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"FMLA (vector)","Bits":"0|Q|0|0|1|1|1|0|0|sz|1|Rm:5|1|1|0|0|1|1|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"FMLS (by element)","Bits":"0|1|0|1|1|1|1|1|1|sz|L|M|Rm:4|0|1|0|1|H|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FMLS <V><d>, <V><n>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"FMLS (by element)","Bits":"0|Q|0|0|1|1|1|1|1|sz|L|M|Rm:4|0|1|0|1|H|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FMLS <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"FMLS (vector)","Bits":"0|Q|0|0|1|1|1|0|1|sz|1|Rm:5|1|1|0|0|1|1|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FMLS <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"FMOV (vector, immediate)","Bits":"0|Q|0|0|1|1|1|1|0|0|0|0|0|a|b|c|1|1|1|1|0|1|d|e|f|g|h|Rd:5","Arch":"Single-precision variant","Syntax":"FMOV <Vd>.<T>, #<imm>","Code":"","Alias":""},
+{"Name":"FMOV (vector, immediate)","Bits":"0|1|1|0|1|1|1|1|0|0|0|0|0|a|b|c|1|1|1|1|0|1|d|e|f|g|h|Rd:5","Arch":"Double-precision variant","Syntax":"FMOV <Vd>.2D, #<imm>","Code":"","Alias":""},
+{"Name":"FMOV (register)","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|0|0|0|0|0|1|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FMOV <Sd>, <Sn>","Code":"","Alias":""},
+{"Name":"FMOV (register)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|0|0|0|0|1|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FMOV <Dd>, <Dn>","Code":"","Alias":""},
+{"Name":"FMOV (general)","Bits":"0|0|0|1|1|1|1|0|00:2|1|00:2|111:3|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"32-bit to single-precision variant","Syntax":"FMOV <Sd>, <Wn>","Code":"","Alias":""},
+{"Name":"FMOV (general)","Bits":"0|0|0|1|1|1|1|0|00:2|1|00:2|110:3|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 32-bit variant","Syntax":"FMOV <Wd>, <Sn>","Code":"","Alias":""},
+{"Name":"FMOV (general)","Bits":"1|0|0|1|1|1|1|0|01:2|1|00:2|111:3|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"64-bit to double-precision variant","Syntax":"FMOV <Dd>, <Xn>","Code":"","Alias":""},
+{"Name":"FMOV (general)","Bits":"1|0|0|1|1|1|1|0|10:2|1|01:2|111:3|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"64-bit to top half of 128-bit variant","Syntax":"FMOV <Vd>.D[1], <Xn>","Code":"","Alias":""},
+{"Name":"FMOV (general)","Bits":"1|0|0|1|1|1|1|0|01:2|1|00:2|110:3|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 64-bit variant","Syntax":"FMOV <Xd>, <Dn>","Code":"","Alias":""},
+{"Name":"FMOV (general)","Bits":"1|0|0|1|1|1|1|0|10:2|1|01:2|110:3|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Top half of 128-bit to 64-bit variant","Syntax":"FMOV <Xd>, <Vn>.D[1]","Code":"","Alias":""},
+{"Name":"FMOV (scalar, immediate)","Bits":"0|0|0|1|1|1|1|0|00:2|1|imm8:8|1|0|0|0|0|0|0|0|Rd:5","Arch":"Single-precision variant","Syntax":"FMOV <Sd>, #<imm>","Code":"","Alias":""},
+{"Name":"FMOV (scalar, immediate)","Bits":"0|0|0|1|1|1|1|0|01:2|1|imm8:8|1|0|0|0|0|0|0|0|Rd:5","Arch":"Double-precision variant","Syntax":"FMOV <Dd>, #<imm>","Code":"","Alias":""},
+{"Name":"FMSUB","Bits":"0|0|0|1|1|1|1|1|00:2|0|Rm:5|1|Ra:5|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FMSUB <Sd>, <Sn>, <Sm>, <Sa>","Code":"","Alias":""},
+{"Name":"FMSUB","Bits":"0|0|0|1|1|1|1|1|01:2|0|Rm:5|1|Ra:5|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FMSUB <Dd>, <Dn>, <Dm>, <Da>","Code":"","Alias":""},
+{"Name":"FMUL (by element)","Bits":"0|1|0|1|1|1|1|1|1|sz|L|M|Rm:4|1|0|0|1|H|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FMUL <V><d>, <V><n>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"FMUL (by element)","Bits":"0|Q|0|0|1|1|1|1|1|sz|L|M|Rm:4|1|0|0|1|H|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FMUL <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"FMUL (vector)","Bits":"0|Q|1|0|1|1|1|0|0|sz|1|Rm:5|1|1|0|1|1|1|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FMUL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"FMUL (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|Rm:5|0|0|0|0|1|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FMUL <Sd>, <Sn>, <Sm>","Code":"","Alias":""},
+{"Name":"FMUL (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|Rm:5|0|0|0|0|1|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FMUL <Dd>, <Dn>, <Dm>","Code":"","Alias":""},
+{"Name":"FMULX (by element)","Bits":"0|1|1|1|1|1|1|1|1|sz|L|M|Rm:4|1|0|0|1|H|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FMULX <V><d>, <V><n>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"FMULX (by element)","Bits":"0|Q|1|0|1|1|1|1|1|sz|L|M|Rm:4|1|0|0|1|H|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FMULX <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"FMULX","Bits":"0|1|0|1|1|1|1|0|0|sz|1|Rm:5|1|1|0|1|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FMULX <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"FMULX","Bits":"0|Q|0|0|1|1|1|0|0|sz|1|Rm:5|1|1|0|1|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FMULX <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"FNEG (vector)","Bits":"0|Q|1|0|1|1|1|0|1|sz|1|0|0|0|0|0|1|1|1|1|1|0|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FNEG <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"FNEG (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|0|0|0|1|0|1|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FNEG <Sd>, <Sn>","Code":"","Alias":""},
+{"Name":"FNEG (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|0|0|1|0|1|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FNEG <Dd>, <Dn>","Code":"","Alias":""},
+{"Name":"FNMADD","Bits":"0|0|0|1|1|1|1|1|00:2|1|Rm:5|0|Ra:5|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FNMADD <Sd>, <Sn>, <Sm>, <Sa>","Code":"","Alias":""},
+{"Name":"FNMADD","Bits":"0|0|0|1|1|1|1|1|01:2|1|Rm:5|0|Ra:5|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FNMADD <Dd>, <Dn>, <Dm>, <Da>","Code":"","Alias":""},
+{"Name":"FNMSUB","Bits":"0|0|0|1|1|1|1|1|00:2|1|Rm:5|1|Ra:5|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FNMSUB <Sd>, <Sn>, <Sm>, <Sa>","Code":"","Alias":""},
+{"Name":"FNMSUB","Bits":"0|0|0|1|1|1|1|1|01:2|1|Rm:5|1|Ra:5|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FNMSUB <Dd>, <Dn>, <Dm>, <Da>","Code":"","Alias":""},
+{"Name":"FNMUL (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|Rm:5|1|0|0|0|1|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FNMUL <Sd>, <Sn>, <Sm>","Code":"","Alias":""},
+{"Name":"FNMUL (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|Rm:5|1|0|0|0|1|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FNMUL <Dd>, <Dn>, <Dm>","Code":"","Alias":""},
+{"Name":"FRECPE","Bits":"0|1|0|1|1|1|1|0|1|sz|1|0|0|0|0|1|1|1|0|1|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FRECPE <V><d>, <V><n>","Code":"","Alias":""},
+{"Name":"FRECPE","Bits":"0|Q|0|0|1|1|1|0|1|sz|1|0|0|0|0|1|1|1|0|1|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FRECPE <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"FRECPS","Bits":"0|1|0|1|1|1|1|0|0|sz|1|Rm:5|1|1|1|1|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FRECPS <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"FRECPS","Bits":"0|Q|0|0|1|1|1|0|0|sz|1|Rm:5|1|1|1|1|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FRECPS <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"FRECPX","Bits":"0|1|0|1|1|1|1|0|1|sz|1|0|0|0|0|1|1|1|1|1|1|0|Rn:5|Rd:5","Arch":"Scalar single-precision and double-precision variant","Syntax":"FRECPX <V><d>, <V><n>","Code":"","Alias":""},
+{"Name":"FRINTA (vector)","Bits":"0|Q|1|0|1|1|1|0|0|sz|1|0|0|0|0|1|1|0|0|0|1|0|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FRINTA <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"FRINTA (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|0|1|1|0|0|1|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FRINTA <Sd>, <Sn>","Code":"","Alias":""},
+{"Name":"FRINTA (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|1|1|0|0|1|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FRINTA <Dd>, <Dn>","Code":"","Alias":""},
+{"Name":"FRINTI (vector)","Bits":"0|Q|1|0|1|1|1|0|1|sz|1|0|0|0|0|1|1|0|0|1|1|0|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FRINTI <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"FRINTI (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|0|1|1|1|1|1|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FRINTI <Sd>, <Sn>","Code":"","Alias":""},
+{"Name":"FRINTI (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|1|1|1|1|1|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FRINTI <Dd>, <Dn>","Code":"","Alias":""},
+{"Name":"FRINTM (vector)","Bits":"0|Q|0|0|1|1|1|0|0|sz|1|0|0|0|0|1|1|0|0|1|1|0|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FRINTM <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"FRINTM (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|0|1|0|1|0|1|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FRINTM <Sd>, <Sn>","Code":"","Alias":""},
+{"Name":"FRINTM (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|1|0|1|0|1|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FRINTM <Dd>, <Dn>","Code":"","Alias":""},
+{"Name":"FRINTN (vector)","Bits":"0|Q|0|0|1|1|1|0|0|sz|1|0|0|0|0|1|1|0|0|0|1|0|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FRINTN <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"FRINTN (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|0|1|0|0|0|1|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FRINTN <Sd>, <Sn>","Code":"","Alias":""},
+{"Name":"FRINTN (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|1|0|0|0|1|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FRINTN <Dd>, <Dn>","Code":"","Alias":""},
+{"Name":"FRINTP (vector)","Bits":"0|Q|0|0|1|1|1|0|1|sz|1|0|0|0|0|1|1|0|0|0|1|0|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FRINTP <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"FRINTP (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|0|1|0|0|1|1|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FRINTP <Sd>, <Sn>","Code":"","Alias":""},
+{"Name":"FRINTP (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|1|0|0|1|1|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FRINTP <Dd>, <Dn>","Code":"","Alias":""},
+{"Name":"FRINTX (vector)","Bits":"0|Q|1|0|1|1|1|0|0|sz|1|0|0|0|0|1|1|0|0|1|1|0|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FRINTX <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"FRINTX (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|0|1|1|1|0|1|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FRINTX <Sd>, <Sn>","Code":"","Alias":""},
+{"Name":"FRINTX (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|1|1|1|0|1|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FRINTX <Dd>, <Dn>","Code":"","Alias":""},
+{"Name":"FRINTZ (vector)","Bits":"0|Q|0|0|1|1|1|0|1|sz|1|0|0|0|0|1|1|0|0|1|1|0|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FRINTZ <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"FRINTZ (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|0|1|0|1|1|1|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FRINTZ <Sd>, <Sn>","Code":"","Alias":""},
+{"Name":"FRINTZ (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|1|0|1|1|1|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FRINTZ <Dd>, <Dn>","Code":"","Alias":""},
+{"Name":"FRSQRTE","Bits":"0|1|1|1|1|1|1|0|1|sz|1|0|0|0|0|1|1|1|0|1|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FRSQRTE <V><d>, <V><n>","Code":"","Alias":""},
+{"Name":"FRSQRTE","Bits":"0|Q|1|0|1|1|1|0|1|sz|1|0|0|0|0|1|1|1|0|1|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FRSQRTE <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"FRSQRTS","Bits":"0|1|0|1|1|1|1|0|1|sz|1|Rm:5|1|1|1|1|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FRSQRTS <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"FRSQRTS","Bits":"0|Q|0|0|1|1|1|0|1|sz|1|Rm:5|1|1|1|1|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FRSQRTS <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"FSQRT (vector)","Bits":"0|Q|1|0|1|1|1|0|1|sz|1|0|0|0|0|1|1|1|1|1|1|0|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FSQRT <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"FSQRT (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|0|0|0|1|1|1|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FSQRT <Sd>, <Sn>","Code":"","Alias":""},
+{"Name":"FSQRT (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|0|0|1|1|1|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FSQRT <Dd>, <Dn>","Code":"","Alias":""},
+{"Name":"FSUB (vector)","Bits":"0|Q|0|0|1|1|1|0|1|sz|1|Rm:5|1|1|0|1|0|1|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"FSUB (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|Rm:5|0|0|1|1|1|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FSUB <Sd>, <Sn>, <Sm>","Code":"","Alias":""},
+{"Name":"FSUB (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|Rm:5|0|0|1|1|1|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FSUB <Dd>, <Dn>, <Dm>","Code":"","Alias":""},
+{"Name":"INS (element)","Bits":"0|1|1|0|1|1|1|0|0|0|0|imm5:5|0|imm4:4|1|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"INS <Vd>.<Ts>[<index1>], <Vn>.<Ts>[<index2>]","Code":"","Alias":"This instruction is used by the alias MOV (element)."},
+{"Name":"INS (general)","Bits":"0|1|0|0|1|1|1|0|0|0|0|imm5:5|0|0|0|1|1|1|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"INS <Vd>.<Ts>[<index>], <R><n>","Code":"","Alias":"This instruction is used by the alias MOV (from general)."},
+{"Name":"LD1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|0|1|0|0|0|0|0|0|0111:4|size:2|Rn:5|Rt:5","Arch":"No offset One register variant","Syntax":"LD1 { <Vt>.<T> }, [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"LD1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|0|1|0|0|0|0|0|0|1010:4|size:2|Rn:5|Rt:5","Arch":"No offset Two registers variant","Syntax":"LD1 { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"LD1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|0|1|0|0|0|0|0|0|0110:4|size:2|Rn:5|Rt:5","Arch":"No offset Three registers variant","Syntax":"LD1 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"LD1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|0|1|0|0|0|0|0|0|0010:4|size:2|Rn:5|Rt:5","Arch":"No offset Four registers variant","Syntax":"LD1 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"LD1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|1|0|11111:5|0111:4|size:2|Rn:5|Rt:5","Arch":"Post-index One register, immediate offset variant","Syntax":"LD1 { <Vt>.<T> }, [<Xn|SP>], <imm>","Code":"","Alias":""},
+{"Name":"LD1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|1|0|Rm:5|0111:4|size:2|Rn:5|Rt:5","Arch":"Post-index One register, register offset variant","Syntax":"LD1 { <Vt>.<T> }, [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"LD1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|1|0|11111:5|1010:4|size:2|Rn:5|Rt:5","Arch":"Post-index Two registers, immediate offset variant","Syntax":"LD1 { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <imm>","Code":"","Alias":""},
+{"Name":"LD1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|1|0|Rm:5|1010:4|size:2|Rn:5|Rt:5","Arch":"Post-index Two registers, register offset variant","Syntax":"LD1 { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"LD1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|1|0|11111:5|0110:4|size:2|Rn:5|Rt:5","Arch":"Post-index Three registers, immediate offset variant","Syntax":"LD1 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <imm>","Code":"","Alias":""},
+{"Name":"LD1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|1|0|Rm:5|0110:4|size:2|Rn:5|Rt:5","Arch":"Post-index Three registers, register offset variant","Syntax":"LD1 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"LD1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|1|0|11111:5|0010:4|size:2|Rn:5|Rt:5","Arch":"Post-index Four registers, immediate offset variant","Syntax":"LD1 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <imm>","Code":"","Alias":""},
+{"Name":"LD1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|1|0|Rm:5|0010:4|size:2|Rn:5|Rt:5","Arch":"Post-index Four registers, register offset variant","Syntax":"LD1 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"LD1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|1|0|0|0|0|0|0|000:3|S|size:2|Rn:5|Rt:5","Arch":"No offset 8-bit variant","Syntax":"LD1 { <Vt>.B }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"LD1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|1|0|0|0|0|0|0|010:3|S|size:2|Rn:5|Rt:5","Arch":"No offset 16-bit variant","Syntax":"LD1 { <Vt>.H }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"LD1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|1|0|0|0|0|0|0|100:3|S|00:2|Rn:5|Rt:5","Arch":"No offset 32-bit variant","Syntax":"LD1 { <Vt>.S }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"LD1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|1|0|0|0|0|0|0|100:3|0|01:2|Rn:5|Rt:5","Arch":"No offset 64-bit variant","Syntax":"LD1 { <Vt>.D }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"LD1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|0|11111:5|000:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 8-bit, immediate offset variant","Syntax":"LD1 { <Vt>.B }[<index>], [<Xn|SP>], #1","Code":"","Alias":""},
+{"Name":"LD1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|0|Rm:5|000:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 8-bit, register offset variant","Syntax":"LD1 { <Vt>.B }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"LD1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|0|11111:5|010:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 16-bit, immediate offset variant","Syntax":"LD1 { <Vt>.H }[<index>], [<Xn|SP>], #2","Code":"","Alias":""},
+{"Name":"LD1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|0|Rm:5|010:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 16-bit, register offset variant","Syntax":"LD1 { <Vt>.H }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"LD1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|0|11111:5|100:3|S|00:2|Rn:5|Rt:5","Arch":"Post-index 32-bit, immediate offset variant","Syntax":"LD1 { <Vt>.S }[<index>], [<Xn|SP>], #4","Code":"","Alias":""},
+{"Name":"LD1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|0|Rm:5|100:3|S|00:2|Rn:5|Rt:5","Arch":"Post-index 32-bit, register offset variant","Syntax":"LD1 { <Vt>.S }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"LD1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|0|11111:5|100:3|0|01:2|Rn:5|Rt:5","Arch":"Post-index 64-bit, immediate offset variant","Syntax":"LD1 { <Vt>.D }[<index>], [<Xn|SP>], #8","Code":"","Alias":""},
+{"Name":"LD1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|0|Rm:5|100:3|0|01:2|Rn:5|Rt:5","Arch":"Post-index 64-bit, register offset variant","Syntax":"LD1 { <Vt>.D }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"LD1R","Bits":"0|Q|0|0|1|1|0|1|0|1|0|0|0|0|0|0|1|1|0|0|size:2|Rn:5|Rt:5","Arch":"No offset No offset variant","Syntax":"LD1R { <Vt>.<T> }, [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"LD1R","Bits":"0|Q|0|0|1|1|0|1|1|1|0|11111:5|1|1|0|0|size:2|Rn:5|Rt:5","Arch":"Post-index Immediate offset variant","Syntax":"LD1R { <Vt>.<T> }, [<Xn|SP>], <imm>","Code":"","Alias":""},
+{"Name":"LD1R","Bits":"0|Q|0|0|1|1|0|1|1|1|0|Rm:5|1|1|0|0|size:2|Rn:5|Rt:5","Arch":"Post-index Register offset variant","Syntax":"LD1R { <Vt>.<T> }, [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"LD2 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|0|1|0|0|0|0|0|0|1|0|0|0|size:2|Rn:5|Rt:5","Arch":"No offset No offset variant","Syntax":"LD2 { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"LD2 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|1|0|11111:5|1|0|0|0|size:2|Rn:5|Rt:5","Arch":"Post-index Immediate offset variant","Syntax":"LD2 { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <imm>","Code":"","Alias":""},
+{"Name":"LD2 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|1|0|Rm:5|1|0|0|0|size:2|Rn:5|Rt:5","Arch":"Post-index Register offset variant","Syntax":"LD2 { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"LD2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|1|1|0|0|0|0|0|000:3|S|size:2|Rn:5|Rt:5","Arch":"No offset 8-bit variant","Syntax":"LD2 { <Vt>.B, <Vt2>.B }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"LD2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|1|1|0|0|0|0|0|010:3|S|size:2|Rn:5|Rt:5","Arch":"No offset 16-bit variant","Syntax":"LD2 { <Vt>.H, <Vt2>.H }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"LD2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|1|1|0|0|0|0|0|100:3|S|00:2|Rn:5|Rt:5","Arch":"No offset 32-bit variant","Syntax":"LD2 { <Vt>.S, <Vt2>.S }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"LD2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|1|1|0|0|0|0|0|100:3|0|01:2|Rn:5|Rt:5","Arch":"No offset 64-bit variant","Syntax":"LD2 { <Vt>.D, <Vt2>.D }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"LD2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|1|11111:5|000:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 8-bit, immediate offset variant","Syntax":"LD2 { <Vt>.B, <Vt2>.B }[<index>], [<Xn|SP>], #2","Code":"","Alias":""},
+{"Name":"LD2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|1|Rm:5|000:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 8-bit, register offset variant","Syntax":"LD2 { <Vt>.B, <Vt2>.B }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"LD2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|1|11111:5|010:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 16-bit, immediate offset variant","Syntax":"LD2 { <Vt>.H, <Vt2>.H }[<index>], [<Xn|SP>], #4","Code":"","Alias":""},
+{"Name":"LD2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|1|Rm:5|010:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 16-bit, register offset variant","Syntax":"LD2 { <Vt>.H, <Vt2>.H }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"LD2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|1|11111:5|100:3|S|00:2|Rn:5|Rt:5","Arch":"Post-index 32-bit, immediate offset variant","Syntax":"LD2 { <Vt>.S, <Vt2>.S }[<index>], [<Xn|SP>], #8","Code":"","Alias":""},
+{"Name":"LD2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|1|Rm:5|100:3|S|00:2|Rn:5|Rt:5","Arch":"Post-index 32-bit, register offset variant","Syntax":"LD2 { <Vt>.S, <Vt2>.S }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"LD2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|1|11111:5|100:3|0|01:2|Rn:5|Rt:5","Arch":"Post-index 64-bit, immediate offset variant","Syntax":"LD2 { <Vt>.D, <Vt2>.D }[<index>], [<Xn|SP>], #16","Code":"","Alias":""},
+{"Name":"LD2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|1|Rm:5|100:3|0|01:2|Rn:5|Rt:5","Arch":"Post-index 64-bit, register offset variant","Syntax":"LD2 { <Vt>.D, <Vt2>.D }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"LD2R","Bits":"0|Q|0|0|1|1|0|1|0|1|1|0|0|0|0|0|1|1|0|0|size:2|Rn:5|Rt:5","Arch":"No offset No offset variant","Syntax":"LD2R { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"LD2R","Bits":"0|Q|0|0|1|1|0|1|1|1|1|11111:5|1|1|0|0|size:2|Rn:5|Rt:5","Arch":"Post-index Immediate offset variant","Syntax":"LD2R { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <imm>","Code":"","Alias":""},
+{"Name":"LD2R","Bits":"0|Q|0|0|1|1|0|1|1|1|1|Rm:5|1|1|0|0|size:2|Rn:5|Rt:5","Arch":"Post-index Register offset variant","Syntax":"LD2R { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"LD3 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|0|1|0|0|0|0|0|0|0|1|0|0|size:2|Rn:5|Rt:5","Arch":"No offset No offset variant","Syntax":"LD3 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"LD3 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|1|0|11111:5|0|1|0|0|size:2|Rn:5|Rt:5","Arch":"Post-index Immediate offset variant","Syntax":"LD3 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <imm>","Code":"","Alias":""},
+{"Name":"LD3 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|1|0|Rm:5|0|1|0|0|size:2|Rn:5|Rt:5","Arch":"Post-index Register offset variant","Syntax":"LD3 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"LD3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|1|0|0|0|0|0|0|001:3|S|size:2|Rn:5|Rt:5","Arch":"No offset 8-bit variant","Syntax":"LD3 { <Vt>.B, <Vt2>.B, <Vt3>.B }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"LD3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|1|0|0|0|0|0|0|011:3|S|size:2|Rn:5|Rt:5","Arch":"No offset 16-bit variant","Syntax":"LD3 { <Vt>.H, <Vt2>.H, <Vt3>.H }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"LD3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|1|0|0|0|0|0|0|101:3|S|00:2|Rn:5|Rt:5","Arch":"No offset 32-bit variant","Syntax":"LD3 { <Vt>.S, <Vt2>.S, <Vt3>.S }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"LD3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|1|0|0|0|0|0|0|101:3|0|01:2|Rn:5|Rt:5","Arch":"No offset 64-bit variant","Syntax":"LD3 { <Vt>.D, <Vt2>.D, <Vt3>.D }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"LD3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|0|11111:5|001:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 8-bit, immediate offset variant","Syntax":"LD3 { <Vt>.B, <Vt2>.B, <Vt3>.B }[<index>], [<Xn|SP>], #3","Code":"","Alias":""},
+{"Name":"LD3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|0|Rm:5|001:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 8-bit, register offset variant","Syntax":"LD3 { <Vt>.B, <Vt2>.B, <Vt3>.B }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"LD3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|0|11111:5|011:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 16-bit, immediate offset variant","Syntax":"LD3 { <Vt>.H, <Vt2>.H, <Vt3>.H }[<index>], [<Xn|SP>], #6","Code":"","Alias":""},
+{"Name":"LD3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|0|Rm:5|011:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 16-bit, register offset variant","Syntax":"LD3 { <Vt>.H, <Vt2>.H, <Vt3>.H }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"LD3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|0|11111:5|101:3|S|00:2|Rn:5|Rt:5","Arch":"Post-index 32-bit, immediate offset variant","Syntax":"LD3 { <Vt>.S, <Vt2>.S, <Vt3>.S }[<index>], [<Xn|SP>], #12","Code":"","Alias":""},
+{"Name":"LD3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|0|Rm:5|101:3|S|00:2|Rn:5|Rt:5","Arch":"Post-index 32-bit, register offset variant","Syntax":"LD3 { <Vt>.S, <Vt2>.S, <Vt3>.S }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"LD3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|0|11111:5|101:3|0|01:2|Rn:5|Rt:5","Arch":"Post-index 64-bit, immediate offset variant","Syntax":"LD3 { <Vt>.D, <Vt2>.D, <Vt3>.D }[<index>], [<Xn|SP>], #24","Code":"","Alias":""},
+{"Name":"LD3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|0|Rm:5|101:3|0|01:2|Rn:5|Rt:5","Arch":"Post-index 64-bit, register offset variant","Syntax":"LD3 { <Vt>.D, <Vt2>.D, <Vt3>.D }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"LD3R","Bits":"0|Q|0|0|1|1|0|1|0|1|0|0|0|0|0|0|1|1|1|0|size:2|Rn:5|Rt:5","Arch":"No offset No offset variant","Syntax":"LD3R { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"LD3R","Bits":"0|Q|0|0|1|1|0|1|1|1|0|11111:5|1|1|1|0|size:2|Rn:5|Rt:5","Arch":"Post-index Immediate offset variant","Syntax":"LD3R { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <imm>","Code":"","Alias":""},
+{"Name":"LD3R","Bits":"0|Q|0|0|1|1|0|1|1|1|0|Rm:5|1|1|1|0|size:2|Rn:5|Rt:5","Arch":"Post-index Register offset variant","Syntax":"LD3R { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"LD4 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|0|1|0|0|0|0|0|0|0|0|0|0|size:2|Rn:5|Rt:5","Arch":"No offset No offset variant","Syntax":"LD4 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"LD4 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|1|0|11111:5|0|0|0|0|size:2|Rn:5|Rt:5","Arch":"Post-index Immediate offset variant","Syntax":"LD4 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <imm>","Code":"","Alias":""},
+{"Name":"LD4 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|1|0|Rm:5|0|0|0|0|size:2|Rn:5|Rt:5","Arch":"Post-index Register offset variant","Syntax":"LD4 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"LD4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|1|1|0|0|0|0|0|001:3|S|size:2|Rn:5|Rt:5","Arch":"No offset 8-bit variant","Syntax":"LD4 { <Vt>.B, <Vt2>.B, <Vt3>.B, <Vt4>.B }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"LD4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|1|1|0|0|0|0|0|011:3|S|size:2|Rn:5|Rt:5","Arch":"No offset 16-bit variant","Syntax":"LD4 { <Vt>.H, <Vt2>.H, <Vt3>.H, <Vt4>.H }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"LD4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|1|1|0|0|0|0|0|101:3|S|00:2|Rn:5|Rt:5","Arch":"No offset 32-bit variant","Syntax":"LD4 { <Vt>.S, <Vt2>.S, <Vt3>.S, <Vt4>.S }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"LD4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|1|1|0|0|0|0|0|101:3|0|01:2|Rn:5|Rt:5","Arch":"No offset 64-bit variant","Syntax":"LD4 { <Vt>.D, <Vt2>.D, <Vt3>.D, <Vt4>.D }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"LD4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|1|11111:5|001:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 8-bit, immediate offset variant","Syntax":"LD4 { <Vt>.B, <Vt2>.B, <Vt3>.B, <Vt4>.B }[<index>], [<Xn|SP>], #4","Code":"","Alias":""},
+{"Name":"LD4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|1|Rm:5|001:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 8-bit, register offset variant","Syntax":"LD4 { <Vt>.B, <Vt2>.B, <Vt3>.B, <Vt4>.B }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"LD4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|1|11111:5|011:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 16-bit, immediate offset variant","Syntax":"LD4 { <Vt>.H, <Vt2>.H, <Vt3>.H, <Vt4>.H }[<index>], [<Xn|SP>], #8","Code":"","Alias":""},
+{"Name":"LD4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|1|Rm:5|011:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 16-bit, register offset variant","Syntax":"LD4 { <Vt>.H, <Vt2>.H, <Vt3>.H, <Vt4>.H }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"LD4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|1|11111:5|101:3|S|00:2|Rn:5|Rt:5","Arch":"Post-index 32-bit, immediate offset variant","Syntax":"LD4 { <Vt>.S, <Vt2>.S, <Vt3>.S, <Vt4>.S }[<index>], [<Xn|SP>], #16","Code":"","Alias":""},
+{"Name":"LD4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|1|Rm:5|101:3|S|00:2|Rn:5|Rt:5","Arch":"Post-index 32-bit, register offset variant","Syntax":"LD4 { <Vt>.S, <Vt2>.S, <Vt3>.S, <Vt4>.S }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"LD4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|1|11111:5|101:3|0|01:2|Rn:5|Rt:5","Arch":"Post-index 64-bit, immediate offset variant","Syntax":"LD4 { <Vt>.D, <Vt2>.D, <Vt3>.D, <Vt4>.D }[<index>], [<Xn|SP>], #32","Code":"","Alias":""},
+{"Name":"LD4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|1|Rm:5|101:3|0|01:2|Rn:5|Rt:5","Arch":"Post-index 64-bit, register offset variant","Syntax":"LD4 { <Vt>.D, <Vt2>.D, <Vt3>.D, <Vt4>.D }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"LD4R","Bits":"0|Q|0|0|1|1|0|1|0|1|1|0|0|0|0|0|1|1|1|0|size:2|Rn:5|Rt:5","Arch":"No offset No offset variant","Syntax":"LD4R { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"LD4R","Bits":"0|Q|0|0|1|1|0|1|1|1|1|11111:5|1|1|1|0|size:2|Rn:5|Rt:5","Arch":"Post-index Immediate offset variant","Syntax":"LD4R { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <imm>","Code":"","Alias":""},
+{"Name":"LD4R","Bits":"0|Q|0|0|1|1|0|1|1|1|1|Rm:5|1|1|1|0|size:2|Rn:5|Rt:5","Arch":"Post-index Register offset variant","Syntax":"LD4R { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"LDNP (SIMD&FP)","Bits":"00:2|1|0|1|1|0|0|0|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDNP <St1>, <St2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
+{"Name":"LDNP (SIMD&FP)","Bits":"01:2|1|0|1|1|0|0|0|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDNP <Dt1>, <Dt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
+{"Name":"LDNP (SIMD&FP)","Bits":"10:2|1|0|1|1|0|0|0|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"128-bit variant","Syntax":"LDNP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
+{"Name":"LDP (SIMD&FP)","Bits":"00:2|1|0|1|1|0|0|1|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Post-index 32-bit variant","Syntax":"LDP <St1>, <St2>, [<Xn|SP>], #<imm>","Code":"","Alias":""},
+{"Name":"LDP (SIMD&FP)","Bits":"01:2|1|0|1|1|0|0|1|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Post-index 64-bit variant","Syntax":"LDP <Dt1>, <Dt2>, [<Xn|SP>], #<imm>","Code":"","Alias":""},
+{"Name":"LDP (SIMD&FP)","Bits":"10:2|1|0|1|1|0|0|1|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Post-index 128-bit variant","Syntax":"LDP <Qt1>, <Qt2>, [<Xn|SP>], #<imm>","Code":"","Alias":""},
+{"Name":"LDP (SIMD&FP)","Bits":"00:2|1|0|1|1|0|1|1|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Pre-index 32-bit variant","Syntax":"LDP <St1>, <St2>, [<Xn|SP>, #<imm>]!","Code":"","Alias":""},
+{"Name":"LDP (SIMD&FP)","Bits":"01:2|1|0|1|1|0|1|1|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Pre-index 64-bit variant","Syntax":"LDP <Dt1>, <Dt2>, [<Xn|SP>, #<imm>]!","Code":"","Alias":""},
+{"Name":"LDP (SIMD&FP)","Bits":"10:2|1|0|1|1|0|1|1|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Pre-index 128-bit variant","Syntax":"LDP <Qt1>, <Qt2>, [<Xn|SP>, #<imm>]!","Code":"","Alias":""},
+{"Name":"LDP (SIMD&FP)","Bits":"00:2|1|0|1|1|0|1|0|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Signed offset 32-bit variant","Syntax":"LDP <St1>, <St2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
+{"Name":"LDP (SIMD&FP)","Bits":"01:2|1|0|1|1|0|1|0|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Signed offset 64-bit variant","Syntax":"LDP <Dt1>, <Dt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
+{"Name":"LDP (SIMD&FP)","Bits":"10:2|1|0|1|1|0|1|0|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Signed offset 128-bit variant","Syntax":"LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
+{"Name":"LDR (immediate, SIMD&FP)","Bits":"00:2|1|1|1|1|0|0|01:2|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 8-bit variant","Syntax":"LDR <Bt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
+{"Name":"LDR (immediate, SIMD&FP)","Bits":"01:2|1|1|1|1|0|0|01:2|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 16-bit variant","Syntax":"LDR <Ht>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
+{"Name":"LDR (immediate, SIMD&FP)","Bits":"10:2|1|1|1|1|0|0|01:2|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 32-bit variant","Syntax":"LDR <St>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
+{"Name":"LDR (immediate, SIMD&FP)","Bits":"11:2|1|1|1|1|0|0|01:2|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 64-bit variant","Syntax":"LDR <Dt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
+{"Name":"LDR (immediate, SIMD&FP)","Bits":"00:2|1|1|1|1|0|0|11:2|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 128-bit variant","Syntax":"LDR <Qt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
+{"Name":"LDR (immediate, SIMD&FP)","Bits":"00:2|1|1|1|1|0|0|01:2|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index 8-bit variant","Syntax":"LDR <Bt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
+{"Name":"LDR (immediate, SIMD&FP)","Bits":"01:2|1|1|1|1|0|0|01:2|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index 16-bit variant","Syntax":"LDR <Ht>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
+{"Name":"LDR (immediate, SIMD&FP)","Bits":"10:2|1|1|1|1|0|0|01:2|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index 32-bit variant","Syntax":"LDR <St>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
+{"Name":"LDR (immediate, SIMD&FP)","Bits":"11:2|1|1|1|1|0|0|01:2|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index 64-bit variant","Syntax":"LDR <Dt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
+{"Name":"LDR (immediate, SIMD&FP)","Bits":"00:2|1|1|1|1|0|0|11:2|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index 128-bit variant","Syntax":"LDR <Qt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
+{"Name":"LDR (immediate, SIMD&FP)","Bits":"00:2|1|1|1|1|0|1|01:2|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 8-bit variant","Syntax":"LDR <Bt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
+{"Name":"LDR (immediate, SIMD&FP)","Bits":"01:2|1|1|1|1|0|1|01:2|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 16-bit variant","Syntax":"LDR <Ht>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
+{"Name":"LDR (immediate, SIMD&FP)","Bits":"10:2|1|1|1|1|0|1|01:2|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 32-bit variant","Syntax":"LDR <St>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
+{"Name":"LDR (immediate, SIMD&FP)","Bits":"11:2|1|1|1|1|0|1|01:2|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 64-bit variant","Syntax":"LDR <Dt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
+{"Name":"LDR (immediate, SIMD&FP)","Bits":"00:2|1|1|1|1|0|1|11:2|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 128-bit variant","Syntax":"LDR <Qt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
+{"Name":"LDR (literal, SIMD&FP)","Bits":"00:2|0|1|1|1|0|0|imm19:19|Rt:5","Arch":"32-bit variant","Syntax":"LDR <St>, <label>","Code":"","Alias":""},
+{"Name":"LDR (literal, SIMD&FP)","Bits":"01:2|0|1|1|1|0|0|imm19:19|Rt:5","Arch":"64-bit variant","Syntax":"LDR <Dt>, <label>","Code":"","Alias":""},
+{"Name":"LDR (literal, SIMD&FP)","Bits":"10:2|0|1|1|1|0|0|imm19:19|Rt:5","Arch":"128-bit variant","Syntax":"LDR <Qt>, <label>","Code":"","Alias":""},
+{"Name":"LDR (register, SIMD&FP)","Bits":"00:2|1|1|1|1|0|0|01:2|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"8-bit variant","Syntax":"LDR <Bt>, [<Xn|SP>, (<Wm>|<Xm>), <extend> {<amount>}]","Code":"","Alias":""},
+{"Name":"LDR (register, SIMD&FP)","Bits":"00:2|1|1|1|1|0|0|01:2|1|Rm:5|011:3|S|1|0|Rn:5|Rt:5","Arch":"8-bit variant","Syntax":"LDR <Bt>, [<Xn|SP>, <Xm>{, LSL <amount>}]","Code":"","Alias":""},
+{"Name":"LDR (register, SIMD&FP)","Bits":"01:2|1|1|1|1|0|0|01:2|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"16-bit variant","Syntax":"LDR <Ht>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]","Code":"","Alias":""},
+{"Name":"LDR (register, SIMD&FP)","Bits":"10:2|1|1|1|1|0|0|01:2|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDR <St>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]","Code":"","Alias":""},
+{"Name":"LDR (register, SIMD&FP)","Bits":"11:2|1|1|1|1|0|0|01:2|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDR <Dt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]","Code":"","Alias":""},
+{"Name":"LDR (register, SIMD&FP)","Bits":"00:2|1|1|1|1|0|0|11:2|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"128-bit variant","Syntax":"LDR <Qt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]","Code":"","Alias":""},
+{"Name":"LDUR (SIMD&FP)","Bits":"00:2|1|1|1|1|0|0|01:2|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"8-bit variant","Syntax":"LDUR <Bt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"LDUR (SIMD&FP)","Bits":"01:2|1|1|1|1|0|0|01:2|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"16-bit variant","Syntax":"LDUR <Ht>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"LDUR (SIMD&FP)","Bits":"10:2|1|1|1|1|0|0|01:2|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDUR <St>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"LDUR (SIMD&FP)","Bits":"11:2|1|1|1|1|0|0|01:2|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDUR <Dt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"LDUR (SIMD&FP)","Bits":"00:2|1|1|1|1|0|0|11:2|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"128-bit variant","Syntax":"LDUR <Qt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"MLA (by element)","Bits":"0|Q|1|0|1|1|1|1|size:2|L|M|Rm:4|0|0|0|0|H|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"MLA <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"MLA (vector)","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|1|0|0|1|0|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"MLA <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"MLS (by element)","Bits":"0|Q|1|0|1|1|1|1|size:2|L|M|Rm:4|0|1|0|0|H|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"MLS <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"MLS (vector)","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|1|0|0|1|0|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"MLS <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"MOV (scalar)","Bits":"0|1|0|1|1|1|1|0|0|0|0|imm5:5|0|0|0|0|0|1|Rn:5|Rd:5","Arch":"Scalar variant","Syntax":"MOV <V><d>, <Vn>.<T>[<index>]","Code":"","Alias":"This instruction is an alias of the DUP (element) instruction."},
+{"Name":"MOV (element)","Bits":"0|1|1|0|1|1|1|0|0|0|0|imm5:5|0|imm4:4|1|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"MOV <Vd>.<Ts>[<index1>], <Vn>.<Ts>[<index2>]","Code":"","Alias":"This instruction is an alias of the INS (element) instruction."},
+{"Name":"MOV (from general)","Bits":"0|1|0|0|1|1|1|0|0|0|0|imm5:5|0|0|0|1|1|1|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"MOV <Vd>.<Ts>[<index>], <R><n>","Code":"","Alias":"This instruction is an alias of the INS (general) instruction."},
+{"Name":"MOV (vector)","Bits":"0|Q|0|0|1|1|1|0|1|0|1|Rm:5|0|0|0|1|1|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"MOV <Vd>.<T>, <Vn>.<T>","Code":"","Alias":"This instruction is an alias of the ORR (vector, register) instruction."},
+{"Name":"MOV (to general)","Bits":"0|0|0|0|1|1|1|0|0|0|0|imm5:5|0|0|1|1|1|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"MOV <Wd>, <Vn>.S[<index>]","Code":"","Alias":"This instruction is an alias of the UMOV instruction."},
+{"Name":"MOV (to general)","Bits":"0|1|0|0|1|1|1|0|0|0|0|imm5:5|0|0|1|1|1|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"MOV <Xd>, <Vn>.D[<index>]","Code":"","Alias":"This instruction is an alias of the UMOV instruction."},
+{"Name":"MOVI","Bits":"0|Q|0|0|1|1|1|1|0|0|0|0|0|a|b|c|1110:4|0|1|d|e|f|g|h|Rd:5","Arch":"8-bit variant","Syntax":"MOVI <Vd>.<T>, #<imm8>{, LSL #0}","Code":"","Alias":""},
+{"Name":"MOVI","Bits":"0|Q|0|0|1|1|1|1|0|0|0|0|0|a|b|c|cmode:4|0|1|d|e|f|g|h|Rd:5","Arch":"16-bit shifted immediate variant","Syntax":"MOVI <Vd>.<T>, #<imm8>{, LSL #<amount>}","Code":"","Alias":""},
+{"Name":"MOVI","Bits":"0|Q|0|0|1|1|1|1|0|0|0|0|0|a|b|c|cmode:4|0|1|d|e|f|g|h|Rd:5","Arch":"32-bit shifted immediate variant","Syntax":"MOVI <Vd>.<T>, #<imm8>{, LSL #<amount>}","Code":"","Alias":""},
+{"Name":"MOVI","Bits":"0|Q|0|0|1|1|1|1|0|0|0|0|0|a|b|c|cmode:4|0|1|d|e|f|g|h|Rd:5","Arch":"32-bit shifting ones variant","Syntax":"MOVI <Vd>.<T>, #<imm8>, MSL #<amount>","Code":"","Alias":""},
+{"Name":"MOVI","Bits":"0|0|1|0|1|1|1|1|0|0|0|0|0|a|b|c|1110:4|0|1|d|e|f|g|h|Rd:5","Arch":"64-bit scalar variant","Syntax":"MOVI <Dd>, #<imm>","Code":"","Alias":""},
+{"Name":"MOVI","Bits":"0|1|1|0|1|1|1|1|0|0|0|0|0|a|b|c|1110:4|0|1|d|e|f|g|h|Rd:5","Arch":"64-bit vector variant","Syntax":"MOVI <Vd>.2D, #<imm>","Code":"","Alias":""},
+{"Name":"MUL (by element)","Bits":"0|Q|0|0|1|1|1|1|size:2|L|M|Rm:4|1|0|0|0|H|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"MUL <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"MUL (vector)","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|1|0|0|1|1|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"MUL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"MVN","Bits":"0|Q|1|0|1|1|1|0|0|0|1|0|0|0|0|0|0|1|0|1|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"MVN <Vd>.<T>, <Vn>.<T>","Code":"","Alias":"This instruction is an alias of the NOT instruction."},
+{"Name":"MVNI","Bits":"0|Q|1|0|1|1|1|1|0|0|0|0|0|a|b|c|cmode:4|0|1|d|e|f|g|h|Rd:5","Arch":"16-bit shifted immediate variant","Syntax":"MVNI <Vd>.<T>, #<imm8>{, LSL #<amount>}","Code":"","Alias":""},
+{"Name":"MVNI","Bits":"0|Q|1|0|1|1|1|1|0|0|0|0|0|a|b|c|cmode:4|0|1|d|e|f|g|h|Rd:5","Arch":"32-bit shifted immediate variant","Syntax":"MVNI <Vd>.<T>, #<imm8>{, LSL #<amount>}","Code":"","Alias":""},
+{"Name":"MVNI","Bits":"0|Q|1|0|1|1|1|1|0|0|0|0|0|a|b|c|cmode:4|0|1|d|e|f|g|h|Rd:5","Arch":"32-bit shifting ones variant","Syntax":"MVNI <Vd>.<T>, #<imm8>, MSL #<amount>","Code":"","Alias":""},
+{"Name":"NEG (vector)","Bits":"0|1|1|1|1|1|1|0|size:2|1|0|0|0|0|0|1|0|1|1|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"NEG <V><d>, <V><n>","Code":"","Alias":""},
+{"Name":"NEG (vector)","Bits":"0|Q|1|0|1|1|1|0|size:2|1|0|0|0|0|0|1|0|1|1|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"NEG <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"NOT","Bits":"0|Q|1|0|1|1|1|0|0|0|1|0|0|0|0|0|0|1|0|1|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"NOT <Vd>.<T>, <Vn>.<T>","Code":"","Alias":"This instruction is used by the alias MVN."},
+{"Name":"ORN (vector)","Bits":"0|Q|0|0|1|1|1|0|1|1|1|Rm:5|0|0|0|1|1|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"ORN <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"ORR (vector, immediate)","Bits":"0|Q|0|0|1|1|1|1|0|0|0|0|0|a|b|c|cmode:4|0|1|d|e|f|g|h|Rd:5","Arch":"16-bit variant","Syntax":"ORR <Vd>.<T>, #<imm8>{, LSL #<amount>}","Code":"","Alias":""},
+{"Name":"ORR (vector, immediate)","Bits":"0|Q|0|0|1|1|1|1|0|0|0|0|0|a|b|c|cmode:4|0|1|d|e|f|g|h|Rd:5","Arch":"32-bit variant","Syntax":"ORR <Vd>.<T>, #<imm8>{, LSL #<amount>}","Code":"","Alias":""},
+{"Name":"ORR (vector, register)","Bits":"0|Q|0|0|1|1|1|0|1|0|1|Rm:5|0|0|0|1|1|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"ORR <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":"This instruction is used by the alias MOV (vector)."},
+{"Name":"PMUL","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|1|0|0|1|1|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"PMUL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"PMULL, PMULL2","Bits":"0|0|0|0|1|1|1|0|size:2|1|Rm:5|1|1|1|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"PMULL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"PMULL, PMULL2","Bits":"0|1|0|0|1|1|1|0|size:2|1|Rm:5|1|1|1|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"PMULL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"RADDHN, RADDHN2","Bits":"0|0|1|0|1|1|1|0|size:2|1|Rm:5|0|1|0|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"RADDHN <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>","Code":"","Alias":""},
+{"Name":"RADDHN, RADDHN2","Bits":"0|1|1|0|1|1|1|0|size:2|1|Rm:5|0|1|0|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"RADDHN2 <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>","Code":"","Alias":""},
+{"Name":"RBIT (vector)","Bits":"0|Q|1|0|1|1|1|0|0|1|1|0|0|0|0|0|0|1|0|1|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"RBIT <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"REV16 (vector)","Bits":"0|Q|0|0|1|1|1|0|size:2|1|0|0|0|0|0|0|0|0|1|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"REV16 <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"REV32 (vector)","Bits":"0|Q|1|0|1|1|1|0|size:2|1|0|0|0|0|0|0|0|0|0|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"REV32 <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"REV64","Bits":"0|Q|0|0|1|1|1|0|size:2|1|0|0|0|0|0|0|0|0|0|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"REV64 <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"RSHRN, RSHRN2","Bits":"0|0|0|0|1|1|1|1|0|immh:4|immb:3|1|0|0|0|1|1|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"RSHRN <Vd>.<Tb>, <Vn>.<Ta>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"RSHRN, RSHRN2","Bits":"0|1|0|0|1|1|1|1|0|immh:4|immb:3|1|0|0|0|1|1|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"RSHRN2 <Vd>.<Tb>, <Vn>.<Ta>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"RSUBHN, RSUBHN2","Bits":"0|0|1|0|1|1|1|0|size:2|1|Rm:5|0|1|1|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"RSUBHN <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>","Code":"","Alias":""},
+{"Name":"RSUBHN, RSUBHN2","Bits":"0|1|1|0|1|1|1|0|size:2|1|Rm:5|0|1|1|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"RSUBHN2 <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>","Code":"","Alias":""},
+{"Name":"SABA","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|0|1|1|1|1|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"SABA <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"SABAL, SABAL2","Bits":"0|0|0|0|1|1|1|0|size:2|1|Rm:5|0|1|0|1|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SABAL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"SABAL, SABAL2","Bits":"0|1|0|0|1|1|1|0|size:2|1|Rm:5|0|1|0|1|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SABAL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"SABD","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|0|1|1|1|0|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"SABD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"SABDL, SABDL2","Bits":"0|0|0|0|1|1|1|0|size:2|1|Rm:5|0|1|1|1|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SABDL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"SABDL, SABDL2","Bits":"0|1|0|0|1|1|1|0|size:2|1|Rm:5|0|1|1|1|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SABDL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"SADALP","Bits":"0|Q|0|0|1|1|1|0|size:2|1|0|0|0|0|0|0|1|1|0|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"SADALP <Vd>.<Ta>, <Vn>.<Tb>","Code":"","Alias":""},
+{"Name":"SADDL, SADDL2","Bits":"0|0|0|0|1|1|1|0|size:2|1|Rm:5|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SADDL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"SADDL, SADDL2","Bits":"0|1|0|0|1|1|1|0|size:2|1|Rm:5|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SADDL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"SADDLP","Bits":"0|Q|0|0|1|1|1|0|size:2|1|0|0|0|0|0|0|0|1|0|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"SADDLP <Vd>.<Ta>, <Vn>.<Tb>","Code":"","Alias":""},
+{"Name":"SADDLV","Bits":"0|Q|0|0|1|1|1|0|size:2|1|1|0|0|0|0|0|0|1|1|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"SADDLV <V><d>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"SADDW, SADDW2","Bits":"0|0|0|0|1|1|1|0|size:2|1|Rm:5|0|0|0|1|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SADDW <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"SADDW, SADDW2","Bits":"0|1|0|0|1|1|1|0|size:2|1|Rm:5|0|0|0|1|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SADDW2 <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"SCVTF (vector, fixed-point)","Bits":"0|1|0|1|1|1|1|1|0|immh:4|immb:3|1|1|1|0|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SCVTF <V><d>, <V><n>, #<fbits>","Code":"","Alias":""},
+{"Name":"SCVTF (vector, fixed-point)","Bits":"0|Q|0|0|1|1|1|1|0|immh:4|immb:3|1|1|1|0|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SCVTF <Vd>.<T>, <Vn>.<T>, #<fbits>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"SCVTF (vector, integer)","Bits":"0|1|0|1|1|1|1|0|0|sz|1|0|0|0|0|1|1|1|0|1|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SCVTF <V><d>, <V><n>","Code":"","Alias":""},
+{"Name":"SCVTF (vector, integer)","Bits":"0|Q|0|0|1|1|1|0|0|sz|1|0|0|0|0|1|1|1|0|1|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SCVTF <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"SCVTF (scalar, fixed-point)","Bits":"0|0|0|1|1|1|1|0|00:2|0|0|0|0|1|0|scale:6|Rn:5|Rd:5","Arch":"32-bit to single-precision variant","Syntax":"SCVTF <Sd>, <Wn>, #<fbits>","Code":"","Alias":""},
+{"Name":"SCVTF (scalar, fixed-point)","Bits":"0|0|0|1|1|1|1|0|01:2|0|0|0|0|1|0|scale:6|Rn:5|Rd:5","Arch":"32-bit to double-precision variant","Syntax":"SCVTF <Dd>, <Wn>, #<fbits>","Code":"","Alias":""},
+{"Name":"SCVTF (scalar, fixed-point)","Bits":"1|0|0|1|1|1|1|0|00:2|0|0|0|0|1|0|scale:6|Rn:5|Rd:5","Arch":"64-bit to single-precision variant","Syntax":"SCVTF <Sd>, <Xn>, #<fbits>","Code":"","Alias":""},
+{"Name":"SCVTF (scalar, fixed-point)","Bits":"1|0|0|1|1|1|1|0|01:2|0|0|0|0|1|0|scale:6|Rn:5|Rd:5","Arch":"64-bit to double-precision variant","Syntax":"SCVTF <Dd>, <Xn>, #<fbits>","Code":"","Alias":""},
+{"Name":"SCVTF (scalar, integer)","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|0|0|1|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"32-bit to single-precision variant","Syntax":"SCVTF <Sd>, <Wn>","Code":"","Alias":""},
+{"Name":"SCVTF (scalar, integer)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|0|1|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"32-bit to double-precision variant","Syntax":"SCVTF <Dd>, <Wn>","Code":"","Alias":""},
+{"Name":"SCVTF (scalar, integer)","Bits":"1|0|0|1|1|1|1|0|00:2|1|0|0|0|1|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"64-bit to single-precision variant","Syntax":"SCVTF <Sd>, <Xn>","Code":"","Alias":""},
+{"Name":"SCVTF (scalar, integer)","Bits":"1|0|0|1|1|1|1|0|01:2|1|0|0|0|1|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"64-bit to double-precision variant","Syntax":"SCVTF <Dd>, <Xn>","Code":"","Alias":""},
+{"Name":"SHA1C","Bits":"0|1|0|1|1|1|1|0|0|0|0|Rm:5|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"SHA1C <Qd>, <Sn>, <Vm>.4S","Code":"","Alias":""},
+{"Name":"SHA1H","Bits":"0|1|0|1|1|1|1|0|0|0|1|0|1|0|0|0|0|0|0|0|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"SHA1H <Sd>, <Sn>","Code":"","Alias":""},
+{"Name":"SHA1M","Bits":"0|1|0|1|1|1|1|0|0|0|0|Rm:5|0|0|1|0|0|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"SHA1M <Qd>, <Sn>, <Vm>.4S","Code":"","Alias":""},
+{"Name":"SHA1P","Bits":"0|1|0|1|1|1|1|0|0|0|0|Rm:5|0|0|0|1|0|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"SHA1P <Qd>, <Sn>, <Vm>.4S","Code":"","Alias":""},
+{"Name":"SHA1SU0","Bits":"0|1|0|1|1|1|1|0|0|0|0|Rm:5|0|0|1|1|0|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"SHA1SU0 <Vd>.4S, <Vn>.4S, <Vm>.4S","Code":"","Alias":""},
+{"Name":"SHA1SU1","Bits":"0|1|0|1|1|1|1|0|0|0|1|0|1|0|0|0|0|0|0|1|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"SHA1SU1 <Vd>.4S, <Vn>.4S","Code":"","Alias":""},
+{"Name":"SHA256H2","Bits":"0|1|0|1|1|1|1|0|0|0|0|Rm:5|0|1|0|1|0|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"SHA256H2 <Qd>, <Qn>, <Vm>.4S","Code":"","Alias":""},
+{"Name":"SHA256H","Bits":"0|1|0|1|1|1|1|0|0|0|0|Rm:5|0|1|0|0|0|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"SHA256H <Qd>, <Qn>, <Vm>.4S","Code":"","Alias":""},
+{"Name":"SHA256SU0","Bits":"0|1|0|1|1|1|1|0|0|0|1|0|1|0|0|0|0|0|1|0|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"SHA256SU0 <Vd>.4S, <Vn>.4S","Code":"","Alias":""},
+{"Name":"SHA256SU1","Bits":"0|1|0|1|1|1|1|0|0|0|0|Rm:5|0|1|1|0|0|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"SHA256SU1 <Vd>.4S, <Vn>.4S, <Vm>.4S","Code":"","Alias":""},
+{"Name":"SHADD","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|0|0|0|0|0|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"SHADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"SHL","Bits":"0|1|0|1|1|1|1|1|0|immh:4|immb:3|0|1|0|1|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SHL <V><d>, <V><n>, #<shift>","Code":"","Alias":""},
+{"Name":"SHL","Bits":"0|Q|0|0|1|1|1|1|0|immh:4|immb:3|0|1|0|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SHL <Vd>.<T>, <Vn>.<T>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"SHLL, SHLL2","Bits":"0|0|1|0|1|1|1|0|size:2|1|0|0|0|0|1|0|0|1|1|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"SHLL <Vd>.<Ta>, <Vn>.<Tb>, #<shift>","Code":"","Alias":""},
+{"Name":"SHLL, SHLL2","Bits":"0|1|1|0|1|1|1|0|size:2|1|0|0|0|0|1|0|0|1|1|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"SHLL2 <Vd>.<Ta>, <Vn>.<Tb>, #<shift>","Code":"","Alias":""},
+{"Name":"SHRN, SHRN2","Bits":"0|0|0|0|1|1|1|1|0|immh:4|immb:3|1|0|0|0|0|1|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"SHRN <Vd>.<Tb>, <Vn>.<Ta>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"SHRN, SHRN2","Bits":"0|1|0|0|1|1|1|1|0|immh:4|immb:3|1|0|0|0|0|1|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"SHRN2 <Vd>.<Tb>, <Vn>.<Ta>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"SHSUB","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|0|0|1|0|0|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"SHSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"SLI","Bits":"0|1|1|1|1|1|1|1|0|immh:4|immb:3|0|1|0|1|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SLI <V><d>, <V><n>, #<shift>","Code":"","Alias":""},
+{"Name":"SLI","Bits":"0|Q|1|0|1|1|1|1|0|immh:4|immb:3|0|1|0|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SLI <Vd>.<T>, <Vn>.<T>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"SMAX","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|0|1|1|0|0|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"SMAX <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"SMAXP","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|1|0|1|0|0|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"SMAXP <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"SMAXV","Bits":"0|Q|0|0|1|1|1|0|size:2|1|1|0|0|0|0|1|0|1|0|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"SMAXV <V><d>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"SMIN","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|0|1|1|0|1|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"SMIN <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"SMINP","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|1|0|1|0|1|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"SMINP <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"SMINV","Bits":"0|Q|0|0|1|1|1|0|size:2|1|1|0|0|0|1|1|0|1|0|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"SMINV <V><d>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"SMLAL, SMLAL2 (by element)","Bits":"0|0|0|0|1|1|1|1|size:2|L|M|Rm:4|0|0|1|0|H|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"SMLAL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"SMLAL, SMLAL2 (by element)","Bits":"0|1|0|0|1|1|1|1|size:2|L|M|Rm:4|0|0|1|0|H|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"SMLAL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"SMLAL, SMLAL2 (vector)","Bits":"0|0|0|0|1|1|1|0|size:2|1|Rm:5|1|0|0|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SMLAL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"SMLAL, SMLAL2 (vector)","Bits":"0|1|0|0|1|1|1|0|size:2|1|Rm:5|1|0|0|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SMLAL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"SMLSL, SMLSL2 (by element)","Bits":"0|0|0|0|1|1|1|1|size:2|L|M|Rm:4|0|1|1|0|H|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"SMLSL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"SMLSL, SMLSL2 (by element)","Bits":"0|1|0|0|1|1|1|1|size:2|L|M|Rm:4|0|1|1|0|H|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"SMLSL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"SMLSL, SMLSL2 (vector)","Bits":"0|0|0|0|1|1|1|0|size:2|1|Rm:5|1|0|1|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SMLSL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"SMLSL, SMLSL2 (vector)","Bits":"0|1|0|0|1|1|1|0|size:2|1|Rm:5|1|0|1|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SMLSL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"SMOV","Bits":"0|0|0|0|1|1|1|0|0|0|0|imm5:5|0|0|1|0|1|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"SMOV <Wd>, <Vn>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"SMOV","Bits":"0|1|0|0|1|1|1|0|0|0|0|imm5:5|0|0|1|0|1|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SMOV <Xd>, <Vn>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"SMULL, SMULL2 (by element)","Bits":"0|0|0|0|1|1|1|1|size:2|L|M|Rm:4|1|0|1|0|H|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"SMULL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"SMULL, SMULL2 (by element)","Bits":"0|1|0|0|1|1|1|1|size:2|L|M|Rm:4|1|0|1|0|H|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"SMULL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"SMULL, SMULL2 (vector)","Bits":"0|0|0|0|1|1|1|0|size:2|1|Rm:5|1|1|0|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SMULL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"SMULL, SMULL2 (vector)","Bits":"0|1|0|0|1|1|1|0|size:2|1|Rm:5|1|1|0|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SMULL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"SQABS","Bits":"0|1|0|1|1|1|1|0|size:2|1|0|0|0|0|0|0|1|1|1|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQABS <V><d>, <V><n>","Code":"","Alias":""},
+{"Name":"SQABS","Bits":"0|Q|0|0|1|1|1|0|size:2|1|0|0|0|0|0|0|1|1|1|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQABS <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"SQADD","Bits":"0|1|0|1|1|1|1|0|size:2|1|Rm:5|0|0|0|0|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQADD <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"SQADD","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|0|0|0|0|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"SQDMLAL, SQDMLAL2 (by element)","Bits":"0|1|0|1|1|1|1|1|size:2|L|M|Rm:4|0|0|1|1|H|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"SQDMLAL, SQDMLAL2 (by element)","Bits":"0|0|0|0|1|1|1|1|size:2|L|M|Rm:4|0|0|1|1|H|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQDMLAL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"SQDMLAL, SQDMLAL2 (by element)","Bits":"0|1|0|0|1|1|1|1|size:2|L|M|Rm:4|0|0|1|1|H|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQDMLAL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"SQDMLAL, SQDMLAL2 (vector)","Bits":"0|1|0|1|1|1|1|0|size:2|1|Rm:5|1|0|0|1|0|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQDMLAL <Va><d>, <Vb><n>, <Vb><m>","Code":"","Alias":""},
+{"Name":"SQDMLAL, SQDMLAL2 (vector)","Bits":"0|0|0|0|1|1|1|0|size:2|1|Rm:5|1|0|0|1|0|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQDMLAL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"SQDMLAL, SQDMLAL2 (vector)","Bits":"0|1|0|0|1|1|1|0|size:2|1|Rm:5|1|0|0|1|0|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQDMLAL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"SQDMLSL, SQDMLSL2 (by element)","Bits":"0|1|0|1|1|1|1|1|size:2|L|M|Rm:4|0|1|1|1|H|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQDMLSL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"SQDMLSL, SQDMLSL2 (by element)","Bits":"0|0|0|0|1|1|1|1|size:2|L|M|Rm:4|0|1|1|1|H|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQDMLSL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"SQDMLSL, SQDMLSL2 (by element)","Bits":"0|1|0|0|1|1|1|1|size:2|L|M|Rm:4|0|1|1|1|H|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQDMLSL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"SQDMLSL, SQDMLSL2 (vector)","Bits":"0|1|0|1|1|1|1|0|size:2|1|Rm:5|1|0|1|1|0|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQDMLSL <Va><d>, <Vb><n>, <Vb><m>","Code":"","Alias":""},
+{"Name":"SQDMLSL, SQDMLSL2 (vector)","Bits":"0|0|0|0|1|1|1|0|size:2|1|Rm:5|1|0|1|1|0|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQDMLSL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"SQDMLSL, SQDMLSL2 (vector)","Bits":"0|1|0|0|1|1|1|0|size:2|1|Rm:5|1|0|1|1|0|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQDMLSL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"SQDMULH (by element)","Bits":"0|1|0|1|1|1|1|1|size:2|L|M|Rm:4|1|1|0|0|H|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQDMULH <V><d>, <V><n>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"SQDMULH (by element)","Bits":"0|Q|0|0|1|1|1|1|size:2|L|M|Rm:4|1|1|0|0|H|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQDMULH <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"SQDMULH (vector)","Bits":"0|1|0|1|1|1|1|0|size:2|1|Rm:5|1|0|1|1|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQDMULH <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"SQDMULH (vector)","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|1|0|1|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQDMULH <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"SQDMULL, SQDMULL2 (by element)","Bits":"0|1|0|1|1|1|1|1|size:2|L|M|Rm:4|1|0|1|1|H|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQDMULL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"SQDMULL, SQDMULL2 (by element)","Bits":"0|0|0|0|1|1|1|1|size:2|L|M|Rm:4|1|0|1|1|H|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQDMULL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"SQDMULL, SQDMULL2 (by element)","Bits":"0|1|0|0|1|1|1|1|size:2|L|M|Rm:4|1|0|1|1|H|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQDMULL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"SQDMULL, SQDMULL2 (vector)","Bits":"0|1|0|1|1|1|1|0|size:2|1|Rm:5|1|1|0|1|0|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQDMULL <Va><d>, <Vb><n>, <Vb><m>","Code":"","Alias":""},
+{"Name":"SQDMULL, SQDMULL2 (vector)","Bits":"0|0|0|0|1|1|1|0|size:2|1|Rm:5|1|1|0|1|0|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQDMULL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"SQDMULL, SQDMULL2 (vector)","Bits":"0|1|0|0|1|1|1|0|size:2|1|Rm:5|1|1|0|1|0|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQDMULL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"SQNEG","Bits":"0|1|1|1|1|1|1|0|size:2|1|0|0|0|0|0|0|1|1|1|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQNEG <V><d>, <V><n>","Code":"","Alias":""},
+{"Name":"SQNEG","Bits":"0|Q|1|0|1|1|1|0|size:2|1|0|0|0|0|0|0|1|1|1|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQNEG <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"SQRDMULH (by element)","Bits":"0|1|0|1|1|1|1|1|size:2|L|M|Rm:4|1|1|0|1|H|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQRDMULH <V><d>, <V><n>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"SQRDMULH (by element)","Bits":"0|Q|0|0|1|1|1|1|size:2|L|M|Rm:4|1|1|0|1|H|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQRDMULH <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"SQRDMULH (vector)","Bits":"0|1|1|1|1|1|1|0|size:2|1|Rm:5|1|0|1|1|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQRDMULH <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"SQRDMULH (vector)","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|1|0|1|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQRDMULH <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"SQRSHL","Bits":"0|1|0|1|1|1|1|0|size:2|1|Rm:5|0|1|0|1|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQRSHL <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"SQRSHL","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|0|1|0|1|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQRSHL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"SQRSHRN, SQRSHRN2","Bits":"0|1|0|1|1|1|1|1|0|immh:4|immb:3|1|0|0|1|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQRSHRN <Vb><d>, <Va><n>, #<shift>","Code":"","Alias":""},
+{"Name":"SQRSHRN, SQRSHRN2","Bits":"0|0|0|0|1|1|1|1|0|immh:4|immb:3|1|0|0|1|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQRSHRN <Vd>.<Tb>, <Vn>.<Ta>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"SQRSHRN, SQRSHRN2","Bits":"0|1|0|0|1|1|1|1|0|immh:4|immb:3|1|0|0|1|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQRSHRN2 <Vd>.<Tb>, <Vn>.<Ta>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"SQRSHRUN, SQRSHRUN2","Bits":"0|1|1|1|1|1|1|1|0|immh:4|immb:3|1|0|0|0|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQRSHRUN <Vb><d>, <Va><n>, #<shift>","Code":"","Alias":""},
+{"Name":"SQRSHRUN, SQRSHRUN2","Bits":"0|0|1|0|1|1|1|1|0|immh:4|immb:3|1|0|0|0|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQRSHRUN <Vd>.<Tb>, <Vn>.<Ta>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"SQRSHRUN, SQRSHRUN2","Bits":"0|1|1|0|1|1|1|1|0|immh:4|immb:3|1|0|0|0|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQRSHRUN2 <Vd>.<Tb>, <Vn>.<Ta>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"SQSHL (immediate)","Bits":"0|1|0|1|1|1|1|1|0|immh:4|immb:3|0|1|1|1|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQSHL <V><d>, <V><n>, #<shift>","Code":"","Alias":""},
+{"Name":"SQSHL (immediate)","Bits":"0|Q|0|0|1|1|1|1|0|immh:4|immb:3|0|1|1|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQSHL <Vd>.<T>, <Vn>.<T>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"SQSHL (register)","Bits":"0|1|0|1|1|1|1|0|size:2|1|Rm:5|0|1|0|0|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQSHL <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"SQSHL (register)","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|0|1|0|0|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQSHL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"SQSHLU","Bits":"0|1|1|1|1|1|1|1|0|immh:4|immb:3|0|1|1|0|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQSHLU <V><d>, <V><n>, #<shift>","Code":"","Alias":""},
+{"Name":"SQSHLU","Bits":"0|Q|1|0|1|1|1|1|0|immh:4|immb:3|0|1|1|0|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQSHLU <Vd>.<T>, <Vn>.<T>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"SQSHRN, SQSHRN2","Bits":"0|1|0|1|1|1|1|1|0|immh:4|immb:3|1|0|0|1|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQSHRN <Vb><d>, <Va><n>, #<shift>","Code":"","Alias":""},
+{"Name":"SQSHRN, SQSHRN2","Bits":"0|0|0|0|1|1|1|1|0|immh:4|immb:3|1|0|0|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQSHRN <Vd>.<Tb>, <Vn>.<Ta>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"SQSHRN, SQSHRN2","Bits":"0|1|0|0|1|1|1|1|0|immh:4|immb:3|1|0|0|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQSHRN2 <Vd>.<Tb>, <Vn>.<Ta>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"SQSHRUN, SQSHRUN2","Bits":"0|1|1|1|1|1|1|1|0|immh:4|immb:3|1|0|0|0|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQSHRUN <Vb><d>, <Va><n>, #<shift>","Code":"","Alias":""},
+{"Name":"SQSHRUN, SQSHRUN2","Bits":"0|0|1|0|1|1|1|1|0|immh:4|immb:3|1|0|0|0|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQSHRUN <Vd>.<Tb>, <Vn>.<Ta>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"SQSHRUN, SQSHRUN2","Bits":"0|1|1|0|1|1|1|1|0|immh:4|immb:3|1|0|0|0|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQSHRUN2 <Vd>.<Tb>, <Vn>.<Ta>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"SQSUB","Bits":"0|1|0|1|1|1|1|0|size:2|1|Rm:5|0|0|1|0|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQSUB <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"SQSUB","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|0|0|1|0|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"SQXTN, SQXTN2","Bits":"0|1|0|1|1|1|1|0|size:2|1|0|0|0|0|1|0|1|0|0|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQXTN <Vb><d>, <Va><n>","Code":"","Alias":""},
+{"Name":"SQXTN, SQXTN2","Bits":"0|0|0|0|1|1|1|0|size:2|1|0|0|0|0|1|0|1|0|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQXTN <Vd>.<Tb>, <Vn>.<Ta>","Code":"","Alias":""},
+{"Name":"SQXTN, SQXTN2","Bits":"0|1|0|0|1|1|1|0|size:2|1|0|0|0|0|1|0|1|0|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQXTN2 <Vd>.<Tb>, <Vn>.<Ta>","Code":"","Alias":""},
+{"Name":"SQXTUN, SQXTUN2","Bits":"0|1|1|1|1|1|1|0|size:2|1|0|0|0|0|1|0|0|1|0|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQXTUN <Vb><d>, <Va><n>","Code":"","Alias":""},
+{"Name":"SQXTUN, SQXTUN2","Bits":"0|0|1|0|1|1|1|0|size:2|1|0|0|0|0|1|0|0|1|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQXTUN <Vd>.<Tb>, <Vn>.<Ta>","Code":"","Alias":""},
+{"Name":"SQXTUN, SQXTUN2","Bits":"0|1|1|0|1|1|1|0|size:2|1|0|0|0|0|1|0|0|1|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQXTUN2 <Vd>.<Tb>, <Vn>.<Ta>","Code":"","Alias":""},
+{"Name":"SRHADD","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|0|0|0|1|0|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"SRHADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"SRI","Bits":"0|1|1|1|1|1|1|1|0|immh:4|immb:3|0|1|0|0|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SRI <V><d>, <V><n>, #<shift>","Code":"","Alias":""},
+{"Name":"SRI","Bits":"0|Q|1|0|1|1|1|1|0|immh:4|immb:3|0|1|0|0|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SRI <Vd>.<T>, <Vn>.<T>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"SRSHL","Bits":"0|1|0|1|1|1|1|0|size:2|1|Rm:5|0|1|0|1|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SRSHL <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"SRSHL","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|0|1|0|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SRSHL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"SRSHR","Bits":"0|1|0|1|1|1|1|1|0|immh:4|immb:3|0|0|1|0|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SRSHR <V><d>, <V><n>, #<shift>","Code":"","Alias":""},
+{"Name":"SRSHR","Bits":"0|Q|0|0|1|1|1|1|0|immh:4|immb:3|0|0|1|0|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SRSHR <Vd>.<T>, <Vn>.<T>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"SRSRA","Bits":"0|1|0|1|1|1|1|1|0|immh:4|immb:3|0|0|1|1|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SRSRA <V><d>, <V><n>, #<shift>","Code":"","Alias":""},
+{"Name":"SRSRA","Bits":"0|Q|0|0|1|1|1|1|0|immh:4|immb:3|0|0|1|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SRSRA <Vd>.<T>, <Vn>.<T>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"SSHL","Bits":"0|1|0|1|1|1|1|0|size:2|1|Rm:5|0|1|0|0|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SSHL <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"SSHL","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|0|1|0|0|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SSHL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"SSHLL, SSHLL2","Bits":"0|0|0|0|1|1|1|1|0|immh:4|immb:3|1|0|1|0|0|1|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"SSHLL <Vd>.<Ta>, <Vn>.<Tb>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":"This instruction is used by the alias SXTL, SXTL2."},
+{"Name":"SSHLL, SSHLL2","Bits":"0|1|0|0|1|1|1|1|0|immh:4|immb:3|1|0|1|0|0|1|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"SSHLL2 <Vd>.<Ta>, <Vn>.<Tb>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":"This instruction is used by the alias SXTL, SXTL2."},
+{"Name":"SSHR","Bits":"0|1|0|1|1|1|1|1|0|immh:4|immb:3|0|0|0|0|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SSHR <V><d>, <V><n>, #<shift>","Code":"","Alias":""},
+{"Name":"SSHR","Bits":"0|Q|0|0|1|1|1|1|0|immh:4|immb:3|0|0|0|0|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SSHR <Vd>.<T>, <Vn>.<T>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"SSRA","Bits":"0|1|0|1|1|1|1|1|0|immh:4|immb:3|0|0|0|1|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SSRA <V><d>, <V><n>, #<shift>","Code":"","Alias":""},
+{"Name":"SSRA","Bits":"0|Q|0|0|1|1|1|1|0|immh:4|immb:3|0|0|0|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SSRA <Vd>.<T>, <Vn>.<T>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"SSUBL, SSUBL2","Bits":"0|0|0|0|1|1|1|0|size:2|1|Rm:5|0|0|1|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SSUBL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"SSUBL, SSUBL2","Bits":"0|1|0|0|1|1|1|0|size:2|1|Rm:5|0|0|1|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SSUBL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"SSUBW, SSUBW2","Bits":"0|0|0|0|1|1|1|0|size:2|1|Rm:5|0|0|1|1|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SSUBW <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"SSUBW, SSUBW2","Bits":"0|1|0|0|1|1|1|0|size:2|1|Rm:5|0|0|1|1|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SSUBW2 <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"ST1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|0|0|0|0|0|0|0|0|0111:4|size:2|Rn:5|Rt:5","Arch":"No offset One register variant","Syntax":"ST1 { <Vt>.<T> }, [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"ST1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|0|0|0|0|0|0|0|0|1010:4|size:2|Rn:5|Rt:5","Arch":"No offset Two registers variant","Syntax":"ST1 { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"ST1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|0|0|0|0|0|0|0|0|0110:4|size:2|Rn:5|Rt:5","Arch":"No offset Three registers variant","Syntax":"ST1 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"ST1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|0|0|0|0|0|0|0|0|0010:4|size:2|Rn:5|Rt:5","Arch":"No offset Four registers variant","Syntax":"ST1 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"ST1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|0|0|11111:5|0111:4|size:2|Rn:5|Rt:5","Arch":"Post-index One register, immediate offset variant","Syntax":"ST1 { <Vt>.<T> }, [<Xn|SP>], <imm>","Code":"","Alias":""},
+{"Name":"ST1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|0|0|Rm:5|0111:4|size:2|Rn:5|Rt:5","Arch":"Post-index One register, register offset variant","Syntax":"ST1 { <Vt>.<T> }, [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"ST1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|0|0|11111:5|1010:4|size:2|Rn:5|Rt:5","Arch":"Post-index Two registers, immediate offset variant","Syntax":"ST1 { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <imm>","Code":"","Alias":""},
+{"Name":"ST1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|0|0|Rm:5|1010:4|size:2|Rn:5|Rt:5","Arch":"Post-index Two registers, register offset variant","Syntax":"ST1 { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"ST1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|0|0|11111:5|0110:4|size:2|Rn:5|Rt:5","Arch":"Post-index Three registers, immediate offset variant","Syntax":"ST1 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <imm>","Code":"","Alias":""},
+{"Name":"ST1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|0|0|Rm:5|0110:4|size:2|Rn:5|Rt:5","Arch":"Post-index Three registers, register offset variant","Syntax":"ST1 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"ST1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|0|0|11111:5|0010:4|size:2|Rn:5|Rt:5","Arch":"Post-index Four registers, immediate offset variant","Syntax":"ST1 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <imm>","Code":"","Alias":""},
+{"Name":"ST1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|0|0|Rm:5|0010:4|size:2|Rn:5|Rt:5","Arch":"Post-index Four registers, register offset variant","Syntax":"ST1 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"ST1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|0|0|0|0|0|0|0|000:3|S|size:2|Rn:5|Rt:5","Arch":"No offset 8-bit variant","Syntax":"ST1 { <Vt>.B }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"ST1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|0|0|0|0|0|0|0|010:3|S|size:2|Rn:5|Rt:5","Arch":"No offset 16-bit variant","Syntax":"ST1 { <Vt>.H }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"ST1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|0|0|0|0|0|0|0|100:3|S|00:2|Rn:5|Rt:5","Arch":"No offset 32-bit variant","Syntax":"ST1 { <Vt>.S }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"ST1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|0|0|0|0|0|0|0|100:3|0|01:2|Rn:5|Rt:5","Arch":"No offset 64-bit variant","Syntax":"ST1 { <Vt>.D }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"ST1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|0|11111:5|000:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 8-bit, immediate offset variant","Syntax":"ST1 { <Vt>.B }[<index>], [<Xn|SP>], #1","Code":"","Alias":""},
+{"Name":"ST1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|0|Rm:5|000:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 8-bit, register offset variant","Syntax":"ST1 { <Vt>.B }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"ST1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|0|11111:5|010:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 16-bit, immediate offset variant","Syntax":"ST1 { <Vt>.H }[<index>], [<Xn|SP>], #2","Code":"","Alias":""},
+{"Name":"ST1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|0|Rm:5|010:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 16-bit, register offset variant","Syntax":"ST1 { <Vt>.H }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"ST1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|0|11111:5|100:3|S|00:2|Rn:5|Rt:5","Arch":"Post-index 32-bit, immediate offset variant","Syntax":"ST1 { <Vt>.S }[<index>], [<Xn|SP>], #4","Code":"","Alias":""},
+{"Name":"ST1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|0|Rm:5|100:3|S|00:2|Rn:5|Rt:5","Arch":"Post-index 32-bit, register offset variant","Syntax":"ST1 { <Vt>.S }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"ST1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|0|11111:5|100:3|0|01:2|Rn:5|Rt:5","Arch":"Post-index 64-bit, immediate offset variant","Syntax":"ST1 { <Vt>.D }[<index>], [<Xn|SP>], #8","Code":"","Alias":""},
+{"Name":"ST1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|0|Rm:5|100:3|0|01:2|Rn:5|Rt:5","Arch":"Post-index 64-bit, register offset variant","Syntax":"ST1 { <Vt>.D }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"ST2 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|0|0|0|0|0|0|0|0|1|0|0|0|size:2|Rn:5|Rt:5","Arch":"No offset No offset variant","Syntax":"ST2 { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"ST2 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|0|0|11111:5|1|0|0|0|size:2|Rn:5|Rt:5","Arch":"Post-index Immediate offset variant","Syntax":"ST2 { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <imm>","Code":"","Alias":""},
+{"Name":"ST2 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|0|0|Rm:5|1|0|0|0|size:2|Rn:5|Rt:5","Arch":"Post-index Register offset variant","Syntax":"ST2 { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"ST2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|0|1|0|0|0|0|0|000:3|S|size:2|Rn:5|Rt:5","Arch":"No offset 8-bit variant","Syntax":"ST2 { <Vt>.B, <Vt2>.B }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"ST2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|0|1|0|0|0|0|0|010:3|S|size:2|Rn:5|Rt:5","Arch":"No offset 16-bit variant","Syntax":"ST2 { <Vt>.H, <Vt2>.H }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"ST2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|0|1|0|0|0|0|0|100:3|S|00:2|Rn:5|Rt:5","Arch":"No offset 32-bit variant","Syntax":"ST2 { <Vt>.S, <Vt2>.S }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"ST2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|0|1|0|0|0|0|0|100:3|0|01:2|Rn:5|Rt:5","Arch":"No offset 64-bit variant","Syntax":"ST2 { <Vt>.D, <Vt2>.D }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"ST2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|1|11111:5|000:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 8-bit, immediate offset variant","Syntax":"ST2 { <Vt>.B, <Vt2>.B }[<index>], [<Xn|SP>], #2","Code":"","Alias":""},
+{"Name":"ST2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|1|Rm:5|000:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 8-bit, register offset variant","Syntax":"ST2 { <Vt>.B, <Vt2>.B }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"ST2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|1|11111:5|010:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 16-bit, immediate offset variant","Syntax":"ST2 { <Vt>.H, <Vt2>.H }[<index>], [<Xn|SP>], #4","Code":"","Alias":""},
+{"Name":"ST2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|1|Rm:5|010:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 16-bit, register offset variant","Syntax":"ST2 { <Vt>.H, <Vt2>.H }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"ST2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|1|11111:5|100:3|S|00:2|Rn:5|Rt:5","Arch":"Post-index 32-bit, immediate offset variant","Syntax":"ST2 { <Vt>.S, <Vt2>.S }[<index>], [<Xn|SP>], #8","Code":"","Alias":""},
+{"Name":"ST2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|1|Rm:5|100:3|S|00:2|Rn:5|Rt:5","Arch":"Post-index 32-bit, register offset variant","Syntax":"ST2 { <Vt>.S, <Vt2>.S }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"ST2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|1|11111:5|100:3|0|01:2|Rn:5|Rt:5","Arch":"Post-index 64-bit, immediate offset variant","Syntax":"ST2 { <Vt>.D, <Vt2>.D }[<index>], [<Xn|SP>], #16","Code":"","Alias":""},
+{"Name":"ST2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|1|Rm:5|100:3|0|01:2|Rn:5|Rt:5","Arch":"Post-index 64-bit, register offset variant","Syntax":"ST2 { <Vt>.D, <Vt2>.D }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"ST3 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|0|0|0|0|0|0|0|0|0|1|0|0|size:2|Rn:5|Rt:5","Arch":"No offset No offset variant","Syntax":"ST3 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"ST3 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|0|0|11111:5|0|1|0|0|size:2|Rn:5|Rt:5","Arch":"Post-index Immediate offset variant","Syntax":"ST3 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <imm>","Code":"","Alias":""},
+{"Name":"ST3 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|0|0|Rm:5|0|1|0|0|size:2|Rn:5|Rt:5","Arch":"Post-index Register offset variant","Syntax":"ST3 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"ST3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|0|0|0|0|0|0|0|001:3|S|size:2|Rn:5|Rt:5","Arch":"No offset 8-bit variant","Syntax":"ST3 { <Vt>.B, <Vt2>.B, <Vt3>.B }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"ST3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|0|0|0|0|0|0|0|011:3|S|size:2|Rn:5|Rt:5","Arch":"No offset 16-bit variant","Syntax":"ST3 { <Vt>.H, <Vt2>.H, <Vt3>.H }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"ST3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|0|0|0|0|0|0|0|101:3|S|00:2|Rn:5|Rt:5","Arch":"No offset 32-bit variant","Syntax":"ST3 { <Vt>.S, <Vt2>.S, <Vt3>.S }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"ST3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|0|0|0|0|0|0|0|101:3|0|01:2|Rn:5|Rt:5","Arch":"No offset 64-bit variant","Syntax":"ST3 { <Vt>.D, <Vt2>.D, <Vt3>.D }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"ST3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|0|11111:5|001:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 8-bit, immediate offset variant","Syntax":"ST3 { <Vt>.B, <Vt2>.B, <Vt3>.B }[<index>], [<Xn|SP>], #3","Code":"","Alias":""},
+{"Name":"ST3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|0|Rm:5|001:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 8-bit, register offset variant","Syntax":"ST3 { <Vt>.B, <Vt2>.B, <Vt3>.B }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"ST3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|0|11111:5|011:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 16-bit, immediate offset variant","Syntax":"ST3 { <Vt>.H, <Vt2>.H, <Vt3>.H }[<index>], [<Xn|SP>], #6","Code":"","Alias":""},
+{"Name":"ST3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|0|Rm:5|011:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 16-bit, register offset variant","Syntax":"ST3 { <Vt>.H, <Vt2>.H, <Vt3>.H }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"ST3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|0|11111:5|101:3|S|00:2|Rn:5|Rt:5","Arch":"Post-index 32-bit, immediate offset variant","Syntax":"ST3 { <Vt>.S, <Vt2>.S, <Vt3>.S }[<index>], [<Xn|SP>], #12","Code":"","Alias":""},
+{"Name":"ST3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|0|Rm:5|101:3|S|00:2|Rn:5|Rt:5","Arch":"Post-index 32-bit, register offset variant","Syntax":"ST3 { <Vt>.S, <Vt2>.S, <Vt3>.S }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"ST3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|0|11111:5|101:3|0|01:2|Rn:5|Rt:5","Arch":"Post-index 64-bit, immediate offset variant","Syntax":"ST3 { <Vt>.D, <Vt2>.D, <Vt3>.D }[<index>], [<Xn|SP>], #24","Code":"","Alias":""},
+{"Name":"ST3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|0|Rm:5|101:3|0|01:2|Rn:5|Rt:5","Arch":"Post-index 64-bit, register offset variant","Syntax":"ST3 { <Vt>.D, <Vt2>.D, <Vt3>.D }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"ST4 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|0|0|0|0|0|0|0|0|0|0|0|0|size:2|Rn:5|Rt:5","Arch":"No offset No offset variant","Syntax":"ST4 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"ST4 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|0|0|11111:5|0|0|0|0|size:2|Rn:5|Rt:5","Arch":"Post-index Immediate offset variant","Syntax":"ST4 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <imm>","Code":"","Alias":""},
+{"Name":"ST4 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|0|0|Rm:5|0|0|0|0|size:2|Rn:5|Rt:5","Arch":"Post-index Register offset variant","Syntax":"ST4 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"ST4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|0|1|0|0|0|0|0|001:3|S|size:2|Rn:5|Rt:5","Arch":"No offset 8-bit variant","Syntax":"ST4 { <Vt>.B, <Vt2>.B, <Vt3>.B, <Vt4>.B }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"ST4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|0|1|0|0|0|0|0|011:3|S|size:2|Rn:5|Rt:5","Arch":"No offset 16-bit variant","Syntax":"ST4 { <Vt>.H, <Vt2>.H, <Vt3>.H, <Vt4>.H }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"ST4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|0|1|0|0|0|0|0|101:3|S|00:2|Rn:5|Rt:5","Arch":"No offset 32-bit variant","Syntax":"ST4 { <Vt>.S, <Vt2>.S, <Vt3>.S, <Vt4>.S }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"ST4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|0|1|0|0|0|0|0|101:3|0|01:2|Rn:5|Rt:5","Arch":"No offset 64-bit variant","Syntax":"ST4 { <Vt>.D, <Vt2>.D, <Vt3>.D, <Vt4>.D }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"ST4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|1|11111:5|001:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 8-bit, immediate offset variant","Syntax":"ST4 { <Vt>.B, <Vt2>.B, <Vt3>.B, <Vt4>.B }[<index>], [<Xn|SP>], #4","Code":"","Alias":""},
+{"Name":"ST4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|1|Rm:5|001:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 8-bit, register offset variant","Syntax":"ST4 { <Vt>.B, <Vt2>.B, <Vt3>.B, <Vt4>.B }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"ST4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|1|11111:5|011:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 16-bit, immediate offset variant","Syntax":"ST4 { <Vt>.H, <Vt2>.H, <Vt3>.H, <Vt4>.H }[<index>], [<Xn|SP>], #8","Code":"","Alias":""},
+{"Name":"ST4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|1|Rm:5|011:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 16-bit, register offset variant","Syntax":"ST4 { <Vt>.H, <Vt2>.H, <Vt3>.H, <Vt4>.H }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"ST4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|1|11111:5|101:3|S|00:2|Rn:5|Rt:5","Arch":"Post-index 32-bit, immediate offset variant","Syntax":"ST4 { <Vt>.S, <Vt2>.S, <Vt3>.S, <Vt4>.S }[<index>], [<Xn|SP>], #16","Code":"","Alias":""},
+{"Name":"ST4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|1|Rm:5|101:3|S|00:2|Rn:5|Rt:5","Arch":"Post-index 32-bit, register offset variant","Syntax":"ST4 { <Vt>.S, <Vt2>.S, <Vt3>.S, <Vt4>.S }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"ST4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|1|11111:5|101:3|0|01:2|Rn:5|Rt:5","Arch":"Post-index 64-bit, immediate offset variant","Syntax":"ST4 { <Vt>.D, <Vt2>.D, <Vt3>.D, <Vt4>.D }[<index>], [<Xn|SP>], #32","Code":"","Alias":""},
+{"Name":"ST4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|1|Rm:5|101:3|0|01:2|Rn:5|Rt:5","Arch":"Post-index 64-bit, register offset variant","Syntax":"ST4 { <Vt>.D, <Vt2>.D, <Vt3>.D, <Vt4>.D }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"STNP (SIMD&FP)","Bits":"00:2|1|0|1|1|0|0|0|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"STNP <St1>, <St2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
+{"Name":"STNP (SIMD&FP)","Bits":"01:2|1|0|1|1|0|0|0|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"STNP <Dt1>, <Dt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
+{"Name":"STNP (SIMD&FP)","Bits":"10:2|1|0|1|1|0|0|0|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"128-bit variant","Syntax":"STNP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
+{"Name":"STP (SIMD&FP)","Bits":"00:2|1|0|1|1|0|0|1|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Post-index 32-bit variant","Syntax":"STP <St1>, <St2>, [<Xn|SP>], #<imm>","Code":"","Alias":""},
+{"Name":"STP (SIMD&FP)","Bits":"01:2|1|0|1|1|0|0|1|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Post-index 64-bit variant","Syntax":"STP <Dt1>, <Dt2>, [<Xn|SP>], #<imm>","Code":"","Alias":""},
+{"Name":"STP (SIMD&FP)","Bits":"10:2|1|0|1|1|0|0|1|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Post-index 128-bit variant","Syntax":"STP <Qt1>, <Qt2>, [<Xn|SP>], #<imm>","Code":"","Alias":""},
+{"Name":"STP (SIMD&FP)","Bits":"00:2|1|0|1|1|0|1|1|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Pre-index 32-bit variant","Syntax":"STP <St1>, <St2>, [<Xn|SP>, #<imm>]!","Code":"","Alias":""},
+{"Name":"STP (SIMD&FP)","Bits":"01:2|1|0|1|1|0|1|1|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Pre-index 64-bit variant","Syntax":"STP <Dt1>, <Dt2>, [<Xn|SP>, #<imm>]!","Code":"","Alias":""},
+{"Name":"STP (SIMD&FP)","Bits":"10:2|1|0|1|1|0|1|1|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Pre-index 128-bit variant","Syntax":"STP <Qt1>, <Qt2>, [<Xn|SP>, #<imm>]!","Code":"","Alias":""},
+{"Name":"STP (SIMD&FP)","Bits":"00:2|1|0|1|1|0|1|0|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Signed offset 32-bit variant","Syntax":"STP <St1>, <St2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
+{"Name":"STP (SIMD&FP)","Bits":"01:2|1|0|1|1|0|1|0|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Signed offset 64-bit variant","Syntax":"STP <Dt1>, <Dt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
+{"Name":"STP (SIMD&FP)","Bits":"10:2|1|0|1|1|0|1|0|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Signed offset 128-bit variant","Syntax":"STP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
+{"Name":"STR (immediate, SIMD&FP)","Bits":"00:2|1|1|1|1|0|0|00:2|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 8-bit variant","Syntax":"STR <Bt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
+{"Name":"STR (immediate, SIMD&FP)","Bits":"01:2|1|1|1|1|0|0|00:2|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 16-bit variant","Syntax":"STR <Ht>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
+{"Name":"STR (immediate, SIMD&FP)","Bits":"10:2|1|1|1|1|0|0|00:2|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 32-bit variant","Syntax":"STR <St>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
+{"Name":"STR (immediate, SIMD&FP)","Bits":"11:2|1|1|1|1|0|0|00:2|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 64-bit variant","Syntax":"STR <Dt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
+{"Name":"STR (immediate, SIMD&FP)","Bits":"00:2|1|1|1|1|0|0|10:2|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 128-bit variant","Syntax":"STR <Qt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
+{"Name":"STR (immediate, SIMD&FP)","Bits":"00:2|1|1|1|1|0|0|00:2|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index 8-bit variant","Syntax":"STR <Bt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
+{"Name":"STR (immediate, SIMD&FP)","Bits":"01:2|1|1|1|1|0|0|00:2|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index 16-bit variant","Syntax":"STR <Ht>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
+{"Name":"STR (immediate, SIMD&FP)","Bits":"10:2|1|1|1|1|0|0|00:2|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index 32-bit variant","Syntax":"STR <St>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
+{"Name":"STR (immediate, SIMD&FP)","Bits":"11:2|1|1|1|1|0|0|00:2|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index 64-bit variant","Syntax":"STR <Dt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
+{"Name":"STR (immediate, SIMD&FP)","Bits":"00:2|1|1|1|1|0|0|10:2|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index 128-bit variant","Syntax":"STR <Qt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
+{"Name":"STR (immediate, SIMD&FP)","Bits":"00:2|1|1|1|1|0|1|00:2|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 8-bit variant","Syntax":"STR <Bt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
+{"Name":"STR (immediate, SIMD&FP)","Bits":"01:2|1|1|1|1|0|1|00:2|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 16-bit variant","Syntax":"STR <Ht>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
+{"Name":"STR (immediate, SIMD&FP)","Bits":"10:2|1|1|1|1|0|1|00:2|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 32-bit variant","Syntax":"STR <St>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
+{"Name":"STR (immediate, SIMD&FP)","Bits":"11:2|1|1|1|1|0|1|00:2|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 64-bit variant","Syntax":"STR <Dt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
+{"Name":"STR (immediate, SIMD&FP)","Bits":"00:2|1|1|1|1|0|1|10:2|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 128-bit variant","Syntax":"STR <Qt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
+{"Name":"STR (register, SIMD&FP)","Bits":"00:2|1|1|1|1|0|0|00:2|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"8-bit variant","Syntax":"STR <Bt>, [<Xn|SP>, (<Wm>|<Xm>), <extend> {<amount>}]","Code":"","Alias":""},
+{"Name":"STR (register, SIMD&FP)","Bits":"00:2|1|1|1|1|0|0|00:2|1|Rm:5|011:3|S|1|0|Rn:5|Rt:5","Arch":"8-bit variant","Syntax":"STR <Bt>, [<Xn|SP>, <Xm>{, LSL <amount>}]","Code":"","Alias":""},
+{"Name":"STR (register, SIMD&FP)","Bits":"01:2|1|1|1|1|0|0|00:2|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"16-bit variant","Syntax":"STR <Ht>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]","Code":"","Alias":""},
+{"Name":"STR (register, SIMD&FP)","Bits":"10:2|1|1|1|1|0|0|00:2|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"STR <St>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]","Code":"","Alias":""},
+{"Name":"STR (register, SIMD&FP)","Bits":"11:2|1|1|1|1|0|0|00:2|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"STR <Dt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]","Code":"","Alias":""},
+{"Name":"STR (register, SIMD&FP)","Bits":"00:2|1|1|1|1|0|0|10:2|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"128-bit variant","Syntax":"STR <Qt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]","Code":"","Alias":""},
+{"Name":"STUR (SIMD&FP)","Bits":"00:2|1|1|1|1|0|0|00:2|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"8-bit variant","Syntax":"STUR <Bt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"STUR (SIMD&FP)","Bits":"01:2|1|1|1|1|0|0|00:2|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"16-bit variant","Syntax":"STUR <Ht>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"STUR (SIMD&FP)","Bits":"10:2|1|1|1|1|0|0|00:2|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"STUR <St>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"STUR (SIMD&FP)","Bits":"11:2|1|1|1|1|0|0|00:2|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"STUR <Dt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"STUR (SIMD&FP)","Bits":"00:2|1|1|1|1|0|0|10:2|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"128-bit variant","Syntax":"STUR <Qt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"SUB (vector)","Bits":"0|1|1|1|1|1|1|0|size:2|1|Rm:5|1|0|0|0|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SUB <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"SUB (vector)","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|1|0|0|0|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"SUBHN, SUBHN2","Bits":"0|0|0|0|1|1|1|0|size:2|1|Rm:5|0|1|1|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SUBHN <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>","Code":"","Alias":""},
+{"Name":"SUBHN, SUBHN2","Bits":"0|1|0|0|1|1|1|0|size:2|1|Rm:5|0|1|1|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SUBHN2 <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>","Code":"","Alias":""},
+{"Name":"SUQADD","Bits":"0|1|0|1|1|1|1|0|size:2|1|0|0|0|0|0|0|0|1|1|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SUQADD <V><d>, <V><n>","Code":"","Alias":""},
+{"Name":"SUQADD","Bits":"0|Q|0|0|1|1|1|0|size:2|1|0|0|0|0|0|0|0|1|1|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SUQADD <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"SXTL, SXTL2","Bits":"0|0|0|0|1|1|1|1|0|immh:4|0|0|0|1|0|1|0|0|1|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"SXTL <Vd>.<Ta>, <Vn>.<Tb>","Code":"","Alias":"This instruction is an alias of the SSHLL, SSHLL2 instruction."},
+{"Name":"SXTL, SXTL2","Bits":"0|1|0|0|1|1|1|1|0|immh:4|0|0|0|1|0|1|0|0|1|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"SXTL2 <Vd>.<Ta>, <Vn>.<Tb>","Code":"","Alias":"This instruction is an alias of the SSHLL, SSHLL2 instruction."},
+{"Name":"TBL","Bits":"0|Q|0|0|1|1|1|0|0|0|0|Rm:5|0|01:2|0|0|0|Rn:5|Rd:5","Arch":"Two register table variant","Syntax":"TBL <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B }, <Vm>.<Ta>","Code":"","Alias":""},
+{"Name":"TBL","Bits":"0|Q|0|0|1|1|1|0|0|0|0|Rm:5|0|10:2|0|0|0|Rn:5|Rd:5","Arch":"Three register table variant","Syntax":"TBL <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B, <Vn+2>.16B }, <Vm>.<Ta>","Code":"","Alias":""},
+{"Name":"TBL","Bits":"0|Q|0|0|1|1|1|0|0|0|0|Rm:5|0|11:2|0|0|0|Rn:5|Rd:5","Arch":"Four register table variant","Syntax":"TBL <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B, <Vn+2>.16B, <Vn+3>.16B }, <Vm>.<Ta>","Code":"","Alias":""},
+{"Name":"TBL","Bits":"0|Q|0|0|1|1|1|0|0|0|0|Rm:5|0|00:2|0|0|0|Rn:5|Rd:5","Arch":"Single register table variant","Syntax":"TBL <Vd>.<Ta>, { <Vn>.16B }, <Vm>.<Ta>","Code":"","Alias":""},
+{"Name":"TBX","Bits":"0|Q|0|0|1|1|1|0|0|0|0|Rm:5|0|01:2|1|0|0|Rn:5|Rd:5","Arch":"Two register table variant","Syntax":"TBX <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B }, <Vm>.<Ta>","Code":"","Alias":""},
+{"Name":"TBX","Bits":"0|Q|0|0|1|1|1|0|0|0|0|Rm:5|0|10:2|1|0|0|Rn:5|Rd:5","Arch":"Three register table variant","Syntax":"TBX <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B, <Vn+2>.16B }, <Vm>.<Ta>","Code":"","Alias":""},
+{"Name":"TBX","Bits":"0|Q|0|0|1|1|1|0|0|0|0|Rm:5|0|11:2|1|0|0|Rn:5|Rd:5","Arch":"Four register table variant","Syntax":"TBX <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B, <Vn+2>.16B, <Vn+3>.16B }, <Vm>.<Ta>","Code":"","Alias":""},
+{"Name":"TBX","Bits":"0|Q|0|0|1|1|1|0|0|0|0|Rm:5|0|00:2|1|0|0|Rn:5|Rd:5","Arch":"Single register table variant","Syntax":"TBX <Vd>.<Ta>, { <Vn>.16B }, <Vm>.<Ta>","Code":"","Alias":""},
+{"Name":"TRN1","Bits":"0|Q|0|0|1|1|1|0|size:2|0|Rm:5|0|0|1|0|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"TRN1 <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"TRN2","Bits":"0|Q|0|0|1|1|1|0|size:2|0|Rm:5|0|1|1|0|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"TRN2 <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"UABA","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|0|1|1|1|1|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"UABA <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"UABAL, UABAL2","Bits":"0|0|1|0|1|1|1|0|size:2|1|Rm:5|0|1|0|1|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"UABAL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"UABAL, UABAL2","Bits":"0|1|1|0|1|1|1|0|size:2|1|Rm:5|0|1|0|1|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"UABAL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"UABD","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|0|1|1|1|0|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"UABD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"UABDL, UABDL2","Bits":"0|0|1|0|1|1|1|0|size:2|1|Rm:5|0|1|1|1|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"UABDL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"UABDL, UABDL2","Bits":"0|1|1|0|1|1|1|0|size:2|1|Rm:5|0|1|1|1|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"UABDL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"UADALP","Bits":"0|Q|1|0|1|1|1|0|size:2|1|0|0|0|0|0|0|1|1|0|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"UADALP <Vd>.<Ta>, <Vn>.<Tb>","Code":"","Alias":""},
+{"Name":"UADDL, UADDL2","Bits":"0|0|1|0|1|1|1|0|size:2|1|Rm:5|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"UADDL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"UADDL, UADDL2","Bits":"0|1|1|0|1|1|1|0|size:2|1|Rm:5|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"UADDL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"UADDLP","Bits":"0|Q|1|0|1|1|1|0|size:2|1|0|0|0|0|0|0|0|1|0|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"UADDLP <Vd>.<Ta>, <Vn>.<Tb>","Code":"","Alias":""},
+{"Name":"UADDLV","Bits":"0|Q|1|0|1|1|1|0|size:2|1|1|0|0|0|0|0|0|1|1|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"UADDLV <V><d>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"UADDW, UADDW2","Bits":"0|0|1|0|1|1|1|0|size:2|1|Rm:5|0|0|0|1|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"UADDW <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"UADDW, UADDW2","Bits":"0|1|1|0|1|1|1|0|size:2|1|Rm:5|0|0|0|1|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"UADDW2 <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"UCVTF (vector, fixed-point)","Bits":"0|1|1|1|1|1|1|1|0|immh:4|immb:3|1|1|1|0|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"UCVTF <V><d>, <V><n>, #<fbits>","Code":"","Alias":""},
+{"Name":"UCVTF (vector, fixed-point)","Bits":"0|Q|1|0|1|1|1|1|0|immh:4|immb:3|1|1|1|0|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"UCVTF <Vd>.<T>, <Vn>.<T>, #<fbits>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"UCVTF (vector, integer)","Bits":"0|1|1|1|1|1|1|0|0|sz|1|0|0|0|0|1|1|1|0|1|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"UCVTF <V><d>, <V><n>","Code":"","Alias":""},
+{"Name":"UCVTF (vector, integer)","Bits":"0|Q|1|0|1|1|1|0|0|sz|1|0|0|0|0|1|1|1|0|1|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"UCVTF <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"UCVTF (scalar, fixed-point)","Bits":"0|0|0|1|1|1|1|0|00:2|0|0|0|0|1|1|scale:6|Rn:5|Rd:5","Arch":"32-bit to single-precision variant","Syntax":"UCVTF <Sd>, <Wn>, #<fbits>","Code":"","Alias":""},
+{"Name":"UCVTF (scalar, fixed-point)","Bits":"0|0|0|1|1|1|1|0|01:2|0|0|0|0|1|1|scale:6|Rn:5|Rd:5","Arch":"32-bit to double-precision variant","Syntax":"UCVTF <Dd>, <Wn>, #<fbits>","Code":"","Alias":""},
+{"Name":"UCVTF (scalar, fixed-point)","Bits":"1|0|0|1|1|1|1|0|00:2|0|0|0|0|1|1|scale:6|Rn:5|Rd:5","Arch":"64-bit to single-precision variant","Syntax":"UCVTF <Sd>, <Xn>, #<fbits>","Code":"","Alias":""},
+{"Name":"UCVTF (scalar, fixed-point)","Bits":"1|0|0|1|1|1|1|0|01:2|0|0|0|0|1|1|scale:6|Rn:5|Rd:5","Arch":"64-bit to double-precision variant","Syntax":"UCVTF <Dd>, <Xn>, #<fbits>","Code":"","Alias":""},
+{"Name":"UCVTF (scalar, integer)","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|0|0|1|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"32-bit to single-precision variant","Syntax":"UCVTF <Sd>, <Wn>","Code":"","Alias":""},
+{"Name":"UCVTF (scalar, integer)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|0|1|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"32-bit to double-precision variant","Syntax":"UCVTF <Dd>, <Wn>","Code":"","Alias":""},
+{"Name":"UCVTF (scalar, integer)","Bits":"1|0|0|1|1|1|1|0|00:2|1|0|0|0|1|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"64-bit to single-precision variant","Syntax":"UCVTF <Sd>, <Xn>","Code":"","Alias":""},
+{"Name":"UCVTF (scalar, integer)","Bits":"1|0|0|1|1|1|1|0|01:2|1|0|0|0|1|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"64-bit to double-precision variant","Syntax":"UCVTF <Dd>, <Xn>","Code":"","Alias":""},
+{"Name":"UHADD","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|0|0|0|0|0|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"UHADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"UHSUB","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|0|0|1|0|0|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"UHSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"UMAX","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|0|1|1|0|0|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"UMAX <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"UMAXP","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|1|0|1|0|0|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"UMAXP <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"UMAXV","Bits":"0|Q|1|0|1|1|1|0|size:2|1|1|0|0|0|0|1|0|1|0|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"UMAXV <V><d>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"UMIN","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|0|1|1|0|1|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"UMIN <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"UMINP","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|1|0|1|0|1|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"UMINP <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"UMINV","Bits":"0|Q|1|0|1|1|1|0|size:2|1|1|0|0|0|1|1|0|1|0|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"UMINV <V><d>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"UMLAL, UMLAL2 (by element)","Bits":"0|0|1|0|1|1|1|1|size:2|L|M|Rm:4|0|0|1|0|H|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"UMLAL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"UMLAL, UMLAL2 (by element)","Bits":"0|1|1|0|1|1|1|1|size:2|L|M|Rm:4|0|0|1|0|H|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"UMLAL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"UMLAL, UMLAL2 (vector)","Bits":"0|0|1|0|1|1|1|0|size:2|1|Rm:5|1|0|0|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"UMLAL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"UMLAL, UMLAL2 (vector)","Bits":"0|1|1|0|1|1|1|0|size:2|1|Rm:5|1|0|0|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"UMLAL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"UMLSL, UMLSL2 (by element)","Bits":"0|0|1|0|1|1|1|1|size:2|L|M|Rm:4|0|1|1|0|H|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"UMLSL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"UMLSL, UMLSL2 (by element)","Bits":"0|1|1|0|1|1|1|1|size:2|L|M|Rm:4|0|1|1|0|H|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"UMLSL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"UMLSL, UMLSL2 (vector)","Bits":"0|0|1|0|1|1|1|0|size:2|1|Rm:5|1|0|1|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"UMLSL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"UMLSL, UMLSL2 (vector)","Bits":"0|1|1|0|1|1|1|0|size:2|1|Rm:5|1|0|1|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"UMLSL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"UMOV","Bits":"0|0|0|0|1|1|1|0|0|0|0|imm5:5|0|0|1|1|1|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"UMOV <Wd>, <Vn>.<Ts>[<index>]","Code":"","Alias":"This instruction is used by the alias MOV (to general)."},
+{"Name":"UMOV","Bits":"0|1|0|0|1|1|1|0|0|0|0|imm5:5|0|0|1|1|1|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"UMOV <Xd>, <Vn>.<Ts>[<index>]","Code":"","Alias":"This instruction is used by the alias MOV (to general)."},
+{"Name":"UMULL, UMULL2 (by element)","Bits":"0|0|1|0|1|1|1|1|size:2|L|M|Rm:4|1|0|1|0|H|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"UMULL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"UMULL, UMULL2 (by element)","Bits":"0|1|1|0|1|1|1|1|size:2|L|M|Rm:4|1|0|1|0|H|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"UMULL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"UMULL, UMULL2 (vector)","Bits":"0|0|1|0|1|1|1|0|size:2|1|Rm:5|1|1|0|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"UMULL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"UMULL, UMULL2 (vector)","Bits":"0|1|1|0|1|1|1|0|size:2|1|Rm:5|1|1|0|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"UMULL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"UQADD","Bits":"0|1|1|1|1|1|1|0|size:2|1|Rm:5|0|0|0|0|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"UQADD <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"UQADD","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|0|0|0|0|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"UQADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"UQRSHL","Bits":"0|1|1|1|1|1|1|0|size:2|1|Rm:5|0|1|0|1|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"UQRSHL <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"UQRSHL","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|0|1|0|1|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"UQRSHL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"UQRSHRN, UQRSHRN2","Bits":"0|1|1|1|1|1|1|1|0|immh:4|immb:3|1|0|0|1|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"UQRSHRN <Vb><d>, <Va><n>, #<shift>","Code":"","Alias":""},
+{"Name":"UQRSHRN, UQRSHRN2","Bits":"0|0|1|0|1|1|1|1|0|immh:4|immb:3|1|0|0|1|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"UQRSHRN <Vd>.<Tb>, <Vn>.<Ta>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"UQRSHRN, UQRSHRN2","Bits":"0|1|1|0|1|1|1|1|0|immh:4|immb:3|1|0|0|1|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"UQRSHRN2 <Vd>.<Tb>, <Vn>.<Ta>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"UQSHL (immediate)","Bits":"0|1|1|1|1|1|1|1|0|immh:4|immb:3|0|1|1|1|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"UQSHL <V><d>, <V><n>, #<shift>","Code":"","Alias":""},
+{"Name":"UQSHL (immediate)","Bits":"0|Q|1|0|1|1|1|1|0|immh:4|immb:3|0|1|1|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"UQSHL <Vd>.<T>, <Vn>.<T>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"UQSHL (register)","Bits":"0|1|1|1|1|1|1|0|size:2|1|Rm:5|0|1|0|0|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"UQSHL <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"UQSHL (register)","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|0|1|0|0|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"UQSHL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"UQSHRN, UQSHRN2","Bits":"0|1|1|1|1|1|1|1|0|immh:4|immb:3|1|0|0|1|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"UQSHRN <Vb><d>, <Va><n>, #<shift>","Code":"","Alias":""},
+{"Name":"UQSHRN, UQSHRN2","Bits":"0|0|1|0|1|1|1|1|0|immh:4|immb:3|1|0|0|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"UQSHRN <Vd>.<Tb>, <Vn>.<Ta>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"UQSHRN, UQSHRN2","Bits":"0|1|1|0|1|1|1|1|0|immh:4|immb:3|1|0|0|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"UQSHRN2 <Vd>.<Tb>, <Vn>.<Ta>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"UQSUB","Bits":"0|1|1|1|1|1|1|0|size:2|1|Rm:5|0|0|1|0|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"UQSUB <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"UQSUB","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|0|0|1|0|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"UQSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"UQXTN, UQXTN2","Bits":"0|1|1|1|1|1|1|0|size:2|1|0|0|0|0|1|0|1|0|0|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"UQXTN <Vb><d>, <Va><n>","Code":"","Alias":""},
+{"Name":"UQXTN, UQXTN2","Bits":"0|0|1|0|1|1|1|0|size:2|1|0|0|0|0|1|0|1|0|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"UQXTN <Vd>.<Tb>, <Vn>.<Ta>","Code":"","Alias":""},
+{"Name":"UQXTN, UQXTN2","Bits":"0|1|1|0|1|1|1|0|size:2|1|0|0|0|0|1|0|1|0|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"UQXTN2 <Vd>.<Tb>, <Vn>.<Ta>","Code":"","Alias":""},
+{"Name":"URECPE","Bits":"0|Q|0|0|1|1|1|0|1|sz|1|0|0|0|0|1|1|1|0|0|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"URECPE <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"URHADD","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|0|0|0|1|0|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"URHADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"URSHL","Bits":"0|1|1|1|1|1|1|0|size:2|1|Rm:5|0|1|0|1|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"URSHL <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"URSHL","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|0|1|0|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"URSHL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"URSHR","Bits":"0|1|1|1|1|1|1|1|0|immh:4|immb:3|0|0|1|0|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"URSHR <V><d>, <V><n>, #<shift>","Code":"","Alias":""},
+{"Name":"URSHR","Bits":"0|Q|1|0|1|1|1|1|0|immh:4|immb:3|0|0|1|0|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"URSHR <Vd>.<T>, <Vn>.<T>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"URSQRTE","Bits":"0|Q|1|0|1|1|1|0|1|sz|1|0|0|0|0|1|1|1|0|0|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"URSQRTE <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"URSRA","Bits":"0|1|1|1|1|1|1|1|0|immh:4|immb:3|0|0|1|1|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"URSRA <V><d>, <V><n>, #<shift>","Code":"","Alias":""},
+{"Name":"URSRA","Bits":"0|Q|1|0|1|1|1|1|0|immh:4|immb:3|0|0|1|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"URSRA <Vd>.<T>, <Vn>.<T>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"USHL","Bits":"0|1|1|1|1|1|1|0|size:2|1|Rm:5|0|1|0|0|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"USHL <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"USHL","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|0|1|0|0|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"USHL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"USHLL, USHLL2","Bits":"0|0|1|0|1|1|1|1|0|immh:4|immb:3|1|0|1|0|0|1|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"USHLL <Vd>.<Ta>, <Vn>.<Tb>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":"This instruction is used by the alias UXTL, UXTL2."},
+{"Name":"USHLL, USHLL2","Bits":"0|1|1|0|1|1|1|1|0|immh:4|immb:3|1|0|1|0|0|1|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"USHLL2 <Vd>.<Ta>, <Vn>.<Tb>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":"This instruction is used by the alias UXTL, UXTL2."},
+{"Name":"USHR","Bits":"0|1|1|1|1|1|1|1|0|immh:4|immb:3|0|0|0|0|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"USHR <V><d>, <V><n>, #<shift>","Code":"","Alias":""},
+{"Name":"USHR","Bits":"0|Q|1|0|1|1|1|1|0|immh:4|immb:3|0|0|0|0|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"USHR <Vd>.<T>, <Vn>.<T>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"USQADD","Bits":"0|1|1|1|1|1|1|0|size:2|1|0|0|0|0|0|0|0|1|1|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"USQADD <V><d>, <V><n>","Code":"","Alias":""},
+{"Name":"USQADD","Bits":"0|Q|1|0|1|1|1|0|size:2|1|0|0|0|0|0|0|0|1|1|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"USQADD <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"USRA","Bits":"0|1|1|1|1|1|1|1|0|immh:4|immb:3|0|0|0|1|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"USRA <V><d>, <V><n>, #<shift>","Code":"","Alias":""},
+{"Name":"USRA","Bits":"0|Q|1|0|1|1|1|1|0|immh:4|immb:3|0|0|0|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"USRA <Vd>.<T>, <Vn>.<T>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"USUBL, USUBL2","Bits":"0|0|1|0|1|1|1|0|size:2|1|Rm:5|0|0|1|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"USUBL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"USUBL, USUBL2","Bits":"0|1|1|0|1|1|1|0|size:2|1|Rm:5|0|0|1|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"USUBL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"USUBW, USUBW2","Bits":"0|0|1|0|1|1|1|0|size:2|1|Rm:5|0|0|1|1|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"USUBW <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"USUBW, USUBW2","Bits":"0|1|1|0|1|1|1|0|size:2|1|Rm:5|0|0|1|1|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"USUBW2 <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"UXTL, UXTL2","Bits":"0|0|1|0|1|1|1|1|0|immh:4|0|0|0|1|0|1|0|0|1|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"UXTL <Vd>.<Ta>, <Vn>.<Tb>","Code":"","Alias":"This instruction is an alias of the USHLL, USHLL2 instruction."},
+{"Name":"UXTL, UXTL2","Bits":"0|1|1|0|1|1|1|1|0|immh:4|0|0|0|1|0|1|0|0|1|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"UXTL2 <Vd>.<Ta>, <Vn>.<Tb>","Code":"","Alias":"This instruction is an alias of the USHLL, USHLL2 instruction."},
+{"Name":"UZP1","Bits":"0|Q|0|0|1|1|1|0|size:2|0|Rm:5|0|0|0|1|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"UZP1 <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"UZP2","Bits":"0|Q|0|0|1|1|1|0|size:2|0|Rm:5|0|1|0|1|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"UZP2 <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"XTN, XTN2","Bits":"0|0|0|0|1|1|1|0|size:2|1|0|0|0|0|1|0|0|1|0|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"XTN <Vd>.<Tb>, <Vn>.<Ta>","Code":"","Alias":""},
+{"Name":"XTN, XTN2","Bits":"0|1|0|0|1|1|1|0|size:2|1|0|0|0|0|1|0|0|1|0|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"XTN2 <Vd>.<Tb>, <Vn>.<Ta>","Code":"","Alias":""},
+{"Name":"ZIP1","Bits":"0|Q|0|0|1|1|1|0|size:2|0|Rm:5|0|0|1|1|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"ZIP1 <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"ZIP2","Bits":"0|Q|0|0|1|1|1|0|size:2|0|Rm:5|0|1|1|1|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"ZIP2 <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""}
+]
diff --git a/pkg/ifuzz/arm64/generated/empty.go b/pkg/ifuzz/arm64/generated/empty.go
new file mode 100644
index 000000000..1933cb1dd
--- /dev/null
+++ b/pkg/ifuzz/arm64/generated/empty.go
@@ -0,0 +1,6 @@
+// Copyright 2020 syzkaller project authors. All rights reserved.
+// Use of this source code is governed by Apache 2 LICENSE that can be found in the LICENSE file.
+
+// To unbreak build with insns.go is excluded by build tags.
+
+package generated
diff --git a/pkg/ifuzz/arm64/generated/insns.go b/pkg/ifuzz/arm64/generated/insns.go
new file mode 100644
index 000000000..9d944ecd1
--- /dev/null
+++ b/pkg/ifuzz/arm64/generated/insns.go
@@ -0,0 +1,7053 @@
+// Code generated by pkg/ifuzz/gen. DO NOT EDIT.
+
+// go:build !codeanalysis
+
+package generated
+
+import (
+	. "github.com/google/syzkaller/pkg/ifuzz/arm64"
+)
+
+func init() {
+	Register(insns_arm64)
+}
+
+var insns_arm64 = []*Insn{
+	{Name: "ADC", OpcodeMask: 4292934656, Opcode: 436207616, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 436207616, Generator: nil},
+	{Name: "ADC", OpcodeMask: 4292934656, Opcode: 2583691264, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2583691264, Generator: nil},
+	{Name: "ADCS", OpcodeMask: 4292934656, Opcode: 973078528, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 973078528, Generator: nil},
+	{Name: "ADCS", OpcodeMask: 4292934656, Opcode: 3120562176, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 3120562176, Generator: nil},
+	{Name: "ADD (extended register)", OpcodeMask: 4292870144, Opcode: 186646528, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"option", 15, 3},
+		{"imm3", 12, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 186646528, Generator: nil},
+	{Name: "ADD (extended register)", OpcodeMask: 4292870144, Opcode: 2334130176, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"option", 15, 3},
+		{"imm3", 12, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2334130176, Generator: nil},
+	{Name: "ADD (immediate)", OpcodeMask: 4278190080, Opcode: 285212672, Fields: []InsnField{
+		{"shift", 23, 2},
+		{"imm12", 21, 12},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 285212672, Generator: nil},
+	{Name: "ADD (immediate)", OpcodeMask: 4278190080, Opcode: 2432696320, Fields: []InsnField{
+		{"shift", 23, 2},
+		{"imm12", 21, 12},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2432696320, Generator: nil},
+	{Name: "ADD (shifted register)", OpcodeMask: 4280287232, Opcode: 184549376, Fields: []InsnField{
+		{"shift", 23, 2},
+		{"Rm", 20, 5},
+		{"imm6", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 184549376, Generator: nil},
+	{Name: "ADD (shifted register)", OpcodeMask: 4280287232, Opcode: 2332033024, Fields: []InsnField{
+		{"shift", 23, 2},
+		{"Rm", 20, 5},
+		{"imm6", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2332033024, Generator: nil},
+	{Name: "ADDS (extended register)", OpcodeMask: 4292870144, Opcode: 723517440, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"option", 15, 3},
+		{"imm3", 12, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 723517440, Generator: nil},
+	{Name: "ADDS (extended register)", OpcodeMask: 4292870144, Opcode: 2871001088, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"option", 15, 3},
+		{"imm3", 12, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2871001088, Generator: nil},
+	{Name: "ADDS (immediate)", OpcodeMask: 4278190080, Opcode: 822083584, Fields: []InsnField{
+		{"shift", 23, 2},
+		{"imm12", 21, 12},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 822083584, Generator: nil},
+	{Name: "ADDS (immediate)", OpcodeMask: 4278190080, Opcode: 2969567232, Fields: []InsnField{
+		{"shift", 23, 2},
+		{"imm12", 21, 12},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2969567232, Generator: nil},
+	{Name: "ADDS (shifted register)", OpcodeMask: 4280287232, Opcode: 721420288, Fields: []InsnField{
+		{"shift", 23, 2},
+		{"Rm", 20, 5},
+		{"imm6", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 721420288, Generator: nil},
+	{Name: "ADDS (shifted register)", OpcodeMask: 4280287232, Opcode: 2868903936, Fields: []InsnField{
+		{"shift", 23, 2},
+		{"Rm", 20, 5},
+		{"imm6", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2868903936, Generator: nil},
+	{Name: "ADR", OpcodeMask: 2667577344, Opcode: 268435456, Fields: []InsnField{
+		{"immlo", 30, 2},
+		{"immhi", 23, 19},
+		{"Rd", 4, 5},
+	}, AsUInt32: 268435456, Generator: nil},
+	{Name: "ADRP", OpcodeMask: 2667577344, Opcode: 2415919104, Fields: []InsnField{
+		{"immlo", 30, 2},
+		{"immhi", 23, 19},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2415919104, Generator: nil},
+	{Name: "AND (immediate)", OpcodeMask: 4290772992, Opcode: 301989888, Fields: []InsnField{
+		{"immr", 21, 6},
+		{"imms", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 301989888, Generator: nil},
+	{Name: "AND (immediate)", OpcodeMask: 4286578688, Opcode: 2449473536, Fields: []InsnField{
+		{"N", 22, 1},
+		{"immr", 21, 6},
+		{"imms", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2449473536, Generator: nil},
+	{Name: "AND (shifted register)", OpcodeMask: 4280287232, Opcode: 167772160, Fields: []InsnField{
+		{"shift", 23, 2},
+		{"Rm", 20, 5},
+		{"imm6", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 167772160, Generator: nil},
+	{Name: "AND (shifted register)", OpcodeMask: 4280287232, Opcode: 2315255808, Fields: []InsnField{
+		{"shift", 23, 2},
+		{"Rm", 20, 5},
+		{"imm6", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2315255808, Generator: nil},
+	{Name: "ANDS (immediate)", OpcodeMask: 4290772992, Opcode: 1912602624, Fields: []InsnField{
+		{"immr", 21, 6},
+		{"imms", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1912602624, Generator: nil},
+	{Name: "ANDS (immediate)", OpcodeMask: 4286578688, Opcode: 4060086272, Fields: []InsnField{
+		{"N", 22, 1},
+		{"immr", 21, 6},
+		{"imms", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 4060086272, Generator: nil},
+	{Name: "ANDS (shifted register)", OpcodeMask: 4280287232, Opcode: 1778384896, Fields: []InsnField{
+		{"shift", 23, 2},
+		{"Rm", 20, 5},
+		{"imm6", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1778384896, Generator: nil},
+	{Name: "ANDS (shifted register)", OpcodeMask: 4280287232, Opcode: 3925868544, Fields: []InsnField{
+		{"shift", 23, 2},
+		{"Rm", 20, 5},
+		{"imm6", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 3925868544, Generator: nil},
+	{Name: "ASR (register)", OpcodeMask: 4292934656, Opcode: 448800768, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 448800768, Generator: nil},
+	{Name: "ASR (register)", OpcodeMask: 4292934656, Opcode: 2596284416, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2596284416, Generator: nil},
+	{Name: "ASR (immediate)", OpcodeMask: 4290837504, Opcode: 318798848, Fields: []InsnField{
+		{"immr", 21, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 318798848, Generator: nil},
+	{Name: "ASR (immediate)", OpcodeMask: 4290837504, Opcode: 2470509568, Fields: []InsnField{
+		{"immr", 21, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2470509568, Generator: nil},
+	{Name: "ASRV", OpcodeMask: 4292934656, Opcode: 448800768, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 448800768, Generator: nil},
+	{Name: "ASRV", OpcodeMask: 4292934656, Opcode: 2596284416, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2596284416, Generator: nil},
+	{Name: "AT", OpcodeMask: 4294504448, Opcode: 3574099968, Fields: []InsnField{
+		{"op1", 18, 3},
+		{"CRm", 11, 4},
+		{"op2", 7, 3},
+		{"Rt", 4, 5},
+	}, AsUInt32: 3574099968, Priv: true, Generator: nil},
+	{Name: "B.cond", OpcodeMask: 4278190096, Opcode: 1409286144, Fields: []InsnField{
+		{"imm19", 23, 19},
+		{"cond", 3, 4},
+	}, AsUInt32: 1409286144, Generator: nil},
+	{Name: "B", OpcodeMask: 4227858432, Opcode: 335544320, Fields: []InsnField{
+		{"imm26", 25, 26},
+	}, AsUInt32: 335544320, Generator: nil},
+	{Name: "BFI", OpcodeMask: 4290772992, Opcode: 855638016, Fields: []InsnField{
+		{"immr", 21, 6},
+		{"imms", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 855638016, Generator: nil},
+	{Name: "BFI", OpcodeMask: 4290772992, Opcode: 3007315968, Fields: []InsnField{
+		{"immr", 21, 6},
+		{"imms", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 3007315968, Generator: nil},
+	{Name: "BFM", OpcodeMask: 4290772992, Opcode: 855638016, Fields: []InsnField{
+		{"immr", 21, 6},
+		{"imms", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 855638016, Generator: nil},
+	{Name: "BFM", OpcodeMask: 4290772992, Opcode: 3007315968, Fields: []InsnField{
+		{"immr", 21, 6},
+		{"imms", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 3007315968, Generator: nil},
+	{Name: "BFXIL", OpcodeMask: 4290772992, Opcode: 855638016, Fields: []InsnField{
+		{"immr", 21, 6},
+		{"imms", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 855638016, Generator: nil},
+	{Name: "BFXIL", OpcodeMask: 4290772992, Opcode: 3007315968, Fields: []InsnField{
+		{"immr", 21, 6},
+		{"imms", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 3007315968, Generator: nil},
+	{Name: "BIC (shifted register)", OpcodeMask: 4280287232, Opcode: 169869312, Fields: []InsnField{
+		{"shift", 23, 2},
+		{"Rm", 20, 5},
+		{"imm6", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 169869312, Generator: nil},
+	{Name: "BIC (shifted register)", OpcodeMask: 4280287232, Opcode: 2317352960, Fields: []InsnField{
+		{"shift", 23, 2},
+		{"Rm", 20, 5},
+		{"imm6", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2317352960, Generator: nil},
+	{Name: "BICS (shifted register)", OpcodeMask: 4280287232, Opcode: 1780482048, Fields: []InsnField{
+		{"shift", 23, 2},
+		{"Rm", 20, 5},
+		{"imm6", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1780482048, Generator: nil},
+	{Name: "BICS (shifted register)", OpcodeMask: 4280287232, Opcode: 3927965696, Fields: []InsnField{
+		{"shift", 23, 2},
+		{"Rm", 20, 5},
+		{"imm6", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 3927965696, Generator: nil},
+	{Name: "BL", OpcodeMask: 4227858432, Opcode: 2483027968, Fields: []InsnField{
+		{"imm26", 25, 26},
+	}, AsUInt32: 2483027968, Generator: nil},
+	{Name: "BLR", OpcodeMask: 4294966303, Opcode: 3594452992, Fields: []InsnField{
+		{"Rn", 9, 5},
+	}, AsUInt32: 3594452992, Generator: nil},
+	{Name: "BR", OpcodeMask: 4294966303, Opcode: 3592355840, Fields: []InsnField{
+		{"Rn", 9, 5},
+	}, AsUInt32: 3592355840, Generator: nil},
+	{Name: "BRK", OpcodeMask: 4292870175, Opcode: 3558866944, Fields: []InsnField{
+		{"imm16", 20, 16},
+	}, AsUInt32: 3558866944, Generator: nil},
+	{Name: "CBNZ", OpcodeMask: 4278190080, Opcode: 889192448, Fields: []InsnField{
+		{"imm19", 23, 19},
+		{"Rt", 4, 5},
+	}, AsUInt32: 889192448, Generator: nil},
+	{Name: "CBNZ", OpcodeMask: 4278190080, Opcode: 3036676096, Fields: []InsnField{
+		{"imm19", 23, 19},
+		{"Rt", 4, 5},
+	}, AsUInt32: 3036676096, Generator: nil},
+	{Name: "CBZ", OpcodeMask: 4278190080, Opcode: 872415232, Fields: []InsnField{
+		{"imm19", 23, 19},
+		{"Rt", 4, 5},
+	}, AsUInt32: 872415232, Generator: nil},
+	{Name: "CBZ", OpcodeMask: 4278190080, Opcode: 3019898880, Fields: []InsnField{
+		{"imm19", 23, 19},
+		{"Rt", 4, 5},
+	}, AsUInt32: 3019898880, Generator: nil},
+	{Name: "CCMN (immediate)", OpcodeMask: 4292873232, Opcode: 977274880, Fields: []InsnField{
+		{"imm5", 20, 5},
+		{"cond", 15, 4},
+		{"Rn", 9, 5},
+		{"nzcv", 3, 4},
+	}, AsUInt32: 977274880, Generator: nil},
+	{Name: "CCMN (immediate)", OpcodeMask: 4292873232, Opcode: 3124758528, Fields: []InsnField{
+		{"imm5", 20, 5},
+		{"cond", 15, 4},
+		{"Rn", 9, 5},
+		{"nzcv", 3, 4},
+	}, AsUInt32: 3124758528, Generator: nil},
+	{Name: "CCMN (register)", OpcodeMask: 4292873232, Opcode: 977272832, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"cond", 15, 4},
+		{"Rn", 9, 5},
+		{"nzcv", 3, 4},
+	}, AsUInt32: 977272832, Generator: nil},
+	{Name: "CCMN (register)", OpcodeMask: 4292873232, Opcode: 3124756480, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"cond", 15, 4},
+		{"Rn", 9, 5},
+		{"nzcv", 3, 4},
+	}, AsUInt32: 3124756480, Generator: nil},
+	{Name: "CCMP (immediate)", OpcodeMask: 4292873232, Opcode: 2051016704, Fields: []InsnField{
+		{"imm5", 20, 5},
+		{"cond", 15, 4},
+		{"Rn", 9, 5},
+		{"nzcv", 3, 4},
+	}, AsUInt32: 2051016704, Generator: nil},
+	{Name: "CCMP (immediate)", OpcodeMask: 4292873232, Opcode: 4198500352, Fields: []InsnField{
+		{"imm5", 20, 5},
+		{"cond", 15, 4},
+		{"Rn", 9, 5},
+		{"nzcv", 3, 4},
+	}, AsUInt32: 4198500352, Generator: nil},
+	{Name: "CCMP (register)", OpcodeMask: 4292873232, Opcode: 2051014656, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"cond", 15, 4},
+		{"Rn", 9, 5},
+		{"nzcv", 3, 4},
+	}, AsUInt32: 2051014656, Generator: nil},
+	{Name: "CCMP (register)", OpcodeMask: 4292873232, Opcode: 4198498304, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"cond", 15, 4},
+		{"Rn", 9, 5},
+		{"nzcv", 3, 4},
+	}, AsUInt32: 4198498304, Generator: nil},
+	{Name: "CINC", OpcodeMask: 4292873216, Opcode: 444597248, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"cond", 15, 4},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 444597248, Generator: nil},
+	{Name: "CINC", OpcodeMask: 4292873216, Opcode: 2592080896, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"cond", 15, 4},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2592080896, Generator: nil},
+	{Name: "CINV", OpcodeMask: 4292873216, Opcode: 1518338048, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"cond", 15, 4},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1518338048, Generator: nil},
+	{Name: "CINV", OpcodeMask: 4292873216, Opcode: 3665821696, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"cond", 15, 4},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 3665821696, Generator: nil},
+	{Name: "CLREX", OpcodeMask: 4294963455, Opcode: 3573755999, Fields: []InsnField{
+		{"CRm", 11, 4},
+	}, AsUInt32: 3573755999, Generator: nil},
+	{Name: "CLS", OpcodeMask: 4294966272, Opcode: 1522537472, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1522537472, Generator: nil},
+	{Name: "CLS", OpcodeMask: 4294966272, Opcode: 3670021120, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 3670021120, Generator: nil},
+	{Name: "CLZ", OpcodeMask: 4294966272, Opcode: 1522536448, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1522536448, Generator: nil},
+	{Name: "CLZ", OpcodeMask: 4294966272, Opcode: 3670020096, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 3670020096, Generator: nil},
+	{Name: "CMN (extended register)", OpcodeMask: 4292870175, Opcode: 723517471, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"option", 15, 3},
+		{"imm3", 12, 3},
+		{"Rn", 9, 5},
+	}, AsUInt32: 723517471, Generator: nil},
+	{Name: "CMN (extended register)", OpcodeMask: 4292870175, Opcode: 2871001119, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"option", 15, 3},
+		{"imm3", 12, 3},
+		{"Rn", 9, 5},
+	}, AsUInt32: 2871001119, Generator: nil},
+	{Name: "CMN (immediate)", OpcodeMask: 4278190111, Opcode: 822083615, Fields: []InsnField{
+		{"shift", 23, 2},
+		{"imm12", 21, 12},
+		{"Rn", 9, 5},
+	}, AsUInt32: 822083615, Generator: nil},
+	{Name: "CMN (immediate)", OpcodeMask: 4278190111, Opcode: 2969567263, Fields: []InsnField{
+		{"shift", 23, 2},
+		{"imm12", 21, 12},
+		{"Rn", 9, 5},
+	}, AsUInt32: 2969567263, Generator: nil},
+	{Name: "CMN (shifted register)", OpcodeMask: 4280287263, Opcode: 721420319, Fields: []InsnField{
+		{"shift", 23, 2},
+		{"Rm", 20, 5},
+		{"imm6", 15, 6},
+		{"Rn", 9, 5},
+	}, AsUInt32: 721420319, Generator: nil},
+	{Name: "CMN (shifted register)", OpcodeMask: 4280287263, Opcode: 2868903967, Fields: []InsnField{
+		{"shift", 23, 2},
+		{"Rm", 20, 5},
+		{"imm6", 15, 6},
+		{"Rn", 9, 5},
+	}, AsUInt32: 2868903967, Generator: nil},
+	{Name: "CMP (extended register)", OpcodeMask: 4292870175, Opcode: 1797259295, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"option", 15, 3},
+		{"imm3", 12, 3},
+		{"Rn", 9, 5},
+	}, AsUInt32: 1797259295, Generator: nil},
+	{Name: "CMP (extended register)", OpcodeMask: 4292870175, Opcode: 3944742943, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"option", 15, 3},
+		{"imm3", 12, 3},
+		{"Rn", 9, 5},
+	}, AsUInt32: 3944742943, Generator: nil},
+	{Name: "CMP (immediate)", OpcodeMask: 4278190111, Opcode: 1895825439, Fields: []InsnField{
+		{"shift", 23, 2},
+		{"imm12", 21, 12},
+		{"Rn", 9, 5},
+	}, AsUInt32: 1895825439, Generator: nil},
+	{Name: "CMP (immediate)", OpcodeMask: 4278190111, Opcode: 4043309087, Fields: []InsnField{
+		{"shift", 23, 2},
+		{"imm12", 21, 12},
+		{"Rn", 9, 5},
+	}, AsUInt32: 4043309087, Generator: nil},
+	{Name: "CMP (shifted register)", OpcodeMask: 4280287263, Opcode: 1795162143, Fields: []InsnField{
+		{"shift", 23, 2},
+		{"Rm", 20, 5},
+		{"imm6", 15, 6},
+		{"Rn", 9, 5},
+	}, AsUInt32: 1795162143, Generator: nil},
+	{Name: "CMP (shifted register)", OpcodeMask: 4280287263, Opcode: 3942645791, Fields: []InsnField{
+		{"shift", 23, 2},
+		{"Rm", 20, 5},
+		{"imm6", 15, 6},
+		{"Rn", 9, 5},
+	}, AsUInt32: 3942645791, Generator: nil},
+	{Name: "CNEG", OpcodeMask: 4292873216, Opcode: 1518339072, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"cond", 15, 4},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1518339072, Generator: nil},
+	{Name: "CNEG", OpcodeMask: 4292873216, Opcode: 3665822720, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"cond", 15, 4},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 3665822720, Generator: nil},
+	{Name: "CRC32B, CRC32H, CRC32W, CRC32X", OpcodeMask: 4292934656, Opcode: 448806912, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 448806912, Generator: nil},
+	{Name: "CRC32B, CRC32H, CRC32W, CRC32X", OpcodeMask: 4292934656, Opcode: 448807936, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 448807936, Generator: nil},
+	{Name: "CRC32B, CRC32H, CRC32W, CRC32X", OpcodeMask: 4292934656, Opcode: 448808960, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 448808960, Generator: nil},
+	{Name: "CRC32B, CRC32H, CRC32W, CRC32X", OpcodeMask: 4292934656, Opcode: 2596293632, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2596293632, Generator: nil},
+	{Name: "CRC32CB, CRC32CH, CRC32CW, CRC32CX", OpcodeMask: 4292934656, Opcode: 448811008, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 448811008, Generator: nil},
+	{Name: "CRC32CB, CRC32CH, CRC32CW, CRC32CX", OpcodeMask: 4292934656, Opcode: 448812032, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 448812032, Generator: nil},
+	{Name: "CRC32CB, CRC32CH, CRC32CW, CRC32CX", OpcodeMask: 4292934656, Opcode: 448813056, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 448813056, Generator: nil},
+	{Name: "CRC32CB, CRC32CH, CRC32CW, CRC32CX", OpcodeMask: 4292934656, Opcode: 2596297728, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2596297728, Generator: nil},
+	{Name: "CSEL", OpcodeMask: 4292873216, Opcode: 444596224, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"cond", 15, 4},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 444596224, Generator: nil},
+	{Name: "CSEL", OpcodeMask: 4292873216, Opcode: 2592079872, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"cond", 15, 4},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2592079872, Generator: nil},
+	{Name: "CSET", OpcodeMask: 4294905824, Opcode: 446629856, Fields: []InsnField{
+		{"cond", 15, 4},
+		{"Rd", 4, 5},
+	}, AsUInt32: 446629856, Generator: nil},
+	{Name: "CSET", OpcodeMask: 4294905824, Opcode: 2594113504, Fields: []InsnField{
+		{"cond", 15, 4},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2594113504, Generator: nil},
+	{Name: "CSETM", OpcodeMask: 4294905824, Opcode: 1520370656, Fields: []InsnField{
+		{"cond", 15, 4},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1520370656, Generator: nil},
+	{Name: "CSETM", OpcodeMask: 4294905824, Opcode: 3667854304, Fields: []InsnField{
+		{"cond", 15, 4},
+		{"Rd", 4, 5},
+	}, AsUInt32: 3667854304, Generator: nil},
+	{Name: "CSINC", OpcodeMask: 4292873216, Opcode: 444597248, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"cond", 15, 4},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 444597248, Generator: nil},
+	{Name: "CSINC", OpcodeMask: 4292873216, Opcode: 2592080896, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"cond", 15, 4},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2592080896, Generator: nil},
+	{Name: "CSINV", OpcodeMask: 4292873216, Opcode: 1518338048, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"cond", 15, 4},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1518338048, Generator: nil},
+	{Name: "CSINV", OpcodeMask: 4292873216, Opcode: 3665821696, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"cond", 15, 4},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 3665821696, Generator: nil},
+	{Name: "CSNEG", OpcodeMask: 4292873216, Opcode: 1518339072, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"cond", 15, 4},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1518339072, Generator: nil},
+	{Name: "CSNEG", OpcodeMask: 4292873216, Opcode: 3665822720, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"cond", 15, 4},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 3665822720, Generator: nil},
+	{Name: "DC", OpcodeMask: 4294504448, Opcode: 3574099968, Fields: []InsnField{
+		{"op1", 18, 3},
+		{"CRm", 11, 4},
+		{"op2", 7, 3},
+		{"Rt", 4, 5},
+	}, AsUInt32: 3574099968, Priv: true, Generator: nil},
+	{Name: "DCPS1", OpcodeMask: 4292870175, Opcode: 3567255553, Fields: []InsnField{
+		{"imm16", 20, 16},
+	}, AsUInt32: 3567255553, Generator: nil},
+	{Name: "DCPS2", OpcodeMask: 4292870175, Opcode: 3567255554, Fields: []InsnField{
+		{"imm16", 20, 16},
+	}, AsUInt32: 3567255554, Generator: nil},
+	{Name: "DCPS3", OpcodeMask: 4292870175, Opcode: 3567255555, Fields: []InsnField{
+		{"imm16", 20, 16},
+	}, AsUInt32: 3567255555, Generator: nil},
+	{Name: "DMB", OpcodeMask: 4294963455, Opcode: 3573756095, Fields: []InsnField{
+		{"CRm", 11, 4},
+	}, AsUInt32: 3573756095, Generator: nil},
+	{Name: "DRPS", OpcodeMask: 4294967295, Opcode: 3602842592, AsUInt32: 3602842592, Generator: nil},
+	{Name: "DSB", OpcodeMask: 4294963455, Opcode: 3573756063, Fields: []InsnField{
+		{"CRm", 11, 4},
+	}, AsUInt32: 3573756063, Generator: nil},
+	{Name: "EON (shifted register)", OpcodeMask: 4280287232, Opcode: 1243611136, Fields: []InsnField{
+		{"shift", 23, 2},
+		{"Rm", 20, 5},
+		{"imm6", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1243611136, Generator: nil},
+	{Name: "EON (shifted register)", OpcodeMask: 4280287232, Opcode: 3391094784, Fields: []InsnField{
+		{"shift", 23, 2},
+		{"Rm", 20, 5},
+		{"imm6", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 3391094784, Generator: nil},
+	{Name: "EOR (immediate)", OpcodeMask: 4290772992, Opcode: 1375731712, Fields: []InsnField{
+		{"immr", 21, 6},
+		{"imms", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1375731712, Generator: nil},
+	{Name: "EOR (immediate)", OpcodeMask: 4286578688, Opcode: 3523215360, Fields: []InsnField{
+		{"N", 22, 1},
+		{"immr", 21, 6},
+		{"imms", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 3523215360, Generator: nil},
+	{Name: "EOR (shifted register)", OpcodeMask: 4280287232, Opcode: 1241513984, Fields: []InsnField{
+		{"shift", 23, 2},
+		{"Rm", 20, 5},
+		{"imm6", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1241513984, Generator: nil},
+	{Name: "EOR (shifted register)", OpcodeMask: 4280287232, Opcode: 3388997632, Fields: []InsnField{
+		{"shift", 23, 2},
+		{"Rm", 20, 5},
+		{"imm6", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 3388997632, Generator: nil},
+	{Name: "ERET", OpcodeMask: 4294967295, Opcode: 3600745440, AsUInt32: 3600745440, Generator: nil},
+	{Name: "EXTR", OpcodeMask: 4292870144, Opcode: 327155712, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"imms", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 327155712, Generator: nil},
+	{Name: "EXTR", OpcodeMask: 4292870144, Opcode: 2478833664, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"imms", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2478833664, Generator: nil},
+	{Name: "HINT", OpcodeMask: 4294967071, Opcode: 3573751839, Fields: []InsnField{
+		{"op2", 7, 3},
+	}, AsUInt32: 3573751839, Generator: nil},
+	{Name: "HINT", OpcodeMask: 4294963231, Opcode: 3573751839, Fields: []InsnField{
+		{"CRm", 11, 4},
+		{"op2", 7, 3},
+	}, AsUInt32: 3573751839, Generator: nil},
+	{Name: "HLT", OpcodeMask: 4292870175, Opcode: 3560964096, Fields: []InsnField{
+		{"imm16", 20, 16},
+	}, AsUInt32: 3560964096, Generator: nil},
+	{Name: "HVC", OpcodeMask: 4292870175, Opcode: 3556769794, Fields: []InsnField{
+		{"imm16", 20, 16},
+	}, AsUInt32: 3556769794, Generator: nil},
+	{Name: "IC", OpcodeMask: 4294504448, Opcode: 3574099968, Fields: []InsnField{
+		{"op1", 18, 3},
+		{"CRm", 11, 4},
+		{"op2", 7, 3},
+		{"Rt", 4, 5},
+	}, AsUInt32: 3574099968, Priv: true, Generator: nil},
+	{Name: "ISB", OpcodeMask: 4294963455, Opcode: 3573756127, Fields: []InsnField{
+		{"CRm", 11, 4},
+	}, AsUInt32: 3573756127, Generator: nil},
+	{Name: "LDAR", OpcodeMask: 4292902912, Opcode: 2294317056, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2294317056, Generator: nil},
+	{Name: "LDAR", OpcodeMask: 4292902912, Opcode: 3368058880, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 3368058880, Generator: nil},
+	{Name: "LDARB", OpcodeMask: 4292902912, Opcode: 146833408, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 146833408, Generator: nil},
+	{Name: "LDARH", OpcodeMask: 4292902912, Opcode: 1220575232, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 1220575232, Generator: nil},
+	{Name: "LDAXP", OpcodeMask: 4292902912, Opcode: 2288025600, Fields: []InsnField{
+		{"Rt2", 14, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2288025600, Generator: nil},
+	{Name: "LDAXP", OpcodeMask: 4292902912, Opcode: 3361767424, Fields: []InsnField{
+		{"Rt2", 14, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 3361767424, Generator: nil},
+	{Name: "LDAXR", OpcodeMask: 4292902912, Opcode: 2285928448, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2285928448, Generator: nil},
+	{Name: "LDAXR", OpcodeMask: 4292902912, Opcode: 3359670272, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 3359670272, Generator: nil},
+	{Name: "LDAXRB", OpcodeMask: 4292902912, Opcode: 138444800, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 138444800, Generator: nil},
+	{Name: "LDAXRH", OpcodeMask: 4292902912, Opcode: 1212186624, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 1212186624, Generator: nil},
+	{Name: "LDNP", OpcodeMask: 4290772992, Opcode: 675282944, Fields: []InsnField{
+		{"imm7", 21, 7},
+		{"Rt2", 14, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 675282944, Generator: nil},
+	{Name: "LDNP", OpcodeMask: 4290772992, Opcode: 2822766592, Fields: []InsnField{
+		{"imm7", 21, 7},
+		{"Rt2", 14, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2822766592, Generator: nil},
+	{Name: "LDP", OpcodeMask: 4290772992, Opcode: 683671552, Fields: []InsnField{
+		{"imm7", 21, 7},
+		{"Rt2", 14, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 683671552, Generator: nil},
+	{Name: "LDP", OpcodeMask: 4290772992, Opcode: 2831155200, Fields: []InsnField{
+		{"imm7", 21, 7},
+		{"Rt2", 14, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2831155200, Generator: nil},
+	{Name: "LDP", OpcodeMask: 4290772992, Opcode: 700448768, Fields: []InsnField{
+		{"imm7", 21, 7},
+		{"Rt2", 14, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 700448768, Generator: nil},
+	{Name: "LDP", OpcodeMask: 4290772992, Opcode: 2847932416, Fields: []InsnField{
+		{"imm7", 21, 7},
+		{"Rt2", 14, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2847932416, Generator: nil},
+	{Name: "LDP", OpcodeMask: 4290772992, Opcode: 692060160, Fields: []InsnField{
+		{"imm7", 21, 7},
+		{"Rt2", 14, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 692060160, Generator: nil},
+	{Name: "LDP", OpcodeMask: 4290772992, Opcode: 2839543808, Fields: []InsnField{
+		{"imm7", 21, 7},
+		{"Rt2", 14, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2839543808, Generator: nil},
+	{Name: "LDPSW", OpcodeMask: 4290772992, Opcode: 1757413376, Fields: []InsnField{
+		{"imm7", 21, 7},
+		{"Rt2", 14, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 1757413376, Generator: nil},
+	{Name: "LDPSW", OpcodeMask: 4290772992, Opcode: 1774190592, Fields: []InsnField{
+		{"imm7", 21, 7},
+		{"Rt2", 14, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 1774190592, Generator: nil},
+	{Name: "LDPSW", OpcodeMask: 4290772992, Opcode: 1765801984, Fields: []InsnField{
+		{"imm7", 21, 7},
+		{"Rt2", 14, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 1765801984, Generator: nil},
+	{Name: "LDR (immediate)", OpcodeMask: 4292873216, Opcode: 3091203072, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 3091203072, Generator: nil},
+	{Name: "LDR (immediate)", OpcodeMask: 4292873216, Opcode: 4164944896, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 4164944896, Generator: nil},
+	{Name: "LDR (immediate)", OpcodeMask: 4292873216, Opcode: 3091205120, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 3091205120, Generator: nil},
+	{Name: "LDR (immediate)", OpcodeMask: 4292873216, Opcode: 4164946944, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 4164946944, Generator: nil},
+	{Name: "LDR (immediate)", OpcodeMask: 4290772992, Opcode: 3107979264, Fields: []InsnField{
+		{"imm12", 21, 12},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 3107979264, Generator: nil},
+	{Name: "LDR (immediate)", OpcodeMask: 4290772992, Opcode: 4181721088, Fields: []InsnField{
+		{"imm12", 21, 12},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 4181721088, Generator: nil},
+	{Name: "LDR (literal)", OpcodeMask: 4278190080, Opcode: 402653184, Fields: []InsnField{
+		{"imm19", 23, 19},
+		{"Rt", 4, 5},
+	}, AsUInt32: 402653184, Generator: nil},
+	{Name: "LDR (literal)", OpcodeMask: 4278190080, Opcode: 1476395008, Fields: []InsnField{
+		{"imm19", 23, 19},
+		{"Rt", 4, 5},
+	}, AsUInt32: 1476395008, Generator: nil},
+	{Name: "LDR (register)", OpcodeMask: 4292873216, Opcode: 3093301248, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"option", 15, 3},
+		{"S", 12, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 3093301248, Generator: nil},
+	{Name: "LDR (register)", OpcodeMask: 4292873216, Opcode: 4167043072, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"option", 15, 3},
+		{"S", 12, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 4167043072, Generator: nil},
+	{Name: "LDRB (immediate)", OpcodeMask: 4292873216, Opcode: 943719424, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 943719424, Generator: nil},
+	{Name: "LDRB (immediate)", OpcodeMask: 4292873216, Opcode: 943721472, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 943721472, Generator: nil},
+	{Name: "LDRB (immediate)", OpcodeMask: 4290772992, Opcode: 960495616, Fields: []InsnField{
+		{"imm12", 21, 12},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 960495616, Generator: nil},
+	{Name: "LDRB (register)", OpcodeMask: 4292873216, Opcode: 945817600, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"option", 15, 3},
+		{"S", 12, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 945817600, Generator: nil},
+	{Name: "LDRB (register)", OpcodeMask: 4292930560, Opcode: 945842176, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"S", 12, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 945842176, Generator: nil},
+	{Name: "LDRH (immediate)", OpcodeMask: 4292873216, Opcode: 2017461248, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2017461248, Generator: nil},
+	{Name: "LDRH (immediate)", OpcodeMask: 4292873216, Opcode: 2017463296, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2017463296, Generator: nil},
+	{Name: "LDRH (immediate)", OpcodeMask: 4290772992, Opcode: 2034237440, Fields: []InsnField{
+		{"imm12", 21, 12},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2034237440, Generator: nil},
+	{Name: "LDRH (register)", OpcodeMask: 4292873216, Opcode: 2019559424, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"option", 15, 3},
+		{"S", 12, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2019559424, Generator: nil},
+	{Name: "LDRSB (immediate)", OpcodeMask: 4292873216, Opcode: 952108032, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 952108032, Generator: nil},
+	{Name: "LDRSB (immediate)", OpcodeMask: 4292873216, Opcode: 947913728, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 947913728, Generator: nil},
+	{Name: "LDRSB (immediate)", OpcodeMask: 4292873216, Opcode: 952110080, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 952110080, Generator: nil},
+	{Name: "LDRSB (immediate)", OpcodeMask: 4292873216, Opcode: 947915776, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 947915776, Generator: nil},
+	{Name: "LDRSB (immediate)", OpcodeMask: 4290772992, Opcode: 968884224, Fields: []InsnField{
+		{"imm12", 21, 12},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 968884224, Generator: nil},
+	{Name: "LDRSB (immediate)", OpcodeMask: 4290772992, Opcode: 964689920, Fields: []InsnField{
+		{"imm12", 21, 12},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 964689920, Generator: nil},
+	{Name: "LDRSB (register)", OpcodeMask: 4292873216, Opcode: 954206208, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"option", 15, 3},
+		{"S", 12, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 954206208, Generator: nil},
+	{Name: "LDRSB (register)", OpcodeMask: 4292930560, Opcode: 954230784, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"S", 12, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 954230784, Generator: nil},
+	{Name: "LDRSB (register)", OpcodeMask: 4292873216, Opcode: 950011904, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"option", 15, 3},
+		{"S", 12, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 950011904, Generator: nil},
+	{Name: "LDRSB (register)", OpcodeMask: 4292930560, Opcode: 950036480, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"S", 12, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 950036480, Generator: nil},
+	{Name: "LDRSH (immediate)", OpcodeMask: 4292873216, Opcode: 2025849856, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2025849856, Generator: nil},
+	{Name: "LDRSH (immediate)", OpcodeMask: 4292873216, Opcode: 2021655552, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2021655552, Generator: nil},
+	{Name: "LDRSH (immediate)", OpcodeMask: 4292873216, Opcode: 2025851904, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2025851904, Generator: nil},
+	{Name: "LDRSH (immediate)", OpcodeMask: 4292873216, Opcode: 2021657600, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2021657600, Generator: nil},
+	{Name: "LDRSH (immediate)", OpcodeMask: 4290772992, Opcode: 2042626048, Fields: []InsnField{
+		{"imm12", 21, 12},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2042626048, Generator: nil},
+	{Name: "LDRSH (immediate)", OpcodeMask: 4290772992, Opcode: 2038431744, Fields: []InsnField{
+		{"imm12", 21, 12},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2038431744, Generator: nil},
+	{Name: "LDRSH (register)", OpcodeMask: 4292873216, Opcode: 2027948032, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"option", 15, 3},
+		{"S", 12, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2027948032, Generator: nil},
+	{Name: "LDRSH (register)", OpcodeMask: 4292873216, Opcode: 2023753728, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"option", 15, 3},
+		{"S", 12, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2023753728, Generator: nil},
+	{Name: "LDRSW (immediate)", OpcodeMask: 4292873216, Opcode: 3095397376, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 3095397376, Generator: nil},
+	{Name: "LDRSW (immediate)", OpcodeMask: 4292873216, Opcode: 3095399424, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 3095399424, Generator: nil},
+	{Name: "LDRSW (immediate)", OpcodeMask: 4290772992, Opcode: 3112173568, Fields: []InsnField{
+		{"imm12", 21, 12},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 3112173568, Generator: nil},
+	{Name: "LDRSW (literal)", OpcodeMask: 4278190080, Opcode: 2550136832, Fields: []InsnField{
+		{"imm19", 23, 19},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2550136832, Generator: nil},
+	{Name: "LDRSW (register)", OpcodeMask: 4292873216, Opcode: 3097495552, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"option", 15, 3},
+		{"S", 12, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 3097495552, Generator: nil},
+	{Name: "LDTR", OpcodeMask: 4292873216, Opcode: 3091204096, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 3091204096, Generator: nil},
+	{Name: "LDTR", OpcodeMask: 4292873216, Opcode: 4164945920, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 4164945920, Generator: nil},
+	{Name: "LDTRB", OpcodeMask: 4292873216, Opcode: 943720448, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 943720448, Generator: nil},
+	{Name: "LDTRH", OpcodeMask: 4292873216, Opcode: 2017462272, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2017462272, Generator: nil},
+	{Name: "LDTRSB", OpcodeMask: 4292873216, Opcode: 952109056, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 952109056, Generator: nil},
+	{Name: "LDTRSB", OpcodeMask: 4292873216, Opcode: 947914752, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 947914752, Generator: nil},
+	{Name: "LDTRSH", OpcodeMask: 4292873216, Opcode: 2025850880, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2025850880, Generator: nil},
+	{Name: "LDTRSH", OpcodeMask: 4292873216, Opcode: 2021656576, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2021656576, Generator: nil},
+	{Name: "LDTRSW", OpcodeMask: 4292873216, Opcode: 3095398400, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 3095398400, Generator: nil},
+	{Name: "LDUR", OpcodeMask: 4292873216, Opcode: 3091202048, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 3091202048, Generator: nil},
+	{Name: "LDUR", OpcodeMask: 4292873216, Opcode: 4164943872, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 4164943872, Generator: nil},
+	{Name: "LDURB", OpcodeMask: 4292873216, Opcode: 943718400, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 943718400, Generator: nil},
+	{Name: "LDURH", OpcodeMask: 4292873216, Opcode: 2017460224, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2017460224, Generator: nil},
+	{Name: "LDURSB", OpcodeMask: 4292873216, Opcode: 952107008, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 952107008, Generator: nil},
+	{Name: "LDURSB", OpcodeMask: 4292873216, Opcode: 947912704, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 947912704, Generator: nil},
+	{Name: "LDURSH", OpcodeMask: 4292873216, Opcode: 2025848832, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2025848832, Generator: nil},
+	{Name: "LDURSH", OpcodeMask: 4292873216, Opcode: 2021654528, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2021654528, Generator: nil},
+	{Name: "LDURSW", OpcodeMask: 4292873216, Opcode: 3095396352, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 3095396352, Generator: nil},
+	{Name: "LDXP", OpcodeMask: 4292902912, Opcode: 2287992832, Fields: []InsnField{
+		{"Rt2", 14, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2287992832, Generator: nil},
+	{Name: "LDXP", OpcodeMask: 4292902912, Opcode: 3361734656, Fields: []InsnField{
+		{"Rt2", 14, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 3361734656, Generator: nil},
+	{Name: "LDXR", OpcodeMask: 4292902912, Opcode: 2285895680, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2285895680, Generator: nil},
+	{Name: "LDXR", OpcodeMask: 4292902912, Opcode: 3359637504, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 3359637504, Generator: nil},
+	{Name: "LDXRB", OpcodeMask: 4292902912, Opcode: 138412032, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 138412032, Generator: nil},
+	{Name: "LDXRH", OpcodeMask: 4292902912, Opcode: 1212153856, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 1212153856, Generator: nil},
+	{Name: "LSL (register)", OpcodeMask: 4292934656, Opcode: 448798720, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 448798720, Generator: nil},
+	{Name: "LSL (register)", OpcodeMask: 4292934656, Opcode: 2596282368, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2596282368, Generator: nil},
+	{Name: "LSL (immediate)", OpcodeMask: 4290772992, Opcode: 1392508928, Fields: []InsnField{
+		{"immr", 21, 6},
+		{"imms", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1392508928, Generator: nil},
+	{Name: "LSL (immediate)", OpcodeMask: 4290772992, Opcode: 3544186880, Fields: []InsnField{
+		{"immr", 21, 6},
+		{"imms", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 3544186880, Generator: nil},
+	{Name: "LSLV", OpcodeMask: 4292934656, Opcode: 448798720, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 448798720, Generator: nil},
+	{Name: "LSLV", OpcodeMask: 4292934656, Opcode: 2596282368, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2596282368, Generator: nil},
+	{Name: "LSR (register)", OpcodeMask: 4292934656, Opcode: 448799744, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 448799744, Generator: nil},
+	{Name: "LSR (register)", OpcodeMask: 4292934656, Opcode: 2596283392, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2596283392, Generator: nil},
+	{Name: "LSR (immediate)", OpcodeMask: 4290837504, Opcode: 1392540672, Fields: []InsnField{
+		{"immr", 21, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1392540672, Generator: nil},
+	{Name: "LSR (immediate)", OpcodeMask: 4290837504, Opcode: 3544251392, Fields: []InsnField{
+		{"immr", 21, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 3544251392, Generator: nil},
+	{Name: "LSRV", OpcodeMask: 4292934656, Opcode: 448799744, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 448799744, Generator: nil},
+	{Name: "LSRV", OpcodeMask: 4292934656, Opcode: 2596283392, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2596283392, Generator: nil},
+	{Name: "MADD", OpcodeMask: 4292902912, Opcode: 452984832, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Ra", 14, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 452984832, Generator: nil},
+	{Name: "MADD", OpcodeMask: 4292902912, Opcode: 2600468480, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Ra", 14, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2600468480, Generator: nil},
+	{Name: "MNEG", OpcodeMask: 4292934656, Opcode: 453049344, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 453049344, Generator: nil},
+	{Name: "MNEG", OpcodeMask: 4292934656, Opcode: 2600532992, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2600532992, Generator: nil},
+	{Name: "MOV (to/from SP)", OpcodeMask: 4294966272, Opcode: 285212672, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 285212672, Generator: nil},
+	{Name: "MOV (to/from SP)", OpcodeMask: 4294966272, Opcode: 2432696320, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2432696320, Generator: nil},
+	{Name: "MOV (inverted wide immediate)", OpcodeMask: 4286578688, Opcode: 310378496, Fields: []InsnField{
+		{"hw", 22, 2},
+		{"imm16", 20, 16},
+		{"Rd", 4, 5},
+	}, AsUInt32: 310378496, Generator: nil},
+	{Name: "MOV (inverted wide immediate)", OpcodeMask: 4286578688, Opcode: 2457862144, Fields: []InsnField{
+		{"hw", 22, 2},
+		{"imm16", 20, 16},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2457862144, Generator: nil},
+	{Name: "MOV (wide immediate)", OpcodeMask: 4286578688, Opcode: 1384120320, Fields: []InsnField{
+		{"hw", 22, 2},
+		{"imm16", 20, 16},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1384120320, Generator: nil},
+	{Name: "MOV (wide immediate)", OpcodeMask: 4286578688, Opcode: 3531603968, Fields: []InsnField{
+		{"hw", 22, 2},
+		{"imm16", 20, 16},
+		{"Rd", 4, 5},
+	}, AsUInt32: 3531603968, Generator: nil},
+	{Name: "MOV (bitmask immediate)", OpcodeMask: 4290773984, Opcode: 838861792, Fields: []InsnField{
+		{"immr", 21, 6},
+		{"imms", 15, 6},
+		{"Rd", 4, 5},
+	}, AsUInt32: 838861792, Generator: nil},
+	{Name: "MOV (bitmask immediate)", OpcodeMask: 4286579680, Opcode: 2986345440, Fields: []InsnField{
+		{"N", 22, 1},
+		{"immr", 21, 6},
+		{"imms", 15, 6},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2986345440, Generator: nil},
+	{Name: "MOV (register)", OpcodeMask: 4292935648, Opcode: 704644064, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 704644064, Generator: nil},
+	{Name: "MOV (register)", OpcodeMask: 4292935648, Opcode: 2852127712, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2852127712, Generator: nil},
+	{Name: "MOVK", OpcodeMask: 4286578688, Opcode: 1920991232, Fields: []InsnField{
+		{"hw", 22, 2},
+		{"imm16", 20, 16},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1920991232, Generator: nil},
+	{Name: "MOVK", OpcodeMask: 4286578688, Opcode: 4068474880, Fields: []InsnField{
+		{"hw", 22, 2},
+		{"imm16", 20, 16},
+		{"Rd", 4, 5},
+	}, AsUInt32: 4068474880, Generator: nil},
+	{Name: "MOVN", OpcodeMask: 4286578688, Opcode: 310378496, Fields: []InsnField{
+		{"hw", 22, 2},
+		{"imm16", 20, 16},
+		{"Rd", 4, 5},
+	}, AsUInt32: 310378496, Generator: nil},
+	{Name: "MOVN", OpcodeMask: 4286578688, Opcode: 2457862144, Fields: []InsnField{
+		{"hw", 22, 2},
+		{"imm16", 20, 16},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2457862144, Generator: nil},
+	{Name: "MOVZ", OpcodeMask: 4286578688, Opcode: 1384120320, Fields: []InsnField{
+		{"hw", 22, 2},
+		{"imm16", 20, 16},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1384120320, Generator: nil},
+	{Name: "MOVZ", OpcodeMask: 4286578688, Opcode: 3531603968, Fields: []InsnField{
+		{"hw", 22, 2},
+		{"imm16", 20, 16},
+		{"Rd", 4, 5},
+	}, AsUInt32: 3531603968, Generator: nil},
+	{Name: "MRS", OpcodeMask: 4293918720, Opcode: 3576692736, Fields: []InsnField{
+		{"o0", 19, 1},
+		{"op1", 18, 3},
+		{"CRn", 15, 4},
+		{"CRm", 11, 4},
+		{"op2", 7, 3},
+		{"Rt", 4, 5},
+	}, AsUInt32: 3576692736, Generator: nil},
+	{Name: "MSR (immediate)", OpcodeMask: 4294504479, Opcode: 3573563423, Fields: []InsnField{
+		{"op1", 18, 3},
+		{"CRm", 11, 4},
+		{"op2", 7, 3},
+	}, AsUInt32: 3573563423, Generator: nil},
+	{Name: "MSR (register)", OpcodeMask: 4293918720, Opcode: 3574595584, Fields: []InsnField{
+		{"o0", 19, 1},
+		{"op1", 18, 3},
+		{"CRn", 15, 4},
+		{"CRm", 11, 4},
+		{"op2", 7, 3},
+		{"Rt", 4, 5},
+	}, AsUInt32: 3574595584, Generator: nil},
+	{Name: "MSUB", OpcodeMask: 4292902912, Opcode: 453017600, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Ra", 14, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 453017600, Generator: nil},
+	{Name: "MSUB", OpcodeMask: 4292902912, Opcode: 2600501248, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Ra", 14, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2600501248, Generator: nil},
+	{Name: "MUL", OpcodeMask: 4292934656, Opcode: 453016576, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 453016576, Generator: nil},
+	{Name: "MUL", OpcodeMask: 4292934656, Opcode: 2600500224, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2600500224, Generator: nil},
+	{Name: "MVN", OpcodeMask: 4280288224, Opcode: 706741216, Fields: []InsnField{
+		{"shift", 23, 2},
+		{"Rm", 20, 5},
+		{"imm6", 15, 6},
+		{"Rd", 4, 5},
+	}, AsUInt32: 706741216, Generator: nil},
+	{Name: "MVN", OpcodeMask: 4280288224, Opcode: 2854224864, Fields: []InsnField{
+		{"shift", 23, 2},
+		{"Rm", 20, 5},
+		{"imm6", 15, 6},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2854224864, Generator: nil},
+	{Name: "NEG (shifted register)", OpcodeMask: 4280288224, Opcode: 1258292192, Fields: []InsnField{
+		{"shift", 23, 2},
+		{"Rm", 20, 5},
+		{"imm6", 15, 6},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1258292192, Generator: nil},
+	{Name: "NEG (shifted register)", OpcodeMask: 4280288224, Opcode: 3405775840, Fields: []InsnField{
+		{"shift", 23, 2},
+		{"Rm", 20, 5},
+		{"imm6", 15, 6},
+		{"Rd", 4, 5},
+	}, AsUInt32: 3405775840, Generator: nil},
+	{Name: "NEGS", OpcodeMask: 4280288224, Opcode: 1795163104, Fields: []InsnField{
+		{"shift", 23, 2},
+		{"Rm", 20, 5},
+		{"imm6", 15, 6},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1795163104, Generator: nil},
+	{Name: "NEGS", OpcodeMask: 4280288224, Opcode: 3942646752, Fields: []InsnField{
+		{"shift", 23, 2},
+		{"Rm", 20, 5},
+		{"imm6", 15, 6},
+		{"Rd", 4, 5},
+	}, AsUInt32: 3942646752, Generator: nil},
+	{Name: "NGC", OpcodeMask: 4292935648, Opcode: 1509950432, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1509950432, Generator: nil},
+	{Name: "NGC", OpcodeMask: 4292935648, Opcode: 3657434080, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 3657434080, Generator: nil},
+	{Name: "NGCS", OpcodeMask: 4292935648, Opcode: 2046821344, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2046821344, Generator: nil},
+	{Name: "NGCS", OpcodeMask: 4292935648, Opcode: 4194304992, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 4194304992, Generator: nil},
+	{Name: "NOP", OpcodeMask: 4294967295, Opcode: 3573751839, AsUInt32: 3573751839, Generator: nil},
+	{Name: "ORN (shifted register)", OpcodeMask: 4280287232, Opcode: 706740224, Fields: []InsnField{
+		{"shift", 23, 2},
+		{"Rm", 20, 5},
+		{"imm6", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 706740224, Generator: nil},
+	{Name: "ORN (shifted register)", OpcodeMask: 4280287232, Opcode: 2854223872, Fields: []InsnField{
+		{"shift", 23, 2},
+		{"Rm", 20, 5},
+		{"imm6", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2854223872, Generator: nil},
+	{Name: "ORR (immediate)", OpcodeMask: 4290772992, Opcode: 838860800, Fields: []InsnField{
+		{"immr", 21, 6},
+		{"imms", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 838860800, Generator: nil},
+	{Name: "ORR (immediate)", OpcodeMask: 4286578688, Opcode: 2986344448, Fields: []InsnField{
+		{"N", 22, 1},
+		{"immr", 21, 6},
+		{"imms", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2986344448, Generator: nil},
+	{Name: "ORR (shifted register)", OpcodeMask: 4280287232, Opcode: 704643072, Fields: []InsnField{
+		{"shift", 23, 2},
+		{"Rm", 20, 5},
+		{"imm6", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 704643072, Generator: nil},
+	{Name: "ORR (shifted register)", OpcodeMask: 4280287232, Opcode: 2852126720, Fields: []InsnField{
+		{"shift", 23, 2},
+		{"Rm", 20, 5},
+		{"imm6", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2852126720, Generator: nil},
+	{Name: "PRFM (immediate)", OpcodeMask: 4290772992, Opcode: 4185915392, Fields: []InsnField{
+		{"imm12", 21, 12},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 4185915392, Generator: nil},
+	{Name: "PRFM (literal)", OpcodeMask: 4278190080, Opcode: 3623878656, Fields: []InsnField{
+		{"imm19", 23, 19},
+		{"Rt", 4, 5},
+	}, AsUInt32: 3623878656, Generator: nil},
+	{Name: "PRFM (register)", OpcodeMask: 4292873216, Opcode: 4171237376, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"option", 15, 3},
+		{"S", 12, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 4171237376, Generator: nil},
+	{Name: "PRFM (unscaled offset)", OpcodeMask: 4292873216, Opcode: 4169138176, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 4169138176, Generator: nil},
+	{Name: "RBIT", OpcodeMask: 4294966272, Opcode: 1522532352, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1522532352, Generator: nil},
+	{Name: "RBIT", OpcodeMask: 4294966272, Opcode: 3670016000, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 3670016000, Generator: nil},
+	{Name: "RET", OpcodeMask: 4294966303, Opcode: 3596550144, Fields: []InsnField{
+		{"Rn", 9, 5},
+	}, AsUInt32: 3596550144, Generator: nil},
+	{Name: "REV", OpcodeMask: 4294966272, Opcode: 1522534400, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1522534400, Generator: nil},
+	{Name: "REV", OpcodeMask: 4294966272, Opcode: 3670019072, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 3670019072, Generator: nil},
+	{Name: "REV16", OpcodeMask: 4294966272, Opcode: 1522533376, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1522533376, Generator: nil},
+	{Name: "REV16", OpcodeMask: 4294966272, Opcode: 3670017024, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 3670017024, Generator: nil},
+	{Name: "REV32", OpcodeMask: 4294966272, Opcode: 3670018048, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 3670018048, Generator: nil},
+	{Name: "REV64", OpcodeMask: 4294966272, Opcode: 3670019072, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 3670019072, Generator: nil},
+	{Name: "ROR (immediate)", OpcodeMask: 4292870144, Opcode: 327155712, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"imms", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 327155712, Generator: nil},
+	{Name: "ROR (immediate)", OpcodeMask: 4292870144, Opcode: 2478833664, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"imms", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2478833664, Generator: nil},
+	{Name: "ROR (register)", OpcodeMask: 4292934656, Opcode: 448801792, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 448801792, Generator: nil},
+	{Name: "ROR (register)", OpcodeMask: 4292934656, Opcode: 2596285440, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2596285440, Generator: nil},
+	{Name: "RORV", OpcodeMask: 4292934656, Opcode: 448801792, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 448801792, Generator: nil},
+	{Name: "RORV", OpcodeMask: 4292934656, Opcode: 2596285440, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2596285440, Generator: nil},
+	{Name: "SBC", OpcodeMask: 4292934656, Opcode: 1509949440, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1509949440, Generator: nil},
+	{Name: "SBC", OpcodeMask: 4292934656, Opcode: 3657433088, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 3657433088, Generator: nil},
+	{Name: "SBCS", OpcodeMask: 4292934656, Opcode: 2046820352, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2046820352, Generator: nil},
+	{Name: "SBCS", OpcodeMask: 4292934656, Opcode: 4194304000, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 4194304000, Generator: nil},
+	{Name: "SBFIZ", OpcodeMask: 4290772992, Opcode: 318767104, Fields: []InsnField{
+		{"immr", 21, 6},
+		{"imms", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 318767104, Generator: nil},
+	{Name: "SBFIZ", OpcodeMask: 4290772992, Opcode: 2470445056, Fields: []InsnField{
+		{"immr", 21, 6},
+		{"imms", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2470445056, Generator: nil},
+	{Name: "SBFM", OpcodeMask: 4290772992, Opcode: 318767104, Fields: []InsnField{
+		{"immr", 21, 6},
+		{"imms", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 318767104, Generator: nil},
+	{Name: "SBFM", OpcodeMask: 4290772992, Opcode: 2470445056, Fields: []InsnField{
+		{"immr", 21, 6},
+		{"imms", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2470445056, Generator: nil},
+	{Name: "SBFX", OpcodeMask: 4290772992, Opcode: 318767104, Fields: []InsnField{
+		{"immr", 21, 6},
+		{"imms", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 318767104, Generator: nil},
+	{Name: "SBFX", OpcodeMask: 4290772992, Opcode: 2470445056, Fields: []InsnField{
+		{"immr", 21, 6},
+		{"imms", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2470445056, Generator: nil},
+	{Name: "SDIV", OpcodeMask: 4292934656, Opcode: 448793600, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 448793600, Generator: nil},
+	{Name: "SDIV", OpcodeMask: 4292934656, Opcode: 2596277248, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2596277248, Generator: nil},
+	{Name: "SEV", OpcodeMask: 4294967295, Opcode: 3573751967, AsUInt32: 3573751967, Generator: nil},
+	{Name: "SEVL", OpcodeMask: 4294967295, Opcode: 3573751999, AsUInt32: 3573751999, Generator: nil},
+	{Name: "SMADDL", OpcodeMask: 4292902912, Opcode: 2602565632, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Ra", 14, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2602565632, Generator: nil},
+	{Name: "SMC", OpcodeMask: 4292870175, Opcode: 3556769795, Fields: []InsnField{
+		{"imm16", 20, 16},
+	}, AsUInt32: 3556769795, Generator: nil},
+	{Name: "SMNEGL", OpcodeMask: 4292934656, Opcode: 2602630144, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2602630144, Generator: nil},
+	{Name: "SMSUBL", OpcodeMask: 4292902912, Opcode: 2602598400, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Ra", 14, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2602598400, Generator: nil},
+	{Name: "SMULH", OpcodeMask: 4292902912, Opcode: 2604662784, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2604662784, Generator: nil},
+	{Name: "SMULL", OpcodeMask: 4292934656, Opcode: 2602597376, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2602597376, Generator: nil},
+	{Name: "STLR", OpcodeMask: 4292902912, Opcode: 2290122752, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2290122752, Generator: nil},
+	{Name: "STLR", OpcodeMask: 4292902912, Opcode: 3363864576, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 3363864576, Generator: nil},
+	{Name: "STLRB", OpcodeMask: 4292902912, Opcode: 142639104, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 142639104, Generator: nil},
+	{Name: "STLRH", OpcodeMask: 4292902912, Opcode: 1216380928, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 1216380928, Generator: nil},
+	{Name: "STLXP", OpcodeMask: 4292902912, Opcode: 2283831296, Fields: []InsnField{
+		{"Rs", 20, 5},
+		{"Rt2", 14, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2283831296, Generator: nil},
+	{Name: "STLXP", OpcodeMask: 4292902912, Opcode: 3357573120, Fields: []InsnField{
+		{"Rs", 20, 5},
+		{"Rt2", 14, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 3357573120, Generator: nil},
+	{Name: "STLXR", OpcodeMask: 4292902912, Opcode: 2281734144, Fields: []InsnField{
+		{"Rs", 20, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2281734144, Generator: nil},
+	{Name: "STLXR", OpcodeMask: 4292902912, Opcode: 3355475968, Fields: []InsnField{
+		{"Rs", 20, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 3355475968, Generator: nil},
+	{Name: "STLXRB", OpcodeMask: 4292902912, Opcode: 134250496, Fields: []InsnField{
+		{"Rs", 20, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 134250496, Generator: nil},
+	{Name: "STLXRH", OpcodeMask: 4292902912, Opcode: 1207992320, Fields: []InsnField{
+		{"Rs", 20, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 1207992320, Generator: nil},
+	{Name: "STNP", OpcodeMask: 4290772992, Opcode: 671088640, Fields: []InsnField{
+		{"imm7", 21, 7},
+		{"Rt2", 14, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 671088640, Generator: nil},
+	{Name: "STNP", OpcodeMask: 4290772992, Opcode: 2818572288, Fields: []InsnField{
+		{"imm7", 21, 7},
+		{"Rt2", 14, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2818572288, Generator: nil},
+	{Name: "STP", OpcodeMask: 4290772992, Opcode: 679477248, Fields: []InsnField{
+		{"imm7", 21, 7},
+		{"Rt2", 14, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 679477248, Generator: nil},
+	{Name: "STP", OpcodeMask: 4290772992, Opcode: 2826960896, Fields: []InsnField{
+		{"imm7", 21, 7},
+		{"Rt2", 14, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2826960896, Generator: nil},
+	{Name: "STP", OpcodeMask: 4290772992, Opcode: 696254464, Fields: []InsnField{
+		{"imm7", 21, 7},
+		{"Rt2", 14, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 696254464, Generator: nil},
+	{Name: "STP", OpcodeMask: 4290772992, Opcode: 2843738112, Fields: []InsnField{
+		{"imm7", 21, 7},
+		{"Rt2", 14, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2843738112, Generator: nil},
+	{Name: "STP", OpcodeMask: 4290772992, Opcode: 687865856, Fields: []InsnField{
+		{"imm7", 21, 7},
+		{"Rt2", 14, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 687865856, Generator: nil},
+	{Name: "STP", OpcodeMask: 4290772992, Opcode: 2835349504, Fields: []InsnField{
+		{"imm7", 21, 7},
+		{"Rt2", 14, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2835349504, Generator: nil},
+	{Name: "STR (immediate)", OpcodeMask: 4292873216, Opcode: 3087008768, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 3087008768, Generator: nil},
+	{Name: "STR (immediate)", OpcodeMask: 4292873216, Opcode: 4160750592, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 4160750592, Generator: nil},
+	{Name: "STR (immediate)", OpcodeMask: 4292873216, Opcode: 3087010816, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 3087010816, Generator: nil},
+	{Name: "STR (immediate)", OpcodeMask: 4292873216, Opcode: 4160752640, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 4160752640, Generator: nil},
+	{Name: "STR (immediate)", OpcodeMask: 4290772992, Opcode: 3103784960, Fields: []InsnField{
+		{"imm12", 21, 12},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 3103784960, Generator: nil},
+	{Name: "STR (immediate)", OpcodeMask: 4290772992, Opcode: 4177526784, Fields: []InsnField{
+		{"imm12", 21, 12},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 4177526784, Generator: nil},
+	{Name: "STR (register)", OpcodeMask: 4292873216, Opcode: 3089106944, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"option", 15, 3},
+		{"S", 12, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 3089106944, Generator: nil},
+	{Name: "STR (register)", OpcodeMask: 4292873216, Opcode: 4162848768, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"option", 15, 3},
+		{"S", 12, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 4162848768, Generator: nil},
+	{Name: "STRB (immediate)", OpcodeMask: 4292873216, Opcode: 939525120, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 939525120, Generator: nil},
+	{Name: "STRB (immediate)", OpcodeMask: 4292873216, Opcode: 939527168, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 939527168, Generator: nil},
+	{Name: "STRB (immediate)", OpcodeMask: 4290772992, Opcode: 956301312, Fields: []InsnField{
+		{"imm12", 21, 12},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 956301312, Generator: nil},
+	{Name: "STRB (register)", OpcodeMask: 4292873216, Opcode: 941623296, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"option", 15, 3},
+		{"S", 12, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 941623296, Generator: nil},
+	{Name: "STRB (register)", OpcodeMask: 4292930560, Opcode: 941647872, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"S", 12, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 941647872, Generator: nil},
+	{Name: "STRH (immediate)", OpcodeMask: 4292873216, Opcode: 2013266944, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2013266944, Generator: nil},
+	{Name: "STRH (immediate)", OpcodeMask: 4292873216, Opcode: 2013268992, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2013268992, Generator: nil},
+	{Name: "STRH (immediate)", OpcodeMask: 4290772992, Opcode: 2030043136, Fields: []InsnField{
+		{"imm12", 21, 12},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2030043136, Generator: nil},
+	{Name: "STRH (register)", OpcodeMask: 4292873216, Opcode: 2015365120, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"option", 15, 3},
+		{"S", 12, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2015365120, Generator: nil},
+	{Name: "STTR", OpcodeMask: 4292873216, Opcode: 3087009792, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 3087009792, Generator: nil},
+	{Name: "STTR", OpcodeMask: 4292873216, Opcode: 4160751616, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 4160751616, Generator: nil},
+	{Name: "STTRB", OpcodeMask: 4292873216, Opcode: 939526144, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 939526144, Generator: nil},
+	{Name: "STTRH", OpcodeMask: 4292873216, Opcode: 2013267968, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2013267968, Generator: nil},
+	{Name: "STUR", OpcodeMask: 4292873216, Opcode: 3087007744, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 3087007744, Generator: nil},
+	{Name: "STUR", OpcodeMask: 4292873216, Opcode: 4160749568, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 4160749568, Generator: nil},
+	{Name: "STURB", OpcodeMask: 4292873216, Opcode: 939524096, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 939524096, Generator: nil},
+	{Name: "STURH", OpcodeMask: 4292873216, Opcode: 2013265920, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2013265920, Generator: nil},
+	{Name: "STXP", OpcodeMask: 4292902912, Opcode: 2283798528, Fields: []InsnField{
+		{"Rs", 20, 5},
+		{"Rt2", 14, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2283798528, Generator: nil},
+	{Name: "STXP", OpcodeMask: 4292902912, Opcode: 3357540352, Fields: []InsnField{
+		{"Rs", 20, 5},
+		{"Rt2", 14, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 3357540352, Generator: nil},
+	{Name: "STXR", OpcodeMask: 4292902912, Opcode: 2281701376, Fields: []InsnField{
+		{"Rs", 20, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2281701376, Generator: nil},
+	{Name: "STXR", OpcodeMask: 4292902912, Opcode: 3355443200, Fields: []InsnField{
+		{"Rs", 20, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 3355443200, Generator: nil},
+	{Name: "STXRB", OpcodeMask: 4292902912, Opcode: 134217728, Fields: []InsnField{
+		{"Rs", 20, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 134217728, Generator: nil},
+	{Name: "STXRH", OpcodeMask: 4292902912, Opcode: 1207959552, Fields: []InsnField{
+		{"Rs", 20, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 1207959552, Generator: nil},
+	{Name: "SUB (extended register)", OpcodeMask: 4292870144, Opcode: 1260388352, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"option", 15, 3},
+		{"imm3", 12, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1260388352, Generator: nil},
+	{Name: "SUB (extended register)", OpcodeMask: 4292870144, Opcode: 3407872000, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"option", 15, 3},
+		{"imm3", 12, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 3407872000, Generator: nil},
+	{Name: "SUB (immediate)", OpcodeMask: 4278190080, Opcode: 1358954496, Fields: []InsnField{
+		{"shift", 23, 2},
+		{"imm12", 21, 12},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1358954496, Generator: nil},
+	{Name: "SUB (immediate)", OpcodeMask: 4278190080, Opcode: 3506438144, Fields: []InsnField{
+		{"shift", 23, 2},
+		{"imm12", 21, 12},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 3506438144, Generator: nil},
+	{Name: "SUB (shifted register)", OpcodeMask: 4280287232, Opcode: 1258291200, Fields: []InsnField{
+		{"shift", 23, 2},
+		{"Rm", 20, 5},
+		{"imm6", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1258291200, Generator: nil},
+	{Name: "SUB (shifted register)", OpcodeMask: 4280287232, Opcode: 3405774848, Fields: []InsnField{
+		{"shift", 23, 2},
+		{"Rm", 20, 5},
+		{"imm6", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 3405774848, Generator: nil},
+	{Name: "SUBS (extended register)", OpcodeMask: 4292870144, Opcode: 1797259264, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"option", 15, 3},
+		{"imm3", 12, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1797259264, Generator: nil},
+	{Name: "SUBS (extended register)", OpcodeMask: 4292870144, Opcode: 3944742912, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"option", 15, 3},
+		{"imm3", 12, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 3944742912, Generator: nil},
+	{Name: "SUBS (immediate)", OpcodeMask: 4278190080, Opcode: 1895825408, Fields: []InsnField{
+		{"shift", 23, 2},
+		{"imm12", 21, 12},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1895825408, Generator: nil},
+	{Name: "SUBS (immediate)", OpcodeMask: 4278190080, Opcode: 4043309056, Fields: []InsnField{
+		{"shift", 23, 2},
+		{"imm12", 21, 12},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 4043309056, Generator: nil},
+	{Name: "SUBS (shifted register)", OpcodeMask: 4280287232, Opcode: 1795162112, Fields: []InsnField{
+		{"shift", 23, 2},
+		{"Rm", 20, 5},
+		{"imm6", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1795162112, Generator: nil},
+	{Name: "SUBS (shifted register)", OpcodeMask: 4280287232, Opcode: 3942645760, Fields: []InsnField{
+		{"shift", 23, 2},
+		{"Rm", 20, 5},
+		{"imm6", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 3942645760, Generator: nil},
+	{Name: "SVC", OpcodeMask: 4292870175, Opcode: 3556769793, Fields: []InsnField{
+		{"imm16", 20, 16},
+	}, AsUInt32: 3556769793, Generator: nil},
+	{Name: "SXTB", OpcodeMask: 4294966272, Opcode: 318774272, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 318774272, Generator: nil},
+	{Name: "SXTB", OpcodeMask: 4294966272, Opcode: 2470452224, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2470452224, Generator: nil},
+	{Name: "SXTH", OpcodeMask: 4294966272, Opcode: 318782464, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 318782464, Generator: nil},
+	{Name: "SXTH", OpcodeMask: 4294966272, Opcode: 2470460416, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2470460416, Generator: nil},
+	{Name: "SXTW", OpcodeMask: 4294966272, Opcode: 2470476800, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2470476800, Generator: nil},
+	{Name: "SYS", OpcodeMask: 4294443008, Opcode: 3574071296, Fields: []InsnField{
+		{"op1", 18, 3},
+		{"CRn", 15, 4},
+		{"CRm", 11, 4},
+		{"op2", 7, 3},
+		{"Rt", 4, 5},
+	}, AsUInt32: 3574071296, Priv: true, Generator: nil},
+	{Name: "SYSL", OpcodeMask: 4294443008, Opcode: 3576168448, Fields: []InsnField{
+		{"op1", 18, 3},
+		{"CRn", 15, 4},
+		{"CRm", 11, 4},
+		{"op2", 7, 3},
+		{"Rt", 4, 5},
+	}, AsUInt32: 3576168448, Priv: true, Generator: nil},
+	{Name: "TBNZ", OpcodeMask: 2130706432, Opcode: 922746880, Fields: []InsnField{
+		{"b5", 31, 1},
+		{"b40", 23, 5},
+		{"imm14", 18, 14},
+		{"Rt", 4, 5},
+	}, AsUInt32: 922746880, Generator: nil},
+	{Name: "TBZ", OpcodeMask: 2130706432, Opcode: 905969664, Fields: []InsnField{
+		{"b5", 31, 1},
+		{"b40", 23, 5},
+		{"imm14", 18, 14},
+		{"Rt", 4, 5},
+	}, AsUInt32: 905969664, Generator: nil},
+	{Name: "TLBI", OpcodeMask: 4294504448, Opcode: 3574104064, Fields: []InsnField{
+		{"op1", 18, 3},
+		{"CRm", 11, 4},
+		{"op2", 7, 3},
+		{"Rt", 4, 5},
+	}, AsUInt32: 3574104064, Priv: true, Generator: nil},
+	{Name: "TST (immediate)", OpcodeMask: 4290773023, Opcode: 1912602655, Fields: []InsnField{
+		{"immr", 21, 6},
+		{"imms", 15, 6},
+		{"Rn", 9, 5},
+	}, AsUInt32: 1912602655, Generator: nil},
+	{Name: "TST (immediate)", OpcodeMask: 4286578719, Opcode: 4060086303, Fields: []InsnField{
+		{"N", 22, 1},
+		{"immr", 21, 6},
+		{"imms", 15, 6},
+		{"Rn", 9, 5},
+	}, AsUInt32: 4060086303, Generator: nil},
+	{Name: "TST (shifted register)", OpcodeMask: 4280287263, Opcode: 1778384927, Fields: []InsnField{
+		{"shift", 23, 2},
+		{"Rm", 20, 5},
+		{"imm6", 15, 6},
+		{"Rn", 9, 5},
+	}, AsUInt32: 1778384927, Generator: nil},
+	{Name: "TST (shifted register)", OpcodeMask: 4280287263, Opcode: 3925868575, Fields: []InsnField{
+		{"shift", 23, 2},
+		{"Rm", 20, 5},
+		{"imm6", 15, 6},
+		{"Rn", 9, 5},
+	}, AsUInt32: 3925868575, Generator: nil},
+	{Name: "UBFIZ", OpcodeMask: 4290772992, Opcode: 1392508928, Fields: []InsnField{
+		{"immr", 21, 6},
+		{"imms", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1392508928, Generator: nil},
+	{Name: "UBFIZ", OpcodeMask: 4290772992, Opcode: 3544186880, Fields: []InsnField{
+		{"immr", 21, 6},
+		{"imms", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 3544186880, Generator: nil},
+	{Name: "UBFM", OpcodeMask: 4290772992, Opcode: 1392508928, Fields: []InsnField{
+		{"immr", 21, 6},
+		{"imms", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1392508928, Generator: nil},
+	{Name: "UBFM", OpcodeMask: 4290772992, Opcode: 3544186880, Fields: []InsnField{
+		{"immr", 21, 6},
+		{"imms", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 3544186880, Generator: nil},
+	{Name: "UBFX", OpcodeMask: 4290772992, Opcode: 1392508928, Fields: []InsnField{
+		{"immr", 21, 6},
+		{"imms", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1392508928, Generator: nil},
+	{Name: "UBFX", OpcodeMask: 4290772992, Opcode: 3544186880, Fields: []InsnField{
+		{"immr", 21, 6},
+		{"imms", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 3544186880, Generator: nil},
+	{Name: "UDIV", OpcodeMask: 4292934656, Opcode: 448792576, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 448792576, Generator: nil},
+	{Name: "UDIV", OpcodeMask: 4292934656, Opcode: 2596276224, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2596276224, Generator: nil},
+	{Name: "UMADDL", OpcodeMask: 4292902912, Opcode: 2610954240, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Ra", 14, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2610954240, Generator: nil},
+	{Name: "UMNEGL", OpcodeMask: 4292934656, Opcode: 2611018752, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2611018752, Generator: nil},
+	{Name: "UMSUBL", OpcodeMask: 4292902912, Opcode: 2610987008, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Ra", 14, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2610987008, Generator: nil},
+	{Name: "UMULH", OpcodeMask: 4292902912, Opcode: 2613051392, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2613051392, Generator: nil},
+	{Name: "UMULL", OpcodeMask: 4292934656, Opcode: 2610985984, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2610985984, Generator: nil},
+	{Name: "UXTB", OpcodeMask: 4294966272, Opcode: 1392516096, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1392516096, Generator: nil},
+	{Name: "UXTH", OpcodeMask: 4294966272, Opcode: 1392524288, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1392524288, Generator: nil},
+	{Name: "WFE", OpcodeMask: 4294967295, Opcode: 3573751903, AsUInt32: 3573751903, Generator: nil},
+	{Name: "WFI", OpcodeMask: 4294967295, Opcode: 3573751935, AsUInt32: 3573751935, Generator: nil},
+	{Name: "YIELD", OpcodeMask: 4294967295, Opcode: 3573751871, AsUInt32: 3573751871, Generator: nil},
+	{Name: "ABS", OpcodeMask: 4282383360, Opcode: 1579202560, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1579202560, Generator: nil},
+	{Name: "ABS", OpcodeMask: 3208641536, Opcode: 237025280, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 237025280, Generator: nil},
+	{Name: "ADD (vector)", OpcodeMask: 4280351744, Opcode: 1579189248, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1579189248, Generator: nil},
+	{Name: "ADD (vector)", OpcodeMask: 3206609920, Opcode: 237011968, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 237011968, Generator: nil},
+	{Name: "ADDHN, ADDHN2", OpcodeMask: 4280351744, Opcode: 236994560, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 236994560, Generator: nil},
+	{Name: "ADDHN, ADDHN2", OpcodeMask: 4280351744, Opcode: 1310736384, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1310736384, Generator: nil},
+	{Name: "ADDP (scalar)", OpcodeMask: 4282383360, Opcode: 1580316672, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1580316672, Generator: nil},
+	{Name: "ADDP (vector)", OpcodeMask: 3206609920, Opcode: 237026304, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 237026304, Generator: nil},
+	{Name: "ADDV", OpcodeMask: 3208641536, Opcode: 238139392, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 238139392, Generator: nil},
+	{Name: "AESD", OpcodeMask: 4294966272, Opcode: 1311266816, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1311266816, Generator: nil},
+	{Name: "AESE", OpcodeMask: 4294966272, Opcode: 1311262720, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1311262720, Generator: nil},
+	{Name: "AESIMC", OpcodeMask: 4294966272, Opcode: 1311275008, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1311275008, Generator: nil},
+	{Name: "AESMC", OpcodeMask: 4294966272, Opcode: 1311270912, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1311270912, Generator: nil},
+	{Name: "AND (vector)", OpcodeMask: 3219192832, Opcode: 236985344, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 236985344, Generator: nil},
+	{Name: "BIC (vector, immediate)", OpcodeMask: 3220704256, Opcode: 788530176, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"a", 18, 1},
+		{"b", 17, 1},
+		{"c", 16, 1},
+		{"cmode", 15, 4},
+		{"d", 9, 1},
+		{"e", 8, 1},
+		{"f", 7, 1},
+		{"g", 6, 1},
+		{"h", 5, 1},
+		{"Rd", 4, 5},
+	}, AsUInt32: 788530176, Generator: nil},
+	{Name: "BIC (vector, immediate)", OpcodeMask: 3220704256, Opcode: 788530176, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"a", 18, 1},
+		{"b", 17, 1},
+		{"c", 16, 1},
+		{"cmode", 15, 4},
+		{"d", 9, 1},
+		{"e", 8, 1},
+		{"f", 7, 1},
+		{"g", 6, 1},
+		{"h", 5, 1},
+		{"Rd", 4, 5},
+	}, AsUInt32: 788530176, Generator: nil},
+	{Name: "BIC (vector, register)", OpcodeMask: 3219192832, Opcode: 241179648, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 241179648, Generator: nil},
+	{Name: "BIF", OpcodeMask: 3219192832, Opcode: 786439168, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 786439168, Generator: nil},
+	{Name: "BIT", OpcodeMask: 3219192832, Opcode: 782244864, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 782244864, Generator: nil},
+	{Name: "BSL", OpcodeMask: 3219192832, Opcode: 778050560, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 778050560, Generator: nil},
+	{Name: "CLS (vector)", OpcodeMask: 3208641536, Opcode: 236996608, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 236996608, Generator: nil},
+	{Name: "CLZ (vector)", OpcodeMask: 3208641536, Opcode: 773867520, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773867520, Generator: nil},
+	{Name: "CMEQ (register)", OpcodeMask: 4280351744, Opcode: 2116062208, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2116062208, Generator: nil},
+	{Name: "CMEQ (register)", OpcodeMask: 3206609920, Opcode: 773884928, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773884928, Generator: nil},
+	{Name: "CMEQ (zero)", OpcodeMask: 4282383360, Opcode: 1579194368, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1579194368, Generator: nil},
+	{Name: "CMEQ (zero)", OpcodeMask: 3208641536, Opcode: 237017088, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 237017088, Generator: nil},
+	{Name: "CMGE (register)", OpcodeMask: 4280351744, Opcode: 1579170816, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1579170816, Generator: nil},
+	{Name: "CMGE (register)", OpcodeMask: 3206609920, Opcode: 236993536, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 236993536, Generator: nil},
+	{Name: "CMGE (zero)", OpcodeMask: 4282383360, Opcode: 2116061184, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2116061184, Generator: nil},
+	{Name: "CMGE (zero)", OpcodeMask: 3208641536, Opcode: 773883904, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773883904, Generator: nil},
+	{Name: "CMGT (register)", OpcodeMask: 4280351744, Opcode: 1579168768, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1579168768, Generator: nil},
+	{Name: "CMGT (register)", OpcodeMask: 3206609920, Opcode: 236991488, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 236991488, Generator: nil},
+	{Name: "CMGT (zero)", OpcodeMask: 4282383360, Opcode: 1579190272, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1579190272, Generator: nil},
+	{Name: "CMGT (zero)", OpcodeMask: 3208641536, Opcode: 237012992, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 237012992, Generator: nil},
+	{Name: "CMHI (register)", OpcodeMask: 4280351744, Opcode: 2116039680, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2116039680, Generator: nil},
+	{Name: "CMHI (register)", OpcodeMask: 3206609920, Opcode: 773862400, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773862400, Generator: nil},
+	{Name: "CMHS (register)", OpcodeMask: 4280351744, Opcode: 2116041728, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2116041728, Generator: nil},
+	{Name: "CMHS (register)", OpcodeMask: 3206609920, Opcode: 773864448, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773864448, Generator: nil},
+	{Name: "CMLE (zero)", OpcodeMask: 4282383360, Opcode: 2116065280, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2116065280, Generator: nil},
+	{Name: "CMLE (zero)", OpcodeMask: 3208641536, Opcode: 773888000, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773888000, Generator: nil},
+	{Name: "CMLT (zero)", OpcodeMask: 4282383360, Opcode: 1579198464, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1579198464, Generator: nil},
+	{Name: "CMLT (zero)", OpcodeMask: 3208641536, Opcode: 237021184, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 237021184, Generator: nil},
+	{Name: "CMTST", OpcodeMask: 4280351744, Opcode: 1579191296, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1579191296, Generator: nil},
+	{Name: "CMTST", OpcodeMask: 3206609920, Opcode: 237014016, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 237014016, Generator: nil},
+	{Name: "CNT", OpcodeMask: 3208641536, Opcode: 237000704, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 237000704, Generator: nil},
+	{Name: "DUP (element)", OpcodeMask: 4292934656, Opcode: 1577059328, Fields: []InsnField{
+		{"imm5", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1577059328, Generator: nil},
+	{Name: "DUP (element)", OpcodeMask: 3219192832, Opcode: 234882048, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"imm5", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 234882048, Generator: nil},
+	{Name: "DUP (general)", OpcodeMask: 3219192832, Opcode: 234884096, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"imm5", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 234884096, Generator: nil},
+	{Name: "EOR (vector)", OpcodeMask: 3219192832, Opcode: 773856256, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773856256, Generator: nil},
+	{Name: "EXT", OpcodeMask: 3219162112, Opcode: 771751936, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"imm4", 14, 4},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 771751936, Generator: nil},
+	{Name: "FABD", OpcodeMask: 4288740352, Opcode: 2124469248, Fields: []InsnField{
+		{"sz", 22, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2124469248, Generator: nil},
+	{Name: "FABD", OpcodeMask: 3214998528, Opcode: 782291968, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 782291968, Generator: nil},
+	{Name: "FABS (vector)", OpcodeMask: 3217030144, Opcode: 245430272, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 245430272, Generator: nil},
+	{Name: "FABS (scalar)", OpcodeMask: 4294966272, Opcode: 505462784, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 505462784, Generator: nil},
+	{Name: "FABS (scalar)", OpcodeMask: 4294966272, Opcode: 509657088, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 509657088, Generator: nil},
+	{Name: "FACGE", OpcodeMask: 4288740352, Opcode: 2116086784, Fields: []InsnField{
+		{"sz", 22, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2116086784, Generator: nil},
+	{Name: "FACGE", OpcodeMask: 3214998528, Opcode: 773909504, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773909504, Generator: nil},
+	{Name: "FACGT", OpcodeMask: 4288740352, Opcode: 2124475392, Fields: []InsnField{
+		{"sz", 22, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2124475392, Generator: nil},
+	{Name: "FACGT", OpcodeMask: 3214998528, Opcode: 782298112, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 782298112, Generator: nil},
+	{Name: "FADD (vector)", OpcodeMask: 3214998528, Opcode: 237032448, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 237032448, Generator: nil},
+	{Name: "FADD (scalar)", OpcodeMask: 4292934656, Opcode: 505423872, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 505423872, Generator: nil},
+	{Name: "FADD (scalar)", OpcodeMask: 4292934656, Opcode: 509618176, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 509618176, Generator: nil},
+	{Name: "FADDP (scalar)", OpcodeMask: 4290771968, Opcode: 2117130240, Fields: []InsnField{
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2117130240, Generator: nil},
+	{Name: "FADDP (vector)", OpcodeMask: 3214998528, Opcode: 773903360, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773903360, Generator: nil},
+	{Name: "FCCMP", OpcodeMask: 4292873232, Opcode: 505414656, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"cond", 15, 4},
+		{"Rn", 9, 5},
+		{"nzcv", 3, 4},
+	}, AsUInt32: 505414656, Generator: nil},
+	{Name: "FCCMP", OpcodeMask: 4292873232, Opcode: 509608960, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"cond", 15, 4},
+		{"Rn", 9, 5},
+		{"nzcv", 3, 4},
+	}, AsUInt32: 509608960, Generator: nil},
+	{Name: "FCCMPE", OpcodeMask: 4292873232, Opcode: 505414672, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"cond", 15, 4},
+		{"Rn", 9, 5},
+		{"nzcv", 3, 4},
+	}, AsUInt32: 505414672, Generator: nil},
+	{Name: "FCCMPE", OpcodeMask: 4292873232, Opcode: 509608976, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"cond", 15, 4},
+		{"Rn", 9, 5},
+		{"nzcv", 3, 4},
+	}, AsUInt32: 509608976, Generator: nil},
+	{Name: "FCMEQ (register)", OpcodeMask: 4288740352, Opcode: 1579213824, Fields: []InsnField{
+		{"sz", 22, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1579213824, Generator: nil},
+	{Name: "FCMEQ (register)", OpcodeMask: 3214998528, Opcode: 237036544, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 237036544, Generator: nil},
+	{Name: "FCMEQ (zero)", OpcodeMask: 4290771968, Opcode: 1587599360, Fields: []InsnField{
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1587599360, Generator: nil},
+	{Name: "FCMEQ (zero)", OpcodeMask: 3217030144, Opcode: 245422080, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 245422080, Generator: nil},
+	{Name: "FCMGE (register)", OpcodeMask: 4288740352, Opcode: 2116084736, Fields: []InsnField{
+		{"sz", 22, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2116084736, Generator: nil},
+	{Name: "FCMGE (register)", OpcodeMask: 3214998528, Opcode: 773907456, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773907456, Generator: nil},
+	{Name: "FCMGE (zero)", OpcodeMask: 4290771968, Opcode: 2124466176, Fields: []InsnField{
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2124466176, Generator: nil},
+	{Name: "FCMGE (zero)", OpcodeMask: 3217030144, Opcode: 782288896, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 782288896, Generator: nil},
+	{Name: "FCMGT (register)", OpcodeMask: 4288740352, Opcode: 2124473344, Fields: []InsnField{
+		{"sz", 22, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2124473344, Generator: nil},
+	{Name: "FCMGT (register)", OpcodeMask: 3214998528, Opcode: 782296064, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 782296064, Generator: nil},
+	{Name: "FCMGT (zero)", OpcodeMask: 4290771968, Opcode: 1587595264, Fields: []InsnField{
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1587595264, Generator: nil},
+	{Name: "FCMGT (zero)", OpcodeMask: 3217030144, Opcode: 245417984, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 245417984, Generator: nil},
+	{Name: "FCMLE (zero)", OpcodeMask: 4290771968, Opcode: 2124470272, Fields: []InsnField{
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2124470272, Generator: nil},
+	{Name: "FCMLE (zero)", OpcodeMask: 3217030144, Opcode: 782292992, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 782292992, Generator: nil},
+	{Name: "FCMLT (zero)", OpcodeMask: 4290771968, Opcode: 1587603456, Fields: []InsnField{
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1587603456, Generator: nil},
+	{Name: "FCMLT (zero)", OpcodeMask: 3217030144, Opcode: 245426176, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 245426176, Generator: nil},
+	{Name: "FCMP", OpcodeMask: 4292934687, Opcode: 505421824, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+	}, AsUInt32: 505421824, Generator: nil},
+	{Name: "FCMP", OpcodeMask: 4292934687, Opcode: 505421832, Fields: []InsnField{
+		{"Rn", 9, 5},
+	}, AsUInt32: 505421832, Generator: nil},
+	{Name: "FCMP", OpcodeMask: 4292934687, Opcode: 509616128, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+	}, AsUInt32: 509616128, Generator: nil},
+	{Name: "FCMP", OpcodeMask: 4292934687, Opcode: 509616136, Fields: []InsnField{
+		{"Rn", 9, 5},
+	}, AsUInt32: 509616136, Generator: nil},
+	{Name: "FCMPE", OpcodeMask: 4292934687, Opcode: 505421840, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+	}, AsUInt32: 505421840, Generator: nil},
+	{Name: "FCMPE", OpcodeMask: 4292934687, Opcode: 505421848, Fields: []InsnField{
+		{"Rn", 9, 5},
+	}, AsUInt32: 505421848, Generator: nil},
+	{Name: "FCMPE", OpcodeMask: 4292934687, Opcode: 509616144, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+	}, AsUInt32: 509616144, Generator: nil},
+	{Name: "FCMPE", OpcodeMask: 4292934687, Opcode: 509616152, Fields: []InsnField{
+		{"Rn", 9, 5},
+	}, AsUInt32: 509616152, Generator: nil},
+	{Name: "FCSEL", OpcodeMask: 4292873216, Opcode: 505416704, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"cond", 15, 4},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 505416704, Generator: nil},
+	{Name: "FCSEL", OpcodeMask: 4292873216, Opcode: 509611008, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"cond", 15, 4},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 509611008, Generator: nil},
+	{Name: "FCVT", OpcodeMask: 4294966272, Opcode: 518144000, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 518144000, Generator: nil},
+	{Name: "FCVT", OpcodeMask: 4294966272, Opcode: 518176768, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 518176768, Generator: nil},
+	{Name: "FCVT", OpcodeMask: 4294966272, Opcode: 505659392, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 505659392, Generator: nil},
+	{Name: "FCVT", OpcodeMask: 4294966272, Opcode: 505593856, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 505593856, Generator: nil},
+	{Name: "FCVT", OpcodeMask: 4294966272, Opcode: 509853696, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 509853696, Generator: nil},
+	{Name: "FCVT", OpcodeMask: 4294966272, Opcode: 509755392, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 509755392, Generator: nil},
+	{Name: "FCVTAS (vector)", OpcodeMask: 4290771968, Opcode: 1579272192, Fields: []InsnField{
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1579272192, Generator: nil},
+	{Name: "FCVTAS (vector)", OpcodeMask: 3217030144, Opcode: 237094912, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 237094912, Generator: nil},
+	{Name: "FCVTAS (scalar)", OpcodeMask: 4294966272, Opcode: 505675776, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 505675776, Generator: nil},
+	{Name: "FCVTAS (scalar)", OpcodeMask: 4294966272, Opcode: 2653159424, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2653159424, Generator: nil},
+	{Name: "FCVTAS (scalar)", OpcodeMask: 4294966272, Opcode: 509870080, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 509870080, Generator: nil},
+	{Name: "FCVTAS (scalar)", OpcodeMask: 4294966272, Opcode: 2657353728, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2657353728, Generator: nil},
+	{Name: "FCVTAU (vector)", OpcodeMask: 4290771968, Opcode: 2116143104, Fields: []InsnField{
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2116143104, Generator: nil},
+	{Name: "FCVTAU (vector)", OpcodeMask: 3217030144, Opcode: 773965824, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773965824, Generator: nil},
+	{Name: "FCVTAU (scalar)", OpcodeMask: 4294966272, Opcode: 505741312, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 505741312, Generator: nil},
+	{Name: "FCVTAU (scalar)", OpcodeMask: 4294966272, Opcode: 2653224960, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2653224960, Generator: nil},
+	{Name: "FCVTAU (scalar)", OpcodeMask: 4294966272, Opcode: 509935616, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 509935616, Generator: nil},
+	{Name: "FCVTAU (scalar)", OpcodeMask: 4294966272, Opcode: 2657419264, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2657419264, Generator: nil},
+	{Name: "FCVTL, FCVTL2", OpcodeMask: 4290771968, Opcode: 237074432, Fields: []InsnField{
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 237074432, Generator: nil},
+	{Name: "FCVTL, FCVTL2", OpcodeMask: 4290771968, Opcode: 1310816256, Fields: []InsnField{
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1310816256, Generator: nil},
+	{Name: "FCVTMS (vector)", OpcodeMask: 4290771968, Opcode: 1579268096, Fields: []InsnField{
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1579268096, Generator: nil},
+	{Name: "FCVTMS (vector)", OpcodeMask: 3217030144, Opcode: 237090816, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 237090816, Generator: nil},
+	{Name: "FCVTMS (scalar)", OpcodeMask: 4294966272, Opcode: 506462208, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 506462208, Generator: nil},
+	{Name: "FCVTMS (scalar)", OpcodeMask: 4294966272, Opcode: 2653945856, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2653945856, Generator: nil},
+	{Name: "FCVTMS (scalar)", OpcodeMask: 4294966272, Opcode: 510656512, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 510656512, Generator: nil},
+	{Name: "FCVTMS (scalar)", OpcodeMask: 4294966272, Opcode: 2658140160, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2658140160, Generator: nil},
+	{Name: "FCVTMU (vector)", OpcodeMask: 4290771968, Opcode: 2116139008, Fields: []InsnField{
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2116139008, Generator: nil},
+	{Name: "FCVTMU (vector)", OpcodeMask: 3217030144, Opcode: 773961728, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773961728, Generator: nil},
+	{Name: "FCVTMU (scalar)", OpcodeMask: 4294966272, Opcode: 506527744, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 506527744, Generator: nil},
+	{Name: "FCVTMU (scalar)", OpcodeMask: 4294966272, Opcode: 2654011392, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2654011392, Generator: nil},
+	{Name: "FCVTMU (scalar)", OpcodeMask: 4294966272, Opcode: 510722048, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 510722048, Generator: nil},
+	{Name: "FCVTMU (scalar)", OpcodeMask: 4294966272, Opcode: 2658205696, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2658205696, Generator: nil},
+	{Name: "FCVTN, FCVTN2", OpcodeMask: 4290771968, Opcode: 237070336, Fields: []InsnField{
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 237070336, Generator: nil},
+	{Name: "FCVTN, FCVTN2", OpcodeMask: 4290771968, Opcode: 1310812160, Fields: []InsnField{
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1310812160, Generator: nil},
+	{Name: "FCVTNS (vector)", OpcodeMask: 4290771968, Opcode: 1579264000, Fields: []InsnField{
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1579264000, Generator: nil},
+	{Name: "FCVTNS (vector)", OpcodeMask: 3217030144, Opcode: 237086720, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 237086720, Generator: nil},
+	{Name: "FCVTNS (scalar)", OpcodeMask: 4294966272, Opcode: 505413632, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 505413632, Generator: nil},
+	{Name: "FCVTNS (scalar)", OpcodeMask: 4294966272, Opcode: 2652897280, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2652897280, Generator: nil},
+	{Name: "FCVTNS (scalar)", OpcodeMask: 4294966272, Opcode: 509607936, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 509607936, Generator: nil},
+	{Name: "FCVTNS (scalar)", OpcodeMask: 4294966272, Opcode: 2657091584, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2657091584, Generator: nil},
+	{Name: "FCVTNU (vector)", OpcodeMask: 4290771968, Opcode: 2116134912, Fields: []InsnField{
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2116134912, Generator: nil},
+	{Name: "FCVTNU (vector)", OpcodeMask: 3217030144, Opcode: 773957632, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773957632, Generator: nil},
+	{Name: "FCVTNU (scalar)", OpcodeMask: 4294966272, Opcode: 505479168, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 505479168, Generator: nil},
+	{Name: "FCVTNU (scalar)", OpcodeMask: 4294966272, Opcode: 2652962816, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2652962816, Generator: nil},
+	{Name: "FCVTNU (scalar)", OpcodeMask: 4294966272, Opcode: 509673472, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 509673472, Generator: nil},
+	{Name: "FCVTNU (scalar)", OpcodeMask: 4294966272, Opcode: 2657157120, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2657157120, Generator: nil},
+	{Name: "FCVTPS (vector)", OpcodeMask: 4290771968, Opcode: 1587652608, Fields: []InsnField{
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1587652608, Generator: nil},
+	{Name: "FCVTPS (vector)", OpcodeMask: 3217030144, Opcode: 245475328, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 245475328, Generator: nil},
+	{Name: "FCVTPS (scalar)", OpcodeMask: 4294966272, Opcode: 505937920, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 505937920, Generator: nil},
+	{Name: "FCVTPS (scalar)", OpcodeMask: 4294966272, Opcode: 2653421568, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2653421568, Generator: nil},
+	{Name: "FCVTPS (scalar)", OpcodeMask: 4294966272, Opcode: 510132224, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 510132224, Generator: nil},
+	{Name: "FCVTPS (scalar)", OpcodeMask: 4294966272, Opcode: 2657615872, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2657615872, Generator: nil},
+	{Name: "FCVTPU (vector)", OpcodeMask: 4290771968, Opcode: 2124523520, Fields: []InsnField{
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2124523520, Generator: nil},
+	{Name: "FCVTPU (vector)", OpcodeMask: 3217030144, Opcode: 782346240, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 782346240, Generator: nil},
+	{Name: "FCVTPU (scalar)", OpcodeMask: 4294966272, Opcode: 506003456, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 506003456, Generator: nil},
+	{Name: "FCVTPU (scalar)", OpcodeMask: 4294966272, Opcode: 2653487104, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2653487104, Generator: nil},
+	{Name: "FCVTPU (scalar)", OpcodeMask: 4294966272, Opcode: 510197760, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 510197760, Generator: nil},
+	{Name: "FCVTPU (scalar)", OpcodeMask: 4294966272, Opcode: 2657681408, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2657681408, Generator: nil},
+	{Name: "FCVTXN, FCVTXN2", OpcodeMask: 4290771968, Opcode: 2116118528, Fields: []InsnField{
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2116118528, Generator: nil},
+	{Name: "FCVTXN, FCVTXN2", OpcodeMask: 4290771968, Opcode: 773941248, Fields: []InsnField{
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773941248, Generator: nil},
+	{Name: "FCVTXN, FCVTXN2", OpcodeMask: 4290771968, Opcode: 1847683072, Fields: []InsnField{
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1847683072, Generator: nil},
+	{Name: "FCVTZS (vector, fixed-point)", OpcodeMask: 4286643200, Opcode: 1593900032, Fields: []InsnField{
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1593900032, Generator: nil},
+	{Name: "FCVTZS (vector, fixed-point)", OpcodeMask: 3212901376, Opcode: 251722752, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 251722752, Generator: nil},
+	{Name: "FCVTZS (vector, integer)", OpcodeMask: 4290771968, Opcode: 1587656704, Fields: []InsnField{
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1587656704, Generator: nil},
+	{Name: "FCVTZS (vector, integer)", OpcodeMask: 3217030144, Opcode: 245479424, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 245479424, Generator: nil},
+	{Name: "FCVTZS (scalar, fixed-point)", OpcodeMask: 4294901760, Opcode: 504889344, Fields: []InsnField{
+		{"scale", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 504889344, Generator: nil},
+	{Name: "FCVTZS (scalar, fixed-point)", OpcodeMask: 4294901760, Opcode: 2652372992, Fields: []InsnField{
+		{"scale", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2652372992, Generator: nil},
+	{Name: "FCVTZS (scalar, fixed-point)", OpcodeMask: 4294901760, Opcode: 509083648, Fields: []InsnField{
+		{"scale", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 509083648, Generator: nil},
+	{Name: "FCVTZS (scalar, fixed-point)", OpcodeMask: 4294901760, Opcode: 2656567296, Fields: []InsnField{
+		{"scale", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2656567296, Generator: nil},
+	{Name: "FCVTZS (scalar, integer)", OpcodeMask: 4294966272, Opcode: 506986496, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 506986496, Generator: nil},
+	{Name: "FCVTZS (scalar, integer)", OpcodeMask: 4294966272, Opcode: 2654470144, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2654470144, Generator: nil},
+	{Name: "FCVTZS (scalar, integer)", OpcodeMask: 4294966272, Opcode: 511180800, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 511180800, Generator: nil},
+	{Name: "FCVTZS (scalar, integer)", OpcodeMask: 4294966272, Opcode: 2658664448, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2658664448, Generator: nil},
+	{Name: "FCVTZU (vector, fixed-point)", OpcodeMask: 4286643200, Opcode: 2130770944, Fields: []InsnField{
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2130770944, Generator: nil},
+	{Name: "FCVTZU (vector, fixed-point)", OpcodeMask: 3212901376, Opcode: 788593664, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 788593664, Generator: nil},
+	{Name: "FCVTZU (vector, integer)", OpcodeMask: 4290771968, Opcode: 2124527616, Fields: []InsnField{
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2124527616, Generator: nil},
+	{Name: "FCVTZU (vector, integer)", OpcodeMask: 3217030144, Opcode: 782350336, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 782350336, Generator: nil},
+	{Name: "FCVTZU (scalar, fixed-point)", OpcodeMask: 4294901760, Opcode: 504954880, Fields: []InsnField{
+		{"scale", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 504954880, Generator: nil},
+	{Name: "FCVTZU (scalar, fixed-point)", OpcodeMask: 4294901760, Opcode: 2652438528, Fields: []InsnField{
+		{"scale", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2652438528, Generator: nil},
+	{Name: "FCVTZU (scalar, fixed-point)", OpcodeMask: 4294901760, Opcode: 509149184, Fields: []InsnField{
+		{"scale", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 509149184, Generator: nil},
+	{Name: "FCVTZU (scalar, fixed-point)", OpcodeMask: 4294901760, Opcode: 2656632832, Fields: []InsnField{
+		{"scale", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2656632832, Generator: nil},
+	{Name: "FCVTZU (scalar, integer)", OpcodeMask: 4294966272, Opcode: 507052032, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 507052032, Generator: nil},
+	{Name: "FCVTZU (scalar, integer)", OpcodeMask: 4294966272, Opcode: 2654535680, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2654535680, Generator: nil},
+	{Name: "FCVTZU (scalar, integer)", OpcodeMask: 4294966272, Opcode: 511246336, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 511246336, Generator: nil},
+	{Name: "FCVTZU (scalar, integer)", OpcodeMask: 4294966272, Opcode: 2658729984, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2658729984, Generator: nil},
+	{Name: "FDIV (vector)", OpcodeMask: 3214998528, Opcode: 773913600, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773913600, Generator: nil},
+	{Name: "FDIV (scalar)", OpcodeMask: 4292934656, Opcode: 505419776, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 505419776, Generator: nil},
+	{Name: "FDIV (scalar)", OpcodeMask: 4292934656, Opcode: 509614080, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 509614080, Generator: nil},
+	{Name: "FMADD", OpcodeMask: 4292902912, Opcode: 520093696, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Ra", 14, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 520093696, Generator: nil},
+	{Name: "FMADD", OpcodeMask: 4292902912, Opcode: 524288000, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Ra", 14, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 524288000, Generator: nil},
+	{Name: "FMAX (vector)", OpcodeMask: 3214998528, Opcode: 237040640, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 237040640, Generator: nil},
+	{Name: "FMAX (scalar)", OpcodeMask: 4292934656, Opcode: 505432064, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 505432064, Generator: nil},
+	{Name: "FMAX (scalar)", OpcodeMask: 4292934656, Opcode: 509626368, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 509626368, Generator: nil},
+	{Name: "FMAXNM (vector)", OpcodeMask: 3214998528, Opcode: 237028352, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 237028352, Generator: nil},
+	{Name: "FMAXNM (scalar)", OpcodeMask: 4292934656, Opcode: 505440256, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 505440256, Generator: nil},
+	{Name: "FMAXNM (scalar)", OpcodeMask: 4292934656, Opcode: 509634560, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 509634560, Generator: nil},
+	{Name: "FMAXNMP (scalar)", OpcodeMask: 4290771968, Opcode: 2117126144, Fields: []InsnField{
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2117126144, Generator: nil},
+	{Name: "FMAXNMP (vector)", OpcodeMask: 3214998528, Opcode: 773899264, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773899264, Generator: nil},
+	{Name: "FMAXNMV", OpcodeMask: 3217030144, Opcode: 774948864, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 774948864, Generator: nil},
+	{Name: "FMAXP (scalar)", OpcodeMask: 4290771968, Opcode: 2117138432, Fields: []InsnField{
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2117138432, Generator: nil},
+	{Name: "FMAXP (vector)", OpcodeMask: 3214998528, Opcode: 773911552, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773911552, Generator: nil},
+	{Name: "FMAXV", OpcodeMask: 3217030144, Opcode: 774961152, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 774961152, Generator: nil},
+	{Name: "FMIN (vector)", OpcodeMask: 3214998528, Opcode: 245429248, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 245429248, Generator: nil},
+	{Name: "FMIN (scalar)", OpcodeMask: 4292934656, Opcode: 505436160, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 505436160, Generator: nil},
+	{Name: "FMIN (scalar)", OpcodeMask: 4292934656, Opcode: 509630464, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 509630464, Generator: nil},
+	{Name: "FMINNM (vector)", OpcodeMask: 3214998528, Opcode: 245416960, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 245416960, Generator: nil},
+	{Name: "FMINNM (scalar)", OpcodeMask: 4292934656, Opcode: 505444352, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 505444352, Generator: nil},
+	{Name: "FMINNM (scalar)", OpcodeMask: 4292934656, Opcode: 509638656, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 509638656, Generator: nil},
+	{Name: "FMINNMP (scalar)", OpcodeMask: 4290771968, Opcode: 2125514752, Fields: []InsnField{
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2125514752, Generator: nil},
+	{Name: "FMINNMP (vector)", OpcodeMask: 3214998528, Opcode: 782287872, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 782287872, Generator: nil},
+	{Name: "FMINNMV", OpcodeMask: 3217030144, Opcode: 783337472, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 783337472, Generator: nil},
+	{Name: "FMINP (scalar)", OpcodeMask: 4290771968, Opcode: 2125527040, Fields: []InsnField{
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2125527040, Generator: nil},
+	{Name: "FMINP (vector)", OpcodeMask: 3214998528, Opcode: 782300160, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 782300160, Generator: nil},
+	{Name: "FMINV", OpcodeMask: 3217030144, Opcode: 783349760, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 783349760, Generator: nil},
+	{Name: "FMLA (by element)", OpcodeMask: 4286641152, Opcode: 1602228224, Fields: []InsnField{
+		{"sz", 22, 1},
+		{"L", 21, 1},
+		{"M", 20, 1},
+		{"Rm", 19, 4},
+		{"H", 11, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1602228224, Generator: nil},
+	{Name: "FMLA (by element)", OpcodeMask: 3212899328, Opcode: 260050944, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"L", 21, 1},
+		{"M", 20, 1},
+		{"Rm", 19, 4},
+		{"H", 11, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 260050944, Generator: nil},
+	{Name: "FMLA (vector)", OpcodeMask: 3214998528, Opcode: 237030400, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 237030400, Generator: nil},
+	{Name: "FMLS (by element)", OpcodeMask: 4286641152, Opcode: 1602244608, Fields: []InsnField{
+		{"sz", 22, 1},
+		{"L", 21, 1},
+		{"M", 20, 1},
+		{"Rm", 19, 4},
+		{"H", 11, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1602244608, Generator: nil},
+	{Name: "FMLS (by element)", OpcodeMask: 3212899328, Opcode: 260067328, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"L", 21, 1},
+		{"M", 20, 1},
+		{"Rm", 19, 4},
+		{"H", 11, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 260067328, Generator: nil},
+	{Name: "FMLS (vector)", OpcodeMask: 3214998528, Opcode: 245419008, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 245419008, Generator: nil},
+	{Name: "FMOV (vector, immediate)", OpcodeMask: 3220765696, Opcode: 251720704, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"a", 18, 1},
+		{"b", 17, 1},
+		{"c", 16, 1},
+		{"d", 9, 1},
+		{"e", 8, 1},
+		{"f", 7, 1},
+		{"g", 6, 1},
+		{"h", 5, 1},
+		{"Rd", 4, 5},
+	}, AsUInt32: 251720704, Generator: nil},
+	{Name: "FMOV (vector, immediate)", OpcodeMask: 4294507520, Opcode: 1862333440, Fields: []InsnField{
+		{"a", 18, 1},
+		{"b", 17, 1},
+		{"c", 16, 1},
+		{"d", 9, 1},
+		{"e", 8, 1},
+		{"f", 7, 1},
+		{"g", 6, 1},
+		{"h", 5, 1},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1862333440, Generator: nil},
+	{Name: "FMOV (register)", OpcodeMask: 4294966272, Opcode: 505430016, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 505430016, Generator: nil},
+	{Name: "FMOV (register)", OpcodeMask: 4294966272, Opcode: 509624320, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 509624320, Generator: nil},
+	{Name: "FMOV (general)", OpcodeMask: 4294966272, Opcode: 505872384, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 505872384, Generator: nil},
+	{Name: "FMOV (general)", OpcodeMask: 4294966272, Opcode: 505806848, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 505806848, Generator: nil},
+	{Name: "FMOV (general)", OpcodeMask: 4294966272, Opcode: 2657550336, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2657550336, Generator: nil},
+	{Name: "FMOV (general)", OpcodeMask: 4294966272, Opcode: 2662268928, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2662268928, Generator: nil},
+	{Name: "FMOV (general)", OpcodeMask: 4294966272, Opcode: 2657484800, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2657484800, Generator: nil},
+	{Name: "FMOV (general)", OpcodeMask: 4294966272, Opcode: 2662203392, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2662203392, Generator: nil},
+	{Name: "FMOV (scalar, immediate)", OpcodeMask: 4292878304, Opcode: 505417728, Fields: []InsnField{
+		{"imm8", 20, 8},
+		{"Rd", 4, 5},
+	}, AsUInt32: 505417728, Generator: nil},
+	{Name: "FMOV (scalar, immediate)", OpcodeMask: 4292878304, Opcode: 509612032, Fields: []InsnField{
+		{"imm8", 20, 8},
+		{"Rd", 4, 5},
+	}, AsUInt32: 509612032, Generator: nil},
+	{Name: "FMSUB", OpcodeMask: 4292902912, Opcode: 520126464, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Ra", 14, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 520126464, Generator: nil},
+	{Name: "FMSUB", OpcodeMask: 4292902912, Opcode: 524320768, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Ra", 14, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 524320768, Generator: nil},
+	{Name: "FMUL (by element)", OpcodeMask: 4286641152, Opcode: 1602260992, Fields: []InsnField{
+		{"sz", 22, 1},
+		{"L", 21, 1},
+		{"M", 20, 1},
+		{"Rm", 19, 4},
+		{"H", 11, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1602260992, Generator: nil},
+	{Name: "FMUL (by element)", OpcodeMask: 3212899328, Opcode: 260083712, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"L", 21, 1},
+		{"M", 20, 1},
+		{"Rm", 19, 4},
+		{"H", 11, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 260083712, Generator: nil},
+	{Name: "FMUL (vector)", OpcodeMask: 3214998528, Opcode: 773905408, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773905408, Generator: nil},
+	{Name: "FMUL (scalar)", OpcodeMask: 4292934656, Opcode: 505415680, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 505415680, Generator: nil},
+	{Name: "FMUL (scalar)", OpcodeMask: 4292934656, Opcode: 509609984, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 509609984, Generator: nil},
+	{Name: "FMULX (by element)", OpcodeMask: 4286641152, Opcode: 2139131904, Fields: []InsnField{
+		{"sz", 22, 1},
+		{"L", 21, 1},
+		{"M", 20, 1},
+		{"Rm", 19, 4},
+		{"H", 11, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2139131904, Generator: nil},
+	{Name: "FMULX (by element)", OpcodeMask: 3212899328, Opcode: 796954624, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"L", 21, 1},
+		{"M", 20, 1},
+		{"Rm", 19, 4},
+		{"H", 11, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 796954624, Generator: nil},
+	{Name: "FMULX", OpcodeMask: 4288740352, Opcode: 1579211776, Fields: []InsnField{
+		{"sz", 22, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1579211776, Generator: nil},
+	{Name: "FMULX", OpcodeMask: 3214998528, Opcode: 237034496, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 237034496, Generator: nil},
+	{Name: "FNEG (vector)", OpcodeMask: 3217030144, Opcode: 782301184, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 782301184, Generator: nil},
+	{Name: "FNEG (scalar)", OpcodeMask: 4294966272, Opcode: 505495552, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 505495552, Generator: nil},
+	{Name: "FNEG (scalar)", OpcodeMask: 4294966272, Opcode: 509689856, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 509689856, Generator: nil},
+	{Name: "FNMADD", OpcodeMask: 4292902912, Opcode: 522190848, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Ra", 14, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 522190848, Generator: nil},
+	{Name: "FNMADD", OpcodeMask: 4292902912, Opcode: 526385152, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Ra", 14, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 526385152, Generator: nil},
+	{Name: "FNMSUB", OpcodeMask: 4292902912, Opcode: 522223616, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Ra", 14, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 522223616, Generator: nil},
+	{Name: "FNMSUB", OpcodeMask: 4292902912, Opcode: 526417920, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Ra", 14, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 526417920, Generator: nil},
+	{Name: "FNMUL (scalar)", OpcodeMask: 4292934656, Opcode: 505448448, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 505448448, Generator: nil},
+	{Name: "FNMUL (scalar)", OpcodeMask: 4292934656, Opcode: 509642752, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 509642752, Generator: nil},
+	{Name: "FRECPE", OpcodeMask: 4290771968, Opcode: 1587664896, Fields: []InsnField{
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1587664896, Generator: nil},
+	{Name: "FRECPE", OpcodeMask: 3217030144, Opcode: 245487616, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 245487616, Generator: nil},
+	{Name: "FRECPS", OpcodeMask: 4288740352, Opcode: 1579219968, Fields: []InsnField{
+		{"sz", 22, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1579219968, Generator: nil},
+	{Name: "FRECPS", OpcodeMask: 3214998528, Opcode: 237042688, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 237042688, Generator: nil},
+	{Name: "FRECPX", OpcodeMask: 4290771968, Opcode: 1587673088, Fields: []InsnField{
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1587673088, Generator: nil},
+	{Name: "FRINTA (vector)", OpcodeMask: 3217030144, Opcode: 773949440, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773949440, Generator: nil},
+	{Name: "FRINTA (scalar)", OpcodeMask: 4294966272, Opcode: 505823232, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 505823232, Generator: nil},
+	{Name: "FRINTA (scalar)", OpcodeMask: 4294966272, Opcode: 510017536, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 510017536, Generator: nil},
+	{Name: "FRINTI (vector)", OpcodeMask: 3217030144, Opcode: 782342144, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 782342144, Generator: nil},
+	{Name: "FRINTI (scalar)", OpcodeMask: 4294966272, Opcode: 505921536, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 505921536, Generator: nil},
+	{Name: "FRINTI (scalar)", OpcodeMask: 4294966272, Opcode: 510115840, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 510115840, Generator: nil},
+	{Name: "FRINTM (vector)", OpcodeMask: 3217030144, Opcode: 237082624, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 237082624, Generator: nil},
+	{Name: "FRINTM (scalar)", OpcodeMask: 4294966272, Opcode: 505757696, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 505757696, Generator: nil},
+	{Name: "FRINTM (scalar)", OpcodeMask: 4294966272, Opcode: 509952000, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 509952000, Generator: nil},
+	{Name: "FRINTN (vector)", OpcodeMask: 3217030144, Opcode: 237078528, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 237078528, Generator: nil},
+	{Name: "FRINTN (scalar)", OpcodeMask: 4294966272, Opcode: 505692160, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 505692160, Generator: nil},
+	{Name: "FRINTN (scalar)", OpcodeMask: 4294966272, Opcode: 509886464, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 509886464, Generator: nil},
+	{Name: "FRINTP (vector)", OpcodeMask: 3217030144, Opcode: 245467136, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 245467136, Generator: nil},
+	{Name: "FRINTP (scalar)", OpcodeMask: 4294966272, Opcode: 505724928, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 505724928, Generator: nil},
+	{Name: "FRINTP (scalar)", OpcodeMask: 4294966272, Opcode: 509919232, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 509919232, Generator: nil},
+	{Name: "FRINTX (vector)", OpcodeMask: 3217030144, Opcode: 773953536, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773953536, Generator: nil},
+	{Name: "FRINTX (scalar)", OpcodeMask: 4294966272, Opcode: 505888768, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 505888768, Generator: nil},
+	{Name: "FRINTX (scalar)", OpcodeMask: 4294966272, Opcode: 510083072, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 510083072, Generator: nil},
+	{Name: "FRINTZ (vector)", OpcodeMask: 3217030144, Opcode: 245471232, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 245471232, Generator: nil},
+	{Name: "FRINTZ (scalar)", OpcodeMask: 4294966272, Opcode: 505790464, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 505790464, Generator: nil},
+	{Name: "FRINTZ (scalar)", OpcodeMask: 4294966272, Opcode: 509984768, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 509984768, Generator: nil},
+	{Name: "FRSQRTE", OpcodeMask: 4290771968, Opcode: 2124535808, Fields: []InsnField{
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2124535808, Generator: nil},
+	{Name: "FRSQRTE", OpcodeMask: 3217030144, Opcode: 782358528, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 782358528, Generator: nil},
+	{Name: "FRSQRTS", OpcodeMask: 4288740352, Opcode: 1587608576, Fields: []InsnField{
+		{"sz", 22, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1587608576, Generator: nil},
+	{Name: "FRSQRTS", OpcodeMask: 3214998528, Opcode: 245431296, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 245431296, Generator: nil},
+	{Name: "FSQRT (vector)", OpcodeMask: 3217030144, Opcode: 782366720, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 782366720, Generator: nil},
+	{Name: "FSQRT (scalar)", OpcodeMask: 4294966272, Opcode: 505528320, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 505528320, Generator: nil},
+	{Name: "FSQRT (scalar)", OpcodeMask: 4294966272, Opcode: 509722624, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 509722624, Generator: nil},
+	{Name: "FSUB (vector)", OpcodeMask: 3214998528, Opcode: 245421056, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 245421056, Generator: nil},
+	{Name: "FSUB (scalar)", OpcodeMask: 4292934656, Opcode: 505427968, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 505427968, Generator: nil},
+	{Name: "FSUB (scalar)", OpcodeMask: 4292934656, Opcode: 509622272, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 509622272, Generator: nil},
+	{Name: "INS (element)", OpcodeMask: 4292903936, Opcode: 1845494784, Fields: []InsnField{
+		{"imm5", 20, 5},
+		{"imm4", 14, 4},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1845494784, Generator: nil},
+	{Name: "INS (general)", OpcodeMask: 4292934656, Opcode: 1308630016, Fields: []InsnField{
+		{"imm5", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1308630016, Generator: nil},
+	{Name: "LD1 (multiple structures)", OpcodeMask: 3221221376, Opcode: 205549568, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 205549568, Generator: nil},
+	{Name: "LD1 (multiple structures)", OpcodeMask: 3221221376, Opcode: 205561856, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 205561856, Generator: nil},
+	{Name: "LD1 (multiple structures)", OpcodeMask: 3221221376, Opcode: 205545472, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 205545472, Generator: nil},
+	{Name: "LD1 (multiple structures)", OpcodeMask: 3221221376, Opcode: 205529088, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 205529088, Generator: nil},
+	{Name: "LD1 (multiple structures)", OpcodeMask: 3221221376, Opcode: 215969792, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 215969792, Generator: nil},
+	{Name: "LD1 (multiple structures)", OpcodeMask: 3219189760, Opcode: 213938176, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 213938176, Generator: nil},
+	{Name: "LD1 (multiple structures)", OpcodeMask: 3221221376, Opcode: 215982080, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 215982080, Generator: nil},
+	{Name: "LD1 (multiple structures)", OpcodeMask: 3219189760, Opcode: 213950464, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 213950464, Generator: nil},
+	{Name: "LD1 (multiple structures)", OpcodeMask: 3221221376, Opcode: 215965696, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 215965696, Generator: nil},
+	{Name: "LD1 (multiple structures)", OpcodeMask: 3219189760, Opcode: 213934080, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 213934080, Generator: nil},
+	{Name: "LD1 (multiple structures)", OpcodeMask: 3221221376, Opcode: 215949312, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 215949312, Generator: nil},
+	{Name: "LD1 (multiple structures)", OpcodeMask: 3219189760, Opcode: 213917696, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 213917696, Generator: nil},
+	{Name: "LD1 (single structure)", OpcodeMask: 3221217280, Opcode: 222298112, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"S", 12, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 222298112, Generator: nil},
+	{Name: "LD1 (single structure)", OpcodeMask: 3221217280, Opcode: 222314496, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"S", 12, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 222314496, Generator: nil},
+	{Name: "LD1 (single structure)", OpcodeMask: 3221220352, Opcode: 222330880, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"S", 12, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 222330880, Generator: nil},
+	{Name: "LD1 (single structure)", OpcodeMask: 3221224448, Opcode: 222331904, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 222331904, Generator: nil},
+	{Name: "LD1 (single structure)", OpcodeMask: 3221217280, Opcode: 232718336, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"S", 12, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 232718336, Generator: nil},
+	{Name: "LD1 (single structure)", OpcodeMask: 3219185664, Opcode: 230686720, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"S", 12, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 230686720, Generator: nil},
+	{Name: "LD1 (single structure)", OpcodeMask: 3221217280, Opcode: 232734720, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"S", 12, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 232734720, Generator: nil},
+	{Name: "LD1 (single structure)", OpcodeMask: 3219185664, Opcode: 230703104, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"S", 12, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 230703104, Generator: nil},
+	{Name: "LD1 (single structure)", OpcodeMask: 3221220352, Opcode: 232751104, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"S", 12, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 232751104, Generator: nil},
+	{Name: "LD1 (single structure)", OpcodeMask: 3219188736, Opcode: 230719488, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"S", 12, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 230719488, Generator: nil},
+	{Name: "LD1 (single structure)", OpcodeMask: 3221224448, Opcode: 232752128, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 232752128, Generator: nil},
+	{Name: "LD1 (single structure)", OpcodeMask: 3219192832, Opcode: 230720512, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 230720512, Generator: nil},
+	{Name: "LD1R", OpcodeMask: 3221221376, Opcode: 222347264, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 222347264, Generator: nil},
+	{Name: "LD1R", OpcodeMask: 3221221376, Opcode: 232767488, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 232767488, Generator: nil},
+	{Name: "LD1R", OpcodeMask: 3219189760, Opcode: 230735872, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 230735872, Generator: nil},
+	{Name: "LD2 (multiple structures)", OpcodeMask: 3221221376, Opcode: 205553664, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 205553664, Generator: nil},
+	{Name: "LD2 (multiple structures)", OpcodeMask: 3221221376, Opcode: 215973888, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 215973888, Generator: nil},
+	{Name: "LD2 (multiple structures)", OpcodeMask: 3219189760, Opcode: 213942272, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 213942272, Generator: nil},
+	{Name: "LD2 (single structure)", OpcodeMask: 3221217280, Opcode: 224395264, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"S", 12, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 224395264, Generator: nil},
+	{Name: "LD2 (single structure)", OpcodeMask: 3221217280, Opcode: 224411648, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"S", 12, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 224411648, Generator: nil},
+	{Name: "LD2 (single structure)", OpcodeMask: 3221220352, Opcode: 224428032, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"S", 12, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 224428032, Generator: nil},
+	{Name: "LD2 (single structure)", OpcodeMask: 3221224448, Opcode: 224429056, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 224429056, Generator: nil},
+	{Name: "LD2 (single structure)", OpcodeMask: 3221217280, Opcode: 234815488, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"S", 12, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 234815488, Generator: nil},
+	{Name: "LD2 (single structure)", OpcodeMask: 3219185664, Opcode: 232783872, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"S", 12, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 232783872, Generator: nil},
+	{Name: "LD2 (single structure)", OpcodeMask: 3221217280, Opcode: 234831872, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"S", 12, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 234831872, Generator: nil},
+	{Name: "LD2 (single structure)", OpcodeMask: 3219185664, Opcode: 232800256, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"S", 12, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 232800256, Generator: nil},
+	{Name: "LD2 (single structure)", OpcodeMask: 3221220352, Opcode: 234848256, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"S", 12, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 234848256, Generator: nil},
+	{Name: "LD2 (single structure)", OpcodeMask: 3219188736, Opcode: 232816640, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"S", 12, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 232816640, Generator: nil},
+	{Name: "LD2 (single structure)", OpcodeMask: 3221224448, Opcode: 234849280, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 234849280, Generator: nil},
+	{Name: "LD2 (single structure)", OpcodeMask: 3219192832, Opcode: 232817664, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 232817664, Generator: nil},
+	{Name: "LD2R", OpcodeMask: 3221221376, Opcode: 224444416, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 224444416, Generator: nil},
+	{Name: "LD2R", OpcodeMask: 3221221376, Opcode: 234864640, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 234864640, Generator: nil},
+	{Name: "LD2R", OpcodeMask: 3219189760, Opcode: 232833024, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 232833024, Generator: nil},
+	{Name: "LD3 (multiple structures)", OpcodeMask: 3221221376, Opcode: 205537280, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 205537280, Generator: nil},
+	{Name: "LD3 (multiple structures)", OpcodeMask: 3221221376, Opcode: 215957504, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 215957504, Generator: nil},
+	{Name: "LD3 (multiple structures)", OpcodeMask: 3219189760, Opcode: 213925888, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 213925888, Generator: nil},
+	{Name: "LD3 (single structure)", OpcodeMask: 3221217280, Opcode: 222306304, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"S", 12, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 222306304, Generator: nil},
+	{Name: "LD3 (single structure)", OpcodeMask: 3221217280, Opcode: 222322688, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"S", 12, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 222322688, Generator: nil},
+	{Name: "LD3 (single structure)", OpcodeMask: 3221220352, Opcode: 222339072, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"S", 12, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 222339072, Generator: nil},
+	{Name: "LD3 (single structure)", OpcodeMask: 3221224448, Opcode: 222340096, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 222340096, Generator: nil},
+	{Name: "LD3 (single structure)", OpcodeMask: 3221217280, Opcode: 232726528, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"S", 12, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 232726528, Generator: nil},
+	{Name: "LD3 (single structure)", OpcodeMask: 3219185664, Opcode: 230694912, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"S", 12, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 230694912, Generator: nil},
+	{Name: "LD3 (single structure)", OpcodeMask: 3221217280, Opcode: 232742912, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"S", 12, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 232742912, Generator: nil},
+	{Name: "LD3 (single structure)", OpcodeMask: 3219185664, Opcode: 230711296, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"S", 12, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 230711296, Generator: nil},
+	{Name: "LD3 (single structure)", OpcodeMask: 3221220352, Opcode: 232759296, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"S", 12, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 232759296, Generator: nil},
+	{Name: "LD3 (single structure)", OpcodeMask: 3219188736, Opcode: 230727680, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"S", 12, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 230727680, Generator: nil},
+	{Name: "LD3 (single structure)", OpcodeMask: 3221224448, Opcode: 232760320, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 232760320, Generator: nil},
+	{Name: "LD3 (single structure)", OpcodeMask: 3219192832, Opcode: 230728704, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 230728704, Generator: nil},
+	{Name: "LD3R", OpcodeMask: 3221221376, Opcode: 222355456, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 222355456, Generator: nil},
+	{Name: "LD3R", OpcodeMask: 3221221376, Opcode: 232775680, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 232775680, Generator: nil},
+	{Name: "LD3R", OpcodeMask: 3219189760, Opcode: 230744064, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 230744064, Generator: nil},
+	{Name: "LD4 (multiple structures)", OpcodeMask: 3221221376, Opcode: 205520896, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 205520896, Generator: nil},
+	{Name: "LD4 (multiple structures)", OpcodeMask: 3221221376, Opcode: 215941120, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 215941120, Generator: nil},
+	{Name: "LD4 (multiple structures)", OpcodeMask: 3219189760, Opcode: 213909504, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 213909504, Generator: nil},
+	{Name: "LD4 (single structure)", OpcodeMask: 3221217280, Opcode: 224403456, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"S", 12, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 224403456, Generator: nil},
+	{Name: "LD4 (single structure)", OpcodeMask: 3221217280, Opcode: 224419840, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"S", 12, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 224419840, Generator: nil},
+	{Name: "LD4 (single structure)", OpcodeMask: 3221220352, Opcode: 224436224, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"S", 12, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 224436224, Generator: nil},
+	{Name: "LD4 (single structure)", OpcodeMask: 3221224448, Opcode: 224437248, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 224437248, Generator: nil},
+	{Name: "LD4 (single structure)", OpcodeMask: 3221217280, Opcode: 234823680, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"S", 12, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 234823680, Generator: nil},
+	{Name: "LD4 (single structure)", OpcodeMask: 3219185664, Opcode: 232792064, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"S", 12, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 232792064, Generator: nil},
+	{Name: "LD4 (single structure)", OpcodeMask: 3221217280, Opcode: 234840064, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"S", 12, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 234840064, Generator: nil},
+	{Name: "LD4 (single structure)", OpcodeMask: 3219185664, Opcode: 232808448, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"S", 12, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 232808448, Generator: nil},
+	{Name: "LD4 (single structure)", OpcodeMask: 3221220352, Opcode: 234856448, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"S", 12, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 234856448, Generator: nil},
+	{Name: "LD4 (single structure)", OpcodeMask: 3219188736, Opcode: 232824832, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"S", 12, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 232824832, Generator: nil},
+	{Name: "LD4 (single structure)", OpcodeMask: 3221224448, Opcode: 234857472, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 234857472, Generator: nil},
+	{Name: "LD4 (single structure)", OpcodeMask: 3219192832, Opcode: 232825856, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 232825856, Generator: nil},
+	{Name: "LD4R", OpcodeMask: 3221221376, Opcode: 224452608, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 224452608, Generator: nil},
+	{Name: "LD4R", OpcodeMask: 3221221376, Opcode: 234872832, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 234872832, Generator: nil},
+	{Name: "LD4R", OpcodeMask: 3219189760, Opcode: 232841216, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 232841216, Generator: nil},
+	{Name: "LDNP (SIMD&FP)", OpcodeMask: 4290772992, Opcode: 742391808, Fields: []InsnField{
+		{"imm7", 21, 7},
+		{"Rt2", 14, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 742391808, Generator: nil},
+	{Name: "LDNP (SIMD&FP)", OpcodeMask: 4290772992, Opcode: 1816133632, Fields: []InsnField{
+		{"imm7", 21, 7},
+		{"Rt2", 14, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 1816133632, Generator: nil},
+	{Name: "LDNP (SIMD&FP)", OpcodeMask: 4290772992, Opcode: 2889875456, Fields: []InsnField{
+		{"imm7", 21, 7},
+		{"Rt2", 14, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2889875456, Generator: nil},
+	{Name: "LDP (SIMD&FP)", OpcodeMask: 4290772992, Opcode: 750780416, Fields: []InsnField{
+		{"imm7", 21, 7},
+		{"Rt2", 14, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 750780416, Generator: nil},
+	{Name: "LDP (SIMD&FP)", OpcodeMask: 4290772992, Opcode: 1824522240, Fields: []InsnField{
+		{"imm7", 21, 7},
+		{"Rt2", 14, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 1824522240, Generator: nil},
+	{Name: "LDP (SIMD&FP)", OpcodeMask: 4290772992, Opcode: 2898264064, Fields: []InsnField{
+		{"imm7", 21, 7},
+		{"Rt2", 14, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2898264064, Generator: nil},
+	{Name: "LDP (SIMD&FP)", OpcodeMask: 4290772992, Opcode: 767557632, Fields: []InsnField{
+		{"imm7", 21, 7},
+		{"Rt2", 14, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 767557632, Generator: nil},
+	{Name: "LDP (SIMD&FP)", OpcodeMask: 4290772992, Opcode: 1841299456, Fields: []InsnField{
+		{"imm7", 21, 7},
+		{"Rt2", 14, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 1841299456, Generator: nil},
+	{Name: "LDP (SIMD&FP)", OpcodeMask: 4290772992, Opcode: 2915041280, Fields: []InsnField{
+		{"imm7", 21, 7},
+		{"Rt2", 14, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2915041280, Generator: nil},
+	{Name: "LDP (SIMD&FP)", OpcodeMask: 4290772992, Opcode: 759169024, Fields: []InsnField{
+		{"imm7", 21, 7},
+		{"Rt2", 14, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 759169024, Generator: nil},
+	{Name: "LDP (SIMD&FP)", OpcodeMask: 4290772992, Opcode: 1832910848, Fields: []InsnField{
+		{"imm7", 21, 7},
+		{"Rt2", 14, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 1832910848, Generator: nil},
+	{Name: "LDP (SIMD&FP)", OpcodeMask: 4290772992, Opcode: 2906652672, Fields: []InsnField{
+		{"imm7", 21, 7},
+		{"Rt2", 14, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2906652672, Generator: nil},
+	{Name: "LDR (immediate, SIMD&FP)", OpcodeMask: 4292873216, Opcode: 1010828288, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 1010828288, Generator: nil},
+	{Name: "LDR (immediate, SIMD&FP)", OpcodeMask: 4292873216, Opcode: 2084570112, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2084570112, Generator: nil},
+	{Name: "LDR (immediate, SIMD&FP)", OpcodeMask: 4292873216, Opcode: 3158311936, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 3158311936, Generator: nil},
+	{Name: "LDR (immediate, SIMD&FP)", OpcodeMask: 4292873216, Opcode: 4232053760, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 4232053760, Generator: nil},
+	{Name: "LDR (immediate, SIMD&FP)", OpcodeMask: 4292873216, Opcode: 1019216896, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 1019216896, Generator: nil},
+	{Name: "LDR (immediate, SIMD&FP)", OpcodeMask: 4292873216, Opcode: 1010830336, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 1010830336, Generator: nil},
+	{Name: "LDR (immediate, SIMD&FP)", OpcodeMask: 4292873216, Opcode: 2084572160, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2084572160, Generator: nil},
+	{Name: "LDR (immediate, SIMD&FP)", OpcodeMask: 4292873216, Opcode: 3158313984, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 3158313984, Generator: nil},
+	{Name: "LDR (immediate, SIMD&FP)", OpcodeMask: 4292873216, Opcode: 4232055808, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 4232055808, Generator: nil},
+	{Name: "LDR (immediate, SIMD&FP)", OpcodeMask: 4292873216, Opcode: 1019218944, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 1019218944, Generator: nil},
+	{Name: "LDR (immediate, SIMD&FP)", OpcodeMask: 4290772992, Opcode: 1027604480, Fields: []InsnField{
+		{"imm12", 21, 12},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 1027604480, Generator: nil},
+	{Name: "LDR (immediate, SIMD&FP)", OpcodeMask: 4290772992, Opcode: 2101346304, Fields: []InsnField{
+		{"imm12", 21, 12},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2101346304, Generator: nil},
+	{Name: "LDR (immediate, SIMD&FP)", OpcodeMask: 4290772992, Opcode: 3175088128, Fields: []InsnField{
+		{"imm12", 21, 12},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 3175088128, Generator: nil},
+	{Name: "LDR (immediate, SIMD&FP)", OpcodeMask: 4290772992, Opcode: 4248829952, Fields: []InsnField{
+		{"imm12", 21, 12},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 4248829952, Generator: nil},
+	{Name: "LDR (immediate, SIMD&FP)", OpcodeMask: 4290772992, Opcode: 1035993088, Fields: []InsnField{
+		{"imm12", 21, 12},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 1035993088, Generator: nil},
+	{Name: "LDR (literal, SIMD&FP)", OpcodeMask: 4278190080, Opcode: 469762048, Fields: []InsnField{
+		{"imm19", 23, 19},
+		{"Rt", 4, 5},
+	}, AsUInt32: 469762048, Generator: nil},
+	{Name: "LDR (literal, SIMD&FP)", OpcodeMask: 4278190080, Opcode: 1543503872, Fields: []InsnField{
+		{"imm19", 23, 19},
+		{"Rt", 4, 5},
+	}, AsUInt32: 1543503872, Generator: nil},
+	{Name: "LDR (literal, SIMD&FP)", OpcodeMask: 4278190080, Opcode: 2617245696, Fields: []InsnField{
+		{"imm19", 23, 19},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2617245696, Generator: nil},
+	{Name: "LDR (register, SIMD&FP)", OpcodeMask: 4292873216, Opcode: 1012926464, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"option", 15, 3},
+		{"S", 12, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 1012926464, Generator: nil},
+	{Name: "LDR (register, SIMD&FP)", OpcodeMask: 4292930560, Opcode: 1012951040, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"S", 12, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 1012951040, Generator: nil},
+	{Name: "LDR (register, SIMD&FP)", OpcodeMask: 4292873216, Opcode: 2086668288, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"option", 15, 3},
+		{"S", 12, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2086668288, Generator: nil},
+	{Name: "LDR (register, SIMD&FP)", OpcodeMask: 4292873216, Opcode: 3160410112, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"option", 15, 3},
+		{"S", 12, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 3160410112, Generator: nil},
+	{Name: "LDR (register, SIMD&FP)", OpcodeMask: 4292873216, Opcode: 4234151936, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"option", 15, 3},
+		{"S", 12, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 4234151936, Generator: nil},
+	{Name: "LDR (register, SIMD&FP)", OpcodeMask: 4292873216, Opcode: 1021315072, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"option", 15, 3},
+		{"S", 12, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 1021315072, Generator: nil},
+	{Name: "LDUR (SIMD&FP)", OpcodeMask: 4292873216, Opcode: 1010827264, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 1010827264, Generator: nil},
+	{Name: "LDUR (SIMD&FP)", OpcodeMask: 4292873216, Opcode: 2084569088, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2084569088, Generator: nil},
+	{Name: "LDUR (SIMD&FP)", OpcodeMask: 4292873216, Opcode: 3158310912, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 3158310912, Generator: nil},
+	{Name: "LDUR (SIMD&FP)", OpcodeMask: 4292873216, Opcode: 4232052736, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 4232052736, Generator: nil},
+	{Name: "LDUR (SIMD&FP)", OpcodeMask: 4292873216, Opcode: 1019215872, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 1019215872, Generator: nil},
+	{Name: "MLA (by element)", OpcodeMask: 3204510720, Opcode: 788529152, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"L", 21, 1},
+		{"M", 20, 1},
+		{"Rm", 19, 4},
+		{"H", 11, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 788529152, Generator: nil},
+	{Name: "MLA (vector)", OpcodeMask: 3206609920, Opcode: 237016064, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 237016064, Generator: nil},
+	{Name: "MLS (by element)", OpcodeMask: 3204510720, Opcode: 788545536, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"L", 21, 1},
+		{"M", 20, 1},
+		{"Rm", 19, 4},
+		{"H", 11, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 788545536, Generator: nil},
+	{Name: "MLS (vector)", OpcodeMask: 3206609920, Opcode: 773886976, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773886976, Generator: nil},
+	{Name: "MOV (scalar)", OpcodeMask: 4292934656, Opcode: 1577059328, Fields: []InsnField{
+		{"imm5", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1577059328, Generator: nil},
+	{Name: "MOV (element)", OpcodeMask: 4292903936, Opcode: 1845494784, Fields: []InsnField{
+		{"imm5", 20, 5},
+		{"imm4", 14, 4},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1845494784, Generator: nil},
+	{Name: "MOV (from general)", OpcodeMask: 4292934656, Opcode: 1308630016, Fields: []InsnField{
+		{"imm5", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1308630016, Generator: nil},
+	{Name: "MOV (vector)", OpcodeMask: 3219192832, Opcode: 245373952, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 245373952, Generator: nil},
+	{Name: "MOV (to general)", OpcodeMask: 4292934656, Opcode: 234896384, Fields: []InsnField{
+		{"imm5", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 234896384, Generator: nil},
+	{Name: "MOV (to general)", OpcodeMask: 4292934656, Opcode: 1308638208, Fields: []InsnField{
+		{"imm5", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1308638208, Generator: nil},
+	{Name: "MOVI", OpcodeMask: 3220765696, Opcode: 251716608, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"a", 18, 1},
+		{"b", 17, 1},
+		{"c", 16, 1},
+		{"d", 9, 1},
+		{"e", 8, 1},
+		{"f", 7, 1},
+		{"g", 6, 1},
+		{"h", 5, 1},
+		{"Rd", 4, 5},
+	}, AsUInt32: 251716608, Generator: nil},
+	{Name: "MOVI", OpcodeMask: 3220704256, Opcode: 251659264, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"a", 18, 1},
+		{"b", 17, 1},
+		{"c", 16, 1},
+		{"cmode", 15, 4},
+		{"d", 9, 1},
+		{"e", 8, 1},
+		{"f", 7, 1},
+		{"g", 6, 1},
+		{"h", 5, 1},
+		{"Rd", 4, 5},
+	}, AsUInt32: 251659264, Generator: nil},
+	{Name: "MOVI", OpcodeMask: 3220704256, Opcode: 251659264, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"a", 18, 1},
+		{"b", 17, 1},
+		{"c", 16, 1},
+		{"cmode", 15, 4},
+		{"d", 9, 1},
+		{"e", 8, 1},
+		{"f", 7, 1},
+		{"g", 6, 1},
+		{"h", 5, 1},
+		{"Rd", 4, 5},
+	}, AsUInt32: 251659264, Generator: nil},
+	{Name: "MOVI", OpcodeMask: 3220704256, Opcode: 251659264, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"a", 18, 1},
+		{"b", 17, 1},
+		{"c", 16, 1},
+		{"cmode", 15, 4},
+		{"d", 9, 1},
+		{"e", 8, 1},
+		{"f", 7, 1},
+		{"g", 6, 1},
+		{"h", 5, 1},
+		{"Rd", 4, 5},
+	}, AsUInt32: 251659264, Generator: nil},
+	{Name: "MOVI", OpcodeMask: 4294507520, Opcode: 788587520, Fields: []InsnField{
+		{"a", 18, 1},
+		{"b", 17, 1},
+		{"c", 16, 1},
+		{"d", 9, 1},
+		{"e", 8, 1},
+		{"f", 7, 1},
+		{"g", 6, 1},
+		{"h", 5, 1},
+		{"Rd", 4, 5},
+	}, AsUInt32: 788587520, Generator: nil},
+	{Name: "MOVI", OpcodeMask: 4294507520, Opcode: 1862329344, Fields: []InsnField{
+		{"a", 18, 1},
+		{"b", 17, 1},
+		{"c", 16, 1},
+		{"d", 9, 1},
+		{"e", 8, 1},
+		{"f", 7, 1},
+		{"g", 6, 1},
+		{"h", 5, 1},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1862329344, Generator: nil},
+	{Name: "MUL (by element)", OpcodeMask: 3204510720, Opcode: 251691008, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"L", 21, 1},
+		{"M", 20, 1},
+		{"Rm", 19, 4},
+		{"H", 11, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 251691008, Generator: nil},
+	{Name: "MUL (vector)", OpcodeMask: 3206609920, Opcode: 237018112, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 237018112, Generator: nil},
+	{Name: "MVN", OpcodeMask: 3221224448, Opcode: 773871616, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773871616, Generator: nil},
+	{Name: "MVNI", OpcodeMask: 3220704256, Opcode: 788530176, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"a", 18, 1},
+		{"b", 17, 1},
+		{"c", 16, 1},
+		{"cmode", 15, 4},
+		{"d", 9, 1},
+		{"e", 8, 1},
+		{"f", 7, 1},
+		{"g", 6, 1},
+		{"h", 5, 1},
+		{"Rd", 4, 5},
+	}, AsUInt32: 788530176, Generator: nil},
+	{Name: "MVNI", OpcodeMask: 3220704256, Opcode: 788530176, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"a", 18, 1},
+		{"b", 17, 1},
+		{"c", 16, 1},
+		{"cmode", 15, 4},
+		{"d", 9, 1},
+		{"e", 8, 1},
+		{"f", 7, 1},
+		{"g", 6, 1},
+		{"h", 5, 1},
+		{"Rd", 4, 5},
+	}, AsUInt32: 788530176, Generator: nil},
+	{Name: "MVNI", OpcodeMask: 3220704256, Opcode: 788530176, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"a", 18, 1},
+		{"b", 17, 1},
+		{"c", 16, 1},
+		{"cmode", 15, 4},
+		{"d", 9, 1},
+		{"e", 8, 1},
+		{"f", 7, 1},
+		{"g", 6, 1},
+		{"h", 5, 1},
+		{"Rd", 4, 5},
+	}, AsUInt32: 788530176, Generator: nil},
+	{Name: "NEG (vector)", OpcodeMask: 4282383360, Opcode: 2116073472, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2116073472, Generator: nil},
+	{Name: "NEG (vector)", OpcodeMask: 3208641536, Opcode: 773896192, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773896192, Generator: nil},
+	{Name: "NOT", OpcodeMask: 3221224448, Opcode: 773871616, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773871616, Generator: nil},
+	{Name: "ORN (vector)", OpcodeMask: 3219192832, Opcode: 249568256, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 249568256, Generator: nil},
+	{Name: "ORR (vector, immediate)", OpcodeMask: 3220704256, Opcode: 251659264, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"a", 18, 1},
+		{"b", 17, 1},
+		{"c", 16, 1},
+		{"cmode", 15, 4},
+		{"d", 9, 1},
+		{"e", 8, 1},
+		{"f", 7, 1},
+		{"g", 6, 1},
+		{"h", 5, 1},
+		{"Rd", 4, 5},
+	}, AsUInt32: 251659264, Generator: nil},
+	{Name: "ORR (vector, immediate)", OpcodeMask: 3220704256, Opcode: 251659264, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"a", 18, 1},
+		{"b", 17, 1},
+		{"c", 16, 1},
+		{"cmode", 15, 4},
+		{"d", 9, 1},
+		{"e", 8, 1},
+		{"f", 7, 1},
+		{"g", 6, 1},
+		{"h", 5, 1},
+		{"Rd", 4, 5},
+	}, AsUInt32: 251659264, Generator: nil},
+	{Name: "ORR (vector, register)", OpcodeMask: 3219192832, Opcode: 245373952, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 245373952, Generator: nil},
+	{Name: "PMUL", OpcodeMask: 3206609920, Opcode: 773889024, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773889024, Generator: nil},
+	{Name: "PMULL, PMULL2", OpcodeMask: 4280351744, Opcode: 237035520, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 237035520, Generator: nil},
+	{Name: "PMULL, PMULL2", OpcodeMask: 4280351744, Opcode: 1310777344, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1310777344, Generator: nil},
+	{Name: "RADDHN, RADDHN2", OpcodeMask: 4280351744, Opcode: 773865472, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773865472, Generator: nil},
+	{Name: "RADDHN, RADDHN2", OpcodeMask: 4280351744, Opcode: 1847607296, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1847607296, Generator: nil},
+	{Name: "RBIT (vector)", OpcodeMask: 3221224448, Opcode: 778065920, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 778065920, Generator: nil},
+	{Name: "REV16 (vector)", OpcodeMask: 3208641536, Opcode: 236984320, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 236984320, Generator: nil},
+	{Name: "REV32 (vector)", OpcodeMask: 3208641536, Opcode: 773851136, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773851136, Generator: nil},
+	{Name: "REV64", OpcodeMask: 3208641536, Opcode: 236980224, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 236980224, Generator: nil},
+	{Name: "RSHRN, RSHRN2", OpcodeMask: 4286643200, Opcode: 251694080, Fields: []InsnField{
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 251694080, Generator: nil},
+	{Name: "RSHRN, RSHRN2", OpcodeMask: 4286643200, Opcode: 1325435904, Fields: []InsnField{
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1325435904, Generator: nil},
+	{Name: "RSUBHN, RSUBHN2", OpcodeMask: 4280351744, Opcode: 773873664, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773873664, Generator: nil},
+	{Name: "RSUBHN, RSUBHN2", OpcodeMask: 4280351744, Opcode: 1847615488, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1847615488, Generator: nil},
+	{Name: "SABA", OpcodeMask: 3206609920, Opcode: 237009920, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 237009920, Generator: nil},
+	{Name: "SABAL, SABAL2", OpcodeMask: 4280351744, Opcode: 236998656, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 236998656, Generator: nil},
+	{Name: "SABAL, SABAL2", OpcodeMask: 4280351744, Opcode: 1310740480, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1310740480, Generator: nil},
+	{Name: "SABD", OpcodeMask: 3206609920, Opcode: 237007872, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 237007872, Generator: nil},
+	{Name: "SABDL, SABDL2", OpcodeMask: 4280351744, Opcode: 237006848, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 237006848, Generator: nil},
+	{Name: "SABDL, SABDL2", OpcodeMask: 4280351744, Opcode: 1310748672, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1310748672, Generator: nil},
+	{Name: "SADALP", OpcodeMask: 3208641536, Opcode: 237004800, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 237004800, Generator: nil},
+	{Name: "SADDL, SADDL2", OpcodeMask: 4280351744, Opcode: 236978176, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 236978176, Generator: nil},
+	{Name: "SADDL, SADDL2", OpcodeMask: 4280351744, Opcode: 1310720000, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1310720000, Generator: nil},
+	{Name: "SADDLP", OpcodeMask: 3208641536, Opcode: 236988416, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 236988416, Generator: nil},
+	{Name: "SADDLV", OpcodeMask: 3208641536, Opcode: 238041088, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 238041088, Generator: nil},
+	{Name: "SADDW, SADDW2", OpcodeMask: 4280351744, Opcode: 236982272, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 236982272, Generator: nil},
+	{Name: "SADDW, SADDW2", OpcodeMask: 4280351744, Opcode: 1310724096, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1310724096, Generator: nil},
+	{Name: "SCVTF (vector, fixed-point)", OpcodeMask: 4286643200, Opcode: 1593893888, Fields: []InsnField{
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1593893888, Generator: nil},
+	{Name: "SCVTF (vector, fixed-point)", OpcodeMask: 3212901376, Opcode: 251716608, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 251716608, Generator: nil},
+	{Name: "SCVTF (vector, integer)", OpcodeMask: 4290771968, Opcode: 1579276288, Fields: []InsnField{
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1579276288, Generator: nil},
+	{Name: "SCVTF (vector, integer)", OpcodeMask: 3217030144, Opcode: 237099008, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 237099008, Generator: nil},
+	{Name: "SCVTF (scalar, fixed-point)", OpcodeMask: 4294901760, Opcode: 503447552, Fields: []InsnField{
+		{"scale", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 503447552, Generator: nil},
+	{Name: "SCVTF (scalar, fixed-point)", OpcodeMask: 4294901760, Opcode: 507641856, Fields: []InsnField{
+		{"scale", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 507641856, Generator: nil},
+	{Name: "SCVTF (scalar, fixed-point)", OpcodeMask: 4294901760, Opcode: 2650931200, Fields: []InsnField{
+		{"scale", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2650931200, Generator: nil},
+	{Name: "SCVTF (scalar, fixed-point)", OpcodeMask: 4294901760, Opcode: 2655125504, Fields: []InsnField{
+		{"scale", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2655125504, Generator: nil},
+	{Name: "SCVTF (scalar, integer)", OpcodeMask: 4294966272, Opcode: 505544704, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 505544704, Generator: nil},
+	{Name: "SCVTF (scalar, integer)", OpcodeMask: 4294966272, Opcode: 509739008, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 509739008, Generator: nil},
+	{Name: "SCVTF (scalar, integer)", OpcodeMask: 4294966272, Opcode: 2653028352, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2653028352, Generator: nil},
+	{Name: "SCVTF (scalar, integer)", OpcodeMask: 4294966272, Opcode: 2657222656, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2657222656, Generator: nil},
+	{Name: "SHA1C", OpcodeMask: 4292934656, Opcode: 1577058304, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1577058304, Generator: nil},
+	{Name: "SHA1H", OpcodeMask: 4294966272, Opcode: 1579681792, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1579681792, Generator: nil},
+	{Name: "SHA1M", OpcodeMask: 4292934656, Opcode: 1577066496, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1577066496, Generator: nil},
+	{Name: "SHA1P", OpcodeMask: 4292934656, Opcode: 1577062400, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1577062400, Generator: nil},
+	{Name: "SHA1SU0", OpcodeMask: 4292934656, Opcode: 1577070592, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1577070592, Generator: nil},
+	{Name: "SHA1SU1", OpcodeMask: 4294966272, Opcode: 1579685888, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1579685888, Generator: nil},
+	{Name: "SHA256H2", OpcodeMask: 4292934656, Opcode: 1577078784, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1577078784, Generator: nil},
+	{Name: "SHA256H", OpcodeMask: 4292934656, Opcode: 1577074688, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1577074688, Generator: nil},
+	{Name: "SHA256SU0", OpcodeMask: 4294966272, Opcode: 1579689984, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1579689984, Generator: nil},
+	{Name: "SHA256SU1", OpcodeMask: 4292934656, Opcode: 1577082880, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1577082880, Generator: nil},
+	{Name: "SHADD", OpcodeMask: 3206609920, Opcode: 236979200, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 236979200, Generator: nil},
+	{Name: "SHL", OpcodeMask: 4286643200, Opcode: 1593857024, Fields: []InsnField{
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1593857024, Generator: nil},
+	{Name: "SHL", OpcodeMask: 3212901376, Opcode: 251679744, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 251679744, Generator: nil},
+	{Name: "SHLL, SHLL2", OpcodeMask: 4282383360, Opcode: 773928960, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773928960, Generator: nil},
+	{Name: "SHLL, SHLL2", OpcodeMask: 4282383360, Opcode: 1847670784, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1847670784, Generator: nil},
+	{Name: "SHRN, SHRN2", OpcodeMask: 4286643200, Opcode: 251692032, Fields: []InsnField{
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 251692032, Generator: nil},
+	{Name: "SHRN, SHRN2", OpcodeMask: 4286643200, Opcode: 1325433856, Fields: []InsnField{
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1325433856, Generator: nil},
+	{Name: "SHSUB", OpcodeMask: 3206609920, Opcode: 236987392, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 236987392, Generator: nil},
+	{Name: "SLI", OpcodeMask: 4286643200, Opcode: 2130727936, Fields: []InsnField{
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2130727936, Generator: nil},
+	{Name: "SLI", OpcodeMask: 3212901376, Opcode: 788550656, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 788550656, Generator: nil},
+	{Name: "SMAX", OpcodeMask: 3206609920, Opcode: 237003776, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 237003776, Generator: nil},
+	{Name: "SMAXP", OpcodeMask: 3206609920, Opcode: 237020160, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 237020160, Generator: nil},
+	{Name: "SMAXV", OpcodeMask: 3208641536, Opcode: 238069760, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 238069760, Generator: nil},
+	{Name: "SMIN", OpcodeMask: 3206609920, Opcode: 237005824, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 237005824, Generator: nil},
+	{Name: "SMINP", OpcodeMask: 3206609920, Opcode: 237022208, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 237022208, Generator: nil},
+	{Name: "SMINV", OpcodeMask: 3208641536, Opcode: 238135296, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 238135296, Generator: nil},
+	{Name: "SMLAL, SMLAL2 (by element)", OpcodeMask: 4278252544, Opcode: 251666432, Fields: []InsnField{
+		{"size", 23, 2},
+		{"L", 21, 1},
+		{"M", 20, 1},
+		{"Rm", 19, 4},
+		{"H", 11, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 251666432, Generator: nil},
+	{Name: "SMLAL, SMLAL2 (by element)", OpcodeMask: 4278252544, Opcode: 1325408256, Fields: []InsnField{
+		{"size", 23, 2},
+		{"L", 21, 1},
+		{"M", 20, 1},
+		{"Rm", 19, 4},
+		{"H", 11, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1325408256, Generator: nil},
+	{Name: "SMLAL, SMLAL2 (vector)", OpcodeMask: 4280351744, Opcode: 237010944, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 237010944, Generator: nil},
+	{Name: "SMLAL, SMLAL2 (vector)", OpcodeMask: 4280351744, Opcode: 1310752768, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1310752768, Generator: nil},
+	{Name: "SMLSL, SMLSL2 (by element)", OpcodeMask: 4278252544, Opcode: 251682816, Fields: []InsnField{
+		{"size", 23, 2},
+		{"L", 21, 1},
+		{"M", 20, 1},
+		{"Rm", 19, 4},
+		{"H", 11, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 251682816, Generator: nil},
+	{Name: "SMLSL, SMLSL2 (by element)", OpcodeMask: 4278252544, Opcode: 1325424640, Fields: []InsnField{
+		{"size", 23, 2},
+		{"L", 21, 1},
+		{"M", 20, 1},
+		{"Rm", 19, 4},
+		{"H", 11, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1325424640, Generator: nil},
+	{Name: "SMLSL, SMLSL2 (vector)", OpcodeMask: 4280351744, Opcode: 237019136, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 237019136, Generator: nil},
+	{Name: "SMLSL, SMLSL2 (vector)", OpcodeMask: 4280351744, Opcode: 1310760960, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1310760960, Generator: nil},
+	{Name: "SMOV", OpcodeMask: 4292934656, Opcode: 234892288, Fields: []InsnField{
+		{"imm5", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 234892288, Generator: nil},
+	{Name: "SMOV", OpcodeMask: 4292934656, Opcode: 1308634112, Fields: []InsnField{
+		{"imm5", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1308634112, Generator: nil},
+	{Name: "SMULL, SMULL2 (by element)", OpcodeMask: 4278252544, Opcode: 251699200, Fields: []InsnField{
+		{"size", 23, 2},
+		{"L", 21, 1},
+		{"M", 20, 1},
+		{"Rm", 19, 4},
+		{"H", 11, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 251699200, Generator: nil},
+	{Name: "SMULL, SMULL2 (by element)", OpcodeMask: 4278252544, Opcode: 1325441024, Fields: []InsnField{
+		{"size", 23, 2},
+		{"L", 21, 1},
+		{"M", 20, 1},
+		{"Rm", 19, 4},
+		{"H", 11, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1325441024, Generator: nil},
+	{Name: "SMULL, SMULL2 (vector)", OpcodeMask: 4280351744, Opcode: 237027328, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 237027328, Generator: nil},
+	{Name: "SMULL, SMULL2 (vector)", OpcodeMask: 4280351744, Opcode: 1310769152, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1310769152, Generator: nil},
+	{Name: "SQABS", OpcodeMask: 4282383360, Opcode: 1579186176, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1579186176, Generator: nil},
+	{Name: "SQABS", OpcodeMask: 3208641536, Opcode: 237008896, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 237008896, Generator: nil},
+	{Name: "SQADD", OpcodeMask: 4280351744, Opcode: 1579158528, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1579158528, Generator: nil},
+	{Name: "SQADD", OpcodeMask: 3206609920, Opcode: 236981248, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 236981248, Generator: nil},
+	{Name: "SQDMLAL, SQDMLAL2 (by element)", OpcodeMask: 4278252544, Opcode: 1593847808, Fields: []InsnField{
+		{"size", 23, 2},
+		{"L", 21, 1},
+		{"M", 20, 1},
+		{"Rm", 19, 4},
+		{"H", 11, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1593847808, Generator: nil},
+	{Name: "SQDMLAL, SQDMLAL2 (by element)", OpcodeMask: 4278252544, Opcode: 251670528, Fields: []InsnField{
+		{"size", 23, 2},
+		{"L", 21, 1},
+		{"M", 20, 1},
+		{"Rm", 19, 4},
+		{"H", 11, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 251670528, Generator: nil},
+	{Name: "SQDMLAL, SQDMLAL2 (by element)", OpcodeMask: 4278252544, Opcode: 1325412352, Fields: []InsnField{
+		{"size", 23, 2},
+		{"L", 21, 1},
+		{"M", 20, 1},
+		{"Rm", 19, 4},
+		{"H", 11, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1325412352, Generator: nil},
+	{Name: "SQDMLAL, SQDMLAL2 (vector)", OpcodeMask: 4280351744, Opcode: 1579192320, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1579192320, Generator: nil},
+	{Name: "SQDMLAL, SQDMLAL2 (vector)", OpcodeMask: 4280351744, Opcode: 237015040, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 237015040, Generator: nil},
+	{Name: "SQDMLAL, SQDMLAL2 (vector)", OpcodeMask: 4280351744, Opcode: 1310756864, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1310756864, Generator: nil},
+	{Name: "SQDMLSL, SQDMLSL2 (by element)", OpcodeMask: 4278252544, Opcode: 1593864192, Fields: []InsnField{
+		{"size", 23, 2},
+		{"L", 21, 1},
+		{"M", 20, 1},
+		{"Rm", 19, 4},
+		{"H", 11, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1593864192, Generator: nil},
+	{Name: "SQDMLSL, SQDMLSL2 (by element)", OpcodeMask: 4278252544, Opcode: 251686912, Fields: []InsnField{
+		{"size", 23, 2},
+		{"L", 21, 1},
+		{"M", 20, 1},
+		{"Rm", 19, 4},
+		{"H", 11, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 251686912, Generator: nil},
+	{Name: "SQDMLSL, SQDMLSL2 (by element)", OpcodeMask: 4278252544, Opcode: 1325428736, Fields: []InsnField{
+		{"size", 23, 2},
+		{"L", 21, 1},
+		{"M", 20, 1},
+		{"Rm", 19, 4},
+		{"H", 11, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1325428736, Generator: nil},
+	{Name: "SQDMLSL, SQDMLSL2 (vector)", OpcodeMask: 4280351744, Opcode: 1579200512, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1579200512, Generator: nil},
+	{Name: "SQDMLSL, SQDMLSL2 (vector)", OpcodeMask: 4280351744, Opcode: 237023232, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 237023232, Generator: nil},
+	{Name: "SQDMLSL, SQDMLSL2 (vector)", OpcodeMask: 4280351744, Opcode: 1310765056, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1310765056, Generator: nil},
+	{Name: "SQDMULH (by element)", OpcodeMask: 4278252544, Opcode: 1593884672, Fields: []InsnField{
+		{"size", 23, 2},
+		{"L", 21, 1},
+		{"M", 20, 1},
+		{"Rm", 19, 4},
+		{"H", 11, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1593884672, Generator: nil},
+	{Name: "SQDMULH (by element)", OpcodeMask: 3204510720, Opcode: 251707392, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"L", 21, 1},
+		{"M", 20, 1},
+		{"Rm", 19, 4},
+		{"H", 11, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 251707392, Generator: nil},
+	{Name: "SQDMULH (vector)", OpcodeMask: 4280351744, Opcode: 1579201536, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1579201536, Generator: nil},
+	{Name: "SQDMULH (vector)", OpcodeMask: 3206609920, Opcode: 237024256, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 237024256, Generator: nil},
+	{Name: "SQDMULL, SQDMULL2 (by element)", OpcodeMask: 4278252544, Opcode: 1593880576, Fields: []InsnField{
+		{"size", 23, 2},
+		{"L", 21, 1},
+		{"M", 20, 1},
+		{"Rm", 19, 4},
+		{"H", 11, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1593880576, Generator: nil},
+	{Name: "SQDMULL, SQDMULL2 (by element)", OpcodeMask: 4278252544, Opcode: 251703296, Fields: []InsnField{
+		{"size", 23, 2},
+		{"L", 21, 1},
+		{"M", 20, 1},
+		{"Rm", 19, 4},
+		{"H", 11, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 251703296, Generator: nil},
+	{Name: "SQDMULL, SQDMULL2 (by element)", OpcodeMask: 4278252544, Opcode: 1325445120, Fields: []InsnField{
+		{"size", 23, 2},
+		{"L", 21, 1},
+		{"M", 20, 1},
+		{"Rm", 19, 4},
+		{"H", 11, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1325445120, Generator: nil},
+	{Name: "SQDMULL, SQDMULL2 (vector)", OpcodeMask: 4280351744, Opcode: 1579208704, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1579208704, Generator: nil},
+	{Name: "SQDMULL, SQDMULL2 (vector)", OpcodeMask: 4280351744, Opcode: 237031424, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 237031424, Generator: nil},
+	{Name: "SQDMULL, SQDMULL2 (vector)", OpcodeMask: 4280351744, Opcode: 1310773248, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1310773248, Generator: nil},
+	{Name: "SQNEG", OpcodeMask: 4282383360, Opcode: 2116057088, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2116057088, Generator: nil},
+	{Name: "SQNEG", OpcodeMask: 3208641536, Opcode: 773879808, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773879808, Generator: nil},
+	{Name: "SQRDMULH (by element)", OpcodeMask: 4278252544, Opcode: 1593888768, Fields: []InsnField{
+		{"size", 23, 2},
+		{"L", 21, 1},
+		{"M", 20, 1},
+		{"Rm", 19, 4},
+		{"H", 11, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1593888768, Generator: nil},
+	{Name: "SQRDMULH (by element)", OpcodeMask: 3204510720, Opcode: 251711488, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"L", 21, 1},
+		{"M", 20, 1},
+		{"Rm", 19, 4},
+		{"H", 11, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 251711488, Generator: nil},
+	{Name: "SQRDMULH (vector)", OpcodeMask: 4280351744, Opcode: 2116072448, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2116072448, Generator: nil},
+	{Name: "SQRDMULH (vector)", OpcodeMask: 3206609920, Opcode: 773895168, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773895168, Generator: nil},
+	{Name: "SQRSHL", OpcodeMask: 4280351744, Opcode: 1579179008, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1579179008, Generator: nil},
+	{Name: "SQRSHL", OpcodeMask: 3206609920, Opcode: 237001728, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 237001728, Generator: nil},
+	{Name: "SQRSHRN, SQRSHRN2", OpcodeMask: 4286643200, Opcode: 1593875456, Fields: []InsnField{
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1593875456, Generator: nil},
+	{Name: "SQRSHRN, SQRSHRN2", OpcodeMask: 4286643200, Opcode: 251698176, Fields: []InsnField{
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 251698176, Generator: nil},
+	{Name: "SQRSHRN, SQRSHRN2", OpcodeMask: 4286643200, Opcode: 1325440000, Fields: []InsnField{
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1325440000, Generator: nil},
+	{Name: "SQRSHRUN, SQRSHRUN2", OpcodeMask: 4286643200, Opcode: 2130742272, Fields: []InsnField{
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2130742272, Generator: nil},
+	{Name: "SQRSHRUN, SQRSHRUN2", OpcodeMask: 4286643200, Opcode: 788564992, Fields: []InsnField{
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 788564992, Generator: nil},
+	{Name: "SQRSHRUN, SQRSHRUN2", OpcodeMask: 4286643200, Opcode: 1862306816, Fields: []InsnField{
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1862306816, Generator: nil},
+	{Name: "SQSHL (immediate)", OpcodeMask: 4286643200, Opcode: 1593865216, Fields: []InsnField{
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1593865216, Generator: nil},
+	{Name: "SQSHL (immediate)", OpcodeMask: 3212901376, Opcode: 251687936, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 251687936, Generator: nil},
+	{Name: "SQSHL (register)", OpcodeMask: 4280351744, Opcode: 1579174912, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1579174912, Generator: nil},
+	{Name: "SQSHL (register)", OpcodeMask: 3206609920, Opcode: 236997632, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 236997632, Generator: nil},
+	{Name: "SQSHLU", OpcodeMask: 4286643200, Opcode: 2130732032, Fields: []InsnField{
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2130732032, Generator: nil},
+	{Name: "SQSHLU", OpcodeMask: 3212901376, Opcode: 788554752, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 788554752, Generator: nil},
+	{Name: "SQSHRN, SQSHRN2", OpcodeMask: 4286643200, Opcode: 1593873408, Fields: []InsnField{
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1593873408, Generator: nil},
+	{Name: "SQSHRN, SQSHRN2", OpcodeMask: 4286643200, Opcode: 251696128, Fields: []InsnField{
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 251696128, Generator: nil},
+	{Name: "SQSHRN, SQSHRN2", OpcodeMask: 4286643200, Opcode: 1325437952, Fields: []InsnField{
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1325437952, Generator: nil},
+	{Name: "SQSHRUN, SQSHRUN2", OpcodeMask: 4286643200, Opcode: 2130740224, Fields: []InsnField{
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2130740224, Generator: nil},
+	{Name: "SQSHRUN, SQSHRUN2", OpcodeMask: 4286643200, Opcode: 788562944, Fields: []InsnField{
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 788562944, Generator: nil},
+	{Name: "SQSHRUN, SQSHRUN2", OpcodeMask: 4286643200, Opcode: 1862304768, Fields: []InsnField{
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1862304768, Generator: nil},
+	{Name: "SQSUB", OpcodeMask: 4280351744, Opcode: 1579166720, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1579166720, Generator: nil},
+	{Name: "SQSUB", OpcodeMask: 3206609920, Opcode: 236989440, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 236989440, Generator: nil},
+	{Name: "SQXTN, SQXTN2", OpcodeMask: 4282383360, Opcode: 1579239424, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1579239424, Generator: nil},
+	{Name: "SQXTN, SQXTN2", OpcodeMask: 4282383360, Opcode: 237062144, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 237062144, Generator: nil},
+	{Name: "SQXTN, SQXTN2", OpcodeMask: 4282383360, Opcode: 1310803968, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1310803968, Generator: nil},
+	{Name: "SQXTUN, SQXTUN2", OpcodeMask: 4282383360, Opcode: 2116102144, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2116102144, Generator: nil},
+	{Name: "SQXTUN, SQXTUN2", OpcodeMask: 4282383360, Opcode: 773924864, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773924864, Generator: nil},
+	{Name: "SQXTUN, SQXTUN2", OpcodeMask: 4282383360, Opcode: 1847666688, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1847666688, Generator: nil},
+	{Name: "SRHADD", OpcodeMask: 3206609920, Opcode: 236983296, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 236983296, Generator: nil},
+	{Name: "SRI", OpcodeMask: 4286643200, Opcode: 2130723840, Fields: []InsnField{
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2130723840, Generator: nil},
+	{Name: "SRI", OpcodeMask: 3212901376, Opcode: 788546560, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 788546560, Generator: nil},
+	{Name: "SRSHL", OpcodeMask: 4280351744, Opcode: 1579176960, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1579176960, Generator: nil},
+	{Name: "SRSHL", OpcodeMask: 3206609920, Opcode: 236999680, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 236999680, Generator: nil},
+	{Name: "SRSHR", OpcodeMask: 4286643200, Opcode: 1593844736, Fields: []InsnField{
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1593844736, Generator: nil},
+	{Name: "SRSHR", OpcodeMask: 3212901376, Opcode: 251667456, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 251667456, Generator: nil},
+	{Name: "SRSRA", OpcodeMask: 4286643200, Opcode: 1593848832, Fields: []InsnField{
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1593848832, Generator: nil},
+	{Name: "SRSRA", OpcodeMask: 3212901376, Opcode: 251671552, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 251671552, Generator: nil},
+	{Name: "SSHL", OpcodeMask: 4280351744, Opcode: 1579172864, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1579172864, Generator: nil},
+	{Name: "SSHL", OpcodeMask: 3206609920, Opcode: 236995584, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 236995584, Generator: nil},
+	{Name: "SSHLL, SSHLL2", OpcodeMask: 4286643200, Opcode: 251700224, Fields: []InsnField{
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 251700224, Generator: nil},
+	{Name: "SSHLL, SSHLL2", OpcodeMask: 4286643200, Opcode: 1325442048, Fields: []InsnField{
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1325442048, Generator: nil},
+	{Name: "SSHR", OpcodeMask: 4286643200, Opcode: 1593836544, Fields: []InsnField{
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1593836544, Generator: nil},
+	{Name: "SSHR", OpcodeMask: 3212901376, Opcode: 251659264, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 251659264, Generator: nil},
+	{Name: "SSRA", OpcodeMask: 4286643200, Opcode: 1593840640, Fields: []InsnField{
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1593840640, Generator: nil},
+	{Name: "SSRA", OpcodeMask: 3212901376, Opcode: 251663360, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 251663360, Generator: nil},
+	{Name: "SSUBL, SSUBL2", OpcodeMask: 4280351744, Opcode: 236986368, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 236986368, Generator: nil},
+	{Name: "SSUBL, SSUBL2", OpcodeMask: 4280351744, Opcode: 1310728192, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1310728192, Generator: nil},
+	{Name: "SSUBW, SSUBW2", OpcodeMask: 4280351744, Opcode: 236990464, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 236990464, Generator: nil},
+	{Name: "SSUBW, SSUBW2", OpcodeMask: 4280351744, Opcode: 1310732288, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1310732288, Generator: nil},
+	{Name: "ST1 (multiple structures)", OpcodeMask: 3221221376, Opcode: 201355264, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 201355264, Generator: nil},
+	{Name: "ST1 (multiple structures)", OpcodeMask: 3221221376, Opcode: 201367552, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 201367552, Generator: nil},
+	{Name: "ST1 (multiple structures)", OpcodeMask: 3221221376, Opcode: 201351168, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 201351168, Generator: nil},
+	{Name: "ST1 (multiple structures)", OpcodeMask: 3221221376, Opcode: 201334784, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 201334784, Generator: nil},
+	{Name: "ST1 (multiple structures)", OpcodeMask: 3221221376, Opcode: 211775488, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 211775488, Generator: nil},
+	{Name: "ST1 (multiple structures)", OpcodeMask: 3219189760, Opcode: 209743872, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 209743872, Generator: nil},
+	{Name: "ST1 (multiple structures)", OpcodeMask: 3221221376, Opcode: 211787776, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 211787776, Generator: nil},
+	{Name: "ST1 (multiple structures)", OpcodeMask: 3219189760, Opcode: 209756160, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 209756160, Generator: nil},
+	{Name: "ST1 (multiple structures)", OpcodeMask: 3221221376, Opcode: 211771392, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 211771392, Generator: nil},
+	{Name: "ST1 (multiple structures)", OpcodeMask: 3219189760, Opcode: 209739776, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 209739776, Generator: nil},
+	{Name: "ST1 (multiple structures)", OpcodeMask: 3221221376, Opcode: 211755008, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 211755008, Generator: nil},
+	{Name: "ST1 (multiple structures)", OpcodeMask: 3219189760, Opcode: 209723392, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 209723392, Generator: nil},
+	{Name: "ST1 (single structure)", OpcodeMask: 3221217280, Opcode: 218103808, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"S", 12, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 218103808, Generator: nil},
+	{Name: "ST1 (single structure)", OpcodeMask: 3221217280, Opcode: 218120192, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"S", 12, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 218120192, Generator: nil},
+	{Name: "ST1 (single structure)", OpcodeMask: 3221220352, Opcode: 218136576, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"S", 12, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 218136576, Generator: nil},
+	{Name: "ST1 (single structure)", OpcodeMask: 3221224448, Opcode: 218137600, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 218137600, Generator: nil},
+	{Name: "ST1 (single structure)", OpcodeMask: 3221217280, Opcode: 228524032, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"S", 12, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 228524032, Generator: nil},
+	{Name: "ST1 (single structure)", OpcodeMask: 3219185664, Opcode: 226492416, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"S", 12, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 226492416, Generator: nil},
+	{Name: "ST1 (single structure)", OpcodeMask: 3221217280, Opcode: 228540416, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"S", 12, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 228540416, Generator: nil},
+	{Name: "ST1 (single structure)", OpcodeMask: 3219185664, Opcode: 226508800, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"S", 12, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 226508800, Generator: nil},
+	{Name: "ST1 (single structure)", OpcodeMask: 3221220352, Opcode: 228556800, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"S", 12, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 228556800, Generator: nil},
+	{Name: "ST1 (single structure)", OpcodeMask: 3219188736, Opcode: 226525184, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"S", 12, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 226525184, Generator: nil},
+	{Name: "ST1 (single structure)", OpcodeMask: 3221224448, Opcode: 228557824, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 228557824, Generator: nil},
+	{Name: "ST1 (single structure)", OpcodeMask: 3219192832, Opcode: 226526208, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 226526208, Generator: nil},
+	{Name: "ST2 (multiple structures)", OpcodeMask: 3221221376, Opcode: 201359360, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 201359360, Generator: nil},
+	{Name: "ST2 (multiple structures)", OpcodeMask: 3221221376, Opcode: 211779584, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 211779584, Generator: nil},
+	{Name: "ST2 (multiple structures)", OpcodeMask: 3219189760, Opcode: 209747968, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 209747968, Generator: nil},
+	{Name: "ST2 (single structure)", OpcodeMask: 3221217280, Opcode: 220200960, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"S", 12, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 220200960, Generator: nil},
+	{Name: "ST2 (single structure)", OpcodeMask: 3221217280, Opcode: 220217344, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"S", 12, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 220217344, Generator: nil},
+	{Name: "ST2 (single structure)", OpcodeMask: 3221220352, Opcode: 220233728, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"S", 12, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 220233728, Generator: nil},
+	{Name: "ST2 (single structure)", OpcodeMask: 3221224448, Opcode: 220234752, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 220234752, Generator: nil},
+	{Name: "ST2 (single structure)", OpcodeMask: 3221217280, Opcode: 230621184, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"S", 12, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 230621184, Generator: nil},
+	{Name: "ST2 (single structure)", OpcodeMask: 3219185664, Opcode: 228589568, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"S", 12, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 228589568, Generator: nil},
+	{Name: "ST2 (single structure)", OpcodeMask: 3221217280, Opcode: 230637568, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"S", 12, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 230637568, Generator: nil},
+	{Name: "ST2 (single structure)", OpcodeMask: 3219185664, Opcode: 228605952, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"S", 12, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 228605952, Generator: nil},
+	{Name: "ST2 (single structure)", OpcodeMask: 3221220352, Opcode: 230653952, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"S", 12, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 230653952, Generator: nil},
+	{Name: "ST2 (single structure)", OpcodeMask: 3219188736, Opcode: 228622336, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"S", 12, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 228622336, Generator: nil},
+	{Name: "ST2 (single structure)", OpcodeMask: 3221224448, Opcode: 230654976, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 230654976, Generator: nil},
+	{Name: "ST2 (single structure)", OpcodeMask: 3219192832, Opcode: 228623360, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 228623360, Generator: nil},
+	{Name: "ST3 (multiple structures)", OpcodeMask: 3221221376, Opcode: 201342976, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 201342976, Generator: nil},
+	{Name: "ST3 (multiple structures)", OpcodeMask: 3221221376, Opcode: 211763200, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 211763200, Generator: nil},
+	{Name: "ST3 (multiple structures)", OpcodeMask: 3219189760, Opcode: 209731584, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 209731584, Generator: nil},
+	{Name: "ST3 (single structure)", OpcodeMask: 3221217280, Opcode: 218112000, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"S", 12, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 218112000, Generator: nil},
+	{Name: "ST3 (single structure)", OpcodeMask: 3221217280, Opcode: 218128384, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"S", 12, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 218128384, Generator: nil},
+	{Name: "ST3 (single structure)", OpcodeMask: 3221220352, Opcode: 218144768, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"S", 12, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 218144768, Generator: nil},
+	{Name: "ST3 (single structure)", OpcodeMask: 3221224448, Opcode: 218145792, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 218145792, Generator: nil},
+	{Name: "ST3 (single structure)", OpcodeMask: 3221217280, Opcode: 228532224, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"S", 12, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 228532224, Generator: nil},
+	{Name: "ST3 (single structure)", OpcodeMask: 3219185664, Opcode: 226500608, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"S", 12, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 226500608, Generator: nil},
+	{Name: "ST3 (single structure)", OpcodeMask: 3221217280, Opcode: 228548608, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"S", 12, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 228548608, Generator: nil},
+	{Name: "ST3 (single structure)", OpcodeMask: 3219185664, Opcode: 226516992, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"S", 12, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 226516992, Generator: nil},
+	{Name: "ST3 (single structure)", OpcodeMask: 3221220352, Opcode: 228564992, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"S", 12, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 228564992, Generator: nil},
+	{Name: "ST3 (single structure)", OpcodeMask: 3219188736, Opcode: 226533376, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"S", 12, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 226533376, Generator: nil},
+	{Name: "ST3 (single structure)", OpcodeMask: 3221224448, Opcode: 228566016, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 228566016, Generator: nil},
+	{Name: "ST3 (single structure)", OpcodeMask: 3219192832, Opcode: 226534400, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 226534400, Generator: nil},
+	{Name: "ST4 (multiple structures)", OpcodeMask: 3221221376, Opcode: 201326592, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 201326592, Generator: nil},
+	{Name: "ST4 (multiple structures)", OpcodeMask: 3221221376, Opcode: 211746816, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 211746816, Generator: nil},
+	{Name: "ST4 (multiple structures)", OpcodeMask: 3219189760, Opcode: 209715200, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 209715200, Generator: nil},
+	{Name: "ST4 (single structure)", OpcodeMask: 3221217280, Opcode: 220209152, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"S", 12, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 220209152, Generator: nil},
+	{Name: "ST4 (single structure)", OpcodeMask: 3221217280, Opcode: 220225536, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"S", 12, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 220225536, Generator: nil},
+	{Name: "ST4 (single structure)", OpcodeMask: 3221220352, Opcode: 220241920, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"S", 12, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 220241920, Generator: nil},
+	{Name: "ST4 (single structure)", OpcodeMask: 3221224448, Opcode: 220242944, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 220242944, Generator: nil},
+	{Name: "ST4 (single structure)", OpcodeMask: 3221217280, Opcode: 230629376, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"S", 12, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 230629376, Generator: nil},
+	{Name: "ST4 (single structure)", OpcodeMask: 3219185664, Opcode: 228597760, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"S", 12, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 228597760, Generator: nil},
+	{Name: "ST4 (single structure)", OpcodeMask: 3221217280, Opcode: 230645760, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"S", 12, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 230645760, Generator: nil},
+	{Name: "ST4 (single structure)", OpcodeMask: 3219185664, Opcode: 228614144, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"S", 12, 1},
+		{"size", 11, 2},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 228614144, Generator: nil},
+	{Name: "ST4 (single structure)", OpcodeMask: 3221220352, Opcode: 230662144, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"S", 12, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 230662144, Generator: nil},
+	{Name: "ST4 (single structure)", OpcodeMask: 3219188736, Opcode: 228630528, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"S", 12, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 228630528, Generator: nil},
+	{Name: "ST4 (single structure)", OpcodeMask: 3221224448, Opcode: 230663168, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 230663168, Generator: nil},
+	{Name: "ST4 (single structure)", OpcodeMask: 3219192832, Opcode: 228631552, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 228631552, Generator: nil},
+	{Name: "STNP (SIMD&FP)", OpcodeMask: 4290772992, Opcode: 738197504, Fields: []InsnField{
+		{"imm7", 21, 7},
+		{"Rt2", 14, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 738197504, Generator: nil},
+	{Name: "STNP (SIMD&FP)", OpcodeMask: 4290772992, Opcode: 1811939328, Fields: []InsnField{
+		{"imm7", 21, 7},
+		{"Rt2", 14, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 1811939328, Generator: nil},
+	{Name: "STNP (SIMD&FP)", OpcodeMask: 4290772992, Opcode: 2885681152, Fields: []InsnField{
+		{"imm7", 21, 7},
+		{"Rt2", 14, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2885681152, Generator: nil},
+	{Name: "STP (SIMD&FP)", OpcodeMask: 4290772992, Opcode: 746586112, Fields: []InsnField{
+		{"imm7", 21, 7},
+		{"Rt2", 14, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 746586112, Generator: nil},
+	{Name: "STP (SIMD&FP)", OpcodeMask: 4290772992, Opcode: 1820327936, Fields: []InsnField{
+		{"imm7", 21, 7},
+		{"Rt2", 14, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 1820327936, Generator: nil},
+	{Name: "STP (SIMD&FP)", OpcodeMask: 4290772992, Opcode: 2894069760, Fields: []InsnField{
+		{"imm7", 21, 7},
+		{"Rt2", 14, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2894069760, Generator: nil},
+	{Name: "STP (SIMD&FP)", OpcodeMask: 4290772992, Opcode: 763363328, Fields: []InsnField{
+		{"imm7", 21, 7},
+		{"Rt2", 14, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 763363328, Generator: nil},
+	{Name: "STP (SIMD&FP)", OpcodeMask: 4290772992, Opcode: 1837105152, Fields: []InsnField{
+		{"imm7", 21, 7},
+		{"Rt2", 14, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 1837105152, Generator: nil},
+	{Name: "STP (SIMD&FP)", OpcodeMask: 4290772992, Opcode: 2910846976, Fields: []InsnField{
+		{"imm7", 21, 7},
+		{"Rt2", 14, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2910846976, Generator: nil},
+	{Name: "STP (SIMD&FP)", OpcodeMask: 4290772992, Opcode: 754974720, Fields: []InsnField{
+		{"imm7", 21, 7},
+		{"Rt2", 14, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 754974720, Generator: nil},
+	{Name: "STP (SIMD&FP)", OpcodeMask: 4290772992, Opcode: 1828716544, Fields: []InsnField{
+		{"imm7", 21, 7},
+		{"Rt2", 14, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 1828716544, Generator: nil},
+	{Name: "STP (SIMD&FP)", OpcodeMask: 4290772992, Opcode: 2902458368, Fields: []InsnField{
+		{"imm7", 21, 7},
+		{"Rt2", 14, 5},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2902458368, Generator: nil},
+	{Name: "STR (immediate, SIMD&FP)", OpcodeMask: 4292873216, Opcode: 1006633984, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 1006633984, Generator: nil},
+	{Name: "STR (immediate, SIMD&FP)", OpcodeMask: 4292873216, Opcode: 2080375808, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2080375808, Generator: nil},
+	{Name: "STR (immediate, SIMD&FP)", OpcodeMask: 4292873216, Opcode: 3154117632, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 3154117632, Generator: nil},
+	{Name: "STR (immediate, SIMD&FP)", OpcodeMask: 4292873216, Opcode: 4227859456, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 4227859456, Generator: nil},
+	{Name: "STR (immediate, SIMD&FP)", OpcodeMask: 4292873216, Opcode: 1015022592, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 1015022592, Generator: nil},
+	{Name: "STR (immediate, SIMD&FP)", OpcodeMask: 4292873216, Opcode: 1006636032, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 1006636032, Generator: nil},
+	{Name: "STR (immediate, SIMD&FP)", OpcodeMask: 4292873216, Opcode: 2080377856, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2080377856, Generator: nil},
+	{Name: "STR (immediate, SIMD&FP)", OpcodeMask: 4292873216, Opcode: 3154119680, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 3154119680, Generator: nil},
+	{Name: "STR (immediate, SIMD&FP)", OpcodeMask: 4292873216, Opcode: 4227861504, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 4227861504, Generator: nil},
+	{Name: "STR (immediate, SIMD&FP)", OpcodeMask: 4292873216, Opcode: 1015024640, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 1015024640, Generator: nil},
+	{Name: "STR (immediate, SIMD&FP)", OpcodeMask: 4290772992, Opcode: 1023410176, Fields: []InsnField{
+		{"imm12", 21, 12},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 1023410176, Generator: nil},
+	{Name: "STR (immediate, SIMD&FP)", OpcodeMask: 4290772992, Opcode: 2097152000, Fields: []InsnField{
+		{"imm12", 21, 12},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2097152000, Generator: nil},
+	{Name: "STR (immediate, SIMD&FP)", OpcodeMask: 4290772992, Opcode: 3170893824, Fields: []InsnField{
+		{"imm12", 21, 12},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 3170893824, Generator: nil},
+	{Name: "STR (immediate, SIMD&FP)", OpcodeMask: 4290772992, Opcode: 4244635648, Fields: []InsnField{
+		{"imm12", 21, 12},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 4244635648, Generator: nil},
+	{Name: "STR (immediate, SIMD&FP)", OpcodeMask: 4290772992, Opcode: 1031798784, Fields: []InsnField{
+		{"imm12", 21, 12},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 1031798784, Generator: nil},
+	{Name: "STR (register, SIMD&FP)", OpcodeMask: 4292873216, Opcode: 1008732160, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"option", 15, 3},
+		{"S", 12, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 1008732160, Generator: nil},
+	{Name: "STR (register, SIMD&FP)", OpcodeMask: 4292930560, Opcode: 1008756736, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"S", 12, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 1008756736, Generator: nil},
+	{Name: "STR (register, SIMD&FP)", OpcodeMask: 4292873216, Opcode: 2082473984, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"option", 15, 3},
+		{"S", 12, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2082473984, Generator: nil},
+	{Name: "STR (register, SIMD&FP)", OpcodeMask: 4292873216, Opcode: 3156215808, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"option", 15, 3},
+		{"S", 12, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 3156215808, Generator: nil},
+	{Name: "STR (register, SIMD&FP)", OpcodeMask: 4292873216, Opcode: 4229957632, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"option", 15, 3},
+		{"S", 12, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 4229957632, Generator: nil},
+	{Name: "STR (register, SIMD&FP)", OpcodeMask: 4292873216, Opcode: 1017120768, Fields: []InsnField{
+		{"Rm", 20, 5},
+		{"option", 15, 3},
+		{"S", 12, 1},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 1017120768, Generator: nil},
+	{Name: "STUR (SIMD&FP)", OpcodeMask: 4292873216, Opcode: 1006632960, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 1006632960, Generator: nil},
+	{Name: "STUR (SIMD&FP)", OpcodeMask: 4292873216, Opcode: 2080374784, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 2080374784, Generator: nil},
+	{Name: "STUR (SIMD&FP)", OpcodeMask: 4292873216, Opcode: 3154116608, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 3154116608, Generator: nil},
+	{Name: "STUR (SIMD&FP)", OpcodeMask: 4292873216, Opcode: 4227858432, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 4227858432, Generator: nil},
+	{Name: "STUR (SIMD&FP)", OpcodeMask: 4292873216, Opcode: 1015021568, Fields: []InsnField{
+		{"imm9", 20, 9},
+		{"Rn", 9, 5},
+		{"Rt", 4, 5},
+	}, AsUInt32: 1015021568, Generator: nil},
+	{Name: "SUB (vector)", OpcodeMask: 4280351744, Opcode: 2116060160, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2116060160, Generator: nil},
+	{Name: "SUB (vector)", OpcodeMask: 3206609920, Opcode: 773882880, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773882880, Generator: nil},
+	{Name: "SUBHN, SUBHN2", OpcodeMask: 4280351744, Opcode: 237002752, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 237002752, Generator: nil},
+	{Name: "SUBHN, SUBHN2", OpcodeMask: 4280351744, Opcode: 1310744576, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1310744576, Generator: nil},
+	{Name: "SUQADD", OpcodeMask: 4282383360, Opcode: 1579169792, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1579169792, Generator: nil},
+	{Name: "SUQADD", OpcodeMask: 3208641536, Opcode: 236992512, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 236992512, Generator: nil},
+	{Name: "SXTL, SXTL2", OpcodeMask: 4287101952, Opcode: 251700224, Fields: []InsnField{
+		{"immh", 22, 4},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 251700224, Generator: nil},
+	{Name: "SXTL, SXTL2", OpcodeMask: 4287101952, Opcode: 1325442048, Fields: []InsnField{
+		{"immh", 22, 4},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1325442048, Generator: nil},
+	{Name: "TBL", OpcodeMask: 3219192832, Opcode: 234889216, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 234889216, Generator: nil},
+	{Name: "TBL", OpcodeMask: 3219192832, Opcode: 234897408, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 234897408, Generator: nil},
+	{Name: "TBL", OpcodeMask: 3219192832, Opcode: 234905600, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 234905600, Generator: nil},
+	{Name: "TBL", OpcodeMask: 3219192832, Opcode: 234881024, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 234881024, Generator: nil},
+	{Name: "TBX", OpcodeMask: 3219192832, Opcode: 234893312, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 234893312, Generator: nil},
+	{Name: "TBX", OpcodeMask: 3219192832, Opcode: 234901504, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 234901504, Generator: nil},
+	{Name: "TBX", OpcodeMask: 3219192832, Opcode: 234909696, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 234909696, Generator: nil},
+	{Name: "TBX", OpcodeMask: 3219192832, Opcode: 234885120, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 234885120, Generator: nil},
+	{Name: "TRN1", OpcodeMask: 3206609920, Opcode: 234891264, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 234891264, Generator: nil},
+	{Name: "TRN2", OpcodeMask: 3206609920, Opcode: 234907648, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 234907648, Generator: nil},
+	{Name: "UABA", OpcodeMask: 3206609920, Opcode: 773880832, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773880832, Generator: nil},
+	{Name: "UABAL, UABAL2", OpcodeMask: 4280351744, Opcode: 773869568, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773869568, Generator: nil},
+	{Name: "UABAL, UABAL2", OpcodeMask: 4280351744, Opcode: 1847611392, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1847611392, Generator: nil},
+	{Name: "UABD", OpcodeMask: 3206609920, Opcode: 773878784, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773878784, Generator: nil},
+	{Name: "UABDL, UABDL2", OpcodeMask: 4280351744, Opcode: 773877760, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773877760, Generator: nil},
+	{Name: "UABDL, UABDL2", OpcodeMask: 4280351744, Opcode: 1847619584, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1847619584, Generator: nil},
+	{Name: "UADALP", OpcodeMask: 3208641536, Opcode: 773875712, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773875712, Generator: nil},
+	{Name: "UADDL, UADDL2", OpcodeMask: 4280351744, Opcode: 773849088, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773849088, Generator: nil},
+	{Name: "UADDL, UADDL2", OpcodeMask: 4280351744, Opcode: 1847590912, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1847590912, Generator: nil},
+	{Name: "UADDLP", OpcodeMask: 3208641536, Opcode: 773859328, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773859328, Generator: nil},
+	{Name: "UADDLV", OpcodeMask: 3208641536, Opcode: 774912000, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 774912000, Generator: nil},
+	{Name: "UADDW, UADDW2", OpcodeMask: 4280351744, Opcode: 773853184, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773853184, Generator: nil},
+	{Name: "UADDW, UADDW2", OpcodeMask: 4280351744, Opcode: 1847595008, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1847595008, Generator: nil},
+	{Name: "UCVTF (vector, fixed-point)", OpcodeMask: 4286643200, Opcode: 2130764800, Fields: []InsnField{
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2130764800, Generator: nil},
+	{Name: "UCVTF (vector, fixed-point)", OpcodeMask: 3212901376, Opcode: 788587520, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 788587520, Generator: nil},
+	{Name: "UCVTF (vector, integer)", OpcodeMask: 4290771968, Opcode: 2116147200, Fields: []InsnField{
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2116147200, Generator: nil},
+	{Name: "UCVTF (vector, integer)", OpcodeMask: 3217030144, Opcode: 773969920, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773969920, Generator: nil},
+	{Name: "UCVTF (scalar, fixed-point)", OpcodeMask: 4294901760, Opcode: 503513088, Fields: []InsnField{
+		{"scale", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 503513088, Generator: nil},
+	{Name: "UCVTF (scalar, fixed-point)", OpcodeMask: 4294901760, Opcode: 507707392, Fields: []InsnField{
+		{"scale", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 507707392, Generator: nil},
+	{Name: "UCVTF (scalar, fixed-point)", OpcodeMask: 4294901760, Opcode: 2650996736, Fields: []InsnField{
+		{"scale", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2650996736, Generator: nil},
+	{Name: "UCVTF (scalar, fixed-point)", OpcodeMask: 4294901760, Opcode: 2655191040, Fields: []InsnField{
+		{"scale", 15, 6},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2655191040, Generator: nil},
+	{Name: "UCVTF (scalar, integer)", OpcodeMask: 4294966272, Opcode: 505610240, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 505610240, Generator: nil},
+	{Name: "UCVTF (scalar, integer)", OpcodeMask: 4294966272, Opcode: 509804544, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 509804544, Generator: nil},
+	{Name: "UCVTF (scalar, integer)", OpcodeMask: 4294966272, Opcode: 2653093888, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2653093888, Generator: nil},
+	{Name: "UCVTF (scalar, integer)", OpcodeMask: 4294966272, Opcode: 2657288192, Fields: []InsnField{
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2657288192, Generator: nil},
+	{Name: "UHADD", OpcodeMask: 3206609920, Opcode: 773850112, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773850112, Generator: nil},
+	{Name: "UHSUB", OpcodeMask: 3206609920, Opcode: 773858304, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773858304, Generator: nil},
+	{Name: "UMAX", OpcodeMask: 3206609920, Opcode: 773874688, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773874688, Generator: nil},
+	{Name: "UMAXP", OpcodeMask: 3206609920, Opcode: 773891072, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773891072, Generator: nil},
+	{Name: "UMAXV", OpcodeMask: 3208641536, Opcode: 774940672, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 774940672, Generator: nil},
+	{Name: "UMIN", OpcodeMask: 3206609920, Opcode: 773876736, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773876736, Generator: nil},
+	{Name: "UMINP", OpcodeMask: 3206609920, Opcode: 773893120, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773893120, Generator: nil},
+	{Name: "UMINV", OpcodeMask: 3208641536, Opcode: 775006208, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 775006208, Generator: nil},
+	{Name: "UMLAL, UMLAL2 (by element)", OpcodeMask: 4278252544, Opcode: 788537344, Fields: []InsnField{
+		{"size", 23, 2},
+		{"L", 21, 1},
+		{"M", 20, 1},
+		{"Rm", 19, 4},
+		{"H", 11, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 788537344, Generator: nil},
+	{Name: "UMLAL, UMLAL2 (by element)", OpcodeMask: 4278252544, Opcode: 1862279168, Fields: []InsnField{
+		{"size", 23, 2},
+		{"L", 21, 1},
+		{"M", 20, 1},
+		{"Rm", 19, 4},
+		{"H", 11, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1862279168, Generator: nil},
+	{Name: "UMLAL, UMLAL2 (vector)", OpcodeMask: 4280351744, Opcode: 773881856, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773881856, Generator: nil},
+	{Name: "UMLAL, UMLAL2 (vector)", OpcodeMask: 4280351744, Opcode: 1847623680, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1847623680, Generator: nil},
+	{Name: "UMLSL, UMLSL2 (by element)", OpcodeMask: 4278252544, Opcode: 788553728, Fields: []InsnField{
+		{"size", 23, 2},
+		{"L", 21, 1},
+		{"M", 20, 1},
+		{"Rm", 19, 4},
+		{"H", 11, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 788553728, Generator: nil},
+	{Name: "UMLSL, UMLSL2 (by element)", OpcodeMask: 4278252544, Opcode: 1862295552, Fields: []InsnField{
+		{"size", 23, 2},
+		{"L", 21, 1},
+		{"M", 20, 1},
+		{"Rm", 19, 4},
+		{"H", 11, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1862295552, Generator: nil},
+	{Name: "UMLSL, UMLSL2 (vector)", OpcodeMask: 4280351744, Opcode: 773890048, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773890048, Generator: nil},
+	{Name: "UMLSL, UMLSL2 (vector)", OpcodeMask: 4280351744, Opcode: 1847631872, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1847631872, Generator: nil},
+	{Name: "UMOV", OpcodeMask: 4292934656, Opcode: 234896384, Fields: []InsnField{
+		{"imm5", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 234896384, Generator: nil},
+	{Name: "UMOV", OpcodeMask: 4292934656, Opcode: 1308638208, Fields: []InsnField{
+		{"imm5", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1308638208, Generator: nil},
+	{Name: "UMULL, UMULL2 (by element)", OpcodeMask: 4278252544, Opcode: 788570112, Fields: []InsnField{
+		{"size", 23, 2},
+		{"L", 21, 1},
+		{"M", 20, 1},
+		{"Rm", 19, 4},
+		{"H", 11, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 788570112, Generator: nil},
+	{Name: "UMULL, UMULL2 (by element)", OpcodeMask: 4278252544, Opcode: 1862311936, Fields: []InsnField{
+		{"size", 23, 2},
+		{"L", 21, 1},
+		{"M", 20, 1},
+		{"Rm", 19, 4},
+		{"H", 11, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1862311936, Generator: nil},
+	{Name: "UMULL, UMULL2 (vector)", OpcodeMask: 4280351744, Opcode: 773898240, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773898240, Generator: nil},
+	{Name: "UMULL, UMULL2 (vector)", OpcodeMask: 4280351744, Opcode: 1847640064, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1847640064, Generator: nil},
+	{Name: "UQADD", OpcodeMask: 4280351744, Opcode: 2116029440, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2116029440, Generator: nil},
+	{Name: "UQADD", OpcodeMask: 3206609920, Opcode: 773852160, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773852160, Generator: nil},
+	{Name: "UQRSHL", OpcodeMask: 4280351744, Opcode: 2116049920, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2116049920, Generator: nil},
+	{Name: "UQRSHL", OpcodeMask: 3206609920, Opcode: 773872640, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773872640, Generator: nil},
+	{Name: "UQRSHRN, UQRSHRN2", OpcodeMask: 4286643200, Opcode: 2130746368, Fields: []InsnField{
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2130746368, Generator: nil},
+	{Name: "UQRSHRN, UQRSHRN2", OpcodeMask: 4286643200, Opcode: 788569088, Fields: []InsnField{
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 788569088, Generator: nil},
+	{Name: "UQRSHRN, UQRSHRN2", OpcodeMask: 4286643200, Opcode: 1862310912, Fields: []InsnField{
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1862310912, Generator: nil},
+	{Name: "UQSHL (immediate)", OpcodeMask: 4286643200, Opcode: 2130736128, Fields: []InsnField{
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2130736128, Generator: nil},
+	{Name: "UQSHL (immediate)", OpcodeMask: 3212901376, Opcode: 788558848, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 788558848, Generator: nil},
+	{Name: "UQSHL (register)", OpcodeMask: 4280351744, Opcode: 2116045824, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2116045824, Generator: nil},
+	{Name: "UQSHL (register)", OpcodeMask: 3206609920, Opcode: 773868544, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773868544, Generator: nil},
+	{Name: "UQSHRN, UQSHRN2", OpcodeMask: 4286643200, Opcode: 2130744320, Fields: []InsnField{
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2130744320, Generator: nil},
+	{Name: "UQSHRN, UQSHRN2", OpcodeMask: 4286643200, Opcode: 788567040, Fields: []InsnField{
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 788567040, Generator: nil},
+	{Name: "UQSHRN, UQSHRN2", OpcodeMask: 4286643200, Opcode: 1862308864, Fields: []InsnField{
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1862308864, Generator: nil},
+	{Name: "UQSUB", OpcodeMask: 4280351744, Opcode: 2116037632, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2116037632, Generator: nil},
+	{Name: "UQSUB", OpcodeMask: 3206609920, Opcode: 773860352, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773860352, Generator: nil},
+	{Name: "UQXTN, UQXTN2", OpcodeMask: 4282383360, Opcode: 2116110336, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2116110336, Generator: nil},
+	{Name: "UQXTN, UQXTN2", OpcodeMask: 4282383360, Opcode: 773933056, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773933056, Generator: nil},
+	{Name: "UQXTN, UQXTN2", OpcodeMask: 4282383360, Opcode: 1847674880, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1847674880, Generator: nil},
+	{Name: "URECPE", OpcodeMask: 3217030144, Opcode: 245483520, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 245483520, Generator: nil},
+	{Name: "URHADD", OpcodeMask: 3206609920, Opcode: 773854208, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773854208, Generator: nil},
+	{Name: "URSHL", OpcodeMask: 4280351744, Opcode: 2116047872, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2116047872, Generator: nil},
+	{Name: "URSHL", OpcodeMask: 3206609920, Opcode: 773870592, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773870592, Generator: nil},
+	{Name: "URSHR", OpcodeMask: 4286643200, Opcode: 2130715648, Fields: []InsnField{
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2130715648, Generator: nil},
+	{Name: "URSHR", OpcodeMask: 3212901376, Opcode: 788538368, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 788538368, Generator: nil},
+	{Name: "URSQRTE", OpcodeMask: 3217030144, Opcode: 782354432, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"sz", 22, 1},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 782354432, Generator: nil},
+	{Name: "URSRA", OpcodeMask: 4286643200, Opcode: 2130719744, Fields: []InsnField{
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2130719744, Generator: nil},
+	{Name: "URSRA", OpcodeMask: 3212901376, Opcode: 788542464, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 788542464, Generator: nil},
+	{Name: "USHL", OpcodeMask: 4280351744, Opcode: 2116043776, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2116043776, Generator: nil},
+	{Name: "USHL", OpcodeMask: 3206609920, Opcode: 773866496, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773866496, Generator: nil},
+	{Name: "USHLL, USHLL2", OpcodeMask: 4286643200, Opcode: 788571136, Fields: []InsnField{
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 788571136, Generator: nil},
+	{Name: "USHLL, USHLL2", OpcodeMask: 4286643200, Opcode: 1862312960, Fields: []InsnField{
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1862312960, Generator: nil},
+	{Name: "USHR", OpcodeMask: 4286643200, Opcode: 2130707456, Fields: []InsnField{
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2130707456, Generator: nil},
+	{Name: "USHR", OpcodeMask: 3212901376, Opcode: 788530176, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 788530176, Generator: nil},
+	{Name: "USQADD", OpcodeMask: 4282383360, Opcode: 2116040704, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2116040704, Generator: nil},
+	{Name: "USQADD", OpcodeMask: 3208641536, Opcode: 773863424, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773863424, Generator: nil},
+	{Name: "USRA", OpcodeMask: 4286643200, Opcode: 2130711552, Fields: []InsnField{
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 2130711552, Generator: nil},
+	{Name: "USRA", OpcodeMask: 3212901376, Opcode: 788534272, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"immh", 22, 4},
+		{"immb", 18, 3},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 788534272, Generator: nil},
+	{Name: "USUBL, USUBL2", OpcodeMask: 4280351744, Opcode: 773857280, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773857280, Generator: nil},
+	{Name: "USUBL, USUBL2", OpcodeMask: 4280351744, Opcode: 1847599104, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1847599104, Generator: nil},
+	{Name: "USUBW, USUBW2", OpcodeMask: 4280351744, Opcode: 773861376, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 773861376, Generator: nil},
+	{Name: "USUBW, USUBW2", OpcodeMask: 4280351744, Opcode: 1847603200, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1847603200, Generator: nil},
+	{Name: "UXTL, UXTL2", OpcodeMask: 4287101952, Opcode: 788571136, Fields: []InsnField{
+		{"immh", 22, 4},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 788571136, Generator: nil},
+	{Name: "UXTL, UXTL2", OpcodeMask: 4287101952, Opcode: 1862312960, Fields: []InsnField{
+		{"immh", 22, 4},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1862312960, Generator: nil},
+	{Name: "UZP1", OpcodeMask: 3206609920, Opcode: 234887168, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 234887168, Generator: nil},
+	{Name: "UZP2", OpcodeMask: 3206609920, Opcode: 234903552, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 234903552, Generator: nil},
+	{Name: "XTN, XTN2", OpcodeMask: 4282383360, Opcode: 237053952, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 237053952, Generator: nil},
+	{Name: "XTN, XTN2", OpcodeMask: 4282383360, Opcode: 1310795776, Fields: []InsnField{
+		{"size", 23, 2},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 1310795776, Generator: nil},
+	{Name: "ZIP1", OpcodeMask: 3206609920, Opcode: 234895360, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 234895360, Generator: nil},
+	{Name: "ZIP2", OpcodeMask: 3206609920, Opcode: 234911744, Fields: []InsnField{
+		{"Q", 30, 1},
+		{"size", 23, 2},
+		{"Rm", 20, 5},
+		{"Rn", 9, 5},
+		{"Rd", 4, 5},
+	}, AsUInt32: 234911744, Generator: nil},
+}
diff --git a/pkg/ifuzz/arm64/pseudo.go b/pkg/ifuzz/arm64/pseudo.go
new file mode 100644
index 000000000..a99842515
--- /dev/null
+++ b/pkg/ifuzz/arm64/pseudo.go
@@ -0,0 +1,73 @@
+// Copyright 2024 syzkaller project authors. All rights reserved.
+// Use of this source code is governed by Apache 2 LICENSE that can be found in the LICENSE file.
+
+// Pseudo instructions for arm64 architecture.
+
+package arm64
+
+import (
+	"math/rand"
+
+	"github.com/google/syzkaller/pkg/ifuzz/iset"
+)
+
+var pseudo = []*Insn{
+	{
+		Name:   "PSEUDO_HCALL",
+		Pseudo: true,
+		Priv:   true,
+		Generator: func(cfg *iset.Config, r *rand.Rand) []byte {
+			gen := makeGen(cfg, r)
+			gen.smcccHvc()
+			return gen.text
+		},
+	},
+}
+
+type generator struct {
+	r    *rand.Rand
+	text []byte
+}
+
+func makeGen(cfg *iset.Config, r *rand.Rand) *generator {
+	return &generator{
+		r: r,
+	}
+}
+
+func (gen *generator) smcccHvc() {
+	cmd := (1 << 31) | (gen.r.Intn(2) << 30) | ((gen.r.Intn(8) & 0x3F) << 24) | (gen.r.Intn(0x10000) & 0xFFFF)
+	gen.movRegImm32(0, cmd)
+	gen.movRegImm16(1, gen.r.Intn(16))
+	gen.movRegImm16(2, gen.r.Intn(16))
+	gen.movRegImm16(3, gen.r.Intn(16))
+	gen.movRegImm16(4, gen.r.Intn(16))
+	gen.byte(0x02, 0x00, 0x00, 0xd4)
+}
+
+func (gen *generator) movRegImm32(reg, imm int) {
+	gen.movRegImm16(reg, imm)
+	// Encoding `movk reg, imm16, LSL #16`.
+	upper := (imm >> 16) & 0xffff
+	opcode := uint32(0xf2a00000)
+	opcode |= uint32(upper) << 5
+	opcode |= uint32(reg & 0xf)
+	gen.imm32(opcode)
+}
+
+func (gen *generator) movRegImm16(reg, imm int) {
+	// Encoding `mov reg, imm16`.
+	imm = imm & 0xffff
+	opcode := uint32(0xd2800000)
+	opcode |= uint32(imm) << 5
+	opcode |= uint32(reg & 0xf)
+	gen.imm32(opcode)
+}
+
+func (gen *generator) imm32(v uint32) {
+	gen.byte(byte(v>>0), byte(v>>8), byte(v>>16), byte(v>>24))
+}
+
+func (gen *generator) byte(v ...uint8) {
+	gen.text = append(gen.text, v...)
+}
diff --git a/pkg/ifuzz/arm64/util.go b/pkg/ifuzz/arm64/util.go
new file mode 100644
index 000000000..8686c0122
--- /dev/null
+++ b/pkg/ifuzz/arm64/util.go
@@ -0,0 +1,9 @@
+// Copyright 2024 syzkaller project authors. All rights reserved.
+// Use of this source code is governed by Apache 2 LICENSE that can be found in the LICENSE file.
+
+package arm64
+
+func extractBits(from uint32, start, size uint) uint32 {
+	mask := uint32((1 << size) - 1)
+	return (from >> (start - size + 1)) & mask
+}
diff --git a/pkg/ifuzz/arm64/util_test.go b/pkg/ifuzz/arm64/util_test.go
new file mode 100644
index 000000000..520b86e65
--- /dev/null
+++ b/pkg/ifuzz/arm64/util_test.go
@@ -0,0 +1,26 @@
+// Copyright 2024 syzkaller project authors. All rights reserved.
+// Use of this source code is governed by Apache 2 LICENSE that can be found in the LICENSE file.
+
+package arm64
+
+import (
+	"testing"
+)
+
+func extractBitsOne(t *testing.T, from uint32, start, size uint, expect uint32) {
+	ret := extractBits(from, start, size)
+	if ret != expect {
+		t.Fatalf("extractBits(%x, %d, %d) returned %x instead of %x", from, start, size, ret, expect)
+	}
+}
+
+func TestExtractBits(t *testing.T) {
+	extractBitsOne(t, 0, 0, 0, 0)
+	extractBitsOne(t, 0xffffffff, 0, 0, 0)
+	for i := uint(0); i <= 31; i++ {
+		extractBitsOne(t, 0xffffffff, i, 1, 1)
+	}
+	extractBitsOne(t, 0xf0f0f0f0, 31, 5, 0b11110)
+	extractBitsOne(t, 0xf0f0f0f0, 25, 4, 0b0011)
+	extractBitsOne(t, 0xf0f0f0f0, 21, 4, 0b1100)
+}
diff --git a/pkg/ifuzz/arm64_test.go b/pkg/ifuzz/arm64_test.go
new file mode 100644
index 000000000..7aae73a85
--- /dev/null
+++ b/pkg/ifuzz/arm64_test.go
@@ -0,0 +1,94 @@
+// Copyright 2024 syzkaller project authors. All rights reserved.
+// Use of this source code is governed by Apache 2 LICENSE that can be found in the LICENSE file.
+
+package ifuzz
+
+import (
+	"encoding/binary"
+	"encoding/hex"
+	"fmt"
+	"strconv"
+	"testing"
+
+	"github.com/google/syzkaller/pkg/ifuzz/arm64"
+	"github.com/google/syzkaller/pkg/ifuzz/iset"
+)
+
+func PrintInsn(insn arm64.Insn) {
+	operands := ""
+	for i, op := range insn.Operands {
+		field := insn.Fields[i]
+		operands += fmt.Sprintf("%s:%d=%x ", field.Name, field.Length, op)
+	}
+	fmt.Printf("{ \"%s\" [0x%x] %s }\n", insn.Name, insn.AsUInt32, operands)
+}
+
+func parseAndPrint(from uint32) {
+	insn, _ := arm64.ParseInsn(from)
+	PrintInsn(insn)
+}
+
+func TestSomething(t *testing.T) {
+	parseAndPrint(0x0)
+	parseAndPrint(0xff3ffc00)
+	parseAndPrint(0x5e20b800)
+	parseAndPrint(0x52800021)
+	parseAndPrint(0x1b020020)
+	parseAndPrint(0x1b007c21)
+	parseAndPrint(0xb9400fe0)
+}
+
+func TestSum(t *testing.T) {
+	data := [][2]string{
+		{"d10043ff", "sub	sp, sp, #0x10"},
+		{"b9000fe0", "str	w0, [sp, #12]"},
+		{"b9000be1", "str	w1, [sp, #8]"},
+		{"b90007e2", "str	w2, [sp, #4]"},
+		{"b9400be1", "ldr	w1, [sp, #8]"},
+		{"b94007e0", "ldr	w0, [sp, #4]"},
+		{"1b007c21", "mul	w1, w1, w0"},
+		{"b9400fe0", "ldr	w0, [sp, #12]"},
+		{"0b000020", "add	w0, w1, w0"},
+		{"910043ff", "add	sp, sp, #0x10"},
+		{"d65f03c0", "ret"},
+	}
+	for _, pair := range data {
+		opcode, err := strconv.ParseUint(pair[0], 16, 32)
+		if err != nil {
+			t.Fatalf("failed to parse opcode")
+		}
+		fmt.Printf("%s\n", pair[1])
+		parseAndPrint(uint32(opcode))
+	}
+}
+
+func TestDecodeSamples(t *testing.T) {
+	testData := []string{
+		"2000000b",
+		"0000409b000028d5007008d5008080880000000e0038201e007008d5000028d50020000c0000181e",
+		"000cc0380094002f0100a0d40000600d000880b8000000fa0000208a000c40380068284e000008d5",
+		// x0[*x1] = *x2
+		"280080b9490040b9097828b8",
+		// hvc(x0, x1, x2, x3, x4)
+		"e00180d2210080d2420080d2630080d2840080d2020000d4",
+		"20e09fd200c0b0f2210080d2420080d2630080d2840080d2020000d4",
+		"000080d200c0b0f2210080d2420080d2630080d2840080d2020000d4",
+	}
+	insnset := iset.Arches["arm64"]
+	for _, str := range testData {
+		text, err := hex.DecodeString(str)
+		fmt.Printf("Decoding % x\n", text)
+		if err != nil {
+			t.Fatalf("invalid hex string")
+		}
+		for len(text) != 0 {
+			size, err := insnset.Decode(iset.ModeLong64, text)
+			if size == 0 || err != nil {
+				t.Errorf("failed to decode text: %v", text)
+				break
+			}
+			parseAndPrint(binary.LittleEndian.Uint32(text[0:4]))
+			text = text[size:]
+		}
+	}
+}
diff --git a/pkg/ifuzz/ifuzz.go b/pkg/ifuzz/ifuzz.go
index 01137b6ea..d33717d5d 100644
--- a/pkg/ifuzz/ifuzz.go
+++ b/pkg/ifuzz/ifuzz.go
@@ -6,6 +6,7 @@ package ifuzz
 import (
 	"math/rand"
 
+	_ "github.com/google/syzkaller/pkg/ifuzz/arm64/generated" // pull in generated instruction descriptions
 	"github.com/google/syzkaller/pkg/ifuzz/iset"
 	_ "github.com/google/syzkaller/pkg/ifuzz/powerpc/generated" // pull in generated instruction descriptions
 	_ "github.com/google/syzkaller/pkg/ifuzz/x86/generated"     // pull in generated instruction descriptions
@@ -20,6 +21,7 @@ type (
 const (
 	ArchX86     = iset.ArchX86
 	ArchPowerPC = iset.ArchPowerPC
+	ArchArm64   = iset.ArchArm64
 	ModeLong64  = iset.ModeLong64
 	ModeProt32  = iset.ModeProt32
 	ModeProt16  = iset.ModeProt16
diff --git a/pkg/ifuzz/ifuzz_test.go b/pkg/ifuzz/ifuzz_test.go
index 79d7bab5d..38863cdbd 100644
--- a/pkg/ifuzz/ifuzz_test.go
+++ b/pkg/ifuzz/ifuzz_test.go
@@ -12,7 +12,7 @@ import (
 	"github.com/google/syzkaller/pkg/testutil"
 )
 
-var allArches = []string{ArchX86, ArchPowerPC}
+var allArches = []string{ArchX86, ArchPowerPC, ArchArm64}
 
 func TestMode(t *testing.T) {
 	for _, arch := range allArches {
diff --git a/pkg/ifuzz/iset/iset.go b/pkg/ifuzz/iset/iset.go
index 65c79a500..83afe67c1 100644
--- a/pkg/ifuzz/iset/iset.go
+++ b/pkg/ifuzz/iset/iset.go
@@ -11,6 +11,7 @@ import (
 const (
 	ArchX86     = "x86"
 	ArchPowerPC = "powerpc"
+	ArchArm64   = "arm64"
 )
 
 var Arches = make(map[string]InsnSet)