pkg/ifuzz/powerpc: update few broken instructions

The source PowerISA latex files have updated so refresh the instruction
list. The fixed are not used by syzkaller in macros so there should be
no huge change in behaviour, if any.

While at this, simplify+comment the conversion script and fix handling of
privileged instructions, apparently a debug version of the convertion
script made it to the git repo.

Signed-off-by: Alexey Kardashevskiy <aik@linux.ibm.com>

2 files changed, 193 insertions, 204 deletions

diff --git a/pkg/ifuzz/powerpc/gen/powerisa31_tex_to_syz b/pkg/ifuzz/powerpc/gen/powerisa31_tex_to_syz
index f2c1c8b71..585d9b7ea 100755
--- a/pkg/ifuzz/powerpc/gen/powerisa31_tex_to_syz
+++ b/pkg/ifuzz/powerpc/gen/powerisa31_tex_to_syz
@@ -21,81 +21,97 @@ def read_file(fname):
 	f.close()
 	return ret
 
+# Returns map<str, str>:  'layoutxxivbform': ([6, 5, 5, 5, 5, 2, 1, 1, 1, 1],
+#	[None, 'T', A', 'B', 'C', None, 'CX', 'AX', 'BX'm 'TX'])
 def get_layouts(layout_file):
 	layout_content = read_file(layout_file)
-	cur_layout = ""
 	last_comment = ""
 	layouts = {}
-	for i in range(len(layout_content)):
-		cur = layout_content[i]
+	for cur in layout_content:
 		if len(cur) > 0 and cur[0] == '%':
 			last_comment = re.sub(r'(^%|bits.*$)', "", cur).strip()
 			continue
-		# \newcommand{\layoutiform}[4]{
 		l = re.match(r'\\newcommand{\\(layout\w+)}.*{', cur)
 		if l:
-			cur_layout = l.group(1)
-			layouts[cur_layout] = last_comment
-			continue
+			a = last_comment.split(" ")
+			pos = []
+			names = []
+			for a1 in a:
+				tmp = re.match(r'(\d+)<(\S+)>', a1)
+				if tmp:
+					pos += [int(tmp.group(1), 10)]
+					names += [tmp.group(2)]
+					continue
+				pos += [int(a1, 10)]
+				names += [None]
+			layouts[l.group(1)] = (pos, names)
+#	pe.pprint(layouts)
 	return layouts
 
-def add_insns(st, l):
-	if len(l) != 1 and len(l) != 2:
-		pe.pprint("!!!Error: broken layout {} for {}".format(l, st))
-		sys.exit(-1)
-	r = {}
-# These lines enable/disable prefixed instrustions
-#	if len(l) != 1:
-#		return r
-	for ins in st:
-		tmp = ins[0].split(" ", 1)
-		r[tmp[0]] = ins[1]
-		r[tmp[0]]["layout"] = l
-		if len(tmp) > 1:
-			r[tmp[0]]["par"] = tmp[1]
-	return r
-
-def sanitize_layout(a, b):
-	a = a.strip().split(" ")
-	b = re.findall(r'{([^}]*)}', b)
-	aa = []
+# Expands names of fields
+# (list<n>, list<n>), string -> list<n>
+def complete_layout(layout, insn_layout):
 	bb = []
 	b_ = 0
-	for a1 in a:
-		tmp = re.match(r'(\d+)<(\S+)>', a1)
-		if tmp:
-			aa += [int(tmp.group(1), 10)]
-			bb += [tmp.group(2)]
+	b = re.findall(r'{([^}]*)}', insn_layout)
+	for i in range(len(layout[0])):
+		if layout[1][i]:
+			bb += [layout[1][i]]
 			continue
-		aa += [int(a1, 10)]
-		bb += [re.sub(r'[{}]+', "", b[b_])]
+
+		# "pnop" is special: {any value\textsuperscript{*}
+		tmpname = re.sub(r'([{}?]+|any value\\textsuperscript{\*)', "", b[b_])
+		tmpname = re.sub(r'/+', '/', tmpname)
+		bb += [tmpname]
 		b_ += 1
-	if b_ != len(b) or len(aa) != len(bb):
-		pe.pprint("!!!error: broken layout {} --- {} --- {}".format(aa, bb, b_))
-		sys.exit(-1)
-	return aa, bb
+	return bb
 
+# Finds instructions in a latex file
+# Returns map<str, list>:
+# 'addc.': [([6, 5, 5, 5, 1, 9, 1], ['31', 'RT', 'RA', 'RB', 'OE', '10', 'Rc'], [-1, -1, -1, -1, 0, -1, 1])],
+# layouts: array of tuples
 def find_insns(tex_file, layouts):
+
+	def add_insns(insn_list, layout):
+		if len(layout) != 1 and len(layout) != 2:
+			pe.pprint("!!!Error: broken layout {} for {}".format(layout, insn_list))
+			sys.exit(-1)
+		r = {}
+		for ins in insn_list:
+			tmp = ins.split(" ", 1)
+
+			ll = []
+			for l in layout:
+				par = []
+				for j in range(len(l[1])):
+					defval = -1
+					# This is dealing with OE/Rc from "addc. RT,RA,RB (OE=0 Rc=1)"
+					if len(tmp) > 1 and ('?' not in l[1][j]):
+						ptmp = re.match(r'.*{}=(\d).*'.format(l[1][j]), tmp[1])
+						if ptmp:
+							defval = int(ptmp.group(1), 10)
+					par += [defval]
+				ll += [(l[0], l[1], par)]
+			pe.pprint("{}".format(tmp[0]))
+			r[tmp[0]] = ll
+		return r
+
 	tex_content = read_file(tex_file)
-	cur_insn_name = ""
-	cur_insn = {}
 	ret = {}
 	layout = []
-	insns_stack = []
-	for i in range(len(tex_content)):
-		cur = tex_content[i]
+	insn_list = []
+	for cur in tex_content:
 		# \instrsyntax{pmxvf16ger2np AT,XA,XB,XMSK,YMSK,PMSK}
 		l = re.match(r'\\instrsyntax{(.*)}', cur)
 		if l:
-			if insns_stack != [] and layout != []:
-				ret.update(add_insns(insns_stack, layout))
-				insns_stack = []
+			if insn_list != [] and layout != []:
+				ret.update(add_insns(insn_list, layout))
+				insn_list = []
 				layout = []
 
-			cur_insn_name = l.group(1)
-			insns_stack += [(cur_insn_name, {"loc": "{}:{}".format(tex_file.rsplit("/", 1)[-1], i)})]
+			insn_list += [l.group(1)]
 			continue
-		if not insns_stack:
+		if not insn_list:
 			continue
 
 		# \layoutxxiiidform{59}{AT}{//}{A}{B}{82}{AX}{BX}{/}
@@ -104,134 +120,110 @@ def find_insns(tex_file, layouts):
 			if len(layout) > 2:
 				pe.pprint("! Wrong layout")
 				sys.exit(-1)
-			layout += [sanitize_layout(layouts[l.group(1)], l.group(2))]
+			layout += [(layouts[l.group(1)][0],
+				complete_layout(layouts[l.group(1)], l.group(2)))]
 
 	if layout:
-		ret.update(add_insns(insns_stack, layout))
+		ret.update(add_insns(insn_list, layout))
 
 	return ret
 
+# Extracts priv. flag from Table H.1: Power ISA Instruction Set Sorted by Mnemonic
+# Returns priv insns list
 def collect_priv(tex_file, insns):
 	tex_cont = read_file(tex_file)
-	for i in range(len(tex_cont)):
-		cur = tex_cont[i]
-		ins = cur.split('}', 1)[0]
-		if ins not in insns:
+	ret = []
+	cur = ""
+	for tcur in tex_cont:
+		if tcur != '\hline':
+			cur += tcur
 			continue
-		l = re.match(r'^{}}}.+\\small (P|H|HV|HV\/P|UV|64)}}&.*'.format(ins), cur)
-		if not l:
-			continue
-		insns[ins]["Priv"] = True
-
-def ppcmask(val, start, len):
-	return (val & ((1 << len) - 1)) << (31 - (start + len - 1))
+		# Merge all lines between \hline and split by tab (which '&' in latex)
+		cur = re.sub(r'\\&', 'AND', cur) # but '&' may occur in the instruction name
+		tmp = cur.split('&')
+		if len(tmp) == 11:
+			ins = re.sub(r'.*{([^{}]+)}$', r'\1', tmp[5])
+			if ins in insns:
+				if re.match(r'.+{(P|H|HV|HV\/P|UV|64)}$', tmp[7]):
+					ret += [ins]
+			cur = ""
+	return ret
 
-fixed_cases = {}
-def add_fixed(field, ins):
-	global fixed_cases
-	if field not in fixed_cases:
-		fixed_cases[field] = []
-	fixed_cases[field] += [ins]
-def print_fixed():
-	pe.pprint(fixed_cases)
+def generate_go(insns, priv):
+	def ppcmask(val, start, len):
+		return (val & ((1 << len) - 1)) << (31 - (start + len - 1))
 
-def generate_go(insns):
 	def generate_opcode(ins, layout):
+		pos_, names_, defval_ = layout[0], layout[1], layout[2]
 		opcode = 0
 		opmask = 0
-		fields = ""
 		pos = 0
 		bits = 0
 		fields = {}
-		for i in range(len(layout[0])):
+		for i in range(len(pos_)):
 			pos += bits
-			bits = layout[0][i]
+			bits = pos_[i]
 
-			# "pnop" is special
-			if layout[1][i].replace('any value\\textsuperscript*', '') == '':
+			# Fields marked `/` must be 0
+			if names_[i] == '/':
+				opmask |= ppcmask(0xffffffff, pos, pos_[i])
 				continue
 
-			if layout[1][i].replace('/', '') == '':
-				opmask |= ppcmask(0xffffffff, pos, layout[0][i])
-				continue
-
-			if layout[1][i].replace('?', '') == '':
-				opmask |= ppcmask(0xffffffff, pos, layout[0][i])
+			if names_[i] == '':
 				continue
 
 			try:
-				num = int(layout[1][i], 10)
-				opcode |= ppcmask(num, pos, layout[0][i])
-				opmask |= ppcmask(0xffffffff, pos, layout[0][i])
+				num = int(names_[i], 10)
+				opcode |= ppcmask(num, pos, pos_[i])
+				opmask |= ppcmask(0xffffffff, pos, pos_[i])
 				continue
 			except:
 				pass
 
-			if 'par' in ival:
-				tmp = re.match(r'.*{}=(\d).*'.format(layout[1][i]), ival['par'])
-				if tmp:
-					opcode |= ppcmask(int(tmp.group(1), 10), pos, layout[0][i])
-					opmask |= ppcmask(0xffffffff, pos, layout[0][i])
-					continue
+			if defval_[i] >= 0:
+				opcode |= ppcmask(defval_[i], pos, pos_[i])
+				opmask |= ppcmask(0xffffffff, pos, pos_[i])
+				continue
 
-			if layout[1][i] not in fields:
-				fields[layout[1][i]] = []
-			fields[layout[1][i]] += [(pos, layout[0][i])]
+			fval = [(pos, pos_[i])]
+			if (ins in ['rldcl', 'rldcl.', 'rldic', 'rldic.', 'rldicl', 'rldicl.',
+				'rldimi', 'rldimi.', 'rldcr', 'rldcr.', 'rldicr', 'rldicr.'] and
+				names_[i] in ["me", "mb"] and fval == [(21, 6)]):
+				fval = [(21, 5), (26, 1)]
+			elif ins in ['mfspr', 'mtspr'] and names_[i] == "spr" and fval == [(11, 10)]:
+				fval = [(16, 5), (11, 5)]
+
+			if names_[i] not in fields:
+				fields[names_[i]] = []
+			fields[names_[i]] += fval
 
-		# Fix up fields
-		for f in fields:
-			if (ins in ['mtvsrbmi', 'addpcis', 'xvtstdcdp', 'xvtstdcsp', 'mftb'] and
-				f in [
-				"b0", "b1", "b2", # mtvsrbmi
-				"dx", "dc", "dm", # xvtstdcdp
-				"d0", "d1", "d2", # addpcis
-				"tbr", # mftb
-				]):
-				add_fixed(f, ins)
-				continue
-			if (ins in ['extswsli', 'extswsli.', 'rldic', 'rldic.', 'rldicl', 'rldicl.', 'rldicr', 'rldicr.', 'rldimi', 'rldimi.', 'sradi', 'sradi.'] and
-				f in ["sh"] and fields[f] == [(16, 5), (30, 1)]):
-				add_fixed(f, ins)
-				continue
-			if (ins in ['rldcl', 'rldcl.', 'rldic', 'rldic.', 'rldicl', 'rldicl.', 'rldimi', 'rldimi.', 'rldcr', 'rldcr.', 'rldicr', 'rldicr.'] and
-				f in ["me", "mb"] and fields[f] == [(21, 6)]): # rldicr
-				add_fixed(f, ins)
-				fields[f] = [(21, 5), (26, 1)]
-				continue
-			if ins in ['mfspr', 'mtspr'] and f == "spr" and fields[f] == [(11, 10)]: # mfspr
-				add_fixed(f, ins)
-				fields[f] = [(16, 5), (11, 5)]
-				continue
-			if re.match(r'[a-z]+', f):
-				add_fixed(f, ins)
-				continue
 
+		# Fix up fields
 		fields_str = ""
-		for fkey, fval_ in sorted(fields.items()):
+		for f, fval in sorted(fields.items()):
 			fields_str += '{'
-			fields_str += 'Name: "{}", Bits: []powerpc.InsnBits'.format(fkey)
+			fields_str += 'Name: "{}", Bits: []powerpc.InsnBits'.format(f)
 			fields_str += '{'
-			for fval in fval_:
-				fields_str += '{{{}, {}}}, '.format(fval[0], fval[1])
-				if int(fval[1]) == 0:
+			for ff in fval:
+				fields_str += '{{{}, {}}}, '.format(ff[0], ff[1])
+				if ff[1] == 0:
 					pe.pprint("!Wrong length!")
 					sys.exit(-1)
 			fields_str = fields_str[:-2] + '}}, '
 
 		return opcode, opmask, fields_str[:-2]
 
-	for ins, ival in sorted(insns.items()):#, key: lambda x: insns[x].opcode):
+	for ins, ival in sorted(insns.items()):
 		tmp = '\t{Name: "'
 		tmp += ins
 		tmp += '", '
-		if len(ival['layout']) >= 1:
-			opcode, opmask, fields = generate_opcode(ins, ival['layout'][0])
-			if "Priv" in ival:
-				tmp += 'Opcode: 0x{:08x}, Mask: 0x{:08x}, Priv: true, Fields: []powerpc.InsnField{{{}}}'.format(opcode, opmask, fields)
-			else:
-				tmp += 'Opcode: 0x{:08x}, Mask: 0x{:08x}, Fields: []powerpc.InsnField{{{}}}'.format(opcode, opmask, fields)
-		if len(ival['layout']) == 2:
-			opcode, opmask, fields = generate_opcode(ins, ival['layout'][1])
+		if len(ival) >= 1:
+			opcode, opmask, fields = generate_opcode(ins, ival[0])
+			tmp += 'Opcode: 0x{:08x}, Mask: 0x{:08x}, Fields: []powerpc.InsnField{{{}}}'.format(opcode, opmask, fields)
+			if ins in priv:
+				tmp += ', Priv: true'
+		if len(ival) == 2:
+			opcode, opmask, fields = generate_opcode(ins, ival[1])
 			tmp += ',\n\t\tOpcodeSuffix: 0x{:08x}, MaskSuffix: 0x{:08x}, FieldsSuffix: []powerpc.InsnField{{{}}}'.format(opcode, opmask, fields)
 
 		tmp += "},"
@@ -245,8 +237,6 @@ insns = {}
 for tex in texfiles:
 	insns.update(find_insns(tex, layouts))
 
-collect_priv(isa_dir + "/Appendices/PPC_ApInstMnem.tex", insns)
-
 print('// Code generated by {}. DO NOT EDIT.'.format(sys.argv[0]))
 print('')
 print('//go:build !codeanalysis')
@@ -261,8 +251,7 @@ print('\tpowerpc.Register(insns)')
 print('}')
 print('')
 print('var insns = []*powerpc.Insn{')
-generate_go(insns)
+generate_go(insns, collect_priv(isa_dir + "/Appendices/PPC_ApInstMnem.tex", insns))
 print("}")
 
 pe.pprint("Processed {} instructions".format(len(insns)))
-print_fixed()
diff --git a/pkg/ifuzz/powerpc/generated/insns.go b/pkg/ifuzz/powerpc/generated/insns.go
index 909ad4a89..3c487fc1b 100644
--- a/pkg/ifuzz/powerpc/generated/insns.go
+++ b/pkg/ifuzz/powerpc/generated/insns.go
@@ -1,4 +1,4 @@
-// Code generated by ./powerisa31_tex_to_syz. DO NOT EDIT.
+// Code generated by ./pkg/ifuzz/powerpc/gen/powerisa31_tex_to_syz. DO NOT EDIT.
 
 //go:build !codeanalysis
 // +build !codeanalysis
@@ -347,28 +347,28 @@ var insns = []*powerpc.Insn{
 	{Name: "ftdiv", Opcode: 0xfc000100, Mask: 0xfc6007ff, Fields: []powerpc.InsnField{{Name: "BF", Bits: []powerpc.InsnBits{{6, 3}}}, {Name: "FRA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "FRB", Bits: []powerpc.InsnBits{{16, 5}}}}},
 	{Name: "ftsqrt", Opcode: 0xfc000140, Mask: 0xfc7f07ff, Fields: []powerpc.InsnField{{Name: "BF", Bits: []powerpc.InsnBits{{6, 3}}}, {Name: "FRB", Bits: []powerpc.InsnBits{{16, 5}}}}},
 	{Name: "hashchk", Opcode: 0x7c0005e4, Mask: 0xfc0007fe, Fields: []powerpc.InsnField{{Name: "D", Bits: []powerpc.InsnBits{{6, 5}}}, {Name: "DX", Bits: []powerpc.InsnBits{{31, 1}}}, {Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}}},
-	{Name: "hashchkp", Opcode: 0x7c000564, Mask: 0xfc0007fe, Priv: true, Fields: []powerpc.InsnField{{Name: "D", Bits: []powerpc.InsnBits{{6, 5}}}, {Name: "DX", Bits: []powerpc.InsnBits{{31, 1}}}, {Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}}},
+	{Name: "hashchkp", Opcode: 0x7c000564, Mask: 0xfc0007fe, Fields: []powerpc.InsnField{{Name: "D", Bits: []powerpc.InsnBits{{6, 5}}}, {Name: "DX", Bits: []powerpc.InsnBits{{31, 1}}}, {Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}}, Priv: true},
 	{Name: "hashst", Opcode: 0x7c0005a4, Mask: 0xfc0007fe, Fields: []powerpc.InsnField{{Name: "D", Bits: []powerpc.InsnBits{{6, 5}}}, {Name: "DX", Bits: []powerpc.InsnBits{{31, 1}}}, {Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}}},
-	{Name: "hashstp", Opcode: 0x7c000524, Mask: 0xfc0007fe, Priv: true, Fields: []powerpc.InsnField{{Name: "D", Bits: []powerpc.InsnBits{{6, 5}}}, {Name: "DX", Bits: []powerpc.InsnBits{{31, 1}}}, {Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}}},
-	{Name: "hrfid", Opcode: 0x4c000224, Mask: 0xffffffff, Priv: true, Fields: []powerpc.InsnField{}},
+	{Name: "hashstp", Opcode: 0x7c000524, Mask: 0xfc0007fe, Fields: []powerpc.InsnField{{Name: "D", Bits: []powerpc.InsnBits{{6, 5}}}, {Name: "DX", Bits: []powerpc.InsnBits{{31, 1}}}, {Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}}, Priv: true},
+	{Name: "hrfid", Opcode: 0x4c000224, Mask: 0xffffffff, Fields: []powerpc.InsnField{}, Priv: true},
 	{Name: "icbi", Opcode: 0x7c0007ac, Mask: 0xffe007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}}},
 	{Name: "icbt", Opcode: 0x7c00002c, Mask: 0xfe0007ff, Fields: []powerpc.InsnField{{Name: "CT", Bits: []powerpc.InsnBits{{7, 4}}}, {Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}}},
 	{Name: "isel", Opcode: 0x7c00001e, Mask: 0xfc00003f, Fields: []powerpc.InsnField{{Name: "BC", Bits: []powerpc.InsnBits{{21, 5}}}, {Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
 	{Name: "isync", Opcode: 0x4c00012c, Mask: 0xffffffff, Fields: []powerpc.InsnField{}},
 	{Name: "lbarx", Opcode: 0x7c000068, Mask: 0xfc0007fe, Fields: []powerpc.InsnField{{Name: "EH", Bits: []powerpc.InsnBits{{31, 1}}}, {Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
 	{Name: "lbz", Opcode: 0x88000000, Mask: 0xfc000000, Fields: []powerpc.InsnField{{Name: "D", Bits: []powerpc.InsnBits{{16, 16}}}, {Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
-	{Name: "lbzcix", Opcode: 0x7c0006aa, Mask: 0xfc0007ff, Priv: true, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
+	{Name: "lbzcix", Opcode: 0x7c0006aa, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}, Priv: true},
 	{Name: "lbzu", Opcode: 0x8c000000, Mask: 0xfc000000, Fields: []powerpc.InsnField{{Name: "D", Bits: []powerpc.InsnBits{{16, 16}}}, {Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
-	{Name: "lbzux", Opcode: 0x7c0000ee, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}, {16, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
-	{Name: "lbzx", Opcode: 0x7c0000ae, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}, {16, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
+	{Name: "lbzux", Opcode: 0x7c0000ee, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
+	{Name: "lbzx", Opcode: 0x7c0000ae, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
 	{Name: "ld", Opcode: 0xe8000000, Mask: 0xfc000003, Fields: []powerpc.InsnField{{Name: "DS", Bits: []powerpc.InsnBits{{16, 14}}}, {Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
 	{Name: "ldarx", Opcode: 0x7c0000a8, Mask: 0xfc0007fe, Fields: []powerpc.InsnField{{Name: "EH", Bits: []powerpc.InsnBits{{31, 1}}}, {Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
 	{Name: "ldat", Opcode: 0x7c0004cc, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "FC", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
-	{Name: "ldbrx", Opcode: 0x7c000428, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}, {16, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
-	{Name: "ldcix", Opcode: 0x7c0006ea, Mask: 0xfc0007ff, Priv: true, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
+	{Name: "ldbrx", Opcode: 0x7c000428, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
+	{Name: "ldcix", Opcode: 0x7c0006ea, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}, Priv: true},
 	{Name: "ldu", Opcode: 0xe8000001, Mask: 0xfc000003, Fields: []powerpc.InsnField{{Name: "DS", Bits: []powerpc.InsnBits{{16, 14}}}, {Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
-	{Name: "ldux", Opcode: 0x7c00006a, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}, {16, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
-	{Name: "ldx", Opcode: 0x7c00002a, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}, {16, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
+	{Name: "ldux", Opcode: 0x7c00006a, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
+	{Name: "ldx", Opcode: 0x7c00002a, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
 	{Name: "lfd", Opcode: 0xc8000000, Mask: 0xfc000000, Fields: []powerpc.InsnField{{Name: "D", Bits: []powerpc.InsnBits{{16, 16}}}, {Name: "FRT", Bits: []powerpc.InsnBits{{6, 5}}}, {Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}}},
 	{Name: "lfdp", Opcode: 0xe4000000, Mask: 0xfc000003, Fields: []powerpc.InsnField{{Name: "DS", Bits: []powerpc.InsnBits{{16, 14}}}, {Name: "FRTp", Bits: []powerpc.InsnBits{{6, 5}}}, {Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}}},
 	{Name: "lfdpx", Opcode: 0x7c00062e, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "FRTp", Bits: []powerpc.InsnBits{{6, 5}}}, {Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}}},
@@ -384,14 +384,14 @@ var insns = []*powerpc.Insn{
 	{Name: "lha", Opcode: 0xa8000000, Mask: 0xfc000000, Fields: []powerpc.InsnField{{Name: "D", Bits: []powerpc.InsnBits{{16, 16}}}, {Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
 	{Name: "lharx", Opcode: 0x7c0000e8, Mask: 0xfc0007fe, Fields: []powerpc.InsnField{{Name: "EH", Bits: []powerpc.InsnBits{{31, 1}}}, {Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
 	{Name: "lhau", Opcode: 0xac000000, Mask: 0xfc000000, Fields: []powerpc.InsnField{{Name: "D", Bits: []powerpc.InsnBits{{16, 16}}}, {Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
-	{Name: "lhaux", Opcode: 0x7c0002ee, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}, {16, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
-	{Name: "lhax", Opcode: 0x7c0002ae, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}, {16, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
-	{Name: "lhbrx", Opcode: 0x7c00062c, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}, {16, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
+	{Name: "lhaux", Opcode: 0x7c0002ee, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
+	{Name: "lhax", Opcode: 0x7c0002ae, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
+	{Name: "lhbrx", Opcode: 0x7c00062c, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
 	{Name: "lhz", Opcode: 0xa0000000, Mask: 0xfc000000, Fields: []powerpc.InsnField{{Name: "D", Bits: []powerpc.InsnBits{{16, 16}}}, {Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
-	{Name: "lhzcix", Opcode: 0x7c00066a, Mask: 0xfc0007ff, Priv: true, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
+	{Name: "lhzcix", Opcode: 0x7c00066a, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}, Priv: true},
 	{Name: "lhzu", Opcode: 0xa4000000, Mask: 0xfc000000, Fields: []powerpc.InsnField{{Name: "D", Bits: []powerpc.InsnBits{{16, 16}}}, {Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
-	{Name: "lhzux", Opcode: 0x7c00026e, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}, {16, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
-	{Name: "lhzx", Opcode: 0x7c00022e, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}, {16, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
+	{Name: "lhzux", Opcode: 0x7c00026e, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
+	{Name: "lhzx", Opcode: 0x7c00022e, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
 	{Name: "lmw", Opcode: 0xb8000000, Mask: 0xfc000000, Fields: []powerpc.InsnField{{Name: "D", Bits: []powerpc.InsnBits{{16, 16}}}, {Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
 	{Name: "lq", Opcode: 0xe0000000, Mask: 0xfc00000f, Fields: []powerpc.InsnField{{Name: "DQ", Bits: []powerpc.InsnBits{{16, 12}}}, {Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RTp", Bits: []powerpc.InsnBits{{6, 5}}}}},
 	{Name: "lqarx", Opcode: 0x7c000228, Mask: 0xfc0007fe, Fields: []powerpc.InsnField{{Name: "EH", Bits: []powerpc.InsnBits{{31, 1}}}, {Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RTp", Bits: []powerpc.InsnBits{{6, 5}}}}},
@@ -407,14 +407,14 @@ var insns = []*powerpc.Insn{
 	{Name: "lwa", Opcode: 0xe8000002, Mask: 0xfc000003, Fields: []powerpc.InsnField{{Name: "DS", Bits: []powerpc.InsnBits{{16, 14}}}, {Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
 	{Name: "lwarx", Opcode: 0x7c000028, Mask: 0xfc0007fe, Fields: []powerpc.InsnField{{Name: "EH", Bits: []powerpc.InsnBits{{31, 1}}}, {Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
 	{Name: "lwat", Opcode: 0x7c00048c, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "FC", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
-	{Name: "lwaux", Opcode: 0x7c0002ea, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}, {16, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
-	{Name: "lwax", Opcode: 0x7c0002aa, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}, {16, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
-	{Name: "lwbrx", Opcode: 0x7c00042c, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}, {16, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
+	{Name: "lwaux", Opcode: 0x7c0002ea, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
+	{Name: "lwax", Opcode: 0x7c0002aa, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
+	{Name: "lwbrx", Opcode: 0x7c00042c, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
 	{Name: "lwz", Opcode: 0x80000000, Mask: 0xfc000000, Fields: []powerpc.InsnField{{Name: "D", Bits: []powerpc.InsnBits{{16, 16}}}, {Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
-	{Name: "lwzcix", Opcode: 0x7c00062a, Mask: 0xfc0007ff, Priv: true, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
+	{Name: "lwzcix", Opcode: 0x7c00062a, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}, Priv: true},
 	{Name: "lwzu", Opcode: 0x84000000, Mask: 0xfc000000, Fields: []powerpc.InsnField{{Name: "D", Bits: []powerpc.InsnBits{{16, 16}}}, {Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
-	{Name: "lwzux", Opcode: 0x7c00006e, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}, {16, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
-	{Name: "lwzx", Opcode: 0x7c00002e, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}, {16, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
+	{Name: "lwzux", Opcode: 0x7c00006e, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
+	{Name: "lwzx", Opcode: 0x7c00002e, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
 	{Name: "lxsd", Opcode: 0xe4000002, Mask: 0xfc000003, Fields: []powerpc.InsnField{{Name: "DS", Bits: []powerpc.InsnBits{{16, 14}}}, {Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "VRT", Bits: []powerpc.InsnBits{{6, 5}}}}},
 	{Name: "lxsdx", Opcode: 0x7c000498, Mask: 0xfc0007fe, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "T", Bits: []powerpc.InsnBits{{6, 5}}}, {Name: "TX", Bits: []powerpc.InsnBits{{31, 1}}}}},
 	{Name: "lxsibzx", Opcode: 0x7c00061a, Mask: 0xfc0007fe, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "T", Bits: []powerpc.InsnBits{{6, 5}}}, {Name: "TX", Bits: []powerpc.InsnBits{{31, 1}}}}},
@@ -456,7 +456,7 @@ var insns = []*powerpc.Insn{
 	{Name: "mffscrn", Opcode: 0xfc16048e, Mask: 0xfc1f07ff, Fields: []powerpc.InsnField{{Name: "FRB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "FRT", Bits: []powerpc.InsnBits{{6, 5}}}}},
 	{Name: "mffscrni", Opcode: 0xfc17048e, Mask: 0xfc1fe7ff, Fields: []powerpc.InsnField{{Name: "FRT", Bits: []powerpc.InsnBits{{6, 5}}}, {Name: "RM", Bits: []powerpc.InsnBits{{19, 2}}}}},
 	{Name: "mffsl", Opcode: 0xfc18048e, Mask: 0xfc1fffff, Fields: []powerpc.InsnField{{Name: "FRT", Bits: []powerpc.InsnBits{{6, 5}}}}},
-	{Name: "mfmsr", Opcode: 0x7c0000a6, Mask: 0xfc1fffff, Priv: true, Fields: []powerpc.InsnField{{Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
+	{Name: "mfmsr", Opcode: 0x7c0000a6, Mask: 0xfc1fffff, Fields: []powerpc.InsnField{{Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}, Priv: true},
 	{Name: "mfocrf", Opcode: 0x7c100026, Mask: 0xfc100fff, Fields: []powerpc.InsnField{{Name: "FXM", Bits: []powerpc.InsnBits{{12, 8}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
 	{Name: "mfspr", Opcode: 0x7c0002a6, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}, {Name: "spr", Bits: []powerpc.InsnBits{{16, 5}, {11, 5}}}}},
 	{Name: "mftb", Opcode: 0x7c0002e6, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}, {Name: "tbr", Bits: []powerpc.InsnBits{{11, 10}}}}},
@@ -468,13 +468,13 @@ var insns = []*powerpc.Insn{
 	{Name: "modsw", Opcode: 0x7c000616, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
 	{Name: "modud", Opcode: 0x7c000212, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
 	{Name: "moduw", Opcode: 0x7c000216, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
-	{Name: "msgclr", Opcode: 0x7c0001dc, Mask: 0xffff07ff, Priv: true, Fields: []powerpc.InsnField{{Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}}},
-	{Name: "msgclrp", Opcode: 0x7c00015c, Mask: 0xffff07ff, Priv: true, Fields: []powerpc.InsnField{{Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}}},
-	{Name: "msgclru", Opcode: 0x7c0000dc, Mask: 0xffff07ff, Priv: true, Fields: []powerpc.InsnField{{Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}}},
-	{Name: "msgsnd", Opcode: 0x7c00019c, Mask: 0xffff07ff, Priv: true, Fields: []powerpc.InsnField{{Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}}},
-	{Name: "msgsndp", Opcode: 0x7c00011c, Mask: 0xffff07ff, Priv: true, Fields: []powerpc.InsnField{{Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}}},
-	{Name: "msgsndu", Opcode: 0x7c00009c, Mask: 0xffff07ff, Priv: true, Fields: []powerpc.InsnField{{Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}}},
-	{Name: "msgsync", Opcode: 0x7c0006ec, Mask: 0xffffffff, Priv: true, Fields: []powerpc.InsnField{}},
+	{Name: "msgclr", Opcode: 0x7c0001dc, Mask: 0xffff07ff, Fields: []powerpc.InsnField{{Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}}, Priv: true},
+	{Name: "msgclrp", Opcode: 0x7c00015c, Mask: 0xffff07ff, Fields: []powerpc.InsnField{{Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}}, Priv: true},
+	{Name: "msgclru", Opcode: 0x7c0000dc, Mask: 0xffff07ff, Fields: []powerpc.InsnField{{Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}}, Priv: true},
+	{Name: "msgsnd", Opcode: 0x7c00019c, Mask: 0xffff07ff, Fields: []powerpc.InsnField{{Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}}, Priv: true},
+	{Name: "msgsndp", Opcode: 0x7c00011c, Mask: 0xffff07ff, Fields: []powerpc.InsnField{{Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}}, Priv: true},
+	{Name: "msgsndu", Opcode: 0x7c00009c, Mask: 0xffff07ff, Fields: []powerpc.InsnField{{Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}}, Priv: true},
+	{Name: "msgsync", Opcode: 0x7c0006ec, Mask: 0xffffffff, Fields: []powerpc.InsnField{}, Priv: true},
 	{Name: "mtcrf", Opcode: 0x7c000120, Mask: 0xfc100fff, Fields: []powerpc.InsnField{{Name: "FXM", Bits: []powerpc.InsnBits{{12, 8}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
 	{Name: "mtfsb0", Opcode: 0xfc00008c, Mask: 0xfc1fffff, Fields: []powerpc.InsnField{{Name: "BT", Bits: []powerpc.InsnBits{{6, 5}}}}},
 	{Name: "mtfsb0.", Opcode: 0xfc00008d, Mask: 0xfc1fffff, Fields: []powerpc.InsnField{{Name: "BT", Bits: []powerpc.InsnBits{{6, 5}}}}},
@@ -484,8 +484,8 @@ var insns = []*powerpc.Insn{
 	{Name: "mtfsf.", Opcode: 0xfc00058f, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "FLM", Bits: []powerpc.InsnBits{{7, 8}}}, {Name: "FRB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "L", Bits: []powerpc.InsnBits{{6, 1}}}, {Name: "W", Bits: []powerpc.InsnBits{{15, 1}}}}},
 	{Name: "mtfsfi", Opcode: 0xfc00010c, Mask: 0xfc7e0fff, Fields: []powerpc.InsnField{{Name: "BF", Bits: []powerpc.InsnBits{{6, 3}}}, {Name: "U", Bits: []powerpc.InsnBits{{16, 4}}}, {Name: "W", Bits: []powerpc.InsnBits{{15, 1}}}}},
 	{Name: "mtfsfi.", Opcode: 0xfc00010d, Mask: 0xfc7e0fff, Fields: []powerpc.InsnField{{Name: "BF", Bits: []powerpc.InsnBits{{6, 3}}}, {Name: "U", Bits: []powerpc.InsnBits{{16, 4}}}, {Name: "W", Bits: []powerpc.InsnBits{{15, 1}}}}},
-	{Name: "mtmsr", Opcode: 0x7c000124, Mask: 0xfc1effff, Priv: true, Fields: []powerpc.InsnField{{Name: "L", Bits: []powerpc.InsnBits{{15, 1}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
-	{Name: "mtmsrd", Opcode: 0x7c000164, Mask: 0xfc1effff, Priv: true, Fields: []powerpc.InsnField{{Name: "L", Bits: []powerpc.InsnBits{{15, 1}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
+	{Name: "mtmsr", Opcode: 0x7c000124, Mask: 0xfc1effff, Fields: []powerpc.InsnField{{Name: "L", Bits: []powerpc.InsnBits{{15, 1}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}, Priv: true},
+	{Name: "mtmsrd", Opcode: 0x7c000164, Mask: 0xfc1effff, Fields: []powerpc.InsnField{{Name: "L", Bits: []powerpc.InsnBits{{15, 1}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}, Priv: true},
 	{Name: "mtocrf", Opcode: 0x7c100120, Mask: 0xfc100fff, Fields: []powerpc.InsnField{{Name: "FXM", Bits: []powerpc.InsnBits{{12, 8}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
 	{Name: "mtspr", Opcode: 0x7c0003a6, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}, {Name: "spr", Bits: []powerpc.InsnBits{{16, 5}, {11, 5}}}}},
 	{Name: "mtvscr", Opcode: 0x10000644, Mask: 0xffff07ff, Fields: []powerpc.InsnField{{Name: "VRB", Bits: []powerpc.InsnBits{{16, 5}}}}},
@@ -650,8 +650,8 @@ var insns = []*powerpc.Insn{
 	{Name: "pstxvp", Opcode: 0x04000000, Mask: 0xffec0000, Fields: []powerpc.InsnField{{Name: "R", Bits: []powerpc.InsnBits{{11, 1}}}, {Name: "d0", Bits: []powerpc.InsnBits{{14, 18}}}},
 		OpcodeSuffix: 0xf8000000, MaskSuffix: 0xfc000000, FieldsSuffix: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "SX", Bits: []powerpc.InsnBits{{10, 1}}}, {Name: "Sp", Bits: []powerpc.InsnBits{{6, 4}}}, {Name: "d1", Bits: []powerpc.InsnBits{{16, 16}}}}},
 	{Name: "rfebb", Opcode: 0x4c000124, Mask: 0xfffff7ff, Fields: []powerpc.InsnField{{Name: "S", Bits: []powerpc.InsnBits{{20, 1}}}}},
-	{Name: "rfid", Opcode: 0x4c000024, Mask: 0xffffffff, Priv: true, Fields: []powerpc.InsnField{}},
-	{Name: "rfscv", Opcode: 0x4c0000a4, Mask: 0xffffffff, Priv: true, Fields: []powerpc.InsnField{}},
+	{Name: "rfid", Opcode: 0x4c000024, Mask: 0xffffffff, Fields: []powerpc.InsnField{}, Priv: true},
+	{Name: "rfscv", Opcode: 0x4c0000a4, Mask: 0xffffffff, Fields: []powerpc.InsnField{}, Priv: true},
 	{Name: "rldcl", Opcode: 0x78000010, Mask: 0xfc00001f, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}, {Name: "mb", Bits: []powerpc.InsnBits{{21, 5}, {26, 1}}}}},
 	{Name: "rldcl.", Opcode: 0x78000011, Mask: 0xfc00001f, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}, {Name: "mb", Bits: []powerpc.InsnBits{{21, 5}, {26, 1}}}}},
 	{Name: "rldcr", Opcode: 0x78000012, Mask: 0xfc00001f, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}, {Name: "me", Bits: []powerpc.InsnBits{{21, 5}, {26, 1}}}}},
@@ -677,15 +677,15 @@ var insns = []*powerpc.Insn{
 	{Name: "setbcr", Opcode: 0x7c000340, Mask: 0xfc00ffff, Fields: []powerpc.InsnField{{Name: "BI", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
 	{Name: "setnbc", Opcode: 0x7c000380, Mask: 0xfc00ffff, Fields: []powerpc.InsnField{{Name: "BI", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
 	{Name: "setnbcr", Opcode: 0x7c0003c0, Mask: 0xfc00ffff, Fields: []powerpc.InsnField{{Name: "BI", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
-	{Name: "slbfee.", Opcode: 0x7c0007a7, Mask: 0xfc1f07ff, Priv: true, Fields: []powerpc.InsnField{{Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
-	{Name: "slbia", Opcode: 0x7c0003e4, Mask: 0xff1fffff, Priv: true, Fields: []powerpc.InsnField{{Name: "IH", Bits: []powerpc.InsnBits{{8, 3}}}}},
-	{Name: "slbiag", Opcode: 0x7c0006a4, Mask: 0xfc1effff, Priv: true, Fields: []powerpc.InsnField{{Name: "L", Bits: []powerpc.InsnBits{{15, 1}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
-	{Name: "slbie", Opcode: 0x7c000364, Mask: 0xffff07ff, Priv: true, Fields: []powerpc.InsnField{{Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}}},
-	{Name: "slbieg", Opcode: 0x7c0003a4, Mask: 0xfc1f07ff, Priv: true, Fields: []powerpc.InsnField{{Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
-	{Name: "slbmfee", Opcode: 0x7c000726, Mask: 0xfc1e07ff, Priv: true, Fields: []powerpc.InsnField{{Name: "L", Bits: []powerpc.InsnBits{{15, 1}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
-	{Name: "slbmfev", Opcode: 0x7c0006a6, Mask: 0xfc1e07ff, Priv: true, Fields: []powerpc.InsnField{{Name: "L", Bits: []powerpc.InsnBits{{15, 1}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}},
-	{Name: "slbmte", Opcode: 0x7c000324, Mask: 0xfc1f07ff, Priv: true, Fields: []powerpc.InsnField{{Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
-	{Name: "slbsync", Opcode: 0x7c0002a4, Mask: 0xffffffff, Priv: true, Fields: []powerpc.InsnField{}},
+	{Name: "slbfee.", Opcode: 0x7c0007a7, Mask: 0xfc1f07ff, Fields: []powerpc.InsnField{{Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}, Priv: true},
+	{Name: "slbia", Opcode: 0x7c0003e4, Mask: 0xff1fffff, Fields: []powerpc.InsnField{{Name: "IH", Bits: []powerpc.InsnBits{{8, 3}}}}, Priv: true},
+	{Name: "slbiag", Opcode: 0x7c0006a4, Mask: 0xfc1effff, Fields: []powerpc.InsnField{{Name: "L", Bits: []powerpc.InsnBits{{15, 1}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}, Priv: true},
+	{Name: "slbie", Opcode: 0x7c000364, Mask: 0xffff07ff, Fields: []powerpc.InsnField{{Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}}, Priv: true},
+	{Name: "slbieg", Opcode: 0x7c0003a4, Mask: 0xfc1f07ff, Fields: []powerpc.InsnField{{Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}, Priv: true},
+	{Name: "slbmfee", Opcode: 0x7c000726, Mask: 0xfc1e07ff, Fields: []powerpc.InsnField{{Name: "L", Bits: []powerpc.InsnBits{{15, 1}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}, Priv: true},
+	{Name: "slbmfev", Opcode: 0x7c0006a6, Mask: 0xfc1e07ff, Fields: []powerpc.InsnField{{Name: "L", Bits: []powerpc.InsnBits{{15, 1}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RT", Bits: []powerpc.InsnBits{{6, 5}}}}, Priv: true},
+	{Name: "slbmte", Opcode: 0x7c000324, Mask: 0xfc1f07ff, Fields: []powerpc.InsnField{{Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}, Priv: true},
+	{Name: "slbsync", Opcode: 0x7c0002a4, Mask: 0xffffffff, Fields: []powerpc.InsnField{}, Priv: true},
 	{Name: "sld", Opcode: 0x7c000036, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
 	{Name: "sld.", Opcode: 0x7c000037, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
 	{Name: "slw", Opcode: 0x7c000030, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
@@ -703,19 +703,19 @@ var insns = []*powerpc.Insn{
 	{Name: "srw", Opcode: 0x7c000430, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
 	{Name: "srw.", Opcode: 0x7c000431, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
 	{Name: "stb", Opcode: 0x98000000, Mask: 0xfc000000, Fields: []powerpc.InsnField{{Name: "D", Bits: []powerpc.InsnBits{{16, 16}}}, {Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
-	{Name: "stbcix", Opcode: 0x7c0007aa, Mask: 0xfc0007ff, Priv: true, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
+	{Name: "stbcix", Opcode: 0x7c0007aa, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}, Priv: true},
 	{Name: "stbcx.", Opcode: 0x7c00056d, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
 	{Name: "stbu", Opcode: 0x9c000000, Mask: 0xfc000000, Fields: []powerpc.InsnField{{Name: "D", Bits: []powerpc.InsnBits{{16, 16}}}, {Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
-	{Name: "stbux", Opcode: 0x7c0001ee, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}, {16, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
-	{Name: "stbx", Opcode: 0x7c0001ae, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}, {16, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
+	{Name: "stbux", Opcode: 0x7c0001ee, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
+	{Name: "stbx", Opcode: 0x7c0001ae, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
 	{Name: "std", Opcode: 0xf8000000, Mask: 0xfc000003, Fields: []powerpc.InsnField{{Name: "DS", Bits: []powerpc.InsnBits{{16, 14}}}, {Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
 	{Name: "stdat", Opcode: 0x7c0005cc, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "FC", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
-	{Name: "stdbrx", Opcode: 0x7c000528, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}, {16, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
-	{Name: "stdcix", Opcode: 0x7c0007ea, Mask: 0xfc0007ff, Priv: true, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
+	{Name: "stdbrx", Opcode: 0x7c000528, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
+	{Name: "stdcix", Opcode: 0x7c0007ea, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}, Priv: true},
 	{Name: "stdcx.", Opcode: 0x7c0001ad, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
 	{Name: "stdu", Opcode: 0xf8000001, Mask: 0xfc000003, Fields: []powerpc.InsnField{{Name: "DS", Bits: []powerpc.InsnBits{{16, 14}}}, {Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
-	{Name: "stdux", Opcode: 0x7c00016a, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}, {16, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
-	{Name: "stdx", Opcode: 0x7c00012a, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}, {16, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
+	{Name: "stdux", Opcode: 0x7c00016a, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
+	{Name: "stdx", Opcode: 0x7c00012a, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
 	{Name: "stfd", Opcode: 0xd8000000, Mask: 0xfc000000, Fields: []powerpc.InsnField{{Name: "D", Bits: []powerpc.InsnBits{{16, 16}}}, {Name: "FRS", Bits: []powerpc.InsnBits{{6, 5}}}, {Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}}},
 	{Name: "stfdp", Opcode: 0xf4000000, Mask: 0xfc000003, Fields: []powerpc.InsnField{{Name: "DS", Bits: []powerpc.InsnBits{{16, 14}}}, {Name: "FRSp", Bits: []powerpc.InsnBits{{6, 5}}}, {Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}}},
 	{Name: "stfdpx", Opcode: 0x7c00072e, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "FRSp", Bits: []powerpc.InsnBits{{6, 5}}}, {Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}}},
@@ -728,14 +728,14 @@ var insns = []*powerpc.Insn{
 	{Name: "stfsux", Opcode: 0x7c00056e, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "FRS", Bits: []powerpc.InsnBits{{6, 5}}}, {Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}}},
 	{Name: "stfsx", Opcode: 0x7c00052e, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "FRS", Bits: []powerpc.InsnBits{{6, 5}}}, {Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}}},
 	{Name: "sth", Opcode: 0xb0000000, Mask: 0xfc000000, Fields: []powerpc.InsnField{{Name: "D", Bits: []powerpc.InsnBits{{16, 16}}}, {Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
-	{Name: "sthbrx", Opcode: 0x7c00072c, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}, {16, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
-	{Name: "sthcix", Opcode: 0x7c00076a, Mask: 0xfc0007ff, Priv: true, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
+	{Name: "sthbrx", Opcode: 0x7c00072c, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
+	{Name: "sthcix", Opcode: 0x7c00076a, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}, Priv: true},
 	{Name: "sthcx.", Opcode: 0x7c0005ad, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
 	{Name: "sthu", Opcode: 0xb4000000, Mask: 0xfc000000, Fields: []powerpc.InsnField{{Name: "D", Bits: []powerpc.InsnBits{{16, 16}}}, {Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
-	{Name: "sthux", Opcode: 0x7c00036e, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}, {16, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
-	{Name: "sthx", Opcode: 0x7c00032e, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}, {16, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
+	{Name: "sthux", Opcode: 0x7c00036e, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
+	{Name: "sthx", Opcode: 0x7c00032e, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
 	{Name: "stmw", Opcode: 0xbc000000, Mask: 0xfc000000, Fields: []powerpc.InsnField{{Name: "D", Bits: []powerpc.InsnBits{{16, 16}}}, {Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
-	{Name: "stop", Opcode: 0x4c0002e4, Mask: 0xffffffff, Priv: true, Fields: []powerpc.InsnField{}},
+	{Name: "stop", Opcode: 0x4c0002e4, Mask: 0xffffffff, Fields: []powerpc.InsnField{}, Priv: true},
 	{Name: "stq", Opcode: 0xf8000002, Mask: 0xfc000003, Fields: []powerpc.InsnField{{Name: "DS", Bits: []powerpc.InsnBits{{16, 14}}}, {Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RSp", Bits: []powerpc.InsnBits{{6, 5}}}}},
 	{Name: "stqcx.", Opcode: 0x7c00016d, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RSp", Bits: []powerpc.InsnBits{{6, 5}}}}},
 	{Name: "stswi", Opcode: 0x7c0005aa, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "NB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
@@ -747,12 +747,12 @@ var insns = []*powerpc.Insn{
 	{Name: "stvxl", Opcode: 0x7c0003ce, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "VRS", Bits: []powerpc.InsnBits{{6, 5}}}}},
 	{Name: "stw", Opcode: 0x90000000, Mask: 0xfc000000, Fields: []powerpc.InsnField{{Name: "D", Bits: []powerpc.InsnBits{{16, 16}}}, {Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
 	{Name: "stwat", Opcode: 0x7c00058c, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "FC", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
-	{Name: "stwbrx", Opcode: 0x7c00052c, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}, {16, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
-	{Name: "stwcix", Opcode: 0x7c00072a, Mask: 0xfc0007ff, Priv: true, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
+	{Name: "stwbrx", Opcode: 0x7c00052c, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
+	{Name: "stwcix", Opcode: 0x7c00072a, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}, Priv: true},
 	{Name: "stwcx.", Opcode: 0x7c00012d, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
 	{Name: "stwu", Opcode: 0x94000000, Mask: 0xfc000000, Fields: []powerpc.InsnField{{Name: "D", Bits: []powerpc.InsnBits{{16, 16}}}, {Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
-	{Name: "stwux", Opcode: 0x7c00016e, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}, {16, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
-	{Name: "stwx", Opcode: 0x7c00012e, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}, {16, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
+	{Name: "stwux", Opcode: 0x7c00016e, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
+	{Name: "stwx", Opcode: 0x7c00012e, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
 	{Name: "stxsd", Opcode: 0xf4000002, Mask: 0xfc000003, Fields: []powerpc.InsnField{{Name: "DS", Bits: []powerpc.InsnBits{{16, 14}}}, {Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "VRS", Bits: []powerpc.InsnBits{{6, 5}}}}},
 	{Name: "stxsdx", Opcode: 0x7c000598, Mask: 0xfc0007fe, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "S", Bits: []powerpc.InsnBits{{6, 5}}}, {Name: "SX", Bits: []powerpc.InsnBits{{31, 1}}}}},
 	{Name: "stxsibx", Opcode: 0x7c00071a, Mask: 0xfc0007fe, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "S", Bits: []powerpc.InsnBits{{6, 5}}}, {Name: "SX", Bits: []powerpc.InsnBits{{31, 1}}}}},
@@ -798,12 +798,12 @@ var insns = []*powerpc.Insn{
 	{Name: "sync", Opcode: 0x7c0004ac, Mask: 0xff1cffff, Fields: []powerpc.InsnField{{Name: "L", Bits: []powerpc.InsnBits{{8, 3}}}, {Name: "SC", Bits: []powerpc.InsnBits{{14, 2}}}}},
 	{Name: "td", Opcode: 0x7c000088, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "TO", Bits: []powerpc.InsnBits{{6, 5}}}}},
 	{Name: "tdi", Opcode: 0x08000000, Mask: 0xfc000000, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "SI", Bits: []powerpc.InsnBits{{16, 16}}}, {Name: "TO", Bits: []powerpc.InsnBits{{6, 5}}}}},
-	{Name: "tlbie", Opcode: 0x7c000264, Mask: 0xfc1007ff, Priv: true, Fields: []powerpc.InsnField{{Name: "PRS", Bits: []powerpc.InsnBits{{14, 1}}}, {Name: "R", Bits: []powerpc.InsnBits{{15, 1}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RIC", Bits: []powerpc.InsnBits{{12, 2}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
-	{Name: "tlbiel", Opcode: 0x7c000224, Mask: 0xfc1007ff, Priv: true, Fields: []powerpc.InsnField{{Name: "PRS", Bits: []powerpc.InsnBits{{14, 1}}}, {Name: "R", Bits: []powerpc.InsnBits{{15, 1}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RIC", Bits: []powerpc.InsnBits{{12, 2}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
-	{Name: "tlbsync", Opcode: 0x7c00046c, Mask: 0xffffffff, Priv: true, Fields: []powerpc.InsnField{}},
+	{Name: "tlbie", Opcode: 0x7c000264, Mask: 0xfc1007ff, Fields: []powerpc.InsnField{{Name: "PRS", Bits: []powerpc.InsnBits{{14, 1}}}, {Name: "R", Bits: []powerpc.InsnBits{{15, 1}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RIC", Bits: []powerpc.InsnBits{{12, 2}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}, Priv: true},
+	{Name: "tlbiel", Opcode: 0x7c000224, Mask: 0xfc1007ff, Fields: []powerpc.InsnField{{Name: "PRS", Bits: []powerpc.InsnBits{{14, 1}}}, {Name: "R", Bits: []powerpc.InsnBits{{15, 1}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RIC", Bits: []powerpc.InsnBits{{12, 2}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}, Priv: true},
+	{Name: "tlbsync", Opcode: 0x7c00046c, Mask: 0xffffffff, Fields: []powerpc.InsnField{}, Priv: true},
 	{Name: "tw", Opcode: 0x7c000008, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "TO", Bits: []powerpc.InsnBits{{6, 5}}}}},
 	{Name: "twi", Opcode: 0x0c000000, Mask: 0xfc000000, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "SI", Bits: []powerpc.InsnBits{{16, 16}}}, {Name: "TO", Bits: []powerpc.InsnBits{{6, 5}}}}},
-	{Name: "urfid", Opcode: 0x4c000264, Mask: 0xffffffff, Priv: true, Fields: []powerpc.InsnField{}},
+	{Name: "urfid", Opcode: 0x4c000264, Mask: 0xffffffff, Fields: []powerpc.InsnField{}, Priv: true},
 	{Name: "vabsdub", Opcode: 0x10000403, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "VRA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "VRB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "VRT", Bits: []powerpc.InsnBits{{6, 5}}}}},
 	{Name: "vabsduh", Opcode: 0x10000443, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "VRA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "VRB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "VRT", Bits: []powerpc.InsnBits{{6, 5}}}}},
 	{Name: "vabsduw", Opcode: 0x10000483, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "VRA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "VRB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "VRT", Bits: []powerpc.InsnBits{{6, 5}}}}},
@@ -1178,7 +1178,7 @@ var insns = []*powerpc.Insn{
 	{Name: "vupklsh", Opcode: 0x100002ce, Mask: 0xfc1f07ff, Fields: []powerpc.InsnField{{Name: "VRB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "VRT", Bits: []powerpc.InsnBits{{6, 5}}}}},
 	{Name: "vupklsw", Opcode: 0x100006ce, Mask: 0xfc1f07ff, Fields: []powerpc.InsnField{{Name: "VRB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "VRT", Bits: []powerpc.InsnBits{{6, 5}}}}},
 	{Name: "vxor", Opcode: 0x100004c4, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "VRA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "VRB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "VRT", Bits: []powerpc.InsnBits{{6, 5}}}}},
-	{Name: "wait", Opcode: 0x7c00003c, Mask: 0xff9cffff, Fields: []powerpc.InsnField{{Name: "PL", Bits: []powerpc.InsnBits{{14, 2}}}, {Name: "WC", Bits: []powerpc.InsnBits{{9, 2}}}}},
+	{Name: "wait", Opcode: 0x7c00003c, Mask: 0xfc9cffff, Fields: []powerpc.InsnField{{Name: "PL", Bits: []powerpc.InsnBits{{14, 2}}}, {Name: "WC", Bits: []powerpc.InsnBits{{9, 2}}}}},
 	{Name: "xor", Opcode: 0x7c000278, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
 	{Name: "xor.", Opcode: 0x7c000279, Mask: 0xfc0007ff, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RB", Bits: []powerpc.InsnBits{{16, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}}},
 	{Name: "xori", Opcode: 0x68000000, Mask: 0xfc000000, Fields: []powerpc.InsnField{{Name: "RA", Bits: []powerpc.InsnBits{{11, 5}}}, {Name: "RS", Bits: []powerpc.InsnBits{{6, 5}}}, {Name: "UI", Bits: []powerpc.InsnBits{{16, 16}}}}},