diff options
| author | Alexey Kardashevskiy <aik@linux.ibm.com> | 2021-10-26 13:13:11 +1100 |
|---|---|---|
| committer | Aleksandr Nogikh <wp32pw@gmail.com> | 2021-11-12 16:33:30 +0100 |
| commit | a8b7d5b5db39496af5048e2fb9fd69ac74b076e3 (patch) | |
| tree | 59012b895954ada6db3c917b3584a957716584a9 /pkg/ifuzz/powerpc/generated | |
| parent | f10e2dd705063905e37098725eb2362ca40fcbcc (diff) | |
pkg/ifuzz/powerpc: ditch M64
There are only 2 instructions - tlbie and tlbiel (TLB invalidation) -
which are marked 64bit only and there is no obvious reason why they
would not work in the 32bit mode - they seem working but even if they
did not, making a special case just for these two is overkill.
This ditches the M64 flag.
Signed-off-by: Alexey Kardashevskiy <aik@linux.ibm.com>
Diffstat (limited to 'pkg/ifuzz/powerpc/generated')
| -rw-r--r-- | pkg/ifuzz/powerpc/generated/insns.go | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/pkg/ifuzz/powerpc/generated/insns.go b/pkg/ifuzz/powerpc/generated/insns.go index 4506314e8..f0dcf9cda 100644 --- a/pkg/ifuzz/powerpc/generated/insns.go +++ b/pkg/ifuzz/powerpc/generated/insns.go @@ -547,8 +547,8 @@ var insns = []*powerpc.Insn{ {Name: "mtocrf", Opcode: 0x7c100120, Mask: 0xfc100fff, Fields: map[string][]powerpc.InsnBits{"FXM": {powerpc.InsnBits{12, 8}}, "RS": {powerpc.InsnBits{6, 5}}}}, {Name: "mtmsr", Opcode: 0x7c000124, Mask: 0xfc1effff, Priv: true, Fields: map[string][]powerpc.InsnBits{"L": {powerpc.InsnBits{15, 1}}, "RS": {powerpc.InsnBits{6, 5}}}}, {Name: "mtmsrd", Opcode: 0x7c000164, Mask: 0xfc1effff, Priv: true, Fields: map[string][]powerpc.InsnBits{"L": {powerpc.InsnBits{15, 1}}, "RS": {powerpc.InsnBits{6, 5}}}}, - {Name: "tlbiel", Opcode: 0x7c000224, Mask: 0xfc1007ff, M64: true, Priv: true, Fields: map[string][]powerpc.InsnBits{"PRS": {powerpc.InsnBits{14, 1}}, "R": {powerpc.InsnBits{15, 1}}, "RB": {powerpc.InsnBits{16, 5}}, "RIC": {powerpc.InsnBits{12, 2}}, "RS": {powerpc.InsnBits{6, 5}}}}, - {Name: "tlbie", Opcode: 0x7c000264, Mask: 0xfc1007ff, M64: true, Priv: true, Fields: map[string][]powerpc.InsnBits{"PRS": {powerpc.InsnBits{14, 1}}, "R": {powerpc.InsnBits{15, 1}}, "RB": {powerpc.InsnBits{16, 5}}, "RIC": {powerpc.InsnBits{12, 2}}, "RS": {powerpc.InsnBits{6, 5}}}}, + {Name: "tlbiel", Opcode: 0x7c000224, Mask: 0xfc1007ff, Priv: true, Fields: map[string][]powerpc.InsnBits{"PRS": {powerpc.InsnBits{14, 1}}, "R": {powerpc.InsnBits{15, 1}}, "RB": {powerpc.InsnBits{16, 5}}, "RIC": {powerpc.InsnBits{12, 2}}, "RS": {powerpc.InsnBits{6, 5}}}}, + {Name: "tlbie", Opcode: 0x7c000264, Mask: 0xfc1007ff, Priv: true, Fields: map[string][]powerpc.InsnBits{"PRS": {powerpc.InsnBits{14, 1}}, "R": {powerpc.InsnBits{15, 1}}, "RB": {powerpc.InsnBits{16, 5}}, "RIC": {powerpc.InsnBits{12, 2}}, "RS": {powerpc.InsnBits{6, 5}}}}, {Name: "slbsync", Opcode: 0x7c0002a4, Mask: 0xffffffff, Priv: true, Fields: map[string][]powerpc.InsnBits{}}, {Name: "slbmte", Opcode: 0x7c000324, Mask: 0xfc1f07ff, Priv: true, Fields: map[string][]powerpc.InsnBits{"RB": {powerpc.InsnBits{16, 5}}, "RS": {powerpc.InsnBits{6, 5}}}}, {Name: "slbie", Opcode: 0x7c000364, Mask: 0xffff07ff, Priv: true, Fields: map[string][]powerpc.InsnBits{"RB": {powerpc.InsnBits{16, 5}}}}, |