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authorDmitry Vyukov <dvyukov@google.com>2017-01-12 10:25:09 +0100
committerDmitry Vyukov <dvyukov@google.com>2017-01-12 10:25:09 +0100
commitbcfae12bec951e6e4261a9910eab4b971f767329 (patch)
tree756905b68062a23ce2e0bdcabdc549d5168d24a7 /ifuzz
parent437a8a0b206a13e2a7b77b3bac92412948ef4a00 (diff)
ifuzz: fix generation of control registers
Diffstat (limited to 'ifuzz')
-rw-r--r--ifuzz/encode.go11
1 files changed, 7 insertions, 4 deletions
diff --git a/ifuzz/encode.go b/ifuzz/encode.go
index ae2453bdf..799def63a 100644
--- a/ifuzz/encode.go
+++ b/ifuzz/encode.go
@@ -33,6 +33,7 @@ func (insn *Insn) Encode(cfg *Config, r *rand.Rand) []byte {
var code []byte
+ rexR := false
var vvvv, vexR, vexX, vexB byte
// LEGACY PREFIXES
@@ -78,6 +79,7 @@ func (insn *Insn) Encode(cfg *Config, r *rand.Rand) []byte {
} else if insn.Rexw == 1 {
rex &^= 1 << 3
}
+ rexR = rex&0x4 != 0
code = append(code, rex)
}
@@ -174,11 +176,12 @@ func (insn *Insn) Encode(cfg *Config, r *rand.Rand) []byte {
} else if insn.Reg == -6 {
reg = byte(r.Intn(6)) // segment register
} else if insn.Reg == -8 {
- reg = byte(r.Intn(7)) // control register
- if reg >= 1 {
- reg++
+ if rexR {
+ reg = 0 // CR8
+ } else {
+ crs := []byte{0, 2, 3, 4}
+ reg = crs[r.Intn(len(crs))]
}
- reg = 0
}
if insn.Avx2Gather {
if reg|(1-vexR)<<3 == vvvv^0xf {